Enhancing the SRAM Failure Analysis Process
Raymond G. Mendaros
Global Failure Analysis (GFA)
Analog Devices General Trias (ADGT)
Gateway Business Park, Brgy. Javalera, Gen. Trias, Cavite, Philippines 4107
Phone: +63 2 867703, Email: raymond.mendaros@analog.com
Abstract- The advent of the 65nm silicon fabrication
technology node and smaller geometries; particularly for static
random-access memory (SRAM) array, posed several Failure
Analysis (FA) challenges such as the fault isolation capability
limitations, physical FA (PFA) approach identification intricacy,
defect node localization complexity and defect to fail mode
correlation difficulty. To address these challenges, device defect
modeling (DDM) process through software simulations and
building of defect databases were introduced. Through the aid of
the DDM process, defect sites were reduced to a single transistor
or node from the SRAM array. Defect models were derived from
the simulation process that guided analysts in identifying the
suitable PFA approach. DDM process was effective in the failure
mechanism to failure mode simulations. The DDM process was
likewise instrumental in building defect databases for SRAM
layout designs. These databases contained relevant information
such as circuit simulation results, fabrication material stacking,
suggested fault isolation techniques and potential defect locations
that served as references for analysts.
geometries such as the 65nm technology node. The limitation
encountered on the PEM system is a common shortcoming for
the OBIRCH and thermal systems.
Keywords –Defect Modeling, Static Random Access Memory,
fault isolation, 65nm technology node, SRAM defect database
The PFA technique or approach to be used may vary
depending on the defect type. For instance, an electrostatic
discharge (ESD) damage such as “pinholes”, due to its
miniscule physical attribute, is preferred to be chemically
deprocessed. Deprocessing will enable the inspection of the
whole layer (top down inspection), thus, has higher chances of
locating submicron defects as compared to the progressive
cross section approach. A via or plug formation defect, on the
other hand, is preferred to be cross-sectioned using a Focus ion
beam (FIB) equipment to have a good view of the defect site
(cross sectional view).
I. INTRODUCTION
Driven by the industry’s requirement of reducing chip
size, semiconductor companies implemented in their products
the 65nm silicon die fabrication process and smaller geometries
[1]. This die fabrication process node, due to the reduced
component size, posed several FA challenges. In this technical
literature, the focus of the study is on the failure analysis
process improvement for 65nm embedded 6T SRAM devices
wherein the learning can be fanned out to smaller fabrication
technology geometries. The FA challenges for leading
technologies are as follows:
1.
FA tools and techniques’ fault isolation limitations
Advanced photon emission microscopy (PEM), optical
beam induced resistance change (OBIRCH) and thermal
camera’s failure analysis fault isolation tools do not anymore
have enough resolutions to pinpoint the exact anomalous
SRAM memory transistor for 65nm and smaller technologies.
As an example, the PEM photo in Figure 1 was captured on a
huge 0.18um technology node. There were two
metal–oxide–semiconductor field-effect (MOSFET) transistors
in the emitting site but because of the tool’s limited optical and
camera magnification capability, even at this huge technology
node, the exact emitting transistor could not be identified. This
capability limitation is magnified when dealing with smaller
Figure 1. PEM detected photon emissions from two NMOS transistors
however, the machine resolution could not resolve which transistor was
emitting. This is a 0.18um technology process.
2. Identification of the suitable physical failure analysis (PFA)
technique or methodology
3. Defect node localization is another FA challenge
SRAM cell has six transistors in its circuit. Since DDM
process simulates a possible defect site through replicating the
failing electrical output response, the suspected defect site can
be narrowed down to a node or transistor.
4. Physical defect to failure mode correlation
Not all visual anomalies seen during physical failure
analysis (PFA) will necessary result to a failure. A suspected
physical defect observed in the chip can be electrically
simulated using the DDM process to determine its consistency
with the device’s failure mode.
To address these FA challenges, DDM process and
defect database generations were implemented in FA process.
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II. EXPERIMENTS
The study was focused on one embedded 6T SRAM
layout design. The memory failures were confined to “stuck to
low” and “stuck to high” memory failures. Timing and voltage
sensitive failures were not included due to the absence of the
exact transistor models for the LTSpice simulation software.
The memory failure types that were covered were single bit,
dual (twin) bit, full row and full column failures.
DDM simulated defect models were documented in the
database. An LTSpice student version (version 1.0.0.1) was
used in all the circuit simulations. The exact transistor models
of the 65nm memory device were not available due to
proprietary reasons. The inputs of the process are the gathered
electrical failure characteristic or behavior of the sample being
analyzed. These are the memory type (e.g. “single bit”) and
output response (e.g. “stuck to low”). The outputs are the
simulated failure memory type and output response that
corresponds to the introduced defect model (e.g. “added
resistance”) in the simulation circuit. The introduced defect
model, location of the defect in the circuit and the plots of the
simulated electrical failure characteristic or behavior are
documented in the database. The process flow is shown in
Figure 2.
Figure 2. Conceptual framework process flow.
This section was divided into 5 subsections. The first
section was the creation of an SRAM Device Defect Modeling
(DDM) simulation circuits using LTSpice (version 1.0.0.1)
software. Figure 3 is a representative single SRAM 6T cell
created in the LTSpice schematics software. For the actual
DDM simulation circuit, several SRAM cells were created in
the software. The memory failures that were considered were
confined to “stuck to low” and “stuck to high” memory failures.
The memory failure types that were covered were: single bit,
dual (twin) bit, full row and full column failures.
Figure 3. LTSpice representative circuit of a single SRAM cell
The second section was the creation of a process flow for
the defect simulations using the DDM circuit. The inputs of the
process were the fail memory types (e.g. single bit, dual bit,
etc.) and output response (e.g. “stuck to low”). The output of the
process were the simulated electrical failure responses. The
modeled defects were recorded in a database.
The third section was the building of defect databases for
specific SRAM layout designs. The contents of the databases
are as follows:
The memory failure type column contained the four
common memory array failures types: Single bit, Dual bit, Row
and Column failures. The Input signal column contained the
input pattern going to the memory array. The failure output
response column listed the SRAM failing response. These were
either “stuck low” or “stuck high” output failure condition.
Commonly for embedded SRAMs, SPI communication
protocol is used. Thus, the output response was either logic
“low” or “high” only. The simulated defect column represented
the modeled defect that replicated the electrical failure mode or
characteristic.
The lay-out location of the simulated defect column, on
the other hand, indicated the location of the modeled defect in
the layout. The next column, cross sectional illustration of the
fab process stacking of the simulated defect, illustrated the Fab
process material stacking of the defect site. The FA techniques
to be considered column listed the fault isolation and PFA
techniques to be utilized based on the modeled defect and
location. Finally, the Images/ Output plots column documents
the simulated electrical output response.
The last two sections (4th and 5th) revealed the areas in
FA process where the DDM process were utilized and
demonstrated. DDM’s usefulness in addressing the different
failure analysis challenges. At least two case studies each were
discussed to validate these two sections of the methodology.
Evidences of the simplified process were discussed.
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III. RESULTS AND DISCUSSION
Figure 6a. Simulator circuit for the dual bit cell
6T SRAM DDM Simulation Circuit Creation
Creating simulation circuits required knowledge on both
the simulation software and electronic circuit’s functionality. In
this study, there were three simulation circuits that were
created. The first circuit is a single cell to simulate single bit
failures. There were two variations of the circuit; with and
without output inverter. See figures 5a and 5b for the LTSpice
circuit and input/output responses.
Figure 6b. Input and output plots of the dual bit cell
The second circuit is a two adjacent cell to simulate dual
(double) bit failures. See Figure 6a and 6b. Two separate
adjacent circuits were created, one lateral and one vertical dual
bit circuits. Figure 6a and 6b represent a lateral dual bit
simulator. The third circuit is composed of nine transistors,
3-rows by 3-columns memory array, to simulate row and
column failures. See Figure 7a. The circuits were validated by
observing their output responses. See Figure 7b and 7c. An
SRAM cell without an inverter circuit at its output manifested
an opposite of its input signal.
Figure 7a. A 3-rows by 3 columns array simulation circuit for row and column
failures
Figure 5a. Single cell simulator without inverter circuit at the output
Figure 7b. Input to the 3-rows by 3 columns array
Figure 5b. Single cell simulator with inverter circuit at the output
Figure 7c. Outputs of the 3-rows by 3 columns array
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Defect simulation process using the DDM circuit
The defect simulation process flow is shown in Figure 2.
The inputs of the process are the fail memory type (e.g. single
bit) and output response (e.g. “stuck to low”). The outputs of
the process are the simulated failure responses and updated
database.
Defect Database
Databases were created with the consideration to the
embedded SRAM lay-out design being utilized by ADI. The
defect database serves as reference and guide for analysts. The
benefits and advantages of the databases are as follows:
a. Defect sites’ locations are identified in the layout
This avoided the tedious circuit analysis, commonly
manual approach, before the DDM process was implemented as
potential defect sites were already identified. Through the
database, once memory fail type and failure output response are
known, analysts already have an idea where to focus the
physical failure analysis and inspection.
DDM failure mechanism-to-fail mode simulations
Two representative failure mechanisms were simulated.
a. Simulation #1 – A Particle Defect
A known programming pattern was loaded into the
device, particularly to the embedded SRAM, but the read codes
(checksum values) do not match the written pattern.
Bitmapping analysis was performed to test the memory array
and found a single bit failure with “stuck to high” output
condition. The bitmapping tool was able to identify the cell’s
physical location in the memory array.
Physical FA (PFA) done by ADI’s subcontractor
uncovered a random fabrication defect. A fall-on nitride (N)
particle between the gate and drain terminals of a transistor in
the failing site was identified. See Figure 8. The electrical
failing signature of the memory cell was confirmed when a
short on the gate and drain and an open contact on the drain
defect models were introduced into the simulation circuit. The
anomalous contact is the common drain of the NMOS in one of
the inverters and pass transistor drain of the worldline. See
Figure 9 for the DDM simulation results.
b. The die fabrication material stackings are illustrated
The information about material stacking were further
verified through Focus Ion Beam (FIB) cross-sections of actual
memory cells. With this information being available, analysts
can effectively plan their physical failure analysis approach. On
the other hand, without this information, the analyst recourses
to layout review and consultations which can cause significant
delays.
c. Transistor and SRAM cell’s nodes such as, source, drain,
gate, Vdd, ground, etc., are identified and labelled.
The delays incurred due to the repeated access and viewing
of lay-outs to identify nodes are avoided. Furthermore, this
complements the material stacking information. The defect
locations are mapped in the FA reports from a top down
(layout) and cross-sectional (material stacking) perspective.
Table 1 showed a portion of the database.
Table 1. Representative defect database from one of the SRAM designs
Figure 8. TEM post FIB cross section (left) and EDX (right) results of the
suspect site
Figure 9. Stuck high output failure was confirmed
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b. Simulation #2 –Resistive W-Plug Contact Defect
ADI ATE testing showed that the programmed value of
“0” was showing an erroneous read value of “1”. Bitmapping
analysis showed two adjacent cells were failing. All the fault
isolation analysis techniques that were performed (PVC,
C-AFM and nano-probing) on the failing cells yielded no
anomalies. Physical analysis was still pursued and found
silicide and contact formation defects that were one cell away
from the bitmapper’s identified physical failing location. See
Figure 10 for the cross-sectional view of the defect and its
location in the layout. The defect observed was modeled and
introduced in the simulation circuit. Simulation results showed
that the defect site was consistent with the electrical failing
signature. See Figure 11 for the simulation results.
differs in the locations where they occur. ESD defects are
expected to be situated near the edges of the transistors’ gate
channel where high electric fields are present while
deprocessing artifacts are observed at the center of the gate
channel [4]. Deprocessing artifacts are represented by
mechanically induced damaged sites in the silicon substrate.
These damaged sites are manifested in the form of silicon pits,
voids, slits and fractures resulting from the tensional or
shearing stresses in the silicon substrate when the polysilicons
separate from the silicon substrate. Figures 12a and 12b are
SEM photos of a valid and invalid ESD pinholes.
A DDM simulation of an artifact defect in one of the
SRAM transistors did not yield to the expected failure mode.
DDM process in this case was the more efficient approach
rather than conducting actual evaluations.
Figure 12a. Valid ESD defect: SEM
photo of pinholes underneath the
gate oxide layer
Figure 10. Focus Ion Beam X-section found silicide and contact formation
defect on the common source of the failing SRAM cells
Figure 12b. Deprocessing artifact: A
pit or void at the center of the channel
b. Failure Mechanism Undetermined Investigation
An electrical failure was confirmed to be SRAM array
related. Fault isolation analysis using C-AFM confirmed a
contrast anomaly on the VDD contact. See figure 13. PFA on
the part, inspecting all the layers of the die, did not uncover the
defect. DDM process was used to explain the potential defect
site. See Figure 14. From the simulation results, the defect site
was in the metal layers but was missed during the PFA.
Figure 11. The stuck-to-low simulation has been confirmed when source of the
output pass transistor is isolated
Demonstrate the Other Usefulness of DDM
a. Wet Chemical Deprocessing Induced Artifacts Verifications
[2,3]
Wet Chemical Deprocessing is one of the techniques in
exposing embedded structures in an integrated circuit (IC).
Layers of the die from the passivation to silicon substrate can be
selectively etched away using this technique. From series of
evaluations conducted, it was discovered that there were silicon
damage sites that were induced during wet chemical
deprocessing. Their physical attributes were identical to the
attributes of electro-static discharge (ESD) defects. It only
Figure 13. C-AFM showing a VDD contact via anomaly
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Figure 14. DDM simulation results.
IV. CONCLUSION
The DDM process was found to be effective in
identifying potential defect sites in the SRAM array. This was
exemplified by the successful simulation cases. The DDM
process was instrumental in generating defect databases. The
information in the database hastened the failure analysis
process; particularly, the fault isolation steps, as analysts had a
clear understanding of the layout and material stacking that
eliminated the tedious and time-consuming reverse circuit
engineering analysis procedure. Furthermore, the DDM
process and defect database have shown that the prevailing
failure analysis challenges of the 65nm technology node can be
addressed by the process.
ACKNOWLEDGMENT
The author wishes to express his gratitude to the ADI
team from Failure analysis, TPG Product Line and Design
groups for their contribution on the analysis of the failures and
inputs to this technical paper.
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[3]
R. Mendaros, et al., “Identification of Wet Chemical Deprocessing
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CMOS Technologies”, ISTFA 2016, Texas, USA
[4]
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