LLC Resonant Converter with 99% Efficiency for
Data Center Server
2021 IEEE Applied Power Electronics Conference and Exposition (APEC) | 978-1-7281-8949-9/21/$31.00 ©2021 IEEE | DOI: 10.1109/APEC42165.2021.9487423
Rimon Gadelrab, Ahmed Nabih, Fred C. Lee and Qiang Li
Virginia Tech Center for Power Electronics Systems (CPES)
The Bradley Department of Electrical and Computer Engineering
Virginia Tech, Blacksburg, VA 24061
rimongg@vt.edu
Abstract— The new generation of processors for CPUs, GPUs
and AI demand a significantly higher current level of 500A-1000
amperes. To accommodate this significant increase in power
demand, the data center server rack must employ a 48V backplane
power bus to deliver 25-30KW to its server processor. A state-ofthe-art silicon-based power module is demonstrated to offer 96%
efficiency and a power density of around 40-50W/in3. In this
paper, a wide-bandgap (WBG)-based LLC converter is
demonstrated to have greatly improved efficiency and power
density. Operating at 500KHz switching frequency, the circuit
topology and design practice is a significant departure from the
current practice. For example, a complicated transformer
structure is broken down into a structure of three simple
transformers that can be easily implemented using a form of fourlayer printed-circuit-board (PCB). Furthermore, these magnetic
components are integrated into a compact structure that is easily
manufacturable. By adding two additional shielding layers into
the four-layer PCB, a 20db reduction in common-mode noises is
realized over the entire frequency spectrum of interest, from 150
KHz up to 30 MHz. Two prototypes of 3kW, 48V DC/DC
converters are demonstrated with a peak efficiency of 99% and a
power density of 530 W/in3 (33 kW/L).
(a)
(b)
Fig. 1. Comparison of Data Center Power Architectures: (a) Current
Architecture with 12V Bus, and (b) Alternative Architecture with 48V
Bus.
The legacy of data center power architecture is illustrated in
Fig. 1(a), where all major processor/memory devices are
powered from a 12V bus. As shown, the i2R loss for a 12V bus
is excessive. Furthermore, the uninterruptible power supply
(UPS) is placed on the high-voltage AC side, which results in
additional power conversion stages. The new data center power
delivery architecture, as shown in Fig.1(b), is deemed to be a
great improvement, as it offers a higher-voltage (48V)
distribution bus, and eliminates the online UPS[6], [7]. For
higher reliability and higher power density, the Open Compute
Project (OCP) has proposed a 48V battery structure that matches
the power of the power supply units (PSUs). It is either directly
connected to the bus or connects through a regulated DC-DC
converter (OCP V3)[10] [10]–[13]. The benefits of this
architecture compared to the current practice [14] are:
Keywords—planar transformer, integrated magnetics,
LLC resonant converter, EMI shielding, data center, server,
and telecom power supply.
I.
INTRODUCTION
Due to its demonstrable efficiency and power density, the
LLC resonant converter has been widely utilized in server and
telecom applications as well as for low-profile power supplies
used in flat panel displays [1]–[5]. It is popular also due to its
inherent zero-voltage switching (ZVS) over the full load range
for the high-side switches, and zero-current-switching (ZCS) /
ZVS for the synchronous rectifiers (SRs). With ever-increasing
demand for higher power in the new generation of processors,
such as CPUs, GPUs and AI, the power demand at the data
center rack level has increased from 10-15 KW to 25-30KW,
with a 48V power bus at the back plane instead of the standard
12V bus [6]–[9]. This change marks a convergence between the
telecom power structure and data center infrastructures, both of
which place great emphasis on efficiency, power density and
cost.
978-1-7281-8949-9/21/$31.00 ©2021 IEEE
•
•
•
•
it saves redundant stages for the UPS;
power flows naturally;
it enables simple fixed-voltage rectifier design at the
nominal output voltage; and
it offers at least 1% higher efficiency.
On the other hand, a regulated DC-DC converter after the
battery will ensure:
•
•
that batteries share the current equally and age
similarly;
mixing old and new batteries is allowed;
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400VDC
VIN
480-720V
Cr
VIN
Tracking
40-60V
3:1
Q1
Lr
n:1:1
Lrs
40V-60V
VO
Lm
3:1
Q2
RL
L1
Lrs
LK
Cr
Lm
3:1
L2
L4
(a)
L3
3:1
(a)
4 Transformers
in one core
(b)
(b)
Fig. 2. (a) SOA Si-based 3kW Front-End Converter, (b) Silicon-based 3Phase Interleaved LLC for High Efficiency and its Magnetic Integration.
•
•
Fig. 3. (a) Proposed Floating Bus Architecture [16], (b) Core Structure of
Four Transformers into One Core, and (c) Hardware Prototype [16].
peak transient power sharing is allowed; and
it offers a fixed 48V output voltage, which is more
efficient for the power system.
II.
PRIOR WORK AND POTENTIAL IMPROVEMENTS
Over the past half a century, power conversion technologies
have evolved on many fronts, including power semiconductor
devices, high-frequency magnetic material, capacitors,
topologies, and power architectures. Many new topologies have
been developed to circumvent switching losses, resulting to
greatly improved efficiency and power density. However, the
design practice for magnetics remains essentially unchanged.
Recently, a structure of four planar transformers (based on PCB
winding structure) has been proposed [15], and has
demonstrated significantly improved power density and
manufacturability.
Figure 2(a) illustrates the state-of-the-art LLC topology for
a 400/48V converter. For the increased power level, multiple
devices have to be paralleled on the secondary side to handle the
high current demand. Two major concerns are: the termination
loss, since the termination points occurs during high di/dt and
dv/dt; and the current sharing among the four devices in parallel.
To circumvent these concerns, a two-phase interleaved LLC
converter, as well as three-phase interleaved LLC converter
were proposed, as shown in Fig. 2 (b). In the case of the threephase interleaved solution, high efficiency has been reported
[7]–[9]. However, this benefit has been offset by the increased
number of bulky magnetic components and its higher cost. Even
though the magnetics can be simplified and integrated into a
simple structure [6], [7], it is still a complicated circuit topology:
the large number of WBG devices that have been paralleled on
the primary side of the three-phase system degrade the
performance of the converter at high switching frequencies (in
the range of Mega-hertz) due to the non-negligible switching
losses of the WBG devices.
The design in [16] proposes an LLC resonant converter that
includes a matrix transformer comprised of four elemental
transformers, and which works mostly as a DCX based on a
floating bus voltage. This design passes the regulation burden of
the output voltage to power-factor correction (PFC), as shown
in Fig. 3, which enables:
• a simplified fixed-voltage rectifier design;
• natural power flow through the rectifier for faster dynamic
response;
• load-independent operation for the LLC resonant converter
with a fixed switching frequency; and
• simpler hold-up time design with a fixed gain.
Section II of this paper investigates a highly efficient
structure for AC to 48V and addresses potential issues and
improvements. Section III proposes a novel magnetic
integration for the matrix transformer with a significant
reduction in core losses, higher manufacturability, and easier
assembly. Design process considering different losses of
magnetics is demonstrated. Section IV presents experimental
results on 500-kHz, 48V, 3kW LLC converters with a peak
efficiency of 99.1% and a power density of 780 W/in3. The
summary is given in Section V.
In [16] four transformers have been integrated into one core
structure, as shown in Fig. 3, using a simple four-layer PCB. An
efficiency of 98.4% has been demonstrated with a fourfold
higher power density of 400 W/in3 as compared to the state-ofthe-art solutions. However, the tested efficiency did not meet the
targeted efficiency of higher than 99%. In the following subsections, issues and potential improvements are presented.
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where is the material conductivity, and Ae is the crosssectional area.
Fig. 5 shows the impact of core size on core loss, knowing
that the hysteresis loss density does not depend on the crosssectional area; hence the difference in core loss density for
different toroid sizes are understood to be the result of higher
eddy losses inside the core.
For the transformer design in [16], the core’s cross-sectional
area is around 450 mm2, the core loss density of which is
represented by the green line in Fig. 4; this green line is 150%
of the core loss density based on the datasheet data, and hence
50% more core losses are included and un-accounted for. Fig. 5
shows a 3D simulation of half the structure proposed in [16],
namely two transformers out of the four-transformers structure,
to simplify the flux path in the core and understand the eddy loss
phenomenon. Therefore, based on Faraday’s law, wherever a
flux flows, it generates an eddy current that circulates the flux,
and this phenomenon could occur in the ferrite materials, as they
are not an ideal insulator.
(a)
Hitachi: ML95s @ 500 kHz
1000
Pv
(kW/m3) 100
Fig 5 shows the flux density and current density in the crosssectional area of the core using 3D FEA Ansys Maxwell
simulation. From the aforementioned eddy loss density
equation, the eddy loss is proportional to the square of the flux
density and is proportional to the cross-sectional area; hence, to
reduce the eddy loss, additional legs are proposed at the corners
of the plate where the flux density is low. These legs would help
to re-distribute the flux in the plate (getting less flux density in
the plate) and hence reducing the plate thickness, which helps to
decrease the core losses by 30%, as shown in Fig. 6.
10
10
100
Bm (mT)
(b)
Fig. 4. Core Loss Density for Toroid with Different Sizes.
a) Eddy Loss in Ferrite Material
For low-voltage, high-current applications, the winding loss
is usually dominant compared to the core loss. For example, for
the 12V bus architecture, using a large number of output sets to
handle the current is preferred [15]. However, moving towards
the 48V architecture, the conduction loss is reduced, and the
volt-second applied to the transformer has increased by a factor
of four, which means, for the same switching frequency and
maximum flux density in the core, the transformer size is four
times bigger. Hence, the impact of the transformer size on the
core loss should be carefully considered.
In the literature, different ways have been discussed to
reduce the eddy loss; for example, using a laminated core.
However, another way to decrease the core loss is to reduce the
number of transformers, which correspondingly reduces the core
size and loss at the expense of increased winding loss. Therefore,
reducing the number of transformers with better magnetic
integration will be considered in section III.
The data sheets for most ferrite materials are based on the
testing results of a small toroid core, which may be 10 times
smaller than the actual transformer used for certain applications.
Therefore, for these small-sized toroid, the only dominant loss
inside the core is the hysteresis loss [17], which is not
proportional to the core cross-sectional area, as follows:
,
where
and
are the steinmetz coefficients, Bm is the
maximum flux density and f is the switching frequency.
However, there is an eddy loss [18] inside the ferrite
material, which could dominate the core loss density for larger
cores, as it is directly proportional to the cross-sectional area, as
follows:
,
Fig. 5. Proposed Improvement for the Four-Transformers Core Structure.
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Shielding
C2
C1
C2
Pri.
Core Leg
Sec.
Sec.
Shielding
Pri.
Pri.
Pri.
Shielding
Shielding
Sec.
C2
C1
C2
Sec.
Pri. GND
Pri. GND
(a)
Fig. 6. 3D FEA Simulation of four-transformers Structure [16] with
cross-sectional views of flux density and current density.
b) Parasitic Capacitance
In addition to the simplicity and cost-effectiveness of the
PCB winding’s planar magnetics, and with the increased
demand for higher power and current levels, PCB windings
with more layers and a larger area are required to handle the
current and to perform good thermal management; however, the
PCB winding will suffer from high interwinding capacitance.
With the high dv/dt and di/dt, the interwinding capacitance
could be detrimental in some cases, causing high losses [19]
and high parasitic ringing, both of which will negatively impact
the electro-magnetic interference (EMI) performance of the
converter, as shown in Fig. 4 [16]. Fig. 4(a) shows the
transformer winding in addition to the shielding layers. Due to
the sizable overlapping area between the layers, a large parasitic
capacitance has been created that can be split into two different
caps. The first cap (C1) is between the primary layers (layers 3
and 4), and the second cap (C2) is created by the primary layers
with the shielding layers.
The impact of these parasitic caps is shown in Fig. 4 (b), in
which part of the magnetizing current is used to charge and
discharge C1 and C2, thus reducing the amount of magnetizing
current that is utilized to achieve ZVS and causing a current dip
in the primary-side resonant current during the commutation
time, as shown in Fig. 4(c). Hence, a larger magnetizing current
is required to achieve ZVS, meaning higher turn-off current
and higher turn-off loss as well.
Different methods for reducing the interwinding
capacitance should be considered in the design. Two methods
are implemented -- the first of these increases the thickness of
the insulation layers. The second method is to cut out the parts
of the winding that do not carry current or that have small
current density, as shown in Fig. 4 (d). Applying these two
methods achieves a 60% reduction in the interwinding
capacitance.
(b)
(c)
(d)
Fig. 7. (a) PCB Winding Arrangement [16], (b) The Paths Generated by
The Parasitic Capacitances C1 and C2, (c) Keywaveforms for Gen. 1[16],
and (d) The Proposed Improved Winding Shape for Gen.2.
structures, interleaved vias are used to connect the CPU to the
motherboard to minimize the parasitic inductances and their
related loss. The same concept is implemented here to
interleave the secondary-side termination, as shown in the 3D
FEA simulations in Fig. 5 (a), which illustrate a huge reduction
c) Parasitic Inductance
At high current levels, the termination loss cannot be
neglected, due to its significant impact on both the conduction
loss and the parasitic inductances. For example, in the CPU
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99.5
Efficiency (%)
Target peak efficiency
99
98.5
0.25%↑
98
97.5
97
0.9%↑
96.5
Gen.2 [This Work]
Gen.1 [16]
96
0
0.5
1
1.5
2
2.5
3
Output Power (kW)
(a)
(a)
(b)
Fig. 8. Termination Impact and Proposed Improvments, (a) Secondary
Side, (b) Primary Side
(b)
in termination loss as well as significant reduction in leakage
flux.
Even though the primary-side current is smaller than the
secondary side due to the large turns-ratio and thus the parasitic
inductance will not introduce a significant loss. However, larger
parasitic inductance may cause ringing during the commutation
process and slow down the commutation process, causing
higher switching losses, especially at high switching
frequencies.
Fig. 5 (b) shows the difference between a non-interleaved
and interleaved termination on the primary side. In the previous
generation, Q1 and Q4 were located physically side by side,
which makes the termination loop long and non-interleaved. In
this work, Q1 and Q4 are located back-to-back, Q1 on the top
layer and Q4 on the bottom layer beneath Q1, hence a smaller
interleaving can be achieved, as shown in Fig. 5 (b). The
proposed layout achieves 60% reduction in the leakage flux and
reduces the parasitic inductance by 40%.
An improved version has been built based on the
aforementioned improvements. Fig. 9 (a) shows the tested
efficiency comparison, and Fig. 9(b) shows the loss breakdown
at full load, which demonstrates the areas that have been
improved. However, this tested efficiency does not meet our
target of 99%.
Notice that the efficiency curve is almost flat at load levels
higher than 30%. In addition, Fig. 9 shows that the core loss and
the SIC switching loss, which are load-independent, are the
largest loss, second only to the SR conduction loss. However,
Fig. 9. Testing Results Comparions: Gen.1 [16] in Red Color and Gen.2
[This Work] in Blue Color.
these losses will be dominant from light load to around 70%
load. Based on these observations, there is room for the tradeoff between load-independent losses, like core loss and
switching losses, and load-dependent losses, like device
conduction loss and transformer winding loss. In the next
section, a novel magnetic integration is proposed that reduces
core losses.
III.
PROPOSED MAGNETIC INTEGRATION AND DESIGN FOR
PLANAR MATRIX TRANSFORMER
To reduce the load-independent loss components, first the
primary-side configurations will be evaluated. Secondly, to
reduce the core losses, a matrix transformer comprised of two
or three elemental transformers can be used, but this will be at
the expense of increased winding losses. Based on the
recommended current rating for each SR device (80V EPC GaN
2029) and to ensure good thermal management, at least three
SRs are required to handle the high output current. Hence, in
case of the two-transformer structure, parallel SRs must be
used; these add higher termination losses due to the parallel
connection. In this paper, a matrix transformer with three
elemental transformers, as shown in Fig. 10, is considered, as it
offers better magnetic integration.
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Half-Bridge
Full-Bridge
4:1
2:1
2:1
4:1
Sec1
Shield
Pri1
Pri2
Shield
Sec2
2:1
4:1
LK
Side View
LK
Lm
Cr
Lm
Cr
2:1
4:1
Bm in the plates = 0.5Bm in the posts
(a)
(a)
(b)
(b)
(c)
Fig. 11. Proposed Magnetic Integration of the Three-Transformer
Structure, (a) Side View, (a) 3D View, (a) Flux Density and Current
Density in The Highlighted Cross-Section of The Plate in the 3D View.
light loads, and will also reduce the cost of the converter by
using half the number of devices as well as improving the power
density because of the footprint savings. Hence, use of the half
bridge will achieve the three design objectives of high
efficiency, high density, and lower price in comparison with the
full bridge. On the other hand, the half-bridge reduces the turns
ratio from 12:1 to 6:1 which in turn reduces the winding area
and thus reduces the interwinding capacitance as well.
(c)
Fig. 10. (a) Circuit Diagram of Proposed Three-Transformer Structure,
(b) Primary-Side Device Loss Comparison: Full-Bridge vs. Half-Bridge,
and (c) Proposed Thermal Mangament to Cool Down the SiC MOSFETs.
However, for the half bridge, the losses are shared between
two devices as compared to among four devices in the case of
the full bridge, and therefore the device temperature will be
higher, especially at heavy-load conditions. Several cooling
options can be used to absorb the heat of the device, for example
adding a heat sink. As this paper is targeting solutions that offer
a high density with a low profile, thermal pads can be embedded
into the PCB and then connected to the thermal vias in order to
cool down the devices, as shown in Fig. 10(c), to allow for
vertical and horizontal heat dissipation.
a) Primary-Side Configuation
Using WBG devices with ZVS turn-on enables highfrequency operation; therefore, the switching loss will split into
turn-off losses and driving losses, which are very small
compared to those in the silicon devices. However, these
switching losses cannot be neglected, and this consideration
plays an important role in converter design. Fig. 10 compares
the primary-side device losses of a full-bridge versus half-bridge
topology.
! "# $# % ! &
'' % (
)*
b) A Novel Magnetic Integration
In this section, a novel PCB-based planar-integrated
magnetic structure is proposed and is shown to be suitable for
integration with three transformers, as shown in Fig. 11.
+
It clear that from light load to 70% load, the half-bridge has
lower losses than the full-bridge, which emphasizes the
importance of considering the switching loss for the WBG
devices, especially at high switching frequencies. Hence
choosing the half bridge will improve efficiency, especially at
In the proposed structure, the flux directions are alternating
in the adjacent legs, which ensures a more uniform flux
distribution. When compared to other matrix transformer
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structures, the flux density in the plates is half the flux density
in the legs. This helps to:
volt-second being applied to the transformer, and hence a small
core size. As mentioned previously, for small core sizes, the
hysteresis loss is dominant, and the eddy loss can be neglected.
Yet for the 48V applications, the core size is at least four times
bigger, and thus the eddy loss cannot be neglected.
• reduce the thickness of the plates for low profile and highpower density;
• Cut the plates’ thicknesses to half which will reduce the eddy
loss inside the core by >50% as compared to that shown in
Fig. 6;
• Simplify the assembly process which can now be automated
to reduce the cost, this is accomplished by designing the
outer leg with zero gap; and
• Confine the leakage flux in the core and reduce the radiated
EMI.
Therefore, a 3D-FEA eddy simulation using Ansys Maxwell
is utilized to calculate the core losses, including both hysteresis
loss and eddy loss. In addition, the FEA method can account for
non-uniform flux distribution in the core as shown in Fig. 13.
However, eddy simulation uses sinusoidal excitation to
compensate for the rectangular excitation applied to the
transformer in the case of the LLC converter; the following
compensation factor has been proposed and verified in [21]:
The proposed structure also produces better current
distribution in its PCB windings because of its:
core loss r, c(
• simple structure of one turn per layer for all the layers, and
• symmetry of the winding structure as the core covers all the
windings symmetrically, which ensures similar Magnetic
Motive Force (MMF) distribution of the 360oC along the
PCB winding layers.
c)
3
456789
)
8
!
;
<
456789 .
A 2D FEA simulation has been used to determine the
winding loss, as follows:
P?@ABCDE@FG@ r, c(
core loss r, c( ! windig loss r, c(.
And then the footprint can be calculated as follows:
Choosing the Ferrite Material
footprint r, c(
To improve current practices, several efforts have been made
and a design optimization procedure has been developed in [15].
The first step is to search for better high-frequency magnetic
materials. Using the core loss measurement techniques in [17]
and [20], different magnetic materials suitable for this
application are tested, and core loss measurement results under
500 kHz excitation are shown in Fig. 12. Among them, ML95s
is selected for the following analysis since it has the lowest core
loss.
L ) W.
Fig. 13 shows the dimension of the proposed structure:
there are two design variables, the core radius r, and the winding
width c. The plate thickness is determined to make the flux
density in the plates equal to the flux density in the posts, such
that:
ℎSTU
;V
.
2X
For the side posts, the cross-sectional area is chosen to
ensure the that flux density in the side posts will be equal to that
in the middle posts.
d) Calculating Core and Winding Losses
The next step to get an accurate loss model for predicting
the different losses in the transformer. An analytical core loss
model has been proposed in [21], which accounts only for the
hysteresis loss. It has demonstrated good accuracy in different
applications and magnetic structures [15], [22]; however, these
structures have low levels of output voltage, leading to a small
Pv (kW/m3) @ 500 kHz
10000
P61 (ACME)
ML95s (Hitachi)
DMR51 (DMEG)
3F36 (Ferroxcube)
1000
100
10
1
10
20
30
40
50
60 70
80 90
100
Bm (mT)
Fig. 13. Magnetic Dimension and the Utilised Mesh for Core Loss
Calculations.
Fig. 12. Core Loss Measurement Results Under 500 kHz Excitation.
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10
14
18 16 14 12
16
42
3480
336
324
30
26
24
22
20
10
10
Change core structure
@ Fixed Ae and Footprint
c
r
8
c
r
Lrect
Ft=3000 mm2
6
12
16
Total
10
14
4
18
12
28
26
24
22
20
c
(mm)
14
8
Winding
2
6
7
8
9
10
11
12
13
14
4
r (mm)
2
(a)
30
Core
0
Loss (W)
0
5
10
15
20
25
Lrect (mm)
30
35
40
(a)
25
5
15
120
(mm)
c (mm)
20
4.8
105
4.6
90
4.4
75
Total
10
Winding
5
Core
0
1000
2000
3000
Footprint
4000
5000
6000
4.2
(mm2)
60
0
(b)
Fig. 14. (A) Transformer Total Loss vs. Core Radius r and Secondary
Winding width c, (b) Minimum Loss Versus Footprint
10
20
Lrect (mm)
30
40
(b)
The transformer’s total loss versus core radius r as the x-axis
and secondary winding width c as the y-axis could be plotted as
shown in Fig. 14 (a), with an output power of 3kW at 50V based
on the aforementioned core loss and winding loss models. The
numbers in the colored solid lines in Fig. 10(a) reflect complete
transformer losses with three elemental transformers, while the
black solid lines show all possible combinations of c and r for a
given footprint. The optimum design points for the given
footprint are the tangential points (marked with blue dots in Fig.
10) between the black solid lines and colored solid lines.
The minimum loss versus footprint for a matrix transformer
with round core posts is plotted in Fig. 10(b) after all the
optimum design points for a given footprint range have been
swept.
Fig. 15. Impact of Core Shape at Fixed Footpint and Core Cross-Sectional
Area (Ae) on: (a) Magnetic Loss, (b) Winding Dimensions, (c) Flux
Distribution.
The design region selected at the knee area for footprints is
2000 mm2 to 4000 mm2 and the design point is chosen at
footprint that is equal to 3000 mm2.
e)
the core’s posts from round to a rectangular shape with halfcircular ends on both sides. As the rectangular part increases, the
plate thickness reduces to keep the same cross-sectional area,
and this leads to significant reductions in both hysteresis and
eddy losses inside the core; the winding loss increase is
negligible up to Lrect = 20mm. Fig. 15 (b) shows the impact of
core shape on the winding dimensions; by changing to the
Further Reduction of Magnetic Loss
The next step for improving the design is to further reduce
the transformer loss and increase the power density without
increasing the footprint. Fig 15 (a) shows the impact of changing
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(a)
Fig. 16. 500-kHz 3-kW 48V LLC Converter Prototype.
rectangular shape, the winding length will increase, however,
the winding width will increase as well. This keeps the same
footprint, balancing the increase of the AC resistance from the
longer winding length and resulting in a slower increase in the
winding loss, as shown in Fig. 15 (a).
IV.
(b)
Efficiency (%)
EXPERIMENTAL RESULTS
100
A prototype 3KW converter is capable of operating at 500
kHz with superior efficiency and power density, as shown in
Fig. 16. Fig. 17 (a) shows the thermal performance at full load
with forced-air cooling, which demonstrates good thermal
performance and effectiveness of the embedded pads’ thermal
vias to cool down the SiC MOSFETs without requiring a heat
sink -- this helps keep a low profile. The key waveforms shown
in Fig. 16(b) illustrate the ZVS waveforms for the primary and
secondary switches, with a dramatic reduction in the parasitic
ringing as compared to those in Fig. 7(c). The tested efficiency
is shown in Fig. 17(c) with a peak efficiency of 99.06% at half
load and 98.5% at full load. It should be noted that the
efficiency is greater than 96% at very light load. The power
density is 450 W/inch3 (37 kW/L).
V.
99.1% Peak
99
0.5%↑
0.2%↑
98
1.3 %↑
97
0.9%↑
96
Gen.3 [This Work]
Gen.2 [This Work]
Gen.1 2019 [16]
95
94
0
SUMMARY AND CONCLUSION
0.5
1
1.5
Load (kW)
2
2.5
3
(c)
The GaN based 1 MHz LLC converter for data center
server applications demonstrates greatly improved power
density while maintaining high efficiency at 1KW [15], [24]. In
the present paper, the authors extend this general approach to a
3KW data center server power application, with further
improvements on two fronts. One aspect allows a floating link
voltage between the PFC and the DC/DC converter in such a
way that the LLC converter is operated essentially around the
optimum operating point, i.e., around the resonant frequency fo.
The burden of controlling the link voltage is placed upon the
front-end PFC, which meets this challenge with ease. The
second aspect is to break down the transformer into three small
transformers which, in turn, can be easily integrated using fourlayer PCB. The integrated core structure enables flux
cancellation and more uniformly distributed flux. The proposed
Fig. 17. Experimental Results: (a) Thermal Test, (b) key Waveforms, (c)
Efficiency.
prototype hardware is demonstrated with 99% efficiency and
450W/in3 power density. Furthermore, the proposed magnetic
components can be easily automated thus, eliminating the labor
expenses associated with the manufacturing and assembling
process.
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