A REPORT ON
IMPLEMENTATION OF A DELAY LOCKED LOOP ON
45nm TECHNLOGY NODE
21104097
Shubham Purohit
Submitted in fulfillment of the course
EE 698G – CIRCUIT DESIGN FOR PHASE AND FREQ. SYNTHESIS
Under the guidance of
Dr. Chithra
Indian Institute of Technology - Kanpur
May 2022
• Problem Statement:
Design of a Delay locked working on the reference frequencies of 500MHz to 600MHz
1) Constraint of VCDL: The frequency range must be met when the control node voltage
is varied from 100mV to 900mV. Ensure that this range is met for supply voltages of
950mV, 1V and 1:05V. Note that the delay range of the VCDL can be larger than the
required range. The constraint is only on meeting the required range for V c between
100mV to 900mV
2) Constraint on PFD+CP: You can assume an ideal current source of 10 uA. Ideal Dflipflops, ideal logic gates and ideal opamps can be used in the design if necessary.
The UP and DN currents and switches within the charge pump should be from the
45nm PDK library. Ideal switches are not allowed. Create symbols for the PFD and the
charge pump.
3) Overall DLL Design: Static Time Offset should be less than 100ps, so the bandwidth to
be chosen must be suitable according to it.
• Design Approach and Schematic:
1) Schematic:
Voltage controlled Delay Unit (VCDU):
The VCDU design is based on tuning by variable resistance (current-starved
inverter) topology. (vc) is control node voltage and (vcbar) is the voltage which is
generated using bias generator (shown below).
Sizing in Bias generator:
Sizing of the transistors in bias generator is done such that the overdrive voltage
across each transistor is minimum and for the corresponding vc we get vcbar to have
accurate working of the VCDU, hence the W/L is chosen 100 for NMOS and 200 for
PMOS in bias generator.
Sizing in the VCDU:
In our architecture of VCDU, we have added weak PMOS and NMOS current source
in charging and discharging paths so that at the extreme values of control node
voltage we don’t have very high propagation delays.
Weak current sources are design with a low W/L, of 2 (for NMOS) and just a greater
than 3 (for PMOS). The rest of the transistors in the inverter were earlier chosen to
be minimum but later arbitrarily tweaked to achieve the required delay range
between 100mV and 900mV at all possible supply voltages. Two inverters are then
connected in cascade to get a VCDU.
(Except the weak current sources everywhere we have taken W/L of PMOS to be 2x
to that of NMOS)
VCDL Schematic:
The VCDL is comprised of 6 VCDU stages, and it meets our delay requirements.
Earlier the stages in the VCDL were 12 but that created the problem of harmonic
locking and to avoid that we reduced the stages to 6.
VCDL Symbol:
VCDL is made of 6 VCDUs to get the delay range such that our required range of
delays we need lie well within the characteristics of the VCDL so that any PVT
variations doesn’t cause delay to get affected.
The data of the propagation delay from high to low was recorded and taken in a
separate excel file for computing in MATLAB.
Simulation was done at three possible supplies of 0.95V, 1V, and 1.05V. As supply
increases, propagation delay decreases. And this was evident from our VCDL
characteristics curve:
(PLOT-1)
This curve of propagation delay (t_plh) from low to high also describes that our DLL
will never be in harmonic locking nor stuck locking.
Also, the Kdl was also calculated by the fact that it is the gain of the VCDL delay w.r.t
control node voltage Vc:
𝐾𝑑𝑙 = 𝜕(𝑇𝑝)/𝜕(𝑉𝑐)
Since we are incrementing vc by 20mV and Tp is the propagation we have
calculated at each step.
Kdl vs Vc voltage curve is as shown which we got from the MATLAB:
Kdl curve is coming distorted because we have taken 20mV step size and it is
discrete and not continuous (PLOT-2)
Schematic of working VCDL at 1V:
In the schematic I have used the input frequency of 500MHz just to characterize the
working of the VCDL because it is one of the input frequency with which we will work.
(Similarly in the schematics attached in the folder also contained the VCDL working
at supply of 0.95V and 1.05V)
Power Dissipation across VCDL as function of Control node voltage Vc at supply
voltage of 1V:
(we can see that as Vc increases we have power across DLL keeps on increasing,
and for finding the DLL’s power consumption at VDD=1V we have considered 5 time
periods and averaged the power over it to get Pavg consumption)
(Plot-3)
Charge Pump + PFD Design:
The PFD has been designed as shown with the help of D-FlipFlops and AND gate in
connection as shown. The reset delay earlier was set to 100ps but later reduced to
50ps to have a reduction in the static phase offset.
Symbol for PFD:
(All the PFD schematics are attached)
Charge Pump:
Earlier the charge pump current was kept to minimum but due to this we have the
DLL bandwidth very low and to compensate for the Icp (charge pump current) it was
current was increased to 60uA. The current in reference branch and the middle
branch has a value of 10uA flowing through it such that they dissipate the minimum
power permissible through them.
Symbol for Charge Pump:
•
Overall Delay Locked Loop Design:
Transient Locking behavior of DLL with Vdd=1.05 V and minimum reference frequency
of 500MHz: (PLOT-4)
This is the DLL which we have designed for VDD = 1.05V and minimum reference
frequency of 500MHz.
The loop filter’s value (i.e., 1pF) is decided such that we get the minimum ripples on
control node voltage, and it also saturates within the minimum number of reference
cycles, and it doesn’t land into the unstable region because we want to ensure:
𝜔𝑢𝑙𝑜𝑜𝑝 <
To have our DLL’s operation to be healthy.
𝜔𝑟𝑒𝑓
10
It represents the complete picture of the DLL transient response.
In the steady state
(locking with an ideal buffer at the output, we can see that rising edges differ by
some static timing offset)
The maximum Static timing offset we achieved in this DLL is around: 51.36ps (it is
visualized by placing an ideal buffer at the end of output signal, to determine the
SPO)
So the DLL locks to one time period of the reference with the calculated timing offset.
(PFA Schematic of the same)
DL-Loop Bandwidth:
It is given by 𝐼𝑐𝑝 ∗ 𝐾𝑑𝑙/(2 ∗ 𝜋 ∗ 𝐶) where Kdl is gain of VCDL in radV-1 , and we have
Icp as 60uA and |Kdl| as around 7.068 rad/V (because at Vc = 336mV and Vdd =
1.05V we have Kdl as -2.25ns/V) so BW is approximately coming as 6.75*107 rad/s
and 𝜔𝑟𝑒𝑓 = 3.14*109 rad/s, hence our condition stated above gets satisfied.
Power consumption in the steady state by the DLL is:
Since Vc at steady settles at around 336mV we have its average power dissipation
of around 181.14uW.
•
Transient Locking behavior of DLL with Vdd=0.95 V and minimum reference frequency
of 600MHz: (PLOT-5)
This is the schematic of the DLL as specified above
Transient Behaviour:
Overall time behaviour of the DLL with VDD=0.95V and maximum reference of
600MHz.
In steady state the behaviour is as shown here.
(from seeing this locking it can be estimated that DLL locks to 1 time period of
600MHz reference but with a little offset, it can be computed as shown below)
The maximum Static timing offset we achieved in this DLL is around: 16.25ps
(it is visualized by placing an ideal buffer at the end of output signal, to determine the
SPO)
So the DLL locks to one time period of the reference with the calculated timing offset.
(PFA Schematic of the same)
DL-Loop Bandwidth:
It is given by 𝐼𝑐𝑝 ∗ 𝐾𝑑𝑙/(2 ∗ 𝜋 ∗ 𝐶) where Kdl is gain of VCDL in radV-1 , and we have
Icp as 60uA and |Kdl| as around 15.4 rad/V (because for the supply of 0.95V and Vc
= 463mV we have Kdl as -4.08ns/V) so BW is approximately coming as 1.47*108
rad/s and 𝜔𝑟𝑒𝑓 = 3.77*109 rad/s, hence our condition stated above gets satisfied.
Power consumption in the steady state by the DLL is:
Since Vc at steady settles at around 463mV we have its average power dissipation
of around 159.44uW.