Logic Circuits and
Microprocessors
(EEC 146)
Instructor
Dr. Hossam Kotb
Assistant Professor
Electrical Engineering Department
Faculty of Engineering
Text Book
“Digital Fundamentals”,
Floyd, Tenth Edition.
Digital
Fundamentals
Tenth Edition
Floyd
Chapter
Floyd, Digital Fundamentals, 10th ed
3/4/5
2008 Pearson
Education
© 2009 Pearson Education,©Upper
Saddle River,
NJ 07458. All Rights Reserved
Objectives
At the end of this topic you will be able to;
• Analyze logic circuits
• Convert between the following:
– Logic Circuit
– Truth table
– Boolean Expression
• Design logic circuits for practical applications
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Introduction
OFF` V1 OFF`
ON
ON
OFF
ON
V2
B
Mixer
OFF
ON
A
A
B
V1
V2
Mixer
0
OFF
LOW
0
OFF
LOW
0
OFF
LOW
1
ON
HIGH
1
ON
HIGH
X
0
OFF
LOW
X
0
OFF
LOW
X
1
ON
HIGH
1
ON
HIGH
0
OFF
LOW
1
ON
HIGH
0
OFF
LOW
0
OFF
LOW
1
ON
HIGH
0
OFF
LOW
0
OFF
LOW
1
ON
HIGH
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Binary Digits and Logic Levels
Digital electronics uses circuits that have two states, which
are represented by two different voltage levels called HIGH
and LOW. The voltages represent numbers in the binary
system.
VH(max)
In binary, a single number is
called a bit (for binary digit). A
bit can have the value of either
a 0 or a 1, depending on if the
voltage is HIGH or LOW.
HIGH
VH(min)
Invalid
VL(max)
LOW
VL(min)
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
LOGIC GATES
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The Inverter
A
X
The inverter performs the Boolean NOT operation. When the
input is LOW, the output is HIGH; when the input is HIGH,
the output is LOW.
Input
Output
A
X
LOW (0) HIGH (1)
HIGH (1) LOW(0)
The NOT operation (complement) is shown with an overbar.
Thus, the Boolean expression for an inverter is X = A.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The Inverter
A
X
Example waveforms:
A
X
A group of inverters can be used to form the 1’s complement
of a binary number:
Binary number
Floyd, Digital Fundamentals, 10th ed
1
0
0
0
1
1
0
1
1
0
1
1
0
0
1’s complement
1
0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The AND Gate
A
X
A
B
B
&
X
The AND gate produces a HIGH output when all inputs are
HIGH; otherwise, the output is LOW. For a 2-input gate,
the truth table is
Inputs Output
A
B
X
0
0
1
1
0
1
0
1
0
0
0
1
The AND operation is usually shown with a dot between the
variables but it may be implied (no dot). Thus, the AND
operation is written as X = A .B or X = AB.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The AND Gate
A
B
X
A
B
&
X
Example waveforms:
A
B
X
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The AND Gate
A
B
C
X
The AND gate produces a HIGH output when all inputs are
HIGH; otherwise, the output is LOW. For a 3-input gate,
the truth table is
A B C X
Floyd, Digital Fundamentals, 10th ed
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The AND Gate
A
B
C
X
The AND gate produces a HIGH output when all inputs are
HIGH; otherwise, the output is LOW. For a 3-input gate,
the truth table is
A B C X
Floyd, Digital Fundamentals, 10th ed
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The AND Gate
Floyd, Digital Fundamentals, 10th ed
A
B
C
X
A
B
C
X
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The AND Gate
Floyd, Digital Fundamentals,
10th
ed
A
B
C
D
X
A
B
C
D
X
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
OFF`
ON
ON
A
B
V1
V2
Mixer
0
0
1
0
0
0
1
X=0
X=0
X=0
1
0
0
1
0
1
1
0
0
1
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
OFF`
ON
A
ON
V1
B
A
A
V2
Mixer
B
B
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Steps of design
OFF`
ON
ON
1-Process
2-Truth table
A
B
V1
V2
Mixer
0
0
1
0
0
0
1
X
X
X
1
0
0
1
0
1
1
0
0
1
Floyd, Digital Fundamentals, 10th ed
4- Expression
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
OFF`
ON
ON
5- Logic Circuits
A
V1
B
A
A
V2
Mixer
B
B
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Steps of design
1- Process.
2- Truth table.
3- Reduction. (Lecture 2 and 3)
4- Expression.
5- Logic Circuits.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The OR Gate
A
B
X
A
B
≥1
X
The OR gate produces a HIGH output if any input is HIGH;
if all inputs are LOW, the output is LOW. For a 2-input gate,
the truth table is
Inputs Output
A
B
X
0
0
1
1
0
1
0
1
0
1
1
1
The OR operation is shown with a plus sign (+) between the
variables. Thus, the OR operation is written as X = A + B.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The OR Gate
A
B
X
A
B
≥1
X
Example waveforms:
A
B
X
The OR operation can be used in computer programming to set certain
bits of a binary number to 1.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The OR Gate
Floyd, Digital Fundamentals, 10th ed
A
B
C
X
A
B
C
X
0
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The OR Gate
Floyd, Digital Fundamentals, 10th ed
A
X
B
C
A
B
C
X
0
0
0
1
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The OR Gate
Floyd, Digital Fundamentals,
10th
ed
A
B
C
D
X
A
B
C
D
X
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
0
0
1
0
LOGIC CIRCUIT; TRUTH TABLE;
BOOLEAN EXPRESSION
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Combinational Logic Circuits
An example of an SOP (Sum Of Product) implementation is
shown. The SOP expression is an AND-OR combination of
the input variables and the appropriate complements.
A
B
C
y
w
D
B
Floyd, Digital Fundamentals, 10th ed
z
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A
B
C
y=ABC=110x
W=y+z
D
B
z=BD=x1x0
Floyd, Digital Fundamentals, 10th ed
A
B
C
D
y
Z
w
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
1
1
0
1
0
1
0
0
0
0
1
1
0
0
11
1
0
1
1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
1
0
1
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
0
1 11
110
0 11
1
0
0
0
1
1
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A
B
C
D
Z
Z1
Z2
Z3
Z4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
0
0
1
0
0
1
0
1
1
0
1
0
0
0
0
0
1
1
1
0
1
0
0
0
1
1
1
1
1
0
0
0
0
0
Floyd, Digital Fundamentals, 10th ed
Z=Z1.Z2.Z3.Z4
Z=Z1+Z2+Z3+Z4
Z1
=A B C D
+
Z2
=A B C D
+
Z3
Z4
z
=A B C D
+
=A B C D
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
A
B
C
D
Z
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0 1 0 0 1
0
1
0
1
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1 1 0 0 1
1
0
1
1
1
1
ABCD
0100 =A B C D
+
ABCD
0
1 1 1 0 1
1
ABCD
0
0 1 1 0 1
1
Summary
ABCD
0
Floyd, Digital Fundamentals, 10th ed
0110 =A B C D
+
z
1100 =A B C D
+
1110 =A B C D
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A
B
C
D
y
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
ABCD
+
y
ABCD
1 1 0 0 1
1 1 0 1
ABCD
1 ABCD
1
1
1
0
0
1
1
1
1
0
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
1100 =A B C D
+
y
1101 =A B C D
0100 =A B C D
+
0110 =A B C D
+
1100 =A B C D
+
1110 =A B C D
Floyd, Digital Fundamentals, 10th ed
z
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
y1
y
y2
z1
z2
z
z3
z4
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
An example of an POS implementation is shown. The POS expression is
an OR-AND combination of the input variables and the appropriate
complements.
A B C D y Z w
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
1
0
1
1
1
0
0
1
1
1
1
1
0
1
0
0
0
0
1
0
1
0
1
1
0
1
1
0
0
0 00
00 1
1 0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
00
0
1
1
0
1
1
1
1
1
1
1
0
1
00
0
1
1
1
1
1
1
1
Floyd, Digital Fundamentals, 10th ed
0
0
W=(A + B + C)(B + D)
y
010x
z
x1x0
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A
B
C
D
y
Y1
Y2
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
1
0
1
1
1
0
0
1
1
1
1
1
0 1 0 0 0
0
1
0 1 0 1 0
1
0
0
1
1
0
1
1
1
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
Floyd, Digital Fundamentals, 10th ed
Y=Y1.Y2
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A
B
C
D
y
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0 1 0 0 0 A+B+C+D
0 1 0 1 0 A+B+C+D
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
Floyd, Digital Fundamentals, 10th ed
0100 =(A +B+ C+ D)
.
y
0101 =(A +B +C+ D)
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A
B
C
D
Z
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0 1 0 0 0
0
1
0
1
1
0 1 1 0 0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1 1 0 0 0
1
1
0
1
1
1
1
A+B+C+D
0100 =A +B+ C+ D
.
0110 =A+ B+C +D
.
A+B+C+D
z
1100 =A +B +C+ D
.
1
1 1 1 0 0
1
A+B+C+D
A+B+C+D
1
Floyd, Digital Fundamentals, 10th ed
1110 =A +B +C+ D
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
A
B
C
D
0100 =(A +B+ C+ D)
.
y
A
B
C
D
0101 =(A +B +C+ D)
0100 =A +B+ C+ D
.
0110 =A+ B+C +D
.
1100 =A +B +C+ D
.
1110 =A +B +C+ D
Floyd, Digital Fundamentals, 10th ed
z
y1
y1
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
z1
z2
z3
z4
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Fixed Function Logic
Two major fixed function logic families are TTL and CMOS.
A third technology is BiCMOS, which combines the first
two. Packaging for fixed function logic is shown.
0.335 – 0.334 in.
0.740 – 0.770 in.
14 13 12 11 10 9
14 13 12 11 10
2
3
4
5
6
6
7
0.228 – 0.244 in.
7
1
Pin no.1
identifiers
8
8
0.250 ± 0.010 in.
1
9
2
3
4
5
Lead no.1
identifier
14
1
14
1
DIP package
Floyd, Digital Fundamentals, 10th ed
SOIC package
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Fixed Function Logic
Some common gate configurations are shown.
VCC
VCC
14 13 12 11 10 9
1
2
3
4
5
6
8
7
GND
VCC
14 13 12 11 10 9
1
2
3
'00
6
7
GND
2
3
4
5
6
8
7
GND
1
2
3
4
5
6
8
7
GND
5
6
8
7
GND
'27
Floyd, Digital Fundamentals, 10th ed
5
6
7
GND
2
3
4
'30
1
2
3
5
6
8
7
GND
2
3
4
5
6
6
7
GND
8
7
GND
14 13 12 11 10 9
1
2
3
4
5
6
8
7
GND
'21
VCC
14 13 12 11 10 9
1
5
VCC
14 13 12 11 10 9
1
4
8
'08
VCC
14 13 12 11 10 9
1
4
14 13 12 11 10 9
'20
VCC
14 13 12 11 10 9
4
3
'11
VCC
3
2
VCC
14 13 12 11 10 9
'10
2
1
8
'04
VCC
14 13 12 11 10 9
1
5
VCC
14 13 12 11 10 9
' 02
VCC
1
4
8
2
3
4
'32
5
6
8
7
GND
14 13 12 11 10 9
1
2
3
4
5
6
8
7
GND
'86
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Fixed Function Logic
Logic symbols show the gates and associated pin numbers.
VCC
(14)
(1)
(3)
(2)
(4)
(6)
(5)
(9)
(8)
(10)
(12)
(11)
(13)
(1)
(2)
(4)
(5)
(9)
(10)
(12)
(13)
&
(3)
(6)
(8)
(11)
(7)
GND
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
Fixed Function Logic
Data sheets include limits and conditions set by the
manufacturer as well as DC and AC characteristics. For
example, some maximum ratings for a 74HC00A are:
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0 V
V
V in
DC InputVoltage (Referenced to GND)
– 0.5 to VCC +0.5 V V
V out DC Output Voltage (Referenced to GND)
– 0.5 to VCC +0.5 V V
I in
DC Input Current, per pin
± 20
mA
Iout
DC Output Current, per pin
± 25
mA
ICC DC Supply Current, VCC and GND pins
± 50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP †
750
mW
500
SOIC Package †
TSSOP Package †
450
Tstg Storage Temperature
–65 to + 150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
°C
260
Plastic DIP, SOIC, or TSSOP Package
300
Ceramic DIP
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The NAND Gate
A
A
X
&
X
B
B
The NAND gate produces a LOW output when all inputs
are HIGH; otherwise, the output is HIGH. For a 2-input
gate, the truth table is
Inputs Output
A
B
X
0
0
1
1
0
1
0
1
1
1
1
0
The NAND operation is shown with a dot between the
variables and an overbar covering them. Thus, the NAND
operation is written as X = A .B (Alternatively, X = AB.)
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The NAND Gate
A
B
X
A
&
X
B
Example waveforms:
A
B
X
The NAND gate is particularly useful because it is a
“universal” gate – all other basic gates can be constructed
from NAND gates.
How would you connect a 2-input NAND gate
to form a basic inverter?
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The NOR Gate
A
B
X
A
B
≥1
X
The NOR gate produces a LOW output if any input is
HIGH; if all inputs are HIGH, the output is LOW. For a
2-input gate, the truth table is
Inputs
Output
A
B
X
0
0
1
1
0
1
0
1
1
0
0
0
The NOR operation is shown with a plus sign (+) between
the variables and an overbar covering them. Thus, the NOR
operation is written as X = A + B.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The NOR Gate
A
B
X
A
B
≥1
X
Example waveforms:
A
B
X
The NOR operation will produce a LOW if any input is HIGH.
+5.0 V
When is the LED is ON for the circuit shown?
The LED will be on when any of
the four inputs are HIGH.
Floyd, Digital Fundamentals, 10th ed
A
B
C
D
330 W
X
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The XOR Gate
A
B
X
A
B
=1
X
The XOR gate produces a HIGH output only when both
inputs are at opposite logic levels. The truth table is
Inputs
Output
A
B
X
0
0
1
1
0
1
0
1
0
1
1
0
The XOR operation is written as X = AB + AB.
Alternatively, it can be written with a circled plus sign
between the variables as X = A + B.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The XOR Gate
A
B
X
A
B
=1
X
Example waveforms:
A
B
X
Notice that the XOR gate will produce a HIGH only when exactly one
input is HIGH.
If the A and B waveforms are both inverted for the above
waveforms, how is the output affected?
There is no change in the output.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The XNOR Gate
A
B
X
A
B
=1
X
The XNOR gate produces a HIGH output only when both
inputs are at the same logic level. The truth table is
Inputs
Output
A
B
X
0
0
1
1
0
1
0
1
1
0
0
1
The XNOR operation shown as X = AB + AB. Alternatively,
the XNOR operation can be shown with a circled dot
between the variables. Thus, it can be shown as X = A . B.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Summary
The XNOR Gate
A
B
X
A
B
=1
X
Example waveforms:
A
B
X
Notice that the XNOR gate will produce a HIGH when both inputs are the
same. This makes it useful for comparison functions.
If the A waveform is inverted but B remains the same, how is
the output affected?
The output will be inverted.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Gate
NOT
Symbol
A
AND
A
OR
A
B
NAND
NOR
A
EXOR
A
Floyd, Digital Fundamentals, 10th ed
QA
Q
Q
B
A
EXNOR
Boolean Equation
B
B
A
B
Q
Q  A.B
Q  A B
Q
Q  A.B
Q
Q  A B
Q
Q  A  B or
Q  A.B  A.B
Q
Q  A  B or
Q  A.B  A.B
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Example1
• A warning light is to be placed on a skip at
night to warn any approaching drivers that
there is a hazard in the road. The light
should only operate in the dark and the
light should be flashing.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
• In any problem of this nature the first stage
is to identify the type of inputs needed to
convert external factors e.g. light or
temperature into an electrical signal that
can be processed to perform the function
required in the design brief. In our problem
two input systems are required, a light
sensor and a pulse generator.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
we will assume the following :
• The light sensor produces a logic 1 in the
dark, and Logic 0 in daylight.
• The pulse generator will be producing a
continuous series of on / off or Logic 1 /
Logic 0 pulses as soon as the power is
switched on.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
Light
Sensor (A)
Logic
System
Warning
Lamp (Q)
Pulse
Generator (B)
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
Input
B
0
0
1
1
Input
A
0
1
0
1
Floyd, Digital Fundamentals, 10th ed
Output
Q
Comments
0
Light Sensor (A) = 0 = Daylight,
Pulse Generator (B) = 0 = Off,
Output (Q) Off
0
Light Sensor (A) = 1 = Dark, Pulse
Generator (B) = 0 = Off, Output
(Q) Off
0
Light Sensor (A) = 0 = Daylight,
Pulse Generator (B) = 1 = On,
Output (Q) Off
1
Light Sensor (A) = 0 = Dark, Pulse
Generator (B) = 1 = On, Output (Q)
On
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
Light
Sensor (A)
A
B
Q
Warning
Lamp (Q)
Pulse
Generator (B)
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
• let us reconsider this problem again with a
different specification for the Light sensor.
What if this had been given as follows:
• The light sensor produces a logic 0 in the
dark, and Logic 1 in daylight.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
Input
B
0
0
1
1
Input
A
0
1
0
1
Floyd, Digital Fundamentals, 10th ed
Output
Q
Comments
0
Light Sensor (A) = 0 = Dark,
Pulse Generator (B) = 0 = Off,
Output (Q) Off
0
Light Sensor (A) = 1 = Daylight,
Pulse Generator (B) = 0 = Off,
Output (Q) Off
1
Light Sensor (A) = 0 = Dark,
Pulse Generator (B) = 1 = On,
Output (Q) On
0
Light Sensor (A) = 0 = Daylight,
Pulse Generator (B) = 1 = On,
Output (Q) Off
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
Q  A.B
Light
Sensor (A)
A
A
A
B
Q
Warning
Lamp (Q)
Pulse
Generator
(B)
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Problem 2
• A market gardener wants to install an
automatic watering system for his green
houses to ensure that his prizewinning
plants do not suffer from a lack of water.
The system however, must have some
safeguards whereby plants should only be
watered in daylight, when the soil is dry
and the door to the greenhouse is closed.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
The following sensors are available:
•
A moisture sensor (A) which outputs a
Logic 0 when dry, and Logic 1 when wet.
•
A light sensor (B) which outputs a
Logic 1 in daylight, and Logic 0 at night.
•
A door switch (C) which outputs a Logic
0 when closed and Logic 1 when open.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
Moisture
Sensor (A)
Light Sensor
(B)
Logic
System
Water
On (Q)
Door Sensor
(C)
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
Input
C
Input
B
Input
A
Output
Q
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Floyd, Digital Fundamentals, 10th ed
Comments
Moisture Sensor (A) = 0 = Dry,
Light Sensor (B) = 0 = Night,
Door Sensor (C) = 0 = Closed,
Output (Q) = Off
Moisture Sensor (A) = 1 = Wet,
Light Sensor (B) = 0 = Night,
Door Sensor (C) = 0 = Closed,
Output (Q) = Off
Moisture Sensor (A) = 0 = Dry,
Light Sensor (B) = 1 = Daylight,
Door Sensor (C) = 0 = Closed,
Output (Q) = On
Moisture Sensor (A) = 1 = Wet,
Light Sensor (B) = 1 = Daylight,
Door Sensor (C) = 0 = Closed,
Output (Q) = Off
Moisture Sensor (A) = 0 = Dry,
Light Sensor (B) = 0 = Night,
Door Sensor (C) = 1 = Open,
Output (Q) = Off
Moisture Sensor (A) = 1 = Wet,
Light Sensor (B) = 0 = Night,
Door Sensor (C) = 1 = Open,
Output (Q) = Off
Moisture Sensor (A) = 0 = Dry,
Light Sensor (B) = 1 = Daylight,
Door Sensor (C) = 1 = Open,
Output (Q) = Off
Moisture Sensor (A) = 1 = Wet,
Light Sensor (B) = 1 = Daylight,
Door Sensor (C) = 1 = Open,
© 2009 Pearson
OutputEducation,
(Q) = OffUpper Saddle River, NJ 07458. All Rights Reserved
0
1
0
0
0
0
0
Solution
Moisture
Sensor (A)
Light
Sensor (B)
Q  A.B.C
Water
On (Q)
Door
Sensor (C)
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
An alternative design that does the same thing can be
formed if only two input AND gates are available, by
combining two such units together as shown below:
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
Q  A.B.C
Moisture
Sensor (A)
Light
Sensor (B)
Water
On (Q)
Door
Sensor (C)
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Problem 3
• An expensive painting in an art gallery is
protected by a modest security system.
The picture is protected by a pressure
switch which is normally closed when the
picture is in place, but opens if the picture
is removed from the wall. If the picture is
removed for cleaning (door sensor should
be locked in this case) , and the alarm
should not sound during this period.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Problem 3
The specification for the available sensors are as
follows:
•
Picture Pressure sensor (A) which outputs a
Logic 0 when picture is in place, and Logic 1
when the picture is removed.
•
A light sensor (B) which outputs a Logic 0
during the day, and Logic 1 at night.
•
A door switch (C) which outputs a Logic 0
when locked and Logic 1 when unlocked.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
Input
C
Input
B
Input
A
Output
Q
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
Floyd, Digital Fundamentals, 10th ed
Comments
Pressure Sensor (A) = 0 = Picture Present,
Light Sensor (B) = 0 = Daytime,
Door Sensor (C) = 0 = Locked,
Output (Q) = Off
Pressure Sensor (A) = 1 = Picture Missing,
Light Sensor (B) = 0 = Daytime,
Door Sensor (C) = 0 = Locked,
Output (Q) = Off (Cleaning in progress)
Pressure Sensor (A) = 0 = Picture Present,
Light Sensor (B) = 1 = Night-time,
Door Sensor (C) = 0 = Locked,
Output (Q) = Off
Pressure Sensor (A) = 1 = Picture Missing,
Light Sensor (B) = 1 = Night-time,
Door Sensor (C) = 0 = Locked,
Output (Q) = On
Pressure Sensor (A) = 0 = Picture Present,
Light Sensor (B) = 0 = Daytime,
Door Sensor (C) = 1 = Un-locked,
Output (Q) = Off
Pressure Sensor (A) = 1 = Picture Missing,
Light Sensor (B) = 0 = Daytime,
Door Sensor (C) = 1 = Un-locked,
Output (Q) = On
Pressure Sensor (A) = 0 = Picture Present,
Light Sensor (B) = 1 = Night-time,
Door Sensor (C) = 1 = Un-locked,
Output (Q) = Off
Pressure Sensor (A) = 1 = Picture Missing,
Light Sensor (B) = 1 = Night-time,
Door Sensor
(C) Upper
= 1 = Saddle
Un-locked,
© 2009 Pearson
Education,
River, NJ 07458. All Rights Reserved
Output (Q) = On
Solution
Input
C
Input
B
Input
A
Output
Q
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
Floyd, Digital Fundamentals, 10th ed
Q  A.B.C  A.B.C  A.B.C
ABC
ABC
ABC
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Solution
Pressure
Sensor (A)
Light
Sensor (B)
Door
Sensor (C)
Alarm
On (Q)
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Example
• The diagram shows a cabinet designed to
house machinery. Sliding panels allow
easy access. The output Q of an electronic
warning system triggers an alarm if the
enable switch A is turned on, when either
panel is open, or both are open.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Example
•
Each
sliding
panel
closes
a
microswitch, when in place.
•
The microswitches, B and C, output a
logic 0 signal when closed.
•
The enable switch A sends a logic 1
signal to the electronic system when
turned on.
•
The system outputs a logic 1 to trigger
the alarm.
Floyd, Digital Fundamentals, 10th ed
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Example
Complete the truth table for the logic system.
Microswitch
(C)
0
Microswitch
(B)
0
Enable
Switch (A)
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Floyd, Digital Fundamentals, 10th ed
Output (Q)
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved