1)
3)
2)
Verilog
module parity( input [7:0] A, output reg even_parity);
reg [4:0] count;
integer i ;
always@(*)
begin
count = 0;
for(i=0; i<=7; i=i+1)
begin
if(A[i]==1'b1)
count = count + 1'b1;
end
if(count[0]==0) //even parity
even_parity = 1;
else
even_parity = 0;
end
Endmodule
TestBench
`timescale 1ns / 1ps
`include "parity.v"
module parity_tb;
wire even_parity;
reg [7:0] A=8’b01010101;
parity dut( .A(A), .even_parity(even_parity));
initial
begin
$dumpfile("parity_tb.v");
$dumpvars(0,parity_tb);
end
Endmodule
******************************************************************************************
4)
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Reg signal is mistaken in 21st line.
Always block statements are pointing to same location at the same time.
Has to change the logic.
The logic is wrong in the code. When done_flag is given input present state S0 goes to next state S1, and
inc_flag is 1 according to the FSM. But the logic is given viceversa.
Always block sensitivity list is changed to always(*) so that it triggers the block when any input is
given.
//
// Verilog file for the fsm for the pattern matching engine
module fsm (clock, reset, start, done_flag, match_address, inc_flag, location,
outcell);
input clock;
// 100 Mhz clock
input reset;
// resets the fsm
input start;
// starts the search
input [8:0] match_address; // address for the pattern match
input done_flag; // signal from compare module saying it has finished
// its search
output inc_flag; // used to increment the address location
output [8:0] location; // location output for pattern match
output [8:0] outcell; // A hash on location
reg [8:0] location, outcell;
reg current_state, next_state;
reg inc_flag;
reg signal;
parameter
s0 = 0,
s1 = 1;
always @(posedge clock or negedge reset)
begin
if (!reset)
current_state = s0;
else
begin
current_state = next_state;
end
end
always @(current_state or start or done_flag)
begin
case (current_state)
s0:
begin
if (start)
begin
location = 9'd0;
in_flag=0;
next_state = s1;
end
else
begin
inc_flag = 0;
next_state = s0;
location-=9'b0;
end
end
s1:
begin
if (done_flag)
begin
location = match_address;
next_state = s0;
end
else
begin
inc_flag = 1;
location=match_address;
next_state = s1;
end
end
endcase
end
always@(posedge clock)
outcell = location ^ (location << 1);
//always@(posedge clock)
//outcell = location ^ (location >> 1);
always@(*)
signal = done_flag & (^location[4:2]);
endmodule
Error in Synopsys.
SD
5)
Clock Period : 2ns
Design:
Synthesis:
Design summary
Clock Summary
Schematic design:
Bitstream generation:
Constraints.dxc file
create_clock -period 2.000 -name clock -waveform {0.000 1.000} [get_ports clock]
set_property PACKAGE_PIN AN25 [get_ports {in[7]}]
set_property PACKAGE_PIN AM28 [get_ports {in[6]}]
set_property PACKAGE_PIN AN28 [get_ports {in[5]}]
set_property PACKAGE_PIN AP25 [get_ports {in[4]}]
set_property PACKAGE_PIN AP26 [get_ports {in[3]}]
set_property PACKAGE_PIN AN27 [get_ports {in[2]}]
set_property PACKAGE_PIN AP27 [get_ports {in[1]}]
set_property PACKAGE_PIN AF24 [get_ports {in[0]}]
set_property PACKAGE_PIN AL31 [get_ports clock]
set_property PACKAGE_PIN AM25 [get_ports d2]
set_property PACKAGE_PIN AP29 [get_ports dec]
set_property PACKAGE_PIN AN29 [get_ports latch]
set_property IOSTANDARD LVCMOS18 [get_ports {in[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {in[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {in[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {in[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {in[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {in[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {in[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {in[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports clock]
set_property IOSTANDARD LVCMOS18 [get_ports d2]
set_property IOSTANDARD LVCMOS18 [get_ports dec]
set_property IOSTANDARD LVCMOS18 [get_ports latch]
set_property IOSTANDARD LVCMOS18 [get_ports zero]
set_property PACKAGE_PIN AM27 [get_ports zero]