uvm factory registration:
1)register:
//component:
`uvm_component_utils(scoreboard)
//object
`uvm_object_utils(sequence_item)
2)create
//component
eg:
class mem_scoreboard extends uvm_scoreboard;
`uvm_component_utils(scoreboard)
sb=mem_scoreboard::type_id::create("sb",this);
function new(string name="mem_scoreboard",uvm_component parent=null);
super.new(name,parent);
endfunction
endclass
//object
class seq_item extends uvm_sequence_item;
`uvm_object_utils_(sequence_item)
si=seq_item::type_id::create("si");
function new(string name="seq_item");
super.new(name);
endfunction
endclass
3)override
four types: a)set_type_override_by_type:
factory.set_type_override_by_type(base_class,derived_class);
b)set_type_override_by_name:
factory.set_type_override_by_name(base_class,derived_class);
c)set_inst_override_by_name:
factory.set_inst_override_by_name(base_class,derived_class,full_path);
d)set_inst_override_by_type:
factory.set_inst_override_by_type(base_class,derived_class,full_path);
--------------------------------------------------------------------------------------
phases syntax:
1)build_phase:
function void build_phase(uvm_phase phase);
super.build_phase(phase);
//config_db get method
//uvm_config_db#(virtual mem_if)::get(null,"*","mem_intf",intf);
endfunction:build_phase
2)connect phase:
function void connect_phase(uvm_phase phase);
//
driver.seq_item_port.connect(sequencer.seq_item_export);//driver and sequencer connection in agent
//mem_agnt.monitor.item_collected_port.connect(scoreboard.item_collected_export);//monitor and scoreboard in env
endfunction:connect_phase
3)run phase:
virtual task run_phase(uvm_phase phase);
forever begin
seq_item_port.get_next_item(req);
drive();
seq_item_port.item_done();
end
endtask:run_phase
-------------------------------------------------------------------
analysis ports:
1)monitor:
uvm_analysis_port#(mem_seq_item)item_collected_port;
2)scoreboard:
unv_analysis_imp#(mem_seq_item,mem_scoreboard)item_collected_export;
------------------------------------------------------------------------
seqence start:in test runphase
seq.start(env.mem_agnt.sequencer);
----------------------------------------------------
run test:in top
intial begin
run_test();
end