Pabna University of Science &
Technology
FET
BIASING
Field-effect transistors biasing
T. H. M. Sumon Rashid
Assistant Professor, Dept. of EEE
FET
Biasing
01
03
J F E T Vs B J E T
Construction, operation and
Transfer characteristics
Self-Bias C o n f i g .
Construction, operation and Trnasfer
Curve
02
Fixed-Bias C o n f i g .
04
D - M O S F E T Biasing
MOSFET types, D-MOSFET
construction and operation
Constructions, advantages and
applications etc.
2
FET vs BJT Overview
Lecture 13
BJT
FET
The current flow is due to the flow of majority as
well as minority charge carriers.
The current flow is due to the flow of majority
charge carriers.
Current flow is due to both electrons and holes,
therefore name bipolar transistor.
The current flow is due to either electrons or holes,
therefore, named unipolar transistor.
It is a current-controlled current device.
It is a voltage-controlled current device.
There are 2 PN junction in BJT.
There are no PN junctions.
The BJT has very simple biasing.
The FET biasing is a little difficult.
The input impedance is comparatively low in the
range of 𝑘 Ω.
The input impedance is very high in the range of
100 𝑀Ω .

The general relationships that can be applied to the dc
analysis of all FET amplifiers are
𝐼𝐺 ≅ 0 𝐴 and 𝐼𝐷 = 𝐼𝑆
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
3
Fixed-Bias Configuration
Lecture 13
The resistor 𝑅𝐺 is present to ensure that 𝑉𝑖 appears at the
input to the FET amplifier for the ac analysis.
𝐼𝐺 ≅ 0 𝐴
and
𝑉𝑅𝐺 = 𝐼𝐺𝑅𝐺 = 0 𝐴
𝑅𝐺 replaced by a short circuit equivalent, Fig.13-2.
Applying KVL,
−𝑉𝐺𝐺 − 𝑉𝐺𝑆 = 0
⟹ 𝑉𝐺𝑆= −𝑉𝐺𝐺
Fig.13-1:Fixed-bias config.
Since, 𝑽𝑮𝑮 is fixed dc supply, the voltage 𝑉𝐺𝑆 is fixed,
resulting in the designation “fixed-bias configuration”.
The resulting level of 𝐼𝐷 is controlled by Shockley’s
equation:
𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 −
𝑉𝑃
Fig.13-2:Fixed-bias
configuration.
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
4
Fixed-Bias Configuration
Lecture 13
Applying KVL to the output
section:
+𝑉𝐷𝑆 + 𝐼𝐷𝑅𝐷 − 𝑉𝐷𝐷 = 0
⟹ 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷
𝑉𝑆 = 0 𝑉
𝑉𝐷𝑆 = 𝑉𝐷 − 𝑉𝑆
Fig.13-3:Plotting Shockley’s equation
Fig.13-4: Finding Q-point Solution
In Fig.13-4, the fixed level 𝑉𝐺𝑆 has been
superimposed as a vertical line.
 The point where the two curves intersect is the
common solution to the configuration.
 Referred to as the quiescent or operating point.

⟹ 𝑉𝐷 = 𝑉𝐷𝑆
𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆
⟹ 𝑉𝐺 = 𝑉𝐺𝑆
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
5
Fixed-Bias Configuration
Lecture 13
Example 1: Determine the following for the network of Fig. 13-5
Boylestad
a. 𝑉𝐺𝑆 𝑄 b. 𝐼𝐷 𝑄 c. 𝑉𝐷𝑆 d. 𝑉𝐷 e. 𝑉𝐺 f. 𝑉𝑆
Solution:
Mathematical Approach
a. 𝑉𝐺𝑆𝑄 = −𝑉𝐺𝐺 = −2 𝑉
b. 𝐼𝐷𝑄 = 𝐼𝐷𝐷𝑆
𝑉𝐺𝑆
1−
𝑉𝑃
2
= 5.625 𝑚𝐴
c. 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷
e.
d. 𝑉𝐷 = 𝑉𝐷𝑆 = 4.75 𝑉
f.
𝑉𝐺 = 𝑉𝐺𝑆 = −2 𝑉
𝑉𝑆 = 0 𝑉
Fig.13-5: Example 1
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
6
Fixed-Bias Configuration
Lecture 13
Graphical Approach
The resulting Shockley curve and the vertical line at 𝑉𝐺𝑆 = −2 𝑉
shown in Fig.13-6.
a. 𝑉𝐺𝑆𝑄 = −𝑉𝐺𝐺 = −2 𝑉
b. 𝐼𝐷𝑄 = 5.6 𝑚 𝐴
c. 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷
= 4.8 𝑉
d. 𝑉𝐷 = 𝑉𝐷𝑆 = 4.8 𝑉
e.
f.
𝑉𝐺 = 𝑉𝐺𝑆 = −2 𝑉
𝑉𝑆 = 0 𝑉
Result of both solutions are quite close.
Fig.13-6: Graphical Solution
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
7
Self-Bias Configuration


Lecture 13
Self-bias configuration require only one dc supplies.
𝑉𝐺𝑆 now determined by the voltage across 𝑅𝑆
Since, 𝐼𝐺 = 0 𝐴, the network for dc analysis
can be redrawn as Fig.13-8.
The current through 𝑅𝑆 is 𝐼𝑆, but 𝐼𝑆 = 𝐼𝐷 and
𝑉𝑅𝑆 = 𝐼𝐷𝑅𝑆
Applying KVL to the closed loop,
−𝑉𝐺𝑆 − 𝑉𝑅𝑆 = 0
Fig.13-7: JFET self-bias
configuration.
𝑉𝐺𝑆 = −𝑉𝑅𝑆 = −𝐼𝐷𝑅𝑆
𝑽𝑮𝑺 is function of 𝑰𝑫, and not fixed.
Fig.13-8 DC analysis Self-bias
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
8
Self-Bias Configuration
Lecture 13
Graphical method is easier to find the Q-point solution. We
can plot the transfer curve using Shockley's equation.
𝑉𝐺𝑆 = −𝐼𝐷𝑅𝑆 [Straight line]
At 𝐼𝐷 = 0 𝐴,
𝐼
At 𝐼𝐷 = 𝐷𝑆𝑆,
2
𝑉𝐺𝑆 = 0 𝑉
𝑉𝐺𝑆 = −
𝐼𝐷𝑆𝑆 𝑅𝑆
2
Applying KVL to output section:
𝑉𝑅𝑆 + 𝑉𝐷𝑆 + 𝑉𝑅𝐷 − 𝑉𝐷𝐷 = 0
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝑉𝑅𝑆 − 𝑉𝑅𝐷 = 𝑉𝐷𝐷 − 𝐼𝑆𝑅𝑆 − 𝐼𝐷𝑅𝐷
𝑉𝑆 = 𝐼𝐷𝑅𝑆
but, 𝐼𝐷 = 𝐼𝑆
So, 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝑆 + 𝑅 𝐷)
𝑉𝐺 = 0 𝑉
Fig.13-9: Sketching self-bias line
𝑉𝐷 = 𝑉𝐷𝑆 + 𝑉𝑆 = 𝑉𝐷𝐷 − 𝑉𝑅𝐷
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
9
Self-Bias Example
Lecture 14
Example 2: Determine the following for the network of Fig. 14-1.
Boylestad
a. 𝑉𝐺𝑆 𝑄 b. 𝐼𝐷 𝑄 c. 𝑉𝐷𝑆 d. 𝑉𝑆 e. 𝑉𝐺 f. 𝑉𝐷
Solution:
a.
h. Find quiescent point for 𝑹𝑺 = 𝟏𝟎𝟎 𝜴 and 𝟏𝟎 𝒌𝜴.
𝑉𝐺𝑆 = −𝐼𝐷𝑅𝑆
Choose, 𝐼𝐷 = 4 𝑚𝐴, 𝑉𝐺𝑆 = −4 𝑉
𝑉𝐺𝑆𝑄 = −2.6 𝑉 [From graph]
b. 𝐼𝐷𝑄 = 2.6 𝑚𝐴 [From graph]
Fig.14-1: Example 2
c. 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷(𝑅𝑆 + 𝑅𝐷) = 8.82 𝑉
d. 𝑉𝑆 = 𝐼𝐷𝑅𝑆
e.
= 2.6 𝑉
𝑉𝐺 = 0 𝑉
f. 𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷
= 11.42 𝑉
Fig.14-2: Example 2
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
10
Self-Bias Example
Lecture 14
Both 𝑅𝑆 = 100 Ω and 𝑅𝑆 = 10 𝑘Ω are plotted
on Fig.14-3.
For, 𝑅𝑆 = 100 Ω:
𝐼𝐷𝑄 = 6.4 𝑚𝐴
𝑉𝐺𝑆𝑄 = −𝐼𝐷𝑅𝑆
≅ −0.64 𝑉
For, 𝑅𝑆 = 10 𝑘Ω:
𝑉𝐺𝑆𝑄 = −4.6 𝑉
𝐼𝐷𝑄 = −
𝑉𝐺𝑆𝑄
𝑅𝑆
≅ 0.46 𝑚𝐴
Fig.14-3: Example 2
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
11
Voltage-divider Biasing
Lecture 14
(a)
Fig.14-4: Voltage-divider bias config.
(b)
Fig.14-5: Redrawn for dc analysis
𝑅2𝑉𝐷𝐷
𝑅1 + 𝑅 2
Applying KVL to the closed loop,
Since, 𝐼𝐺 = 0 𝐴,
𝑉𝐺 =
So, 𝐼𝑅1 = 𝐼𝑅2
And the series equivalent
circuit shown if fig.13-12 (a).
𝑉𝐺 − 𝑉𝐺𝑆 − 𝑉𝑅𝑆 = 0
𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑅 𝑆
⟹ 𝑉𝐺𝑆 = 𝑉𝐺 − 𝐼𝐷𝑅𝑆
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
12
Voltage-divider Biasing
Lecture 14
𝑉𝐺𝑆 = 𝑉𝐺 − 𝐼𝐷𝑅𝑆
𝑽𝑮 and 𝑹𝑺 are fixed and the equation above is
still a straight line equation.
If 𝐼𝐷 = 0 𝑚𝐴,
𝑉𝐺𝑆 = 𝑉𝐺
If 𝑉𝐺𝑆 = 0 𝑉,
𝐼𝐷 =
𝑉𝐺
𝑅𝑆
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷(𝑅𝐷 + 𝑅𝑆)
Fig.14-6: Sketching the network equation
𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷
𝑉𝑆 = 𝐼𝐷𝑅𝑆
Fig.14-7:Effect of 𝑅𝑆 on the resulting Q-point
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
13
D-MOSFET Biasing
Lecture 14
JFET and D-MOSFET have similar Transfer curve.
Therefore, the analysis also similar.
The only difference is, D-MOSFET permit operating point with
positive values of 𝑉𝐺𝑆 and level of 𝐼𝐷 exceed 𝐼𝐷𝑆𝑆.



Example 6: For n-channel depletion type MOSFET of Fig. 14-8,
Boylestad
determine:
a. 𝐼𝐷 𝑄 and 𝑉𝐺𝑆 𝑄 b. 𝑉𝐷𝑆
Solution: Transfer curve:
a.
At, 𝐼𝐷 = 𝐼 𝐷𝑆𝑆 = 1.5 𝑚𝐴,
4
Fig.14-8: Example 6
𝑉𝐺𝑆 = 0.5 VP = −1.5 V
For D-MOSFET, For positive value
of 𝑉𝐺𝑆 , 𝐼𝐷 increases rapidly. So,
define only for 𝑉𝐺𝑆 = +1 𝑉
𝐼𝐷 = 𝐼𝐷𝑆𝑆
𝑉𝐺𝑆
1−
𝑉𝑃
2
= 10.67 𝑚𝐴
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
14
D-MOSFET Biasing
Lecture 14
Proceeding as JEFTs, we have
𝑉𝐺 =
𝑅2 𝑉𝐷𝐷
𝑅1 + 𝑅2
= 1.5 𝑉
𝑉𝐺𝑆 = 𝑉𝐺 − 𝐼𝐷𝑅𝑆 = 1.5 𝑉 − 𝐼𝐷 (750Ω)
Setting, 𝐼𝐷 = 0 𝑚𝐴,
𝑉𝐺𝑆 = 𝑉𝐺 = 1.5 𝑉
𝑉𝐺
Setting, 𝑉𝐺𝑆 = 0 𝑉, 𝐼𝐷 =
= 2 𝑚𝐴
𝑅𝑆
Transfer curve and resulting bias line shown in Fig. 149. The resulting operating point is given by
𝐼𝐷𝑄 = 3.1 𝑚𝐴
𝑉𝐺𝑆𝑄 = −0.8 𝑉
b.
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷(𝑅𝐷 + 𝑅𝑆) = 10.1 𝑉
Fig.14-9: Determining Q-point
[Prepared and Conducted by: T. H. M. Sumon Rashid, Assistant Professor, Dept. of EEE, Pabna University of Science and Technology]
15
THANKS
Do you have any questions?
CREDITS:
T. H. M. Sumon Rashid
Assistant Professor, Dept. of EEE
Pabna University of Science & Technology