Title Of The Experiment: Write a program to design and simulate an AND,
OR, NOT, XOR, XNOR, NAND, NOR gate.
AND GATE:
Code:
FILE NAME: AND (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end AND;
architecture Behavioral of AND is
begin
c<=a and b;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='0';
3.
b<='0';
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wait for 100 ns;
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a<='0';
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b<='1';
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wait for 100 ns;
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a<='1';
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b<='0';
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wait for 100 ns;
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a<='1';
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b<='1';
13.
wait for 100 ns;
14.
wait;
15.
end process;
16. END;
Output:
Code:
FILE NAME: OR (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OR is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end OR;
architecture Behavioral of OR is
begin
c<=a or b;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='0';
3.
b<='0';
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wait for 100 ns;
5.
a<='0';
6.
b<='1';
7.
wait for 100 ns;
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a<='1';
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b<='0';
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wait for 100 ns;
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a<='1';
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b<='1';
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wait for 100 ns;
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wait;
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end process;
16.
END;
Output:
Code:
FILE NAME: NOT (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NOT is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end NOT;
architecture Behavioral of NOT is
begin
b<= not a;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
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begin
a<='0';
wait for 100 ns;
a<='1';
wait for 100 ns;
wait;
end process;
END;
Output:
Code:
FILE NAME: XOR (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity XOR is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end XOR;
architecture Behavioral of XOR is
begin
c<=a xor b;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1.
begin
2.
a<='0';
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b<='0';
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wait for 100 ns;
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a<='0';
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b<='1';
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wait for 100 ns;
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a<='1';
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b<='0';
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wait for 100 ns;
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a<='1';
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b<='1';
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wait for 100 ns;
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wait;
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end process;
16.
END;
Output:
Code:
FILE NAME: XNOR (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity XNOR is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end XNOR;
architecture Behavioral of XNOR is
begin
c<=not(a xor b);
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='0';
3.
b<='0';
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wait for 100 ns;
5.
a<='0';
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b<='1';
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wait for 100 ns;
8.
a<='1';
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b<='0';
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wait for 100 ns;
11.
a<='1';
12.
b<='1';
13.
wait for 100 ns;
14.
wait;
15.
end process;
16. END;
Output:
Code:
FILE NAME: NAND (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NAND is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end NAND;
architecture Behavioral of NAND is
begin
c<= a nand b;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='0';
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b<='0';
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wait for 100 ns;
5.
a<='0';
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b<='1';
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wait for 100 ns;
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a<='1';
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b<='0';
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wait for 100 ns;
11.
a<='1';
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b<='1';
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wait for 100 ns;
14.
wait;
15.
end process;
16.
END;
Output:
Code:
FILE NAME: NOR (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NOR is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end NOR;
architecture Behavioral of NOR is
begin
c<= a nor b;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='0';
3.
b<='0';
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wait for 100 ns;
5.
a<='0';
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b<='1';
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wait for 100 ns;
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a<='1';
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b<='0';
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wait for 100 ns;
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a<='1';
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b<='1';
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wait for 100 ns;
14.
wait;
15.
end process;
16. END;
Output:
Title Of The Experiment: Write a program to implement all basic gate
using two universal gates such as NAND & NOR.
AND GATE USING NAND GATE:
Code:
FILE NAME: AndNAND (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AndNAND is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : inout STD_LOGIC);
end AndNAND;
architecture Behavioral of AndNAND is
begin
c<= (a nand b) nand (a nand b);
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='0';
3.
b<='0';
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wait for 100 ns;
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a<='0';
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b<='1';
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wait for 100 ns;
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a<='1';
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b<='0';
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wait for 100 ns;
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a<='1';
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b<='1';
13.
wait for 100 ns;
14.
wait;
15.
end process;
16. END;
Output:
Code:FILE NAME: OrNAND (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OrNAND is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : inout STD_LOGIC);
end OrNAND;
architecture Behavioral of OrNAND is
begin
c<= (a nand a) nand (b nand b);
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='0';
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b<='0';
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wait for 100 ns;
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a<='0';
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b<='1';
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wait for 100 ns;
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a<='1';
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b<='0';
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wait for 100 ns;
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a<='1';
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b<='1';
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wait for 100 ns;
14.
wait;
15.
end process;
16.
END;
Output:-
Code:FILE NAME: NotNAND (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NotNAND is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end NotNAND;
architecture Behavioral of NotNAND is
begin
b<= a nand a;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
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begin
a<='0';
wait for 100 ns;
a<='1';
wait for 100 ns;
wait;
end process;
END;
Output:-
Code:FILE NAME: AndNOR (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AndNOR is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : inout STD_LOGIC);
end AndNOR;
architecture Behavioral of AndNOR is
begin
c<= (a nor a) nor (b nor b);
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='0';
3.
b<='0';
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wait for 100 ns;
5.
a<='0';
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b<='1';
7.
wait for 100 ns;
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a<='1';
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b<='0';
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wait for 100 ns;
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a<='1';
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b<='1';
13.
wait for 100 ns;
14.
wait;
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end process;
16.
END;
Output:-
Code:FILE NAME: OrNOR (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OrNOR is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : inout STD_LOGIC);
end OrNOR;
architecture Behavioral of OrNOR is
begin
c<= (a nor b) nor (a nor b);
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='0';
3.
b<='0';
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wait for 100 ns;
5.
a<='0';
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b<='1';
7.
wait for 100 ns;
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a<='1';
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b<='0';
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wait for 100 ns;
11.
a<='1';
12.
b<='1';
13.
wait for 100 ns;
14.
wait;
15.
end process;
16.
END;
Output:-
Code:FILE NAME: NotNOR (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NotNOR is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end NotNOR;
architecture Behavioral of NotNOR is
begin
b<= a nor a;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
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begin
a<='0';
wait for 100 ns;
a<='1';
wait for 100 ns;
wait;
end process;
END;
Output:-
Title Of The Experiment: Write a program to simulate a Half-adder
circuit.
Code:
FILE NAME: HALFADD (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HALFADD is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end HALFADD;
architecture Behavioral of HALFADD is
begin
s<= a xor b;
c<= a and b;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='0';
3.
b<='0';
4.
wait for 100 ns;
5.
a<='0';
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b<='1';
7.
wait for 100 ns;
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a<='1';
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b<='0';
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wait for 100 ns;
11.
a<='1';
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b<='1';
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wait for 100 ns;
14.
wait;
15.
end process;
16.
END;
Output:
Title Of The Experiment: Write a program to simulate a Full-adder
circuit.
CODE:
FILE NAME: FULLADD (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164 . ALL;
entity FULLADD is
port (a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD _LOGIC;
s : OUT STD_LOGIC;
cout : OUT STD_LOGIC);
end FULLADD;
architecture Behavioral of FULLADD is
begin
s<= (a xor b) xor c;
cout<= (a and b) or (c and (a xor b));
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<=’0’;
3.
b<=’0’;
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c<=’0’;
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wait for 100ns;
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a<=’0’;
7.
b<=’0’;
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c<=’1’;
9.
wait for 100ns;
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a<=’0’;
11.
b<=’1’;
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c<=’0’;
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wait for 100ns;
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a<=’0’;
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b<=’1’;
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c<=’1’;
wait for 100ns;
a<=’1’;
b<=’0’;
c<=’0’;
wait for 100ns;
a<=’1’;
b<=’0’;
c<=’1’;
wait for 100ns;
a<=’1’;
b<=’1’;
c<=’0’;
wait for 100ns;
a<=’1’;
b<=’1’;
c<=’1’;
wait for 100ns;
wait;
end process;
END;
Output:
Title Of The Experiment: Write a program to simulate a Half-subtractor
circuit.
Code:
FILE NAME: HALFSUB (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HALFSUB is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
d : out STD_LOGIC;
bout : out STD_LOGIC);
end HALFSUB;
architecture Behavioral of HALFSUB is
begin
d<= a xor b;
bout<= (not a) and b;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='0';
3.
b<='0';
4.
wait for 100 ns;
5.
a<='0';
6.
b<='1';
7.
wait for 100 ns;
8.
a<='1';
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b<='0';
10.
wait for 100 ns;
11.
a<='1';
12.
b<='1';
13.
wait for 100 ns;
14.
wait;
15.
end process;
16. END;
Output:
Title Of The Experiment: Write a program to simulate a Full-subtractor
circuit.
Code:FILE NAME: FULLSUB (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164 . ALL;
entity FULLSUB is
port (a : IN STD_LOGIC;
b : IN STD_LOGIC;
c : IN STD _LOGIC;
d : OUT STD_LOGIC;
bout : OUT STD_LOGIC);
end FULLSUB;
architecture Behavioral of FULLSUB is
begin
d<= (a xor b) xor c;
bout <= ((b xor c) and (not a)) or (b and c);
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<=’0’;
3.
b<=’0’;
4.
c<=’0’;
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wait for 100ns;
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a<=’0’;
7.
b<=’0’;
8.
c<=’1’;
9.
wait for 100ns;
10.
a<=’0’;
11.
b<=’1’;
12.
c<=’0’;
13.
wait for 100ns;
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a<=’0’;
15.
b<=’1’;
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c<=’1’;
wait for 100ns;
a<=’1’;
b<=’0’;
c<=’0’;
wait for 100ns;
a<=’1’;
b<=’0’;
c<=’1’;
wait for 100ns;
a<=’1’;
b<=’1’;
c<=’0’;
wait for 100ns;
a<=’1’;
b<=’1’;
c<=’1’;
wait for 100ns;
wait;
end process;
END;
Output:
Title Of The Experiment: Write a program to design 2:1 Multiplexer.
Code:
FILE NAME: MUX2:1 (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX2:1 is
Port ( p0 : in STD_LOGIC;
p1 : in STD_LOGIC;
s : in STD_LOGIC;
y : out STD_LOGIC);
end MUX2:1;
architecture Behavioral of MUX2:1 is
begin
y<=p0
when s='0'
else p1;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
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begin
s<='0';
p0<='0';
p1<='0';
wait for 100 ns;
s<='0';
p0<='0';
p1<='1';
wait for 100 ns;
s<='0';
p0<='1';
p1<='0';
wait for 100 ns;
s<='0';
p0<='1';
p1<='1';
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wait for 100 ns;
s<='1';
p0<='0';
p1<='0';
wait for 100 ns;
s<='1';
p0<='0';
p1<='1';
wait for 100 ns;
s<='1';
p0<='1';
p1<='0';
wait for 100 ns;
s<='1';
p0<='1';
p1<='1';
wait for 100 ns;
wait;
end process;
END;
Output:
Title Of The Experiment: Write a program to design 4:1 Multiplexer.
Code:
FILE NAME: MUX4:1 (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164 . ALL;
entity MUX4:1 is
Port( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s1 : in STD_LOGIC;
s0 : in STD_LOGIC;
y : out STD_LOGIC);
end MUX4:1;
architectural Behavioral of MUX4:1 is
begin
process(a,b,c,d,s0,s1)
begin
if(s0='0' and s1='0')
then y<=a;
elsif(s0='0' and s1='1')
then y<=b;
elsif(s0='1' and s1='0')
then y<=c;
else y<=d;
end if;
end process ;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
a<='1';
3.
b<='0';
4.
c<='1';
5.
d<='0';
6.
s0<='0';
7.
s1<='0';
8.
wait for 100 ns;
9.
s0<='0';
10.
s1<='1';
11.
wait for 100 ns;
12.
s0<='1';
13.
s1<='0';
14.
wait for 100 ns;
15.
s0<='1';
16.
s1<='1';
17.
wait for 100ns;
18.
wait;
19.
end process;
20.
END;
Output:
Title Of The Experiment: Write a program to design 8:1 Multiplexer.
Code:
FILE NAME: MUX8:1 (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164 . ALL;
entity MUX8:1 is
Port ( s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
s2 : in STD_LOGIC;
yout : out STD_LOGIC;
i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3 : in STD_LOGIC;
i4 : in STD_LOGIC;
i5 : in STD_LOGIC;
i6 : in STD_LOGIC;
i7 : in STD_LOGIC);
end MUX8:1;
architectural Behavioral of MUX8:1 is
begin
process (s0,s1,s2,i0,i1,i2,i3,i4,i5,i6,i7)
begin
if(s0='0' and s1='0' and s2='0')
then yout<=i0;
elsif(s0='0' and s1='0' and s2='1')
then yout<=i1;
elsif(s0='0' and s1='1' and s2='0')
then yout<=i2;
elsif(s0='0' and s1='1' and s2='1')
then yout<=i3;
elsif(s0='1' and s1='0' and s2='0')
then yout<=i4;
elsif(s0='1' and s1='0' and s2='1')
then yout<=i5;
elsif(s0='1' and s1='1' and s2='0')
34.
35.
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then yout<=i6;
else yout<=i7;
end if;
end process;
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
i0<='0';
3.
i1<='1';
4.
i2<='0';
5.
i3<='1';
6.
i4<='0';
7.
i5<='1';
8.
i6<='0';
9.
i7<='1';
10.
s0<='0';
11.
s1<='0';
12.
s2<='0';
13.
wait for 100 ns;
14.
s0<='0';
15.
s1<='0';
16.
s2<='1';
17.
wait for 100 ns;
18.
s0<='0';
19.
s1<='1';
20.
s2<='0';
21.
wait for 100 ns;
22.
s0<='0';
23.
s1<='1';
24.
s2<='1';
25.
wait for 100 ns;
26.
s0<='1';
27.
s1<='0';
28.
s2<='0';
29.
wait for 100 ns;
30.
s0<='1';
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s1<='0';
32.
s2<='1';
33.
wait for 100 ns;
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s0<='1';
s1<='1';
s2<='0';
wait for 100 ns;
s0<='1';
s1<='1';
s2<='1';
wait for 100 ns;
wait;
end process;
END;
Output:
Title Of The Experiment: Write a program to design 4:2 Encoder.
Code:
FILE NAME: ENCODER4:2 (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ENCODER4:2 is
Port ( s : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (1 downto 0));
end ENCODER4:2 ;
architecture Behavioral of ENCODER4:2 is
begin
Y<="00" WHEN S="0001"
ELSE "01" WHEN S="0010"
ELSE "10" WHEN S="0100"
ELSE "11" WHEN S="1000"
ELSE"--";
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
s<="0001";
3.
wait for 100 ns;
4.
s<="0010";
5.
wait for 100 ns;
6.
s<="0100";
7.
wait for 100 ns;
8.
s<="1000";
9.
wait for 100 ns;
10.
wait;
11.
end process;
12. END;
Output:
Title Of The Experiment: Write a program to design 2:4 Decoder.
Code:
FILE NAME: DECODER2:4 (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DECODER2:4 is
Port( I : in STD_LOGIC_VECTOR (1 downto 0);
D : out STD_LOGIC_VECTOR (3 downto 0));
end DECODER2:4;
architectural Behavioral of DECODER2:4 is
begin
D<="0001" WHEN I="00"
ELSE "0010" WHEN I="01"
ELSE "0100" WHEN I="10"
ELSE "1000" WHEN I="11"
ELSE "----";
end behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
I<="00";
3.
wait for 100 ns;
4.
I<="01";
5.
wait for 100 ns;
6.
I<="10";
7.
wait for 100 ns;
8.
I<="11";
9.
wait for 100 ns;
10.
wait;
11.
end process;
12. END;
Output:
Title Of The Experiment: Write a program to design 4 Bit Comparator.
Code:
FILE NAME: COMPARATOR (VHDL MODULE)
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity COMPARATOR is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
X : out STD_LOGIC;
Y : out STD_LOGIC;
Z : out STD_LOGIC);
end COMPARATOR;
architectural Behavioral of COMPARATOR is
begin
X<='0';
Y<='0';
Z<='0';
X<='1' WHEN A>B ELSE '0';
Y<='1' WHEN A<B ELSE '0';
Z<='1' WHEN A=B ELSE '0';
end Behavioral;
FILE NAME: RIYA29 (VHDL TEST BENCH)
1. begin
2.
A<="1000";
3.
B<="0100";
4.
wait for 100 ns;
5.
A<="1000";
6.
B<="1100";
7.
wait for 100 ns;
8.
A<="1000";
9.
B<="1000";
10.
wait for 100 ns;
11.
wait;
12.
end process;
13. End;
Output: