Microprocessor Systems
ECL 3060 (3-0-0) = 3 Credits
Microprocessor Systems Lab
ECP 3060 (0-0-2) = 1 Credit
DR. SUMEET GUPTA
ASSOCIATE PROFESSOR
SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING
SHRI MATA VAISHNO DEVI UNIVERSITY, KATRA
Syllabus
Introduction to 8085 Microprocessor: Functional block diagram – Registers, ALU, Bus
systems, Memory & Instruction cycles Timing diagrams, Address Decoding techniques,
Addressing modes, Instruction Set, Assembly Language Programming, Interrupts-Types &
handling, ISR, Stack architecture
Memory and Peripheral interfacing: Basic interfacing concepts - Memory space
partitioning - Buffering of buses – Timing constraints - Memory control signals - Read and
write cycles, Interfacing RAM, ROM, 8255PPI, Interfacing applications using 8255. Need
for direct memory access - DMA transfer types
Intel 16 bit Microprocessor: Register organization of 8086 – Architecture - Physical
Memory organization - I/O addressing capability, Addressing modes of 8086 - Instruction
set of 8086 - Assembler directives and operators, Assembly language programming,
Interrupt Architecture
Freescale 32 bit ColdFire Processor:-Introduction to ColdFire Core, Comparison with
8085 & 8086 Architecture, Introduction to MCF5223X Microprocessor Architecture &
Functional Blocks
Course Outcome
CO No.
Course Outcome
CO1
The student will be able to analyze, specify, design, write and test assembly language
programs for 8085 microprocessor and basic programs to run on 8086 microprocessor
based systems.
CO2
The student will be able to understand the various aspects of the internal architecture of
the 8085 microprocessor and will be able to design hardware circuits to interface the 8085
microprocessor to various ICs like RAM, ROM, 8255 etc.
CO3
The student will be able to calculate the worst-case execution time of programs or parts of
programs, and to design and build, or to modify, software to maximize its run time
memory or execution-time behavior.
CO4
The student will be able to compare the architecture design for 8085, 8086 & Coldfiree 32
bit microprocessor
Pedagogy
1. Flipped Class – Pre-loaded Video Lectures which you will view before coming
to the live class
2. Live Classes - For discussions and doubt clearing
3. Quizzes – Multiple Choice Types
4. Assignments - Zero plagiarism policy – Copying will get you a zero
5. Lab Work – To the extent possible
6. Project – Simulation Based
Microprocessors System
74LS374
8085 Block Diagram
8085 Microprocessor
Consists of:
1. CPU + ALU + Registers
2. 8 bit Data Bus (Multiplexed)
3. 16 bit Address Bus (8 bit Multiplexed with Data Bus)
4. 5 Sources of hardware Interrupt
5. 02 Serial Data Lines
6. DMA Interface
7. Control lines for interfacing
8085 Microprocessor
Fetch-Decode-Execute Cycle
A microprocessor, till the time it is ON and is not in HALT mode, will continuously follow the
Fetch Decode Execute Cycle
1. Fetch the Instruction from the ROM into the Instruction Register (IR)
2. Decode the Instruction i.e. understand what the instruction is
3. Execute the Instruction i.e. perform all micro-steps needed to complete the task
mentioned by the instruction
Then go back to Step No. 1 and repeat the process infinite number of times
8085 Microprocessor – Pin Description
Pins
Direction Description
X1, X2
IN
This is where the Crystal is connected to the Oscillator circuit inside 8085 where Clock is
generated. Typically 6MHz crystal is connected and internal clock is 3MHz (Crystal frequency/2)
CLK OUT
OUT
The Clock signal generated inside the 8085 is also available as an output at this pin and can be
connected to external device, if needed
Vcc, GND
IN
Voltage Supply and Ground. As IC is TTL, Supply is Typically 5V
AD7-AD0
IN & OUT Multiplexed Address and Data Bus (LSB of Address Bus A7-A0 is time multiplexed with Data Bus
D7-D0
A8-A15
OUT
MSB of Address Bus
ALE
OUT
Used to demultiplex the time multiplexed Address and Data Bus AD7-AD0 to A7-A0 & D7-D0
RD, WR, IO/M
OUT
Signal used for Reading a byte or Writing a byte from/to external Input/Output Device or
Memory
RESETIN,
RESET OUT
IN, OUT
Applying a 0 on RESETIN RESETS the 8085 and simultaneously generates a 1 on RESET OUT which
could be used to REST other external devices if needed.
HOLD, HLDA
IN, OUT
Hold & Hold Acknowledge (Active Low) are used for Direct Memory access (DMA)
8085 Microprocessor – Pin Description
Pins
Direction Description
S0,S1
OUT
These Status signals indicate the status of thee internal circuit of the 8085
READY
IN
Slow external devices use this signal to convey to 8085 that they are ready for the next
operation
TRAP, RST 7.5, IN, OUT
RST 6.5, RST
5.5, INTR,
INTA
First 05 are the Interrupt Signals while INTA is the Interrupt Acknowledgement Signal generated
by 8085 in response to receipt of INTR interrupt
SID, SOD
These are used to Serially receive or transmit 01 byte of data, bit by bit
IN, OUT
8085 Microprocessor – Memory Read Cycle
8085 Microprocessor – Memory Write Cycle
e.g. STA 2022H
In T1:
Address available on A8-A15 & A7-A0
ALE Pulse
Io/M =0
WR=1
In T2:
A7-A0 becomes tri-state
ALE=0
Put Data on Data Bus D7-D0
Io/M=0
WR=0
In T3:
After some time WR=1
Remove Data from D7-D0, Bus is tri-state
Complete the Cycle
8085 Microprocessor – De-multiplexing of AD7-AD0
8085 Microprocessor – De-multiplexing of AD7-AD0
8085 Microprocessor – RAM Interface
A14
A12
/WR
A13
A1
A9
A8
A7
A6
A5
A3
A11
/RD
A4
A2
/WR
/RD
A10
/CS
A0
D4
D0
D1
D3
D5
D7
D2
D6
/RD
/WR
8085 Microprocessor – Address Space
Address Space means the total unique addresses that can be generated by the 8085 microprocessors on its 16
address lines. Since 8085 has 16 address lines thus a total of 2^16 = 65536 addresses
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0 0
0 0 0 0 0 0 0 0 0 0 0
0000H (Starting Address)
1 1
1
FFFFH (Last Address)
2^4
2^7
2^8
2^9
2^10
2^11
2^12
2^13
2^14
2^15
2^16
= 16
=128
= 256
=512
=1024 (1KB)
=2048 (2KB)
=4096 (4KB)
=8192 (8KB)
=16384 (16KB)
=32768 (32KB)
=65536 (64KB)
1
1
1
1 1
1
1
1 1 1
1 1
1
8085 Microprocessor – Address Space
Q1. 01 ROM IC of 32KB and 01 RAM IC of 32KB are to be interfaced with the 8085. Assuming the starting address of
ROM IC is 0000H what will be address map for the ROM and RAM?
Q2. 02 ROM ICs of 8KB each and 01 RAM IC of 16KB is interfaced to 8085. Assuming the starting address of first ROM
IC is 0000H what will be address map for the ROMs and RAM?
Q3. 01 ROM IC of 2KB and on ROM IC of 8KB and 02 RAM IC of 8KB each is interfaced to 8085. Assuming the starting
address of first ROM IC is 0000H what will be address map for the ROMs and RAM?
Q4. IO/M is used by microprocessor to indicate if its doing a Rad or write operation with Input/Output Device or
Memory. This signal along with /RD and /WR signal is used to perform the Memory Rad/Write or IO Read/write
operations. Design a circuit which accepts these three signals as input and generates four outputs namely /IOR,
/IOW, /MEMR,/MEMW8085.
74138 3 to 8 Decoder
Instruction Set of 8085 Microprocessor
Instruction Format: Instruction consists of 01 Opcode (Operation Code) and either 0, 1 or 2 operands
E.g. LDA 2000H
LDA (3AH)
20H
00H
OpCode means the code of the operation to be done e.g. Add, Subtract, Increment, decrement, move etc.
Operands means the values over which the operations are to be done
The opcodes are fixed and were designed when the 8085 microprocessor was designed. We can’t change
it.
The operands can be either given directly in the instruction, in registers, in memory locations
E.g. LDA 2000H
LDA (3AH)
20H
00H
We already know that reading one byte of memory takes 3 T States. This combination of 3 T states is
called a Machine Cycle represented by M
The Instructions are stored in the ROM and need to be fetched from the ROM to the Microprocessor
Fetching the Opcode (1 Byte) takes 3 T states and 01 additional T state is taken to decode the Opcode
Therefore, the Machine cycle for Opcode Fetch is of 4 T-States and not 3 T states
This is called M1 Machine cycle – Machine cycle for fetching the OpCode
So with this logic how many machine cycles will be required to fetch the complete instruction LDA
2000H? The answer is 3 Machine cycles M1, M2 & M3
How many total t states to fetch this instructions?
4 T states in M1, 3 T States in M2 & 3 T states in M3 – Total of 10 T States to fetch this instruction
Instruction Fetch Cycle of 8085 – Part –A – Op-code
Fetch
M1 Machine Cycle – Opcode Fetch & Decode
T1 – 8085 puts the address of ROM
memory location from where the Op
code is to be fetched on higher and
lower address bus
T2 – 8085 enables the /RD signal so that
the opcode can be read from ROM
memory location
T3 – The opcode is fetched and stored
in Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes
place so that 8085 knows what is to be
done next
Instruction Fetch Cycle of 8085 – Part –B – Operand
Fetch
M2 Machine Cycle – Operand Fetch
M3 Machine Cycle – Operand Fetch
Operand Fetch is Memory Read Cycle
All Instructions
operand fetch
may
not
require
In case of instructions where there is
no operand fetch required, only M1
cycle will occur for fetch.
Operand
Operand
In some cases, there will b 01 operand
or 02 operands
Accordingly either M2 will run or M2
and M3 both will run
Example of Program written in Assembly Language
of 8085
Question: Write a program in Assembly language of 8085 microprocessor to add the two bytes
stored at memory location 2000H & 2001H and store the sum in 2002H.
LDA 2000H
//Read number from memory location 2000H and copy into Accumulator (A)
MOV B,A
//Copy the contents of Register A (Source) into Register B (Destination)
LDA 2001H
//Read number from memory location 2001H and copy into Accumulator (A)
ADD B
//Perform the addition of the two bytes stored in A and B and store sum in A
STA 2002H
//Store the value in A into memory location 2002H
HLT
//Stop
Registers in 8085
Flag register in 8085
1. CY Flag – Carry Flag - This flag becomes 1 when addition or subtraction of two bytes results in
generation of carry or borrow else it is 0. This carry or borrow is reflected in the Carry flag.
2. P Flag - Parity Flag - If after any arithmetic or logical operation the result has even parity, an
even number of 1 bits, the parity flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.
3. Z Flag – Zero Flag - If after any arithmetic or logical operation the result is zero, the Zero
flag is set i.e. 1, otherwise it is reset i.e. 0.
4. S Flag – Sign Flag – The S flag corresponds to the Most Significant Bit of the Accumulator
after arithmetic or logical operation is carried out. If signed number representation is being
used then a 1 would indicate that the number is negative and 0 would indicate that number is
positive
5. AC Flag – Auxiliary Carry Flag - If after any arithmetic operation there is a carry from the
lower nibble to the upper nibble then AC Flag is set i.e. becomes 1 else AC flag is reset i.e. 0
Instruction Set of 8085 Microprocessor
There are a total of 246 instructions in the instructions set of 8085 microprocessor and these can be
categorized as:
1. Data Transfer Instructions – These instructions can be used to transfer data between Register to
register, Register to memory, memory to register . e.g. LDA, STA, MOV, MVI. Execution of these
instructions have not effect on the flags.
2. Arithmetic & Logical Instructions - These instructions can be used to perform arithmetic and logical
operations. Result of the operation, in most cases is stored in Accumulator. e.g. ADD, SUB, INR, DCR,
AND, XOR, ORA etc. Execution of most of these instructions have effect on the flags.
3. Branching Instructions – These instructions can be used to change the sequence of flow of the
program. This change in flow can be conditional or unconditional. e.g. JMP, JZ, JNZ, CALL, RET
4. Control Instructions - These instruction control the basic functioning of the microprocessor. e.g.
HLT, NOP, SIM, RIM, DI, EI
Data Transfer Instructions
MOV destination, source
MVI
destination, 8 bit number
LDA
16 bit address
STA
16 bit address
LHLD
16 bit address
SHLD
16 bit address
LXI
16 bit number
LDAX Register pair which contains address
STAX
Register pair which contains address
XCHG Exchange
Data Transfer Instructions (MOV)
MOV destination, source
Both destination or source can be registers
One can be Register and another can be Memory represented by M
E.g. MOV A,B
MOV C,D
MOV B,E
MOV A,M
Register H
20H
Copy contents of B in A
A
B
Copy contents of D in C
C
D
Copy contents of E in B
B
E
Copy contents of memory location whose address is in HL into A
A
[HL]
Register L
03H
If Register H has the value 20H & L has the value 03H then the Register pair HL has
the value 2003H
Now on execution of MOV A,M the data stored in 2003H will be copied to A i.e.
after execution of instruction value in A will be 1FH which was stored at 2003H
2000H
5AH
2001H
2FH
2002H
39H
2003H
1FH
2004H
22H
Data Transfer Instructions (MOV)
MOV destination, source
Size of Instruction :
01 Byte
T-States Required for fetching & execution:
◦ For Register to Register transfer only 01 Machine cycle with 04 T states
◦ For Register to Memory transfer and vice versa: 02 Machine Cycles
M1- 04 T- states,
M2 -03 T-States
Instruction Fetch & Execute Cycle for MOV rd,rs
M1 Machine Cycle – Opcode Fetch, Decode & Execute
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. As both
source and destination register are inside the
8085 so execution of instruction also is
completed in T4
Instruction Fetch Cycle for MOV rd,M
M1 Machine Cycle – Opcode Fetch
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next.
Instruction Execute Cycle for MOV rd,M
M2 Machine Cycle –
This is memory Read cycle
The content of memory location, whose
address is in HL, is copied into the Register
mentioned in the instruction.
H
L
Data
Data Transfer Instructions (MVI reg/M, 8 bit
value)
MVI destination, source
Destination can be a register of M (Memory)
E.g. MVI A,2FH
MVI C, 77H
MVI M, 8CH
Register H
20H
Move immediately into A the value 2FH
A
2FH
Move immediately into C the value 77H C
C
77H
Move immediately into the Memory location the number 8CH. location is
Memory the one whose address is in
[HL]
8CH
Register L
03H
If Register H has the value 20H & L has the value 03H then the Register pair HL has
the value 2003H
Now on execution of MVI, 8CH, the data at memory location 2003H will be
replaced with 8CH
2000H
5AH
2001H
2FH
2002H
39H
2003H
1FH / 8CH
2004H
22H
Data Transfer Instructions (MVI)
MVI
reg/M, 8 bit number
Size of Instruction :
02 Byte
T-States Required for fetching & execution:
◦ For storing data into Register: 02 Machine cycle
M1- 04 T- states – Fetch op code
M2 -03 T-States – Fetch operand and store in register
◦ For storing data in Memory: 03 Machine Cycles
M1- 04 T- states – Fetch op code
M2 -03 T-States – Fetch operand
M3 – 03 T States – Memory write cycle
Instruction Fetch & Execute Cycle for MVI rd, 8 bit number
M1 Machine Cycle – Opcode Fetch, Decode
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode, 8085 knows this instruction’s size is 02
bytes and thus initiates operand fetch cycle M2
Instruction Fetch & Execute Cycle for MVI rd, 8 bit number
M2 Machine Cycle – Operand Fetch
Operand Fetch is Memory Read Cycle
Since the operand i.. 8 bit value is to be
stored in Register only, execution
happens in T3 of M2
Operand
Instruction Fetch & Execute Cycle for MVI M, 8 bit number
M1 Machine Cycle – Opcode Fetch, Decode
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode, 8085 knows this instruction’s size is 02
bytes and thus initiates operand fetch cycle M2
Instruction Fetch & Execute Cycle for MVI rd, 8 bit number
M2 Machine Cycle – Operand Fetch M3 Machine Cycle – Memory Write
H
Operand
L
8 bit no.
Comparison between MOV & MVI
MOV Rd, Rs – M1 – 04 T
MVI Rd, 8 BIT VALUE – M1,M2 – 07 T
MOV Rd, M – M1, M2 – 07 T
MVI M, 8 BIT VALUE – M1,M2, M3 – 10 T
MOV M, Rs – M1, M2 – 07 T
Size: 01 Byte – Opcode
Size: 02 Bytes - Opcode, 8 bit number
Instruction
Meaning
Size
T States
MVI H, 21H
H <- 21H
2
7
MVI L, 20H
L <- 20H
2
7
MVI M, 67H
[HL] <- 67H
2
10
MOV B,M
B <- 67H
1
7
MVI L, 24H
L <- 24H
2
7
MOV M,B
[HL] <- 67H
1
7
INX H
HL < - HL + 1
1
6
MOV M, B
[HL] <- 67H
1
7
Data Transfer Instructions (LDA 16 bit address)
LDA 16 bit address
Load into Accumulator (A), the data from memory location whose 16 bit address is given in
instruction
E.g. LDA 2100H
Move into A the data from memory location 2100H A
[2100H]
LDA 374FH
Move into A the data from memory location 374FH A
[374FH]
Data Transfer Instructions (LDA)
LDA
16 BIT ADDRESS e.g. LDA 2100H
Size of Instruction :
3 Byte
T-States Required for fetching & execution:
M1- 04 T- states – Fetch op code
M2 -03 T-States – Fetch operand 1
M3 – 03 T States – Fetch operand 2
M4 - 03 T States – Read number from
memory location and store in A
Instruction Fetch & Execute Cycle for LDA 16 bit address
M1 Machine Cycle – Opcode Fetch, Decode
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode, 8085 knows this instruction’s size is 03
bytes and thus initiates operand fetch cycle M2
& M3
Instruction Fetch & Execute Cycle for LDA 16 bit address
M2 Machine Cycle – Operand Fetch M3 Machine Cycle – Operand Fetch
Operand
Operand
M4 Machine Cycle – Memory Read
8 bit no.
Data Transfer Instructions (STA 16 bit address)
STA 16 bit address
Store the contents of the Accumulator (A), into memory location whose 16 bit address is given in
instruction
E.g. STA 2100H
Move into A the data from memory location 2100H A
[2100H]
STA 374FH
Move into A the data from memory location 374FH A
[374FH]
Data Transfer Instructions (STA 16 bit
address)
STA
16 BIT ADDRESS e.g. STA 2100H
Size of Instruction :
3 Byte
T-States Required for fetching & execution:
M1- 04 T- states – Fetch op code
M2 -03 T-States – Fetch operand 1
M3 – 03 T States – Fetch operand 2
M4 - 03 T States – Store number in A
into memory location
Instruction Fetch & Execute Cycle for STA 16 bit address
M1 Machine Cycle – Opcode Fetch, Decode
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode, 8085 knows this instruction’s size is 03
bytes and thus initiates operand fetch cycle M2
& M3
Instruction Fetch & Execute Cycle for STA 16 bit address
M2 Machine Cycle – Operand Fetch M3 Machine Cycle – Operand Fetch
Operand
Operand
M4 Machine Cycle – Memory Write
A
Data Transfer Instructions (LXI Rp, 16 bit number)
LXI Rp, 16 bit number
Load into Register Pair (BC, DE, HL,SP) the 16 bit number given in the instruction itself
E.g. LXI H, 2100H
LXI B, 2420H
LXI D, 4142H
LXI SP, 3042H
Copy 21H into H, 00H into L
Copy 24H into B, 20H into C
Copy 41H into D, 42H into E
Copy 3042h in 16 bit Register SP
H
B
D
SP
21H L
21H C
21H E
3042H
00H
00H
00H
Data Transfer Instructions (LXI Rp, 16 bit number)
LXI Rp,
16 bit number e.g. LXI H, 2100H
Size of Instruction :
3 Byte
T-States Required for fetching & execution:
M1- 04 T- states – Fetch op code
M2 -03 T-States – Fetch operand 1
M3 – 03 T States – Fetch operand 2
The two operands fetched are stored in the Register pair directly without any
additional T-state
Instruction Fetch & Execute Cycle for LXI Rp, 16 bit number
M1 Machine Cycle – Opcode Fetch, Decode
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode, 8085 knows this instruction’s size is 03
bytes and thus initiates operand fetch cycle M2
& M3
Instruction Fetch & Execute Cycle for LXI Rp, 16 bit number
M2 Machine Cycle – Operand Fetch M3 Machine Cycle – Operand Fetch
The operands are stored in the Register
pair as they are fetched, thus no
additional T state is required for
execution of instruction
Operand
Operand
Write a program in 8085 Assembly language to read
two bytes of data from 2000H & 2001H and
exchange the two bytes
LDA 2000H
A < - [2000H]
3
13
LXI H, 2000H
HL < - 2000H
3
10
MOV B,A
B <- A
1
4
MOV B,M
B <- [2000H]
1
7
LDA 2001H
A <- [2001H]
3
13
LDA 2001H
A <- [2001H]
3
13
STA 2000H
[2000H] <- A
3
13
STA 2000H
[2000H] <- A
3
13
MOV A,B
A <- B
1
4
MOV A,B
A <- B
1
4
STA 2001H
[2001H] <- A
3
13
STA 2001H
[2001H] <- A
3
13
14
60
◦
A
5AH
2000H
77H
2001H
5AH
B
5AH
◦
60
14
Arithmetic Instructions
ADD R/M
A <- A + R/M
ADC
R/M + Carry
A <- A + R/M + Carry
ADI
8 bit number
A <- A + 8 bit number
ACI
8 bit number + Carry
A <- A + 8 bit number + Carry
SUB
R/M
A <- A - R/M
SBB
R/M – Carry
A <- A - R/M - Carry
SUI
8 bit number
A <- A - 8 bit number
SBI
8 bit number – Carry
A <- A - 8 bit number – Carry
INR
R/M
R <-R+1 M<- M+1
DCR
R/M
R <-R-1 M<- M-1
INX
Rp
Rp <- Rp + 1
DCX Rp
Rp <- Rp - 1
Arithmetic Instructions (ADD R/M)
ADD R/M
(ALL FLAGS ARE AFFECTED)
Add the 8 bit number in A with the 8 bit number in other register R or memory
E.g. ADD B
ADD E
ADD M
Register H
Register L
Add number in A with number in B and store answer in A
Add number in A with number in B and store answer in A
Add number in A with number in M and store answer in A
Register A
A+B
A+E
A + [HL]
2000H
5AH
2001H
2FH
If Register H has the value 20H & L has the value 03H and A has the value 0FH then 2002H
execution of ADD M will result in 0FH + 1FH and the answer 2EH will be stored in A
2003H
39H
2004H
22H
20H
03H
0FH
1FH
Arithmetic Instructions (ADD R/M)
ADD R/M
Size of Instruction : 01 Byte
T-States Required for fetching & execution:
◦ If other number is in Register then only 01 Machine cycle with 04 T states
◦ For other number is in Memory then : 02 Machine Cycles
M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand and perform
addition in same Machine cycle
Instruction Fetch & Execute Cycle for ADD R
M1 Machine Cycle – Opcode Fetch, Decode & Execute
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. As both
source and destination register are inside the
8085 so execution of instruction also is
completed in T4
Instruction Fetch Cycle for ADD M
M1 Machine Cycle – Opcode Fetch
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for ADD M
M2 Machine Cycle –
This is memory Read cycle
The content of memory location, whose
address is in HL, are brough into a temporary
register and then addition is performed and
answer stored in A.
H
L
Data
Flag register in 8085
1. CY Flag – Carry Flag - This flag becomes 1 when addition or subtraction of two bytes results in
generation of carry or borrow else it is 0. This carry or borrow is reflected in the Carry flag.
2. P Flag - Parity Flag - If after any arithmetic or logical operation the result has even parity, an
even number of 1 bits, the parity flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.
3. Z Flag – Zero Flag - If after any arithmetic or logical operation the result is zero, the Zero
flag is set i.e. 1, otherwise it is reset i.e. 0.
4. S Flag – Sign Flag – The S flag corresponds to the Most Significant Bit of the Accumulator
after arithmetic or logical operation is carried out. If signed number representation is being
used then a 1 would indicate that the number is negative and 0 would indicate that number is
positive
5. AC Flag – Auxiliary Carry Flag - If after any arithmetic operation there is a carry from the
lower nibble to the upper nibble then AC Flag is set i.e. becomes 1 else AC flag is reset i.e. 0
Let’s see how Flags are affected by ADD instruction
MVI A,09H
A= 5DH CY= 0
AC= 0
S= 0
Z= 0
P= 0
AC= 1
S= 0
Z= 0
P= 1
AC= 0
S= 0
Z= 0
P= 1
MVI B, 54H
ADD B
5D = 0101 1101
MVI A, 9FH
A= 11H CY= 1
MVI E, 72H
11H = 0001 0001
ADD E
9FH
72H
1
MVI A, 9FH
A= 2DH CY= 0
MVI B, 72H
SUB B
2D = 0010 1101
LXIH 2020H
H=20H L= 20H A= F8H CY= 1
MVI A, 7FH
F8 = 1111 1000
MVI M, 87H
SUB M
AC= 0
S= 1
Z= 0
P= 1
Arithmetic Instructions (ADC R/M)
ADC R/M
(ALL FLAGS ARE AFFECTED)
Add the 8 bit number in A with the 8 bit number in other register R or memory + Carry Flag
E.g. ADC B
ADC E
ADC M
Register H
20H
Register L
03H
Add number in A with number in B and store answer in A
Add number in A with number in B and store answer in A
Add number in A with number in M and store answer in A
Register A
0FH
If Register H has the value 20H & L has the value 03H and A has the value 0FH and
value of Carry Flag is 1 then execution of ADD M will result in 0FH + 1FH and the
answer 2FH will be stored in A
A + B + Carry Flag
A + E + Carry Flag
A + [HL] + Carry Flag
2000H
5AH
2001H
2FH
2002H
39H
2003H
1FH
2004H
22H
Arithmetic Instructions (ADC R/M)
ADC R/M
Size of Instruction : 01 Byte
T-States Required for fetching & execution:
◦ If other number is in Register then only 01 Machine cycle with 04 T states
◦ For other number is in Memory then : 02 Machine Cycles
M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand and perform
addition in same Machine cycle
Instruction Fetch & Execute Cycle for ADC R
M1 Machine Cycle – Opcode Fetch, Decode & Execute
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. As both
source and destination register are inside the
8085 so execution of instruction also is
completed in T4
Instruction Fetch Cycle for ADC M
M1 Machine Cycle – Opcode Fetch
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for ADD M
M2 Machine Cycle –
This is memory Read cycle
The content of memory location, whose
address is in HL, are brough into a temporary
register and then addition is performed and
answer stored in A.
H
L
Data
Arithmetic Instructions (ADI 8 bit number)
ADI 8 bit number
(ALL FLAGS ARE AFFECTED)
Add the 8 bit number in A with the 8 bit number given in the instructions
E.g. ADI 20H
Register A
0FH
Add number in A with the number 20H
A
A + 20H
Register A
2FH
If Register A has the value 0FH, then after execution of the instruction ADI 20H, the new value in A shall be 2FH.
Arithmetic Instructions (ADI 8 bit number)
ADI 8 bit number
Size of Instruction :
02 Byte
T-States Required for fetching & execution:
◦ 02 Machine Cycles
◦ M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand (8 bit number) and perform addition in same
Machine cycle
Instruction Fetch & Execute Cycle for ADI 8 bit number
M1 Machine Cycle – Opcode Fetch
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for ADI 8 bit number
M2 Machine Cycle – Operand Fetch &
Execution
This is memory Read cycle
Operand (8 bit number is fetched and
addition is performed in this Machine Cycle
itself
Data
Arithmetic Instructions (ACI 8 bit number)
ACI 8 bit number
(ALL FLAGS ARE AFFECTED)
Add the 8 bit number in A with the 8 bit number given in the instruction + Carry Flag
E.g. ACI 20H
Add number in A with the number 20H
CY
Register A
0FH
1
A
A + 20H + Carry Flag
Register A
After execution of ACI 20H
30H
CY
0
If Register A has the value 0FH and if carry flag is 1, then after execution of the instruction ACI 20H, the new
value in A shall be 30H and new value in Carry Flag shall be 0.
Arithmetic Instructions (ACI 8 bit number)
ACI 8 bit number
Size of Instruction :
02 Byte
T-States Required for fetching & execution:
◦ 02 Machine Cycles
◦ M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand (8 bit number) and perform addition in same
Machine cycle
Instruction Fetch & Execute Cycle for ACI 8 bit number
M1 Machine Cycle – Opcode Fetch
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for ACI 8 bit number
M2 Machine Cycle – Operand Fetch &
Execution
This is memory Read cycle
Operand (8 bit number is fetched and
addition is performed in this Machine Cycle
itself
Data
Arithmetic Instructions (SUB R/M)
SUB R/M
(ALL FLAGS ARE AFFECTED)
Subtract from the 8 bit number in A, the 8 bit number in other register R or memory
E.g. SUB B
SUB E
SUB M
Register H
Register L
Subtract from the number in A, number in B and store answer in A
Subtract from the number in A, number in E and store answer in A
subtract from the number in A, number in M and store answer in A
Register A
A-B
A-E
A - [HL]
2000H
5AH
2001H
2FH
If Register H has the value 20H & L has the value 03H and A has the value 0FH then 2002H
execution of SUB M will result in 0FH - 07H and the answer 08H will be stored in A
2003H
39H
2004H
22H
20H
03H
0FH
07H
Arithmetic Instructions (SUB R/M)
SUB R/M
Size of Instruction : 01 Byte
T-States Required for fetching & execution:
◦ If other number is in Register then only 01 Machine cycle with 04 T states
◦ For other number is in Memory then : 02 Machine Cycles
M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand and perform
addition in same Machine cycle
Instruction Fetch & Execute Cycle for SUB R
M1 Machine Cycle – Opcode Fetch, Decode & Execute
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. As both
source and destination register are inside the
8085 so execution of instruction also is
completed in T4
Instruction Fetch Cycle for SUB M
M1 Machine Cycle – Opcode Fetch
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for SUB M
M2 Machine Cycle –
This is memory Read cycle
The content of memory location, whose
address is in HL, are brough into a temporary
register and then subtraction is performed
and answer stored in A.
H
L
Data
Arithmetic Instructions (SBB R/M)
SBB R/M
(ALL FLAGS ARE AFFECTED)
Subtract from the 8 bit number in A, the 8 bit number in other register R or memory - Carry Flag
E.g. SBB B
SBB E
SBB M
Register H
20H
Subtract from number in A, number in B and store answer in A
Subtract from number in A, number in E and store answer in A
Subtract from number in A, number in M and store answer in A
Register L
03H
Register A
0FH
If Register H has the value 20H & L has the value 03H and A has the value 0FH and
value of Carry Flag is 1 then execution of SBB M will result in 0FH - 03H -1 and the
answer 0BH will be stored in A
A - B - Carry Flag
A - E - Carry Flag
A - [HL] - Carry Flag
2000H
5AH
2001H
2FH
2002H
39H
2003H
03H
2004H
22H
Arithmetic Instructions (SBB R/M)
ADC R/M
Size of Instruction : 01 Byte
T-States Required for fetching & execution:
◦ If other number is in Register then only 01 Machine cycle with 04 T states
◦ For other number is in Memory then : 02 Machine Cycles
M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand and perform
addition in same Machine cycle
Instruction Fetch & Execute Cycle for SBB R
M1 Machine Cycle – Opcode Fetch, Decode & Execute
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. As both
source and destination register are inside the
8085 so execution of instruction also is
completed in T4
Instruction Fetch Cycle for SBB M
M1 Machine Cycle – Opcode Fetch
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for SBB M
M2 Machine Cycle –
This is memory Read cycle
The content of memory location, whose
address is in HL, are brough into a temporary
register and then subtraction is performed
and answer stored in A.
H
L
Data
Arithmetic Instructions (SUI 8 bit number)
SUI 8 bit number
(ALL FLAGS ARE AFFECTED)
Subtract from the 8 bit number in A, the 8 bit number given in the instructions
E.g. SUI 20H
Register A
7FH
Subtract from number in A, the number 20H
A
A - 20H
Register A
5FH
If Register A has the value 7FH, then after execution of the instruction SUI 20H, the new value in A shall be 5FH.
Arithmetic Instructions (SUI 8 bit number)
SUI 8 bit number
Size of Instruction :
02 Byte
T-States Required for fetching & execution:
◦ 02 Machine Cycles
◦ M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand (8 bit number) and perform addition in same
Machine cycle
Instruction Fetch & Execute Cycle for SUI 8 bit number
M1 Machine Cycle – Opcode Fetch
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for SUI 8 bit number
M2 Machine Cycle – Operand Fetch &
Execution
This is memory Read cycle
Operand (8 bit number is fetched and
subtraction is performed in this Machine
Cycle itself
Data
Arithmetic Instructions (SCI 8 bit number)
SCI 8 bit number
(ALL FLAGS ARE AFFECTED)
Subtract from the 8 bit number in A, 8 bit number given in the instruction - Carry Flag
E.g. SCI 20H
Subtract from number in A, number 20H
CY
Register A
7FH
1
A
A -20H - Carry Flag
Register A
After execution of ACI 20H
5EH
CY
0
If Register A has the value 7FH and if carry flag is 1, then after execution of the instruction SCI 20H, the new
value in A shall be 5EH and new value in Carry Flag shall be 0.
Arithmetic Instructions (SCI 8 bit number)
SCI 8 bit number
Size of Instruction :
02 Byte
T-States Required for fetching & execution:
◦ 02 Machine Cycles
◦ M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch operand (8 bit number) and perform addition in same
Machine cycle
Instruction Fetch & Execute Cycle for SCI 8 bit number
M1 Machine Cycle – Opcode Fetch
T1 – 8085 puts the address of ROM memory
location from where the Op code is to be fetched
on higher and lower address bus
T2 – 8085 enables the /RD signal so that the
opcode can be read from ROM memory location
T3 – The opcode is fetched and stored in
Instruction Register (IR) in the 8085
T4 – Decoding of the Opcode takes place so that
8085 knows what is to be done next. Looking at
opcode 8085 understands that the operand is to
be fetched and that requires an additional
memory read cycle.
Instruction Execute Cycle for ACI 8 bit number
M2 Machine Cycle – Operand Fetch &
Execution
This is memory Read cycle
Operand (8 bit number is fetched and
subtraction is performed in this Machine
Cycle itself
Data
Arithmetic Instructions (INR R/M
INR R/M
(ALL FLAGS EXCEPT CARRY FLAG ARE AFFECTED)
Increment contents of Register or Memory by 1
E.g. INR C
INR M
Increment contents of register C by 1
C
C+1
Increment contents of memory location, whose address is in HL, by 1
[HL]
[HL] + 1
Arithmetic Instructions (DCR R/M
INR R/M
(ALL FLAGS EXCEPT CARRY FLAG ARE AFFECTED)
Decrement contents of Register or Memory by 1
E.g. INR C
INR M
Increment contents of register C by 1
C
C-1
Increment contents of memory location, whose address is in HL, by 1
[HL]
[HL] - 1
Arithmetic Instructions (INR R/M) / (DCR R/M)
INR R/M or DCR R/M
Size of Instruction :
01 Byte
T-States Required for fetching & execution:
◦
In case if INR/DCR R
◦ 01 Machine cycle of 4 T States
◦ In case of INR/DCR M
◦ M1- 04 T- states – Fetch op code
M2 -03 T-States - Fetch the data stored in memory location whose address is in HL, into the ALU and increment
M3 – 03 T-States – Incremented number is written back into memory location whose address is in HL
Arithmetic Instructions (INX Rp) / (DCX Rp)
INX Rp / DCX Rp
(No flags are affected)
Increment or decrementing contents of Register pair BC, DE, HL or SP
E.g. INX B
INX H
Increment contents of register BC by 1
BC
BC+1
Increment contents of memory location, whose address is in HL, by 1
HL
HL + 1
Write a program in 8085 assembly language to subtract the
number stored at 2001H from the number stored at 2002H
and store the difference in 2003H
LDA 2001H
3
13
LXI H 2002H
3
10
LXI H 2002H
3
10
MOV B,A
1
4
MOV A,M
1
7
MOV A,M
1
7
LDA 2002H
3
13
DCX H
1
6
DCX H
1
6
SUB B
1
4
SUB M
1
7
SUB M
1
7
STA 2003H
3
13
STA 2003H
3
13
INX H
1
6
11
47
9
43
INX H
1
6
MOV M,A
1
7
9
49
Write a program in 8085 assembly language to add the
number 54H to the numbers stored at memory location
2000H, 2001H & 2002H
LDA 2000H
LXI H, 2000H
LDA 2000H
ADI 54H
MVI A, 54H
MVI B, 54H
STA 2000h
ADD M
ADD B
LDA 2001H
MOV M,A
STA 2000H
ADI 54H
INX H
STA 2001H
MVI A, 54H
LDA 2002H
ADD M
ADI 54H
MOV M,A
STA 2002H
Write a program in 8085 assembly language to add the 03
numbers stored at memory location 2000H, 2001H & 2002H
and store the sum in 2003H
LXI H, 2000H
LDA 2000H
MOV A,M
MOV B,A
INX H
LDA 2001H
ADD M
ADD B
INX H
MOV B,A
ADD M
LDA 2002H
INX H
ADD B
MOV M,A
STA 2003H
Write a program in 8085 assembly language to add the 02 16
bit numbers stored at memory location 2000H, 2001H &
2002H, 2003H and store the sum in 2004H, 2005H
LDA 2000H
LDA 2000H
MOV B,A
LXI H, 2002
LDA 2002H
ADD M
ADD B
STA 2004H
STA 2004H
LDA 2001H
MOV B,A
LDA 2003H
ADC B
STA 2005H
LDA 2001H
LXI H, 2003H
ADC M
STA 2005H
Write a program in 8085 assembly language to add the 02 8
bit numbers stored at memory location 2000H & 2001H and
store the 16 bit sum in 2003H, 2002H
MVI A, 00H
2
7
STA 2003H
//Store 00H at 2003H
3
13
LDA 2000H
//Adding two bytes from 3
13
LDA 2000H
//Adding two bytes from 3
13
MOV B,A
//2000h & 2001H
1
4
MOV B,A
//2000h & 2001H
1
4
LDA 2001H
//Store sum at 2002H
3
13
LDA 2001H
//Store sum at 2002H
3
13
ADD B
1
4
ADD B
1
4
STA 2002H
3
13
STA 2002H
3
13
3
13
MVI A, 00H
2
7
2
ACI 00H
//Add carry bit to the
2
7
STA 2003H
//number at 2003H
3
13
18
74
LDA 2003H
ACI 00H
7
STA 2003H
//Add carry bit to the
//number at 2003H
3
13
24
96
Logic Instructions
ANA R/M
A <- A AND R/M
ANI
8 bit number
A <- A AND 8 bit number
XRA
R/M
A <- A XOR R/M
Effect on Flags
XRI
8 bit number
A <- A XOR 8 bit number
1. Zero flag (ZF), Sign flag (SF), Parity
ORA
ORI
R/M
8 bit number
A <- A OR R/M
A <- A OR 8 bit number SBI
CMA
A <- NOT A
CMP R/M
A - R/M
CPI
A - 8 bit number
8 bit number
CMC
COMPLEMENT CARRY FLAG
STC
CARRY FLAG=1
flag (PF) are affected
2. Carry flag & Overflow Flags are not
affected
3. Except NOT, all logical instructions
clear carry flag (CF) and overflow flag
(OF)
4. AC is undefined
Logic Instructions (Contd.)
RLC
RRC
RAL
RAR
Each binary bit of the accumulator is rotated left by one
Rotate the accumulator left
position. Bit D7 is placed in the position of D0 as well as in
the Carry flag. CY is modified according to bit D7.
Each binary bit of the accumulator is rotated right by one
Rotate the accumulator right
position. Bit D0 is placed in the position of D7 as well as in
the Carry flag. CY is modified according to bit D0.
Each binary bit of the accumulator is rotated left by one
Rotate the accumulator left through position through the Carry flag. Bit D7 is placed in the
carry
Carry flag, and the Carry flag is placed in the least
significant position D0. CY is modified according to bit D7.
Rotate the accumulator right
through carry
Each binary bit of the accumulator is rotated right by one
position through the Carry flag. Bit D0 is placed in the
Carry flag, and the Carry flag is placed in the most
significant position D7. CY is modified according to bit D0.
Logic Instructions (Contd.)
RLC
Rotate the accumulator left
CY = 0
RLC
A= 10011100
CY =1
A = 00111001
Each binary bit of the accumulator is rotated left by one
position. Bit D7 is placed in the position of D0 as well as in
the Carry flag. CY is modified according to bit D7.
A = 0010 0111
RLC
RLC
RLC
RLC
Logic Instructions (Contd.)
RRC
Rotate the accumulator right
A= 10011100
RRC
A = 01001110
CY = 0
CY = 0
Each binary bit of the accumulator is rotated right by one
position. Bit D0 is placed in the position of D7 as well as in
the Carry flag. CY is modified according to bit D0.
Logic Instructions (Contd.)
RAL
Each binary bit of the accumulator is rotated left by one
Rotate the accumulator left through position through the Carry flag. Bit D7 is placed in the
carry
Carry flag, and the Carry flag is placed in the least
significant position D0. CY is modified according to bit D7.
Logic Instructions (Contd.)
RAR
Rotate the accumulator right
through carry
Each binary bit of the accumulator is rotated right by one
position through the Carry flag. Bit D0 is placed in the
Carry flag, and the Carry flag is placed in the most
significant position D7. CY is modified according to bit D0.
Write a program in 8085 assembly language to perform
the Logic AND operation on the two numbers stored at
2000H & 2001H and store the answer in 2002H
LXI H, 2000H
MOV A,M
//Read number from 2000H and bring into A
INX H
ANA M
//Logical AND with number at 2001H
INX H
MOV M,A
//Store result at 2002H
Branching Instructions
There are three categories of Branching Instructions in the Instruction set of 8085:
1. Jump (unconditional and conditional)
2. Call (unconditional and conditional)
3. Return (unconditional and conditional)
OPCODE
OPERAND
EXPLANATION
EXAMPLE
JMP
address
Jumps to the address
JMP 2050
CALL
Address
Start Fetching Instruction from that address
CALL 2050
Return from Subroutine unconditionally
RET
RET
Branching Instructions (JMP)
OPCODE
OPERAND
EXPLANATION
EXAMPLE
JC
address
Jumps to the address if carry flag is 1
JC 2050
JNC
address
Jumps to the address if carry flag is 0
JNC 2050
JZ
address
Jumps to the address if zero flag is 1
JZ 2050
JNZ
address
Jumps to the address if zero flag is 0
JNZ 2050
JPE
address
Jumps to the address if parity flag is 1
JPE 2050
JPO
address
Jumps to the address if parity flag is 0
JPO 2050
JM
address
Jumps to the address if sign flag is 1
JM 2050
JP
address
Jumps to the address if sign flag 0
JP 2050
Branching Instructions (CALL)
OPCODE
OPERAND
EXPLANATION
EXAMPLE
CC
address
Call if carry flag is 1
CC 2050
CNC
address
Call if carry flag is 0
CNC 2050
CZ
address
Calls if zero flag is 1
CZ 2050
CNZ
address
Calls if zero flag is 0
CNZ 2050
CPE
address
Calls if parity flag is 1
CPE 2050
CPO
address
Calls if parity flag is 0
CPO 2050
CM
address
Calls if sign flag is 1
CM 2050
CP
address
Calls if sign flag is 0
CP 2050
Branching Instructions (RET)
OPCODE
OPERAND
EXPLANATION
EXAMPLE
RC
none
Return from the subroutine if carry flag is 1
RC
RNC
none
Return from the subroutine if carry flag is 0
RNC
RZ
none
Return from the subroutine if zero flag is 1
RZ
RNZ
none
Return from the subroutine if zero flag is 0
RNZ
RPE
none
Return from the subroutine if parity flag is 1
RPE
RPO
none
Return from the subroutine if parity flag is 0
RPO
RM
none
Returns from the subroutine if sign flag is 1
RM
RP
none
Returns from the subroutine if sign flag is 0
RP
Write a program in 8085 assembly language to add the 02 8
bit numbers stored at memory location 2000H & 2001H and
store the 16 bit sum in 2003H, 2002H
LDA 2000H
//Adding two bytes from 3
13
LDA 2000H
//Adding two bytes from
3
13
MOV B,A
//2000h & 2001H
4
MOV B,A
//2000h & 2001H
1
4
LDA 2001H
//Store sum at 2002H
3
13
ADD B
1
4
STA 2002H
3
13
LDA 2001H
//Store sum at 2002H
1
3
13
ADD B
1
4
STA 2002H
3
13
JC up
IF CY=1 then goto NXT else goto next instruction
MVI A, 00H
MVI A, 00H
2
7
STA 2003H
HLT
ACI 00H
//Add carry bit to the
2
7
STA 2003H
//number at 2003H
3
13
up: MVI A, 01H
18
74
STA 2003H
HLT
Write a program in 8085 assembly language to store the
number 00H in 5 memory locations starting from 2000H and
the program shall be stored from 1000H
LXI H, 2000H
A
MVI A, 00H
1000H
LXI H, 2000H
MOV M,A
1003H
MVI A, 00H
INX H
MOV M,A
INX H
MOV M,A
INX H
MOV M,A
10
00
2
1005H
MVI C, 05H
2
7
1007H
MOV M,A
1
7
1008H
INX H
1
6
1009H
DCR C
1
4
100AH
JNZ 1007H
3
7 / 10
100DH
HLT
1
4
C
00
7
INX H
MOV M,A
3
H
20
L
05
Z
1
Write a program in 8085 assembly language to add the 05
numbers stored starting from memory location 2000H and
store the 16 bit sum at 2005H & 2006H
A
MVI C,04H
MVI D,00H
LXI H,2000H
MOV A,M
AGAIN: INX H
ADD M
JNC AHEAD
INR D
AHEAD: DCR C
JNZ AGAIN
INX H
MOV M,A
INX H
MOV M,D
HLT
;Set counter for 4 loop
;Using as MSB
; Initialise to starting memory
;Get number from 2000H
;Point to next address
;Perform addition
;If carry then increment D
;Reduce counter
;repeat addition
;Point to LSB location
;Store LSB
;Point to MSB location
;Store
70
01
C
0
D
H
L
04
20
2000H
7F
2001H
22
Z
CY
2002H
36
CD
1
0
2003H
5F
2004H
4A
2005H
70
2006H
00
What will be the contents of Register A, HL, Memory and the
flags at the completion of following programs
A
LXI H, 2000H
MVI M, 07H
INX H
MVI M,5AH
LDA 2000H
ADD M
INX H
MOV M,A
HLT
61
C
H
L
02
20
2000H
07
2001H
5A
2002H
61
2003H
2004H
2005H
P
S
Z
AC
CY
0
0
0
1
0
What will be the contents of Register A, HL and the flags at
the completion of following programs
A
LXI H, 2000H
MVI D,09H
AGAIN: MVI M, 07H
INX H
DCR D
JNZ AGAIN
HLT
D
00
H
L
09
20
2000H
07
2001H
07
2002H
07
07
07
2003H
2004H
2005H
07
P
S
Z
AC
CY
0
0
1
0
0
Data Transfer Instructions (LHLD 16 bit
address)
LHLD 16 bit address
Load into Register L the data at memory location whose address is given in instruction and load into H
the data from the next memory location
E.g. If for the Memory locations given below execution of LHLD 2000H will result in 5A in L and 2F in
H.
Execution of LHLD 2003H will result in 1FH in L and 22H in H
L
(address)
H
(address +1)
Size of Instruction: 3 Bytes
Number of Machine Cycles to Fetch the Instruction: 03 M1, M2 & M3 (10 T)
Number of Machine Cycles to Execute the Instruction: 02 M4 & M5 (6 T)
2000H
5AH
2001H
2FH
2002H
39H
2003H
1FH
2004H
22H
Data Transfer Instructions (SHLD 16 bit
address)
SHLD 16 bit address
Store the data in L into memory location whose address is given in instruction and store number in H
into the next memory location
E.g. Suppose data in HL is 379FH
Then SHLD 2000H will result in 9FH in memory location 2000H and 27H in 2001H
(address)
L
(address +1)
H
Size of Instruction: 3 Bytes
Number of Machine Cycles to Fetch the Instruction: 03 M1, M2 & M3 (10 T)
Number of Machine Cycles to Execute the Instruction: 02 M4 & M5 (6 T)
2000H
5AH
2001H
2FH
2002H
39H
2003H
1FH
2004H
22H
Data Transfer Instructions (LDAX Rp)
LDAX Rp
Load into Accumulator the data from memory location whose address is given in the Register Pair
E.g. LDAX B
Suppose 16 bit number in BC is 2000H then the number stored in 2000H will be copied into
Accumulator
A
(BC)
Size of Instruction: 1 Bytes
Number of Machine Cycles to Fetch the Instruction: 01 M1 (4 T)
Number of Machine Cycles to Execute the Instruction: 01 M2 (3 T)
2000H
5AH
2001H
2FH
2002H
39H
2003H
1FH
2004H
22H
Data Transfer Instructions (STAX Rp)
STAX Rp
Copy the number in Accumulator to memory location whose address is given in the Register Pair
E.g. STAX B
Suppose 16 bit number in BC is 2000H and number in A is 7FH then 7FH will be transferred into
memory location 2000H
(BC)
A
Size of Instruction: 1 Bytes
Number of Machine Cycles to Fetch the Instruction: 01 M1 (4 T)
Number of Machine Cycles to Execute the Instruction: 01 M2 (3 T)
2000H
5AH
2001H
2FH
2002H
39H
2003H
1FH
2004H
22H
Data Transfer Instructions (XCHG)
XCHG
Exchange values of HL & DE register pair
E.g. STAX B
Suppose 16 bit number in HL is 2000H and DE is 5000H then after execution of XCHG HL will contain
5000H and DE will contain 2000H
Size of Instruction: 1 Bytes
Number of Machine Cycles to Fetch & Execute the Instruction: 01 M1 (4 T)
2000H
5AH
2001H
2FH
2002H
39H
2003H
1FH
2004H
22H
Arithmetic Instruction (DAA)
DAA
Used for addition of two BCD numbers
• If the LS hex digit in A is <= 9 and AC flag is 0, the LS hex digit value will not be altered.
• If the LS hex digit is >9, or if AC flag is set to 1, it adds 6 to the LS hex digit of A. If carry results, then it
increments the MS hex digit if this addition resulted in a carry to the MS digit position. In this process,
the Cy flag will be set to 1 if the MS hex digit was incremented from F to 0.
• If the MS hex digit is <= 9 and Cy flag is 0, the MS hex digit will not be altered, and Cy flag is reset to 0.
• If the MS hex digit is > 9, or if Cy flag is set to 1, it adds 6 to the MS hex digit of A and sets Cy flag to 1.
Size of Instruction: 1 Bytes
Number of Machine Cycles to Fetch & Execute the Instruction: 01 M1 (4 T)
DAA Instruction
Suppose there are 20 Chairs in a room, then in Hexadecimal we say 14H Chairs
In binary we represent the same as 0001 0100
In BCD we write 20 as 0010 0000
Suppose we add 15 more chairs in the same room, then in Hexadecimal the new count shall be 23H
14 H + 0FH = 23H
Now in BCD 20 Chairs = 0010 0000
15 Chairs = 0001 0101
Total chairs = 0011 0101 = 35
Suppose there are 09 chairs in the room = 0000 1001
Add 03 more chairs in the room
= 0000 0011
So total Chairs in the room
= 0000 1100 (Am I getting answer in BCD? – N
I fix the problem by adding 06H in the answer 0000 1100
0000 0110
0001 0010 (12)
Usage of DAA Instruction
MVI A, 09H
MVI B, 03H
ADD B
DAA
A=09H
B=03H
A=0CH
A=12H
0001 0010
Arithmetic Instruction (DAD Rp)
DAD Rp
16 bit addition of contents of HL + contents of Register Pair. Only Carry Flag is affected
HL
HL + Rp
E.g.
DAD B
HL
HL + BC
DAD D
HL
HL + DE
DAD H
HL
HL + HL
DAD SP
HL
HL + SP
Size of Instruction: 1 Bytes
Number of Machine Cycles to Fetch & Execute the Instruction: 01 M1 (6 T)
Memory Stack & Related Instructions
Stack is a designated part of the RAM connected to the microprocessor which behaves in the Last In
First Out mode of operation.
In 8085 microprocessor, the Stack behaves in reverse manner i.e the Top of the Stack is the highest
memory address and the memory addresses lower than that are used as part of stack. The address of
Top of Stack is stored in SP (stack Pointer) Register.
The instruction used to store data into the stack is PUSH which essentially results in two memory write
cycles as two byres are stored in the stack in response to PUSH.
The instruction used to get back data from the stack is POP which essentially results in two memory
read cycles as two bytes are read back from the stack in response to POP.
Memory Stack & Related Instructions (PUSH
Rp)
PUSH Rp
Store two bytes of the Register Pair into the stack. Higher byte is stored in memory whose address is
on lower than the ToS and the lower byte is stored in memory address even one lower than that.
E.g.
PUSH B
PUSH D
PUSH H
PUSH PSW
Stores B & C on stack
Stores D & E on stack
Stores H & L on stack
Stores A & FLAG REGISTER (PSW) on stack
In response to PUSH Rp steps are as follows:
1. Address in SP is reduced by 1 (SP < - SP-1)
2. Store Higher Byte in stack memory whose address is in SP
3. Address in SP is reduced by 1 (SP < - SP-1)
4. Store Lower Byte in stack memory whose address is in SP
Example of (PUSH Rp)
Suppose initial value of BC=917FH, SP=2FFFH
Execution of PUSH B instruction will result in following steps by CU of 8085
Step 1: SP=SP-1 i.e. SP=2FFEH
Step 2: Store B in this memory i.e. value in B (91H) will be stored in 2FFEH
Step 3: SP=SP-1 i.e. SP=2FFDH
Step 4: Store C in this memory i.e. value in C (7FH) will be stored in 2FFDH
2FFBH
5AH
2FFCH
2FH
2FFDH
39H
2FFEH
1FH
2FFFH
22H
Memory Stack & Related Instructions (POP Rp)
POP Rp
Read two bytes from the top of Stack and store them in the Register Pair. Data stored at memory
whose address is in SP Register will be read into Lower Register and the data stored at the next higher
memory location is read into Higher Register.
E.g.
POP B
POP D
POP H
POP PSW
Two bytes will be read from Stack memory and stored in B & C Register
Two bytes will be read from Stack memory and stored in D & E Register
Two bytes will be read from Stack memory and stored in H & L Register
Two bytes will be read from Stack memory and stored in A & FLAG REGISTER (PSW)
In response to POP Rp steps are as follows:
1. Data stored at memory location whose address is in SP is copied into the lower Register of Register Pair
2. Address in SP is incremented by 1 (SP < - SP+1)
3. Data stored at memory location whose address is in SP is copied into the Higher Register of Register Pair
4. Address in SP is incremented by 1 (SP < - SP+1)
Example of (POP Rp)
Suppose initial value of BC=917FH, SP=2FFDH and value in 2FFD is 39H and
2FFBH
5AH
Value in 2FFEH is 1FH
2FFCH
2FH
Execution of POP B instruction will result in following steps by CU of 8085:
2FFDH
39H
2FFEH
1FH
2FFFH
22H
Step 1: Copy into C the contents of memory location whose address is in
SP (2FFDH) i.e. the number 39H is copied into C
Step 2: SP=SP+1 i.e. SP=2FFEH
Step 3: Copy into C the contents of memory location whose address is in SP (2FFEH)
i.e. the number 1FH is copied into B
Step 4: SP=SP+1 i.e. SP=2FFFH
So new value in BC=1F39H
The contents of Accumulator and Zero Flag at the end of execution
of following program are 39h, 1___________
BC = 2957H
DE = 3962H
2FF9H
62H
2FFA
H
2FFBH
39H
2FFCH
29H
2FFDH
YYH
BC = 2957H
2FFEH
XXH
HL = XXYYH
2FFFH
22H
A FLAGS = XX YYH
A FLAGS = 39 62H
SP
57H
Write a program in 8085 assembly language to add the 02 16 bit
numbers stored at memory location 2000H, 2001H & 2002H, 2003H and
store the sum in 2004H, 2005H
LHLD 2000H
//Read 2000H into L, 2001H into H
XCHG
//Store HL in DE i.e. first 16 bit number in DE
LHLD 2002H
//Read 2002H into L, 2003H into H
DAD D
//HL=HL+DE
SHLD 2004H
//Store 16 bit answer at 2004H and 2005H
Write a program in 8085 assembly language to add the 02 16 bit
numbers stored at memory location 2000H, 2001H & 2002H, 2003H and
store the sum in 2004H, 2005H & 2006H
Write a program in 8085 assembly language unpack the packed 2 digit
BCD number stored at memory location 2000H and store the two
unpacked BCD numbers at 2001H & 2002H
2000H
57
0101 0111
2001H
05
0000 0101
2002H
07
0000 0111
Mask off the Upper Nibble
AND 57 with 0F
0101 0111
0000 1111
0000 0111
Mask off the Lower Nibble
AND 57 with F0
0101 0111
1111 0000
0101 0000
= 0000 0101
Write a program in 8085 assembly language unpack the packed 2 digit
BCD number stored at memory location 2000H and store the two
unpacked BCD numbers at 2001H & 2002H
LDA 2000H
ANI 0F
STA 2002H
LDA 2000H
ANI F0
RLC
RLC
RLC
RLC
STA 2001H
Write a SUBROUTINE in 8085 assembly language which unpacks the packed
2 digit BCD number passed to it in H and returns the two unpacked BCD
numbers in H & L registers. Now write a program to read packed 2 digit
BCD number from 2000H and store unpacked 2 digits in 2001H and 2002H.
Call the subroutine for the unpacking
LDA 2000H
Main Program
ANI 0x0F
LXI SP, 2FFFH
STA 2002H
LDA 2000H
LDA 2000H
MOV H,A
ANI 0xF0
CALL UNPACK
RLC
MOV A,H
RLC
RLC
RLC
STA 2001H
STA 2001H
MOV A,L
STA 2002H
HLT
Subroutine Called UNPACK
//This subroutine will accept a packed 2 digit BCD
number in Register H, then unpack the two BCD digits and
store them in Register H & L. Then return to Calling
Program
MOV B,H
MOV A,B
ANI 0x0F
MOV H,A
MOV A,B
ANI 0xF0
RLC
RLC
RLC
RLC
MOV L,A
RET
Write a program in 8085 assembly language to transfer 10 bytes of
data starting from memory location 2000H onwards to memory
location starting from 3000H onwards
LXI B, 2000H
//Initialize BC to 2000H
10 X 1 =10
LXI D, 3000H
//Initialize DE to 3000H
10 X 1 = 10
MVI H, 0x0A
//Set counter for 10 times
7 X 1 =7
AGAIN: LDAX B
//Read one byte from memory whose address is in BC
7 X 10=70
STAX D
//Store the byte in memory whose address is in DE
7 X 10 = 70
INX B
//Increment both pointers
6 X 10 =60
INX D
DCR H
JNZ AGAIN
HLT
6 X 10 = 60
//Reduce counter and check to run the loop 10 times
4 X 10 = 40
10 X9 + 7 X 1 = 97
4 X 1 =4
Write a program in 8085 assembly language to transfer 10 bytes of
data starting from memory location 2000H onwards to memory
location starting from 3000H onwards
LXI H, 2000H
//Initialize BC to 2000H
LXI D, 3000H
//Initialize DE to 3000H
MVI C, 0x0A //Set counter for 10 times
AGAIN: MOV A,M
XCHG
MOV M,A
//Read one byte from memory
//Exchange HL & DE
//Increment both pointers
XCHG
INX H
INX D
DCR C
JNZ AGAIN
HLT
//Reduce counter and check to run the loop 10 times
Write a program in 8085 assembly language to add the 05
numbers stored starting from memory location 2000H and
store the 16 bit sum at 2005H & 2006H
A
MVI C,04H
MVI D,00H
LXI H,2000H
MOV A,M
AGAIN: INX H
ADD M
JNC AHEAD
INR D
AHEAD: DCR C
JNZ AGAIN
INX H
MOV M,A
INX H
MOV M,D
HLT
;Set counter for 4 loop
;Using as MSB
; Initialise to starting memory
;Get number from 2000H
;Point to next address
;Perform addition
;If carry then increment D
;Reduce counter
;repeat addition
;Point to LSB location
;Store LSB
;Point to MSB location
;Store
70
01
C
0
D
H
L
04
20
2000H
7F
2001H
22
Z
CY
2002H
36
CD
1
0
2003H
5F
2004H
4A
2005H
70
2006H
00
Write a SUBROUTINE in 8085 assembly language which unpacks the packed
2 digit BCD number passed to it in H and returns the two unpacked BCD
numbers in H & L registers. Now write a program to read packed 2 digit
BCD number from 2000H and store unpacked 2 digits in 2001H and 2002H.
Call the subroutine for the unpacking
LDA 2000H
Main Program
ANI 0x0F
LXI SP, 2FFFH
STA 2002H
LDA 2000H
LDA 2000H
MOV H,A
ANI 0xF0
CALL UNPACK
RLC
MOV A,H
RLC
RLC
RLC
STA 2001H
STA 2001H
MOV A,L
STA 2002H
HLT
Subroutine Called UNPACK
//This subroutine will accept a packed 2 digit BCD
number in Register H, then unpack the two BCD digits and
store them in Register H & L. Then return to Calling
Program
MOV B,H
MOV A,B
ANI 0x0F
MOV H,A
MOV A,B
ANI 0xF0
RLC
RLC
RLC
RLC
MOV L,A
RET
Program Counter (PC)
A
010AH
H
0100H
LXI SP, 2FFFH
0103H
LDA 2000H
0106H
MOV H,A
0107H
CALL 0200H
010AH
MOV A,H
010BH
STA 2001H
010EH
MOV A,L
010FH
STA 2002H
0112H
HLT
SP
2FFFH
38
C
0
03
Main Program
Instruction
B
L
08
Address
03
Address
Instruction
0200H
MOV B,H
0201H
MOV A,B
0202H
ANI 0x0F
0204H
MOV H,A
2000H
38
0205H
MOV A,B
2001H
00
0206H
ANI 0xF0
2002H
00
0208H
RLC
0209H
RLC
2FFCH
5F
020AH
RLC
2FFDH
0A (PCL)
020BH
RLC
2FFEH
01 (PCH)
020CH
MOV L,A
2FFFH
00
020DH
RET
Program Counter (PC)
010AH
A
H
B
03
38
03
Main Program
Subroutine Unpack
Instruction
Address
Instruction
0200H
PUSH B
0300H
RLC
0201H
MOV B,H
0301H
RLC
0202H
MOV A,B
0302H
RLC
0203H
ANI 0x0F
0304H
RLC
0205H
MOV H,A
0305H
RET
Instruction
0100H
LXI SP, 2FFFH
2000H
38
LDA 2000H
2001H
00
0106H
MOV H,A
2002H
00
0107H
CALL 0200H
010AH
MOV A,H
2FF9H
00
010BH
STA 2001H
0206H
MOV A,B
2FFAH
00
010EH
MOV A,L
0208H
ANI 0xF0
2FFBH
0B (PCL)
010FH
STA 2002H
020BH
CALL 0300H
2FFCH
02 (PCH)
0112H
HLT
020EH
MOV L,A
2FFDH
0A (PCL)
020FH
POP B
2FFEH
01 (PCH)
0210H
RET
2FFFH
00
2FFFH
Subroutine SWAP
Address
Address
SP
0
L
08
0103H
C
Interrupts in 8085
What are Interrupts?
Types of Interrupts
◦ Hardware Interrupts
◦ Software Interrupts
Interrupt Architecture of 8085
Interrupt Vector addresses and priority
SIM & RIM Instructions
Servicing of Interrupts
Writing Interrupt Service Routines
Classification of Interrupts in 8085
Hardwar & Software Interrupts in 8085
Hardware Interrupts
Some pins on the 8085 allow, peripheral device to interrupt the main program for I/O operations. When an interrupt
occurs, the 8085 completes the instruction it is currently executing and transfers the program control to a
subroutine’ that services the peripheral device. Upon completion of the service routine, the CPU returns to the main
program. These Types of Interrupts in 8085, where CPU pins are used to receive interrupt requests, are
called hardware interrupts. Hardware Interrupts in 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5, INTR
Software Interrupts
In software interrupts, the cause of the interrupt is an execution of the instruction. These are special instructions
supported by the microprocessor. After execution of these instructions microprocessor completes the execution of
the instruction it is currently executing and transfers the program control to the subroutine program. Upon
completion of the execution of the subroutine program, program control returns to the main program. Software
Interrupts in 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7
Interrupt Architecture of 8085
What happens because of Occurrences of Interrupt?
1. The instruction being executed by the Microprocessor at that time is completed
2. The current value of Program Counter is PUSHED on to the stack automatically
3. The Vector address of the Interrupt is loaded into the Program counter automatically
4. The microprocessor fetches the next instruction from this Vector address where the
Interrupt Service Routine (subroutine) is stored
5. On completion of ISR, the RET instruction is executed
6. Two bytes from top of the stack are POP into the Program counter
7. Execution of the Main program will continue.
Questions to try about sub-routines
1.
Create a subroutine which finds out the highest and number out of the two numbers passed to it. It will
accept the two numbers in B & C and return the highest number in B. Also write a Main program to test the
sub-routine.
2.
Create a subroutine which finds out the highest and lowest number out of the 10 numbers stored in memory
whose starting address is passed to the sub-routine in HL Register. The subroutine will return the highest
and smallest number in register H & L. Also write a Main program to test the sub-routine.
3.
Create a subroutine which will generate a delay of 250 microseconds. Also write a Main program to test the
sub-routine.
4.
Create a subroutine which performs the multiplication of two 8 bit numbers returns the 16 bit product. The
subroutine accepts two 8 bit numbers in register H & L and returns their 16 bit product in register H&L. Also
write a Main program to test the sub-routine.
5.
Create a subroutine which performs division of one 8 bit number by another, The subroutine accepts the
dividend 8 bit number in H and the 8 bit divisor in L and returns the quotient in H & remainder in L.
6.
Write a program to transmit a 8 bit number using SOD pin and then receive a 8 bit number using SID pin.
Lab Questions
1.
Write a program to find the sum of 2, 02 digit Packed BCD numbers at 2000H & 2001H and
store their BCD sum at 2003H.
2.
Write a program to read packed 2 digit BCD number from 2000H and store unpacked 2 digits
in 2001H and 2002H. The program will call a subroutine for the unpacking which unpacks
the packed 2 digit BCD number passed to it in H and returns the two unpacked BCD numbers
in H & L registers.
3.
Write a program which finds out the highest and smallest number out of 10 numbers stored
starting from memory location 2000H and store the highest number at 200AH and smallest
at 200BH. The program will call a subroutine which finds out the highest and lowest number
out of the 10 numbers stored in memory whose starting address is passed to the sub-routine
in HL Register. The subroutine will return the highest and smallest number in register H & L.
4.
Create a subroutine which will generate a delay of 250 microseconds. Also write a Main
program to test the sub-routine.
Write a program to find the sum of 2, 02 digit Packed BCD numbers
at 2000H & 2001H and store their BCD sum at 2003H.
LDA 2000H
MOV B,A
LDA 2001H
ADD B
DAA
STA 2002H
Write a program to read packed 2 digit BCD number from 2000H and store unpacked 2 digits in
2001H and 2002H. The program will call a subroutine for the unpacking which unpacks the
packed 2 digit BCD number passed to it in H and returns the two unpacked BCD numbers in H &
L registers.
LXI SP, 2FFFH
MOV B,H
LDA 2000H
MOV A,H
MOV H,A
ANI 0x0FH
CALL UNPACK
MOV A,L
STA 2001H
MOV L, A
MOV A, B
ANI 0xF0
RLC
MOV A,H
RLC
STA 2002H
RLC
HLT
RLC
MOV H,A
RET
Write a program which finds out the highest and smallest number out of 10 numbers stored
starting from memory location 2000H and store the highest number at 200AH and smallest at
200BH. The program will call a subroutine which finds out the highest and lowest number out
of the 10 numbers stored in memory whose starting address is passed to the sub-routine in HL
Register. The subroutine will return the highest and smallest number in register H & L.
PUSH H
//Store HL
MOV A,M
MOV A,M
//First no in A
MVI C, 0x09
MVI C, 0x09
//counter
AGAIN1: INX H
AGAIN: INX H
//Next location
CMP M
CMP M
//A-[HL]
JC NXTNUM1
STA 200AH
JNC NXTNUM
//A must be bigger
MOV A,M
MOV A,L
MOV A,M
//Else move no from memory into A
NXTNUM1: DCR C
STA 200BH
NXTNUM: DCR C //Check if all comparisons done
JNZ AGAIN1
HLT
JNZ AGAIN
//Jump if all comparisons not over
MOV L,A
MOV D,A
//Store higher no in D
MOV H,D
POP H
//Get starting address back in HL
RET
LXI SP,2FFFH
LXI H, 2000H
CALL HILO
MOV A, H
8085 Instructions related to Interrupts
1.Enable Interrupt (EI) – The interrupt enable flip-flop is set and all interrupts are
enabled following the execution of next instruction followed by EI. No flags are
affected. After a system reset, the interrupt enable flip-flop is reset, thus disabling the
interrupts. This instruction is necessary to enable the interrupts again (except TRAP).
2.Disable Interrupt (DI) – This instruction is used to reset the value of enable flip-flop
hence disabling all the interrupts. No flags are affected by this instruction.
8085 Instructions related to Interrupts
SIM (Set Interrupt Mask)
It is used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by setting various bits to form masks or
generate output data via the Serial Output Data (SOD) line. First the required value is loaded in accumulator then SIM will
take the bit pattern from it.
8085 Instructions related to Interrupts
RIM (Read Interrupt Mask)
This instruction is used to read the status of the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into
the A register a byte which defines the condition of the mask bits for the interrupts. It also reads the condition
of SID (Serial Input Data) bit on the microprocessor.
An Infrared based detection system is connected at the Entry Door of a
classroom and generates a pulse signal whenever a person enters the class.
This signal is connected to the TRAP Pin of 8085. Write a program in assembly
language of 8085 to count the number of students in the class and store the
same at memory location 2000H. Write ISR of TRAP accordingly.
MAIN PROGRAM
Interrupt Service
Routine (ISR for
TRAP)
0300H LXI SP, 2FFFH
0400H LDA 2000H
0303H EI
0403H INC A
0304H MVI A, 00H
0404H STA 2000H
0306H STA 2000H
0407H RET
0024H JMP 0400H
0309H JMP 0309H
An Infrared based detection system is connected at the Entry Door of a classroom and
generates a pulse signal whenever a person enters the class. This signal is connected to the
TRAP Pin of 8085. Similarly the circuit from exit door also generates a pulse which is connected
to RST 5.5 Interrupt. Write a program in assembly language of 8085 to count the number of
students in the class and store the same at memory location 2000H. Write ISR of TRAP and RST
5.5 accordingly.
002CH JMP 0500H
Interrupt Service
Routine (ISR for
TRAP)
Interrupt Service
Routine (ISR for RST
5.5)
MAIN PROGRAM
0400H LDA 2000H
0500H LDA 2000H
0300H LXI SP, 2FFFH
0403H INC A
0503H DCR A
0303H EI
0404H STA 2000H
0504H STA 2000H
0304H MVI A, 00H
0407H RET
0507H RET
0024H JMP 0400H
0306H STA 2000H
0309H JMP 0309H
Write a small code snippet of 8085 assembly language to Enable RST 7.5 & RST 6.5, Reset RST
7.5 and Disable RST 5.5
LXI SP, 2FFFH
MVI A, 19H
SIM
EI
Write code to transmit an 8 bit number on SOD pin of 8085.
LDA 2000H
MOV B,A
MVI C, 08H
AGAIN: MOV A,B
RLC
MOV B,A
JC SENDONE
MVI A, 40H
SIM
JMP NEXT
SENDONE: MVI A, C0H
SIM
NEXT: DCR C
JNZ AGAIN
HLT
Write a small code snippet of 8085 assembly language to Enable RST 7.5, RST 6.5 & RST 5.5. An
external pulse signal is connected to RST 5.5 and the number of pulses counted will be
automatically updated at memory location 2000H. Whenever RST 6.5 interrupt occurs, it will
disable RST 5.5 and whenever RST 7.5 occurs, it will enable RST 5.5. Write Main program and
the ISR of RST 5.5, RST 7.5 & RST 6.5 accordingly.
0034H JMP 0500H
Interrupt Service
Routine (ISR for RST
5.5)
Interrupt Service
Routine (ISR for RST
6.5)
Interrupt Service
Routine (ISR for RST
7.5)
003CH JMP 0600H
0400H LDA 2000H
0500H MVI A, 09H
0600H MVI A, 08H
0403H INC A
0502H SIM
0602H SIM
MAIN PROGRAM
0404H STA 2000H
0503H RET
0603H RET
0300H LXI SP, 2FFFH
0407H RET
002CH JMP 0400H
0303H EI
0304H MVI A, 00H
0306H STA 2000H
0309H JMP 0309H
Write a program in 8085 assembly language to copy 15 bytes of data from2000H
onwards to 3000H onwards in reverse
Write a program in 8085 which accepts an 8 bit number from memory location 2000H
and returns the packed BCD equivalent in 2001H & 2002H. The main program should
call a subroutine which accepts the 8 bit numbers in H and returns the answer in H&L
Registers
AGAIN:
LXI H, 2000H
LXI B, 300EH
//Initialize source pointer
//Initialize destination pointer
MVI D, 0x0F
//Initialize counter to count the number of bytes moved
MOV A,M
STAX B
INX H
DCX B
//Copy number from source address
//Copy number to destination address
//Increment source address
//Decrement destination address
DCR D
JNZ AGAIN
HLT
//Check if all numbers transferred, else repeat the process
Write a program in 8085 which accepts an 8 bit binary number from memory location
2000H and returns the packed BCD equivalent in 2001H & 2002H. The main program
should call a subroutine which accepts the 8 bit numbers in H and returns the answer
in H&L Registers
2000H FF
Step 1:
Step 2:
Step 3:
Step 4:
2002H
divide FF by 100
Store Quotient in 2001H
Divide Remainder by 10
Rotate the quotient left by 4 times and OR with remainder and store in
IC 8255 Programmable Peripheral Interface
IC 8255 Programmable Peripheral Interface
IC 8255 is a 40 Pin IC which contains the following
1. Parallel Port A (8 bits PA7-PA0, which can be configured as Output Port or Input Port)
2. Parallel Port B (8 bits PB7-PB0, which can be configured as Output Port or Input Port)
3. Parallel Port C (8 Bits) divided into two Port of 4 bit each Port CLower (PC3-PC0) & Port CUpper (PC7-PC4)
4. Control Register CR (8 bit) using which it is possible to configure the Ports of IC 8255
◦ 8255 Can work in I/O Mode (Input/Output Mode) or BSR Mode (Bit Set Reset Mode)
◦ In I/O Mode, 8255 can work in Mode 0, 1 or 2
◦ Mode 0 –In this mode all the three ports (port A, B, C) can work as simple input or simple output Port. In this
mode there is no interrupt handling capacity.
◦ Mode 1 – Handshake I/O mode or strobbed I/O mode. In this mode either port A or port B can work as simple
input port or simple output port, and port C bits are used for handshake signals before actual data transmission.
It has interrupt handling capacity and input and output are latched.
◦ Mode 2 – Bi-directional data bus mode. In this mode only port A works, and port B can work either in mode 0 or
mode 1. 6 bits port C are used as handshake signals. It also has interrupt handling capacity
IC 8255 PPI – Control Register
IC 8255 PPI – How to Access Ports & CR
CS/
A1
A0
Selection
0
0
0
PORT A
0
0
1
PORT B
0
1
0
PORT C
0
1
1
Control
Register
1
X
X
No Selection
Interface two LEDs to 8085 microprocessor through Port A of IC
8255. Write program such that they blink alternately infinite number
of times.
A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
1
LD1
RD/
LD2
WR/
A1
A0
A2
A3
A4
A5
A6
A7
AD7-AD0
of 8085
Port A
Port B
Port C
CR
00H
01H
02H
03H
Interface two LEDs to 8085 microprocessor through Port A of IC
8255. Write program such that they blink alternately infinite number
of times.
MVI A, 80H
OUT 03H
AGAIN:
//Value 80H stored in Control Register of 8255
MVI A, 80H
OUT 00H
//Value 80H stored in Port A i.e. LD2 ON and LD1 OFF
CALL DELAY
//Call delay subroutine for delay of 500 milliseconds
MVI A, 40H
OUT 00H
CALL DELAY
JMP AGAIN
//Value 40H stored in Port A i.e. LD2 OFF and LD1 ON
Interface two LEDs and 01 Switch to 8085 microprocessor through Port A of IC 8255. Write
program such that LD1 is ON and LD2 OFF if key is pressed else LD1 is OFF and LD2 is ON
+5V
SW1
LD1
RD/
LD2
WR/
A1
A0
A2
A3
A4
A5
A6
A7
AD7-AD0
of 8085
Port A
Port B
Port C
CR
00H
01H
02H
03H
Interface two LEDs and 01 Switch to 8085 microprocessor through
Port A of IC 8255. Write program such that LD1 is ON and LD2 OFF if
key is pressed else LD1 is OFF and LD2 is ON
MVI A, 82H
OUT 03H
AGAIN: IN 01H
RLC
JC NEXT
MVI A, 80H
OUT 00H
JMP AGAIN
//Value 82H stored in Control Register of 8255 so that Port A
// & C are output Ports while Port B is configured as I/P Port
//Read the Data at Port B and store in Accumulator
//Copy A7 bit into Carry flag
//If Switch is pressed then goto NEXT
//Turn ON LD1 and turn OFF LD2
NEXT: MVI A, 40H
OUT 00H
JMP AGAIN
//Turn OFF LD1 and turn ON LD2
Interface 01 Common Cathode 7 segment LED Display to 8085 microprocessor through Port B
of IC 8255. Write program to display count from 0 to 9 when the switch is pressed every time.
+5V
SW1
Port A
Port B
Port C
CR
RD/
A1
A0
A2
A3
A4
A5
A6
A7
WR/
AD7-AD0
of 8085
00H
01H
02H
03H
7 Segment Interface and Codes to Display
Count
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
A B C D E F G DP
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
0: 1 1 1 1 1 1 0 0 = FC
1: 0
1
1
0
0
0
0
0
=60
2: 1
1
0
1
1
0
1
0
= DA
3:
Interface 01 Common Cathode 7 segment LED Display to 8085 microprocessor through
Port B of IC 8255. Write program to display count from 0 to 9 when the switch is pressed
every time.
0500H MVI A, 90H
0502H OUT 03H
0504H MVI C, 09H
0506H LXI H, 0600H
0509H MOV A, M
050AH OUT 01H
050CH CALL DELAY
050FH IN 00H
0511H RLC
0513H JNC 050FH
0515H INX H
0516H DCR C
0517H JNZ 0509H
051AH JMP 0504H
//Value 90H stored in Control Register of 8255 so that Port B
// & C are output Ports while Port A is configured as I/P Port
//Initialize Counter
//Start address of memory location where display codes are stored
//Put Display Code on LED Display i.e. Port B
//Read the Data at Port A and store in Accumulator
//Copy A7 bit into Carry flag
//If Switch is Not pressed then check for switch press again
//Point to next display code
//Put Next Display Code on Port
//Start from Displaying Zero
0600H 0xFC
0604H
0608H
0601H 0x60
0605H
0609H
0602H 0xDA
0606H
0603H
0607H
Write program to multiply two 8 bit numbers stored at memory location 2000H & 2001H
and store the 16 bit product at 2002H & 2003H. The multiplication shall be done by a
subroutine which shall accept the two input numbers in H&L and return the product in
H&L.
Main Program
Subroutine MULT
LXI SP, 2FFFH
LHLD 2000H
CALL MULT
SHLD 2002H
HLT
ADD_AGAIN:
CONTINUE:
MOV A,H
CMI 00H
JZ STOR_ZERO
MOV A,L
CMI 00H
JZ STOR_ZERO
MOV C, L
MOV A,H
MOV B,A
MVI H,00H
MVI L,00H
ADD L
JC INC_MSB
MOV L,A
MOV A,B
DCR C
JNZ ADDAGAIN
RET
Subroutine MULT
INC_MSB:
INR H
JMP CONTINUE
STOR_ZERO:
MVI H,00H
MVI L,00H
RET
Write program to DIVIDE 8 bit number stored at memory location 2000H BY 8 BIT
NUMBER stored at 2001H and store the Quotient at 2002H & remainder at 2003H. The
division will be done by a subroutine which shall accept the Divisor in H, Dividend in L and
return Quotient
in H and
Subroutine
DIVRemainder in L.
Main Program
LXI SP, 2FFFH
LHLD 2000H
CALL DIV
SHLD 2002H
HLT
MOV A,L
CMI 00H
JZ EXIT
MVI C,00H
MOV A,H
CMP L
JC EXIT1
EXIT:
MVI H,00H
MVI L,00H
RET
EXIT1: MOV L,H
MOV H,C
RET
8086 Microprocessor – 16 Bit Microprocessor
1.
40 Pin IC
2.
16 Data Lines Multiplexed with 16 lines of address Bus (AD15-AD0)
3.
Total 20 Address Lines so can be interfaced with 1MB memory
4.
Can work in Min/Max Mode (Single Processor or Multiprocessor Environment)
5.
02 Hardware Interrupts TRAP, INTR but total 256 Interrupts feasible
6.
Internal Oscillator Circuit Not Available. External Clock to be connected
7.
To CLK Pin (Maximum 10MHz)
8.
It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage,
which improves performance.
10. Fetch stage can prefetch up to 6 bytes of instructions and stores
them in the queue.
BIU: Bus Interface Unit EU: Execution Unit
8086 Execution Unit (U)
EU (Execution Unit) Execution unit gives instructions to BIU stating from where to fetch the
data and then decode and execute those instructions. Its function is to control operations on
data using the instruction decoder & ALU. EU has no direct connection with system buses as
shown in the above figure, it performs operations over data through BIU.
ALU It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
Control Unit: Controls are functional units of the 8086 Microprocessor
Flag Register It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status
according to the result stored in the accumulator. It has 9 flags and they are divided into 2
groups − Conditional Flags and Control Flags.
General Purpose Registers: AH & AL (AX), BH & BL (BX), CH & CL (CX), DH & DL (DX) – These
Registers can work as individual 8 bit Registers or together a 16 bit Registers
Pointer & Index Registers: Base Pointer (BP), Stack Pointer (SP), Source Index (SI),
Destination Index (DI)
8086 Bus Interface Unit (BIU)
BIU (Bus Interface Unit) BIU takes care of all data and addresses transfers on the buses for the EU like sending
addresses, fetching instructions from the memory, reading data from the ports and the memory as well as writing
data to the ports and the memory. EU has no direction connection with System Buses so this is possible with the
BIU. EU and BIU are connected with the Internal Bus.
It has the following functional parts −
Instruction queue − BIU contains the instruction queue. BIU gets up-to 6 bytes of next instructions and stores them
in the instruction queue. When EU executes instructions and is ready for its next instruction, then it simply reads the
instruction from this instruction queue resulting in increased execution speed.
Fetching the next instruction while the current instruction executes is called pipelining.
Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of instructions and data in
memory, which are used by the processor to access memory locations. It also contains 1 pointer register IP, which
holds the address of the next instruction to executed by the EU.
CS − It stands for Code Segment. It is used for addressing a memory location in the code segment of the memory,
where the executable program is stored.
DS − It stands for Data Segment. It consists of data used by the program and is accessed in the data segment by an
offset address or the content of other register that holds the offset address.
SS − It stands for Stack Segment. It handles memory to store data and addresses during execution.
ES − It stands for Extra Segment. ES is additional data segment, which is used by the string to hold the extra
destination data.
Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to be executed.
Pipelining & The Instruction Queue in 8086
Fetching the next instruction while the current instruction executes is known as pipelining
This is done to speed up program execution, the bus interface unit fetches as many as 6
instruction bytes ahead of time from the memory and these are held for execution unit in the
(FIFO) group of registers called QUEUE.
The BIU can fetch instruction byte while EU is decoding or executing an instruction which
does not require the use of buses. When is EU is ready for the next instruction, it simply reads
the instruction from queue in the BIU.
the Queue is filled when at least two bytes are empty as 8086 has a 16 bit data bus
Flag Register 8086
• Carry flag − This flag indicates an overflow condition for arithmetic operations.
• Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from lower nibble (i.e. D0 – D3) to
upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The processor uses this flag
to perform binary to BCD conversion.
• Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits of the result contains
even number of 1’s, then the Parity Flag is set. For odd number of 1’s, the Parity Flag is reset.
• Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0.
• Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative, then the sign flag is
set to 1 else set to 0.
• Overflow flag − This flag represents the result when the system capacity is exceeded.
• Trap flag − It is used for single step control and allows the user to execute one instruction at a time for debugging. If it
is set, then the program can be run in a single step mode.
• Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption of a program. It is set to
1 for interrupt enabled condition and set to 0 for interrupt disabled condition.
• Direction flag − It is used in string operation. As the name suggests when it is set then string bytes are accessed from
the higher memory address to the lower memory address and vice-a-versa.
8086 Pin Description
BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data using
data bus D8-D15. This signal is low during the first clock cycle, thereafter it is active.
NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input, which
causes an interrupt request to the microprocessor.
TEST
This signal is like wait state and is available at pin 23. When this signal is high, then the processor has
to wait for IDLE state, else the execution continues.
MN /MX
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the processor is to
operate in; when it is high, it works in the minimum mode and vice-versa.
INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor receives
this signal, it acknowledges the interrupt.
8086 Pin Description
DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It decides the
direction of data flow through the transreceiver. When it is high, data is transmitted out
and vice-a-versa.
HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.
HOLD
This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.
DEN : Data enable. This pin is provided as an output enable for the 8286/8287 in a
minimum system which uses transceiver. DEN is active low(0) during each memory and
input-output access and for INTA cycles
8086 Pin Description
LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to
leave the system bus. It is activated using the LOCK prefix on any instruction and is
available at pin 29.
RQ/GT1 and RQ/GT0
These are the Request/Grant signals used by the other processors requesting the CPU
to release the system bus. When the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.
8086 Pin Description
QS1 and QS0
These are queue status signals and are available at pin 24 and 25. These signals provide the status of
instruction queue. Their conditions are shown in the following table −
QS0
QS1
Status
0
0
No operation
0
1
First byte of opcode from the
queue
1
0
Empty the queue
1
1
Subsequent byte from the
queue
8086 Pin Description
S0, S1, S2
These are the status signals that provide the status of operation, which is used by the Bus Controller
8288 to generate memory & I/O control signals. These are available at pin 26, 27, and 28. Following is
the table showing their status −
S2
S1
S0
Status
0
0
0
Interrupt acknowledgement
0
0
1
I/O Read
0
1
0
I/O Write
0
1
1
Halt
1
0
0
Opcode fetch
1
0
1
Memory read
1
1
0
Memory write
1
1
1
Passive
Memory Segmentation in 8086
Segmentation is the process in which the main memory of the computer is logically divided into
different segments and each segment has its own base address. It is basically used to enhance the
speed of execution of the computer system, so that the processor is able to fetch and execute the
data from the memory easily and fast.
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called
as Segment Registers.
• Code segment register (CS): is used for addressing memory location in the code segment of the
memory, where the executable program is stored.
• Data segment register (DS): points to the data segment of the memory where the data is stored.
• Extra Segment Register (ES): also refers to a segment in the memory which is another data segment
in the memory.
• Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment
is that segment of memory which is used to store stack data.
Need for Memory Segmentation
Physical address lines of 8086 are 20 i.e. actual memory address is 20bit wide
However, the Registers inside 8086 are not bigger than 16 bit
Thus to store the 20 bit address in the Registers inside 8086, the 20 bit address is divided into
two parts Segment Address (16 bit) and Offset Address (16 bit) and the Physical Address is
obtained by combining the two addresses as:
Physical address (20 bits) = Segment Address (16 bit) X 10H + Offset address (16 bit)
Physical Address (20 bit) Generation in 8086
Physical address (20 bits) = Segment Address (16 bit) X 10H + Offset address (16 bit)
CS: 0200H
Offset: 1020H
Physical 20 bit Address = CS Shift left and add 0 at end
Physical Address: 02000H
1020H
03020H
Combinations of Segment Registers &
Offset
Segment Register
Offset Register
Purpose
CS
IP (Instruction Pointer)
To get address of Instruction
DS
BX, DI, SI
To get address of Data in Data
segment
SS
SP, BP
To get address in Stack Segment
ES
BX, DI, SI
To get address of Data in Extra
Segment
Memory Segmentation in 8086
Advantages of Memory segmentation
The main advantages of segmentation are as follows:
• It provides a powerful memory management mechanism.
• Data related or stack related operations can be performed in different segments.
• Code related operation can be done in separate code segments.
• It allows to processes to easily share data.
• It allows to extend the address ability of the processor, i.e. segmentation allows the use of 16
bit registers to give an addressing capability of 1 Megabytes. Without segmentation, it would
require 20 bit registers.
• It is possible to enhance the memory size of code data or stack segments beyond 64 KB by
allotting more than one segment for each area.
Write program to DIVIDE 8 bit number stored at memory location 2000H BY 8 BIT
NUMBER stored at 2001H and store the Quotient at 2002H & remainder at 2003H. The
division will be done by a subroutine which shall accept the Divisor in H, Dividend in L and
return Quotient in H and Remainder in L.
Subroutine DIV
Main Program
LXI SP, 2FFFH
LHLD 2000H
CALL DIV
SHLD 2002H
HLT
MOV A,L
CMI 00H
JZ EXIT
MVI C,00H
MOV A,H
CMP L
JC EXIT1
EXIT:
MVI H,00H
MVI L,00H
RET
EXIT1: MOV L,H
MOV H,C
RET
Write program to DIVIDE 8 bit number stored at memory location 2000H BY 8 BIT
NUMBER stored at 2001H and store the Quotient at 2002H & remainder at 2003H. The
division will be done by a subroutine which shall accept the Divisor in H, Dividend in L and
return Quotient in H Subroutine
and Remainder
in L.
DIV
Main Program
LXI SP, 2FFFH
LHLD 2000H
CALL DIV
SHLD 2002H
HLT
15-L
5-H
Q- Reg C – Return in H
R
TRY_AGAIN:
MOV A,H
CPI 00H
JZ EXIT
MOV A,L
CPI 00H
JZ EXIT1
MVI C,00H
MOV A,L
CMP H
JC EXIT2
SUB H
INR C
MOV L,A
JMP TRY_AGAIN
EXIT:
MVI H,FFH
MVI L,FFH
RET
EXIT1: MVI H,0x00
MVI L,0x00
RET
EXIT2: MOV H,C
MOV L,L
RET
Memory Organization for 8086
The memory address space of the 8086-based microcomputers has different logical and physical
organizations.
Logically, memory is implemented as a single 1M × 8 memory bank. The byte-wide storage locations
are assigned consecutive addresses over the range from 00000H through FFFFFH 8086 Memory
Physically, memory is implemented as two independent 512 Kbyte banks:
the low (even) bank and
the high (odd) bank.
8086 Memory Interfacing
Most the memory ICs are byte oriented i.e., each memory location can store only one byte of
data.
The 8086 is a 16-bit microprocessor, it can transfer 16-bit data.
So in addition to byte, word (16-bit) has to be stored in the memory.
To implement this , the entire memory is divided into two memory banks: Bank0 and Bank1.
Bank0 is selected only when A0 is zero and Bank1 is selected only when BHE’ is zero.
A0 is zero for all even addresses, so Bank0 is usually referred as even addressed memory bank.
BHE’ is used to access higher order memory bank, referred to as odd addressed memory bank.
Memory Organization for 8086
Memory Organization for 8086
To distinguish between odd and even bytes, the CPU provides a signal called
BHE (bus high enable). BHE/ and A0 are used to select the odd and even byte,
as shown in the table below:
Types of Memory decoding Techniques
Address Decoding Techniques
1. Absolute decoding 2. Linear decoding
3. Block decoding
Absolute decoding
In the absolute decoding technique the memory chip is selected only for the specified logic level
on the address lines: no other logic levels can select the chip.
Control signals BHE and A0 are use to enable output of odd and even memory banks
respectively. As each memory chip has 8K memory locations, thirteen address lines are required
to address each locations, independently.
All remaining address lines are used to generate an unique chip select signal. This address
technique is normally used in large memory systems
Absolute decoding
Linear decoding
In small system hardware for the decoding logic can be eliminated by using only required
number of addressing lines (not all). Other lines are simple ignored.
This technique is referred as linear decoding or partial decoding.
Control signals BHE and A0 are used to enable odd and even memory banks, respectively.
This gives you multiple addresses (shadow addresses). This technique reduces the cost of
decoding circuit, but it gas drawback of multiple addresses.
Linear decoding
Memory Interfacing Problem
Interface two 4Kx8 EPROM and two 4Kx8 RAM chips with 8086. Select suitable mapping of
addresses.
4KB x 2 ROM ICs Will require 13 Address Lines (A12-A0)
4KB X 2 RAM ICs Will require 13 Address Lines (A12-A0)
FE000
FFFFF
FC000
FDFFF
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 1 1
1 0 0
0 0 0 0 0 0 0 0 0 0 0
1 1 1 1
1 1
1 1 1
1 1 1 1 1 1 1 1 1 1 1
1
1
1
1
1
1
1
1
1 1
1 1
0 0 0
0 1 1
0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1
Condition for Selection of the ICs
ROM- Even Bank should be selected when A0=0 and BHE/= 0 or 1 and A13=A14=A15=A16=A17=A18=A19=1
ROM- Odd Bank should be selected when A0=1 or 0 and BHE/=0 and A13=A14=A15=A16=A17=A18=A19=1
RAM- Even Bank should be selected when A0=0 and BHE/= 0 or 1 and A13=0,A14=A15=A16=A17=A18=A19=1
RAM- Odd Bank should be selected when A0=1 or 1 and BHE/=0 and A13=0, A14=A15=A16=A17=A18=A19=1
Memory IC Selection Table
Decoder Inputs <- 8086 Connections
A2 <- A13
A1 <- A0
A0 <- BHE/
Operation
16 bit (Word) transfer on D15-D0
0
0
0
Even and Odd Address from RAM
8 bit (Byte) transfer on D7-D0
0
0
1
Only Even Address from RAM
8 bit (Byte) transfer on D15-D8
0
1
0
Only Odd Address from RAM
16 bit (Word) transfer on D15-D0
1
0
0
Even and Odd Address from ROM
8 bit (Byte) transfer on D7-D0
1
0
1
Only Even Address from ROM
8 bit (Byte) transfer on D15-D8
1
1
0
Only Odd Address from ROM
Memory Interfacing Problem
Design an interface between 8086 CPU and two chips of 16K×8 EPROM and two chips of 32K×8
RAM. Select the starting address of EPROM suitably. The RAM address must start at 00000 H.
16KB x 2= 32KB Will require 15 Address Lines (A14-A0)
32KB x 2= 64KB Will require 16 Address Lines (A15-A0)
F8000
FFFFF
00000
0FFFF
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 1 0
0 0 0
0 0 0 0 0 0 0 0 0 0 0
1 1 1 1
1 1
1 1 1
1 1 1 1 1 1 1 1 1 1 1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0 0
1 1
0 0
1 1
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
Condition for Selection of the ICs
ROM- Even Bank should be selected when A0=0 and BHE/= 0 or 1 and A15=A16=A17=A18=A19=1
ROM- Odd Bank should be selected when A0=1 or 0 and BHE/=0 and A15=A16=A17=A18=A19=1
RAM- Even Bank should be selected when A0=0 and BHE/= 0 or 1 and A16=A17=A18=A19=0
RAM- Odd Bank should be selected when A0=1 or 0 and BHE/=0 and A16=A17=A18=A19=0
Memory Interfacing Problem
It is required to interface two chips of 32K×8 ROM and four chips of 32K×8 RAM with 8086, according to
following map. ROM 1 and ROM 2 F0000H - FFFFFH, RAM 1 and RAM 2 D0000H - DFFFFH, RAM 3 and
RAM 4 E0000H – EFFFFH
32KB x 2 ROM= 64KB Will require 16 Address Lines (A15-A0)
32KB x 4 RAM=128KB Will require 17 Address Lines (A16-A0)
F0000
FFFFF
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 0 0
0 0 0
0 0 0 0 0 0 0 0 0 0 0
1 1 1 1
1 1
1 1 1
1 1 1 1 1 1 1 1 1 1 1
D0000
DFFFF
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0 0
1 1
0 0
1 1
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
E0000
EFFFF
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0 0
1 1
0 0
1 1
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
Condition for Selection of the ICs
ROM- Even Bank should be selected when A0=0 and BHE/= 0 or 1 and A16=A17=A18=A19=1
ROM- Odd Bank should be selected when A0=1 or 0 and BHE/=0 and A16=A16=A18=A19=1
RAM1- Even Bank should be selected when A0=0 and BHE/= 0 or 1 and A17=0 AND =A16=A18=A19=1
RAM1- Odd Bank should be selected when A0=1 or 0 and BHE/=0 and A17=0 AND =A16=A18=A19=1
RAM2- Even Bank should be selected when A0=0 and BHE/= 0 or 1 and A17=A18=A19=1
RAM2- Odd Bank should be selected when A0=1 or 0 and BHE/=0 and A17=A18=A19=1
Lab Questions for 8085
Write a program to find the factorial of a number stored in memory location 2000H (Assume number is <=8) and
store the factorial in 2001H & 2002H. Use two subroutines. One called FACT which accepts a number in Register
B and returns the factorial in BC. Another called MULT which accepts ONE 8 BIT NUMBER IN B AND ONE 16 BIT
NUMBER in H&L and returns the product in H&L.
7 X 6 =42
42 X 5 =210
210 X 4= 840
840 X 3 = 2520
2520 X 2 =
Interface ONE 7 Segment Common Cathode LED display to 8085 microprocessor through Port A of IC 8255.
Write program such that the counting 0 to 9 is displayed on the LED Segment with a delay of 1 second in
between.
Write a program to find the factorial of a number stored in memory location 2000H (Assume number is
<=8) and store the factorial in 2001H & 2002H. Use two subroutines. One called FACT which accepts a
number in Register B and returns the factorial in BC. Another called MULT which accepts ONE 8 BIT
NUMBER IN B AND ONE 16 BIT NUMBER in H&L and returns the product in H&L.
MAIN
LXI SP, 27FFH
LDA 2000H
MOV B,A
CALL FACT
MOV A,C
STA 2001H
MOV A,B
STA 2002H
HLT
FACT
MOV A,B
CPI 00H
JZ EXIT
LXI H, 0001H
MUL_AGAIN: CALL MULT
DCR B
MOV A,B
CPI 01H
JNZ MUL_AGAIN
MOV C,L
MOV B,H
RET
EXIT: MVI L,01H
MOV H, 00H
RET
MULT
AGAIN:
MOV D,H
MOV E,L
DCR B
DAD D
DCR B
JNZ AGAIN
RET
HL=0001
B x HL =HL
B=B-1
B x HL = HL
B=B-1
B x HL = HL
B=B-1
B x HL= HL
B=B-1
B x HL= HL
B=B-1
B x HL= HL
B=B-1
BC=HL
Instruction Set of 8086 Microprocessor
The 8086 microprocessor consists of 8 types of instructions −
• Data Transfer Instructions
• Arithmetic Instructions
• Bit Manipulation Instructions
• String Instructions
• Program Execution Transfer Instructions (Branch & Loop Instructions)
• Processor Control Instructions
• Iteration Control Instructions
• Interrupt Instructions
Data Transfer Instructions
• MOV − Used to copy the byte or word from the provided source to the provided destination.
• PUSH − Used to put a word at the top of the stack.
• POP − Used to get a word from the top of the stack to the provided location.
• PUSHA − Used to put all the registers into the stack.
• POPA − Used to get words from the stack to all registers.
• XCHG − Used to exchange the data from two locations.
• XLAT − Used to translate a byte in AL using a table in the memory.
Instructions for input and output port transfer
• IN − Used to read a byte or word from the provided port to the accumulator.
• OUT − Used to send out a byte or word from the accumulator to the provided port.
Data Transfer Instructions
Instructions to transfer the address
• LEA − Used to load the address of operand into the provided register.
• LDS − Used to load DS register and other provided register from the memory
• LES − Used to load ES register and other provided register from the memory.
Instructions to transfer flag registers
• LAHF − Used to load AH with the low byte of the flag register.
• SAHF − Used to store AH register to low byte of the flag register.
• PUSHF − Used to copy the flag register at the top of the stack.
MOV Instruction
MOV CX, 037AH
Put immediate number 037AH to CX
MOV BL, [437AH]
Copy byte in DS at offset 437AH to BL
MOV AX, BX
Copy content of register BX to AX
MOV DL, [BX]
Copy byte from memory at [BX] to DL
MOV DS, BX
Copy word from BX to DS register
MOV RESULT [BP], AX Copy AX to two memory locations; AL to the first location, AH to the second;
EA of the first memory location is sum of the displacement represented by RESULTS and content of
BP. Physical address = EA + SS.
MOV ES: RESULTS [BP], AX
Same as the above instruction, but physical address = EA + ES,
because of the segment override prefix ES
XCHG & LEA Instruction
XCHG AX, DX
Exchange word in AX with word in DX
XCHG BL, CH
Exchange byte in BL with byte in CH
XCHG AL, PRICES [BX]
Exchange byte in AL with byte in memory at EA = PRICE [BX] in DS.
LEA – LEA Register, Source This instruction determines the offset of the variable or memory
location named as the source and puts this offset in the indicated 16-bit register. LEA does not
affect any flag.
LEA BX, PRICES
Load BX with offset of PRICE in DS
LEA BP, SS: STACK_TOP Load BP with offset of STACK_TOP in SS
LEA CX, [BX][DI]
Load CX with EA = [BX] + [DI]
LDS & LES Instruction
LDS BX, [4326]
Copy content of memory at displacement 4326H in DS to BL, content of 4327H to
BH. Copy content at displacement of 4328H and 4329H in DS to DS register.
LDS SI, SPTR
Copy content of memory at displacement SPTR and SPTR + 1 in DS to SI register.
Copy content of memory at displacements SPTR + 2 and SPTR + 3 in DS to DS register. DS: SI now points at
start of the desired string.
LES BX, [789AH]
Copy content of memory at displacement 789AH in DS to BL, content of
789BH to BH, content of memory at displacement 789CH and 789DH in DS is copied to ES register.
LES DI, [BX]
Copy content of memory at offset [BX] and offset [BX] + 1 in DS to DI register. Copy
content of memory at offset [BX] + 2 and [BX] + 3 to ES register.
Arithmetic Instructions
Instructions to perform addition
• ADD − Used to add the provided byte to byte/word to word.
• ADC − Used to add with carry.
• INC − Used to increment the provided byte/word by 1.
• AAA − Used to adjust ASCII after addition.
• DAA − Used to adjust the decimal after the addition/subtraction operation.
Instructions to perform subtraction
• SUB − Used to subtract the byte from byte/word from word.
• SBB − Used to perform subtraction with borrow.
• DEC − Used to decrement the provided byte/word by 1.
• NEG − Used to negate each bit of the provided byte/word and add 1/2’s complement.
• CMP − Used to compare 2 provided byte/word.
• AAS − Used to adjust ASCII codes after subtraction.
• DAS − Used to adjust decimal after subtraction.
ADD & ADC
ADD AL, 74H
Add immediate number 74H to content of AL. Result in AL
ADC CL, BL
Add content of BL plus carry status to content of CL
ADD DX, BX
Add content of BX to content of DX
ADD DX, [SI]
Add word from memory at offset [SI] in DS to content of DX
ADC AL, PRICES [BX]
content of AL
Add byte from effective address PRICES [BX] plus carry status to
ADD AL, PRICES [BX]
Add content of memory at effective address PRICES [BX] to AL
SUB & SBB
SUB CX, BX
CX – BX; Result in CX
SBB CH, AL
Subtract content of AL and content of CF from content of CH. Result in CH
SUB AX, 3427H
Subtract immediate number 3427H from AX
SBB BX, [3427H]
Subtract word at displacement 3427H in DS and content of CF from BX
SUB PRICES [BX], 04H
Subtract 04 from byte at effective address PRICES [BX], if PRICES is declared
with DB; Subtract 04 from word at effective address PRICES [BX], if it is declared with DW.
SBB CX, TABLE [BX]
Subtract word from effective address TABLE [BX] and status of CF from CX. SBB
TABLE [BX], CX Subtract CX and status of CF from word in memory at effective address TABLE[BX].
Arithmetic Instructions
Instruction to perform multiplication
• MUL − Used to multiply unsigned byte by byte/word by word.
• IMUL − Used to multiply signed byte by byte/word by word.
• AAM − Used to adjust ASCII codes after multiplication.
Instructions to perform division
• DIV − Used to divide the unsigned word by byte or unsigned double word by word.
• IDIV − Used to divide the signed word by byte or signed double word by word.
• AAD − Used to adjust ASCII codes after division.
• CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower byte.
• CWD − Used to fill the upper word of the double word with the sign bit of the lower word.
MUL & DIV
MUL BH
Multiply AL with BH; result in AX
MUL CX
Multiply AX with CX; result high word in DX, low word in AX
MUL BYTE PTR [BX]
AX = AL x BH
DX AX = AX x CX
Multiply AL with byte in DS pointed to by [BX]
MUL FACTOR [BX]
Multiply AL with byte at effective address FACTOR [BX], if it is declared as type byte
with DB. Multiply AX with word at effective address FACTOR [BX], if it is declared as type word with DW.
DIV BL
Divide word in AX by byte in BL; Quotient in AL, remainder in AH
DIV CX
Divide down word in DX and AX by word in CX; Quotient in AX, and remainder in DX.
DIV SCALE [BX] Perform AX / (byte at effective address SCALE [BX]) if SCALE [BX] is of type byte; or (DX and
AX) / (word at effective address SCALE[BX] if SCALE[BX] is of type word
INC & DEC
INC BL
Add 1 to contains of BL register
INC CX
Add 1 to contains of CX register
INC BYTE PTR [BX]
Increment byte in data segment at offset contained in BX.
INC WORD PTR [BX]
Increment the word at offset of [BX] and [BX + 1] in the data segment.
INC TEMP
Increment byte or word named TEMP in the data segment. Increment byte if
MAX_TEMP declared with DB. Increment word if MAX_TEMP is declared with DW.
INC PRICES [BX]
Increment element pointed to by [BX] in array PRICES. Increment a word if
PRICES is declared as an array of words; Increment a byte if PRICES is declared as an array of bytes.
DEC CL
Subtract 1 from content of CL register
DEC BP
Subtract 1 from content of BP register
DEC BYTE PTR [BX]
Subtract 1 from byte at offset [BX] in DS.
DEC WORD PTR [BP]
Subtract 1 from a word at offset [BP] in SS.
DEC COUNT
Subtract 1 from byte or word named COUNT in DS. Decrement a byte if COUNT is
declared with a DB; Decrement a word if COUNT is declared with a DW.
Logic Instructions/Bit Manipulation Instructions
Instructions to perform logical operation
• NOT − Used to invert each bit of a byte or word.
• AND − Used for adding each bit in a byte/word with the corresponding bit in another byte/word.
• OR − Used to multiply each bit in a byte/word with the corresponding bit in another byte/word.
• XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the corresponding bit
in another byte/word.
• TEST − Used to add operands to update flags, without affecting operands.
Instructions to perform shift operations
• SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
• SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.
• SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into the new MSB.
AND/OR/XOR
AND CX, [SI]
AND word in DS at offset [SI] with word in CX register; Result in CX register
AND BH, CL
AND byte in CL with byte in BH; Result in BH
AND BX, 00FFH 00FFH Masks upper byte, leaves lower byte unchanged
OR AH, CL
CL ORed with AH, result in AH, CL not changed
OR BP, SI
SI ORed with BP, result in BP, SI not changed
OR SI, BP
BP ORed with SI, result in SI, BP not changed
OR BL, 80H
BL ORed with immediate number 80H; sets MSB of BL to 1
OR CX, TABLE [SI] CX ORed with word from effective address TABLE [SI]; Content of memory is not changed
XOR CL, BH
Byte in BH exclusive-ORed with byte in CL. Result in CL. BH not changed.
XOR BP, DI
Word in DI exclusive-ORed with word in BP. Result in BP. DI not changed.
XOR WORD PTR [BX], 00FFH Exclusive-OR immediate number 00FFH with word at offset [BX] in the data segment.
Result in memory location [BX]
NOT BX
Complement content or BX register
NOT BYTE PTR [BX] Complement memory byte at offset [BX] in data segment.
Logic Instructions/Bit Manipulation Instructions
Instructions to perform rotate operations
• ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry
Flag [CF].
• ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry
Flag [CF].
• RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to MSB.
• RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB.
RCL (Rotate Left through carry)
RCL – RCL Destination, Count
RCL DX, 1
Word in DX 1 bit left, MSB to CF, CF to LSB
MOV CL, 4
Load the number of bit positions to rotate into CL
RCL SUM [BX], CL
Rotate byte or word at effective address SUM [BX] 4 bits left Original
bit 4 now in CF, original CF now in bit 3.
RCR (Rotate Right through carry)
RCR – RCR Destination, Count
RCR BX, 1
Word in BX right 1 bit, CF to MSB, LSB to CF
MOV CL, 4
Load CL for rotating 4 bit position
RCR BYTE PTR [BX], 4
3, Bit 4 – original CF.
Rotate the byte at offset [BX] in DS 4 bit positions right CF = original bit
ROL (Rotate Left)
ROL – ROL Destination, Count
ROL AX, 1
Rotate the word in AX 1 bit position left, MSB to LSB and CF
MOV CL, 04H
Load number of bits to rotate in CL
ROL BL, CL
Rotate BL 4 bit positions
ROL FACTOR [BX], 1
left into CF
Rotate the word or byte in DS at EA = FACTOR [BX] by 1 bit position
ROR (Rotate Right)
ROR – ROR Destination, Count
ROR AX, 1
Rotate the word in AX 1 bit position Right, LSB to MSB and CF
MOV CL, 04H
Load number of bits to rotate in CL
ROR BL, CL
Rotate BL 4 bit positions
ROR FACTOR [BX], 1
CF
Rotate the word or byte in DS at EA = FACTOR [BX] by 1 bit position right into
String Related Instructions
String Instructions
String is a group of bytes/words and their memory is always allocated in a sequential order.
•REP − Used to repeat the given instruction till CX ≠ 0.
•REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
•REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
•MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
•COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
•INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided memory location.
•OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided memory location to the I/O
port.
•SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL or string word with a
word in AX.
•LODS/LODSB/LODSW − Used to store the string byte into AL or string word into AX.
String Related Instructions
String Instructions
String is a group of bytes/words and their memory is always allocated in a sequential order.
•REP − Used to repeat the given instruction till CX ≠ 0.
•REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
•REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
•MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
•COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
•INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided memory location.
•OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided memory location to the I/O
port.
•SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL or string word with a
word in AX.
•LODS/LODSB/LODSW − Used to store the string byte into AL or string word into AX.
Program Execution Transfer Instructions (Branch and
Loop Instructions)
Instructions to transfer the instruction during an execution without any condition −
• CALL − Used to call a procedure and save their return address to the stack.
• RET − Used to return from the procedure to the main program.
• JMP − Used to jump to the provided address to proceed to the next instruction.
Instructions to transfer the instruction during an execution with some conditions −
• JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
• JAE/JNB − Used to jump if above/not below instruction satisfies.
• JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
• JC − Used to jump if carry flag CF = 1
• JE/JZ − Used to jump if equal/zero flag ZF = 1
• JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
• JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
• JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
Program Execution Transfer Instructions (Branch and
Loop Instructions)
• JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.
• JNC − Used to jump if no carry flag (CF = 0)
• JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
• JNO − Used to jump if no overflow flag OF = 0
• JNP/JPO − Used to jump if not parity/parity odd PF = 0
• JNS − Used to jump if not sign SF = 0
• JO − Used to jump if overflow flag OF = 1
• JP/JPE − Used to jump if parity/parity even PF = 1
• JS − Used to jump if sign flag SF = 1
JA / JNBE (JUMP IF ABOVE / JUMP IF NOT BELOW OR EQUAL)
If, after a compare or some other instructions which affect flags, the zero flag and the carry flag both
are 0, this instruction will cause execution to jump to a label given in the instruction. If CF and ZF are
not both 0, the instruction will have no effect on program execution.
JAE / JNB / JNC (JUMP IF ABOVE OR EQUAL / JUMP IF NOT BELOW / JUMP IF NO CARRY)
If, after a compare or some other instructions which affect flags, the carry flag is 0, this instruction
will cause execution to jump to a label given in the instruction. If CF is 1, the instruction will have no
effect on program execution.
JB / JC / JNAE (JUMP IF BELOW / JUMP IF CARRY / JUMP IF NOT ABOVE OR EQUAL)
If, after a compare or some other instructions which affect flags, the carry flag is a 1, this instruction
will cause execution to jump to a label given in the instruction. If CF is 0, the instruction will have no
effect on program execution.
JBE / JNA (JUMP IF BELOW OR EQUAL / JUMP IF NOT ABOVE)
If, after a compare or some other instructions which affect flags, either the zero flag or the carry flag is 1, this
instruction will cause execution to jump to a label given in the instruction.
JG / JNLE (JUMP IF GREATER / JUMP IF NOT LESS THAN OR EQUAL)
This instruction is usually used after a Compare instruction. The instruction will cause a jump to the label given
in the instruction, if the zero flag is 0 and the carry flag is the same as the overflow flag. are both 0, the
instruction will have no effect on program execution.
JGE / JNL (JUMP IF GREATER THAN OR EQUAL / JUMP IF NOT LESS THAN)
This instruction is usually used after a Compare instruction. The instruction will cause a jump to the label given
in the instruction, if the sign flag is equal to the overflow flag.
JE / JZ (JUMP IF EQUAL / JUMP IF ZERO)
This instruction is usually used after a Compare instruction. If the zero flag is set, then this instruction will cause
a jump to the label given in the instruction.
JNE / JNZ (JUMP NOT EQUAL / JUMP IF NOT ZERO)
This instruction is usually used after a Compare instruction. If the zero flag is 0, then this instruction will cause a
jump to the label given in the instruction.
JCXZ (JUMP IF THE CX REGISTER IS ZERO)
This instruction will cause a jump to the label to a given in the instruction, if the CX register contains all 0’s. The
instruction does not look at the zero flag when it decides whether to jump or not.
Process Control Instructions
These instructions are used to control the processor action by setting/resetting the flag values.
Following are the instructions under this group −
• STC − Used to set carry flag CF to 1
• CLC − Used to clear/reset carry flag CF to 0
• CMC − Used to put complement at the state of carry flag CF.
• STD − Used to set the direction flag DF to 1
• CLD − Used to clear/reset the direction flag DF to 0
• STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
• CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.
Iteration Control Instructions
These instructions are used to execute the given instructions for number of times. Following is the list of
instructions under this group −
• LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0
• LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0
• LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX = 0
• JCXZ − Used to jump to the provided address if CX = 0
LOOP (JUMP TO SPECIFIED LABEL IF CX not equal TO 0 AFTER AUTO DECREMENT)
This instruction is used to repeat a series of instructions some number of times. The number of
times the instruction sequence is to be repeated is loaded into CX. Each time the LOOP
instruction executes, CX is automatically decremented by 1. If CX is not 0, execution will jump to
a destination specified by a label in the instruction. If CX = 0 after the auto decrement,
execution will simply go on to the next instruction after LOOP. The destination address for the
jump must be in the range of –128 bytes to +127 bytes from the address of the instruction after
the LOOP instruction. This instruction does not affect any flag
MOV CX, 0002H
MOV AX,000FH
AGAIN: DEC AX
LOOP AGAIN
CX=CX-1, IF CX<>0 THEN JUMP TO AGAIN
LOOPE / LOOPZ (LOOP WHILE CX not equal TO 0 AND ZF = 1) This instruction is used to repeat
a group of instructions some number of times, or until the zero flag becomes 0. The number of
times the instruction sequence is to be repeated is loaded into CX. Each time the LOOP
instruction executes, CX is automatically decremented by 1. If CX not equal TO 0 and ZF = 1,
execution will jump to a destination specified by a label in the instruction. If CX = 0, execution
simply go on the next instruction after LOOPE/LOOPZ.
LOOPNE / LOOPNZ (LOOP WHILE CX not equal TO 0 AND ZF = 0) This instruction is used to
repeat a group of instructions some number of times, or until the zero flag becomes a 1. The
number of times the instruction sequence is to be repeated is loaded into the count register CX.
Each time the LOOPNE / LOOPNZ instruction executes, CX is automatically decremented by 1. If
CX not equal TO 0 and ZF = 0, execution will jump to a destination specified by a label in the
instruction. If CX = 0, after the auto decrement or if ZF = 1, execution simply go on the next
instruction after LOOPNE / LOOPNZ.
Interrupt Instructions
These instructions are used to call the interrupt during program execution.
• INT − Used to interrupt the program during execution and calling service specified.
• INTO − Used to interrupt the program during execution if OF = 1
• IRET − Used to return from interrupt service to the main program
Write a program to copy 10 bytes from memory location 2000H
onwards to 3000H onwards inside the Data Segment
ORG 0100H
//Start program from address 0100H inside Code segment. ORG is assembler directive
MOV SI,2000H
MOV DI,3000H
MOV CX, 000AH
NEXT: MOV AL, [DS:SI]
MOV [DS:DI],AL
INC SI
INC DI
LOOP NEXT
//FIRST IT DECREMENTS CX THEN JUMPS IF CX<>0
Lab Questions for 8085
Interface ONE 7 Segment Common Cathode LED display to 8085 microprocessor through Port B of IC 8255.
Write program such that the counting 0 to 9 is displayed on the LED Segment with a delay of 1 second in
between.
Interface ONE 7 Segment Common Cathode LED display to 8085 microprocessor through Port
B of IC 8255. Write program such that the counting 0 to 9 is displayed on the LED Segment
with a delay of 1 second in between.
Port A
Port B
Port C
CR
RD/
A1
A0
A2
A3
A4
A5
A6
A7
WR/
AD7-AD0
of 8085
00H
01H
02H
03H
7 Segment Interface and Codes to Display
Count
A B C D E F G DP
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
0: 1 1 1 1 1 1 0 0 = FC
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
1: 0
1
1
0
0
0
0
0
=60
2: 1
1
0
1
1
0
1
0
= DA
3:
1
1
1
1
0
0
1
0 = F2
4:
5:
6:
7:
8:
9:
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
= 66
= B6
= BE
= E0
= FE
= F6
Interface 01 Common Cathode 7 segment LED Display to 8085 microprocessor through
Port B of IC 8255. Write program to display count from 0 to 9 when the switch is pressed
every time.
LXI SP, 27FF
MVI A, 80H
OUT 03H
RESTART: MVI C, 09H
LXI H, 0600H
AGAIN: MOV A, M
OUT 01H
CALL DELAY
INX H
DCR C
JNZ AGAIN
JMP RESTART
//Value 80H stored in Control Register of 8255 so that Port A, B & C are o/p Ports
//Initialize Counter
//Start address of memory location where display codes are stored
//Put Display Code on LED Display i.e. Port B
//Give delay of 1 second
//Point to next display code
//Put Next Display Code on Port
//Start from Displaying Zero
0600H 0xFC
0604H
0x66
0608H
0xFE
0601H 0x60
0605H
0xB6
0609H
0xF6
0602H 0xDA
0606H
0xBE
0603H 0xF2
0607H
0xE0
Calculation & Program for Delay of 1 second
Assuming that Crystal used is of 6MHz, thus internal clock is of 3MHZ and thus each T state is of 0.33 microsecond. Since we need
delay of 1 second thus the number of T states in the Delay subroutine should be 1/0.33 microsecond = 3 x 1000000 = 3000000 T states
MVI A, 0XFF
7
7X1
AGAIN2:
MVI C, 0xFF
7
7X1=7
7 X 255 = 1785
AGAIN:
DCR C
4
4 X 255= 1020
1020 X 255 = 260100
NOP
4
4 X 8 X 255 = 8160 8160 X 255 = 2080800
NOP
4
NOP
4
NOP
4
NOP
NOP
NOP
NOP
JNZ AGAIN
7/10
10 X 254 + 7 X 1= 2547
DCR A
4 X 255= 1020
JNZ AGAIN2
10 X 254 + 7 X1 = 2547
11734 X 255 =2992170
Write a program to copy 10 bytes from memory location 2000H
onwards to 3000H onwards in reverse inside the Data Segment
ORG 0100H
MOV SI,2000H
MOV DI,3009H
MOV CX, 000AH
NEXT: MOV AL, [DS:SI]
MOV [DS:DI],AL
INC SI
DEC DI
LOOP NEXT
;Start program from address 0100H inside Code segment. ORG is assembler directive
;Store starting address in SI and destination address in DI
;Set counter for transfer of 10 bytes
;Copy one byte into AL from source address and copy into destination address
;Both SI and DI are referring to Data segment
;Increment source address and decrement destination address
;FIRST IT DECREMENTS CX THEN JUMPS IF CX<>0
Write a program to multiply two 8 bit numbers stored at 2000H
& 2001H in DS and store the 16 bit product at 2002H & 2003H
ORG 0100H
//Start program from address 0100H inside Code segment. ORG is assembler directive
MOV SI,2000H
MOV AL, [DS:SI]
INC SI
MOV BL,[DS:SI]
MUL BL
; AX= AL x BL
INC SI
MOV [DS:SI],AX
Write a program to multiply two 16 bit numbers stored at
2000H & 2001H, 2ND NUMBER AT 2002H & 2003H and store the
32 bit product at 2004H, 2005H, 2006H & 2007H
ORG 0100H
//Start program from address 0100H inside Code segment. ORG is assembler directive
MOV SI,2000H
MOV AX, [DS:SI]
;1st 16 bit number in AX
INC SI
INC SI
;Point to 2002H
MOV BX,[DS:SI]
;2nd 16 bit number in BX
MUL BX
; DX AX= AX x BX
INC SI
INC SI
;Point to 2004H
MOV [DS:SI],DX
INC SI
INC SI
;Point to 2006H
MOV [DS:SI],AX
Write a program to divide a 16 bit number stored at 2000H &
2001H by a 8 bit number stored at 2002H and store the
quotient in 2003H and remainder in 2004H in DS
ORG 0100H
//Start program from address 0100H inside Code segment. ORG is assembler directive
MOV SI,2000H
MOV AX,[DS:SI]
MOV BL,[2002H]
DIV BL
MOV SI,2003H
MOV [DS:SI],AL
INC SI
MOV [DS:SI],AH
;AX is divide by BL Quotient in AL, remainder in AH
Write a program to find the smallest number out of 16
numbers stored from memory location 2000H and store the
smallest number at 2010H in DS
ORG 0100H
//Start program from address
0100H inside Code segment. ORG is assembler directive
CODE SEGMENT
ASSUME CS: CODE, DS:DATA
MOV SI,2000H
MOV CX, 000FH
MOV AL,[DS:SI]
AGAIN:INC SI
CMP AL,[DS:SI]
JLE AHEAD
MOV AL, [DS:SI]
CALL NEAR FACTORIAL
CALL FAR HIGHER
AHEAD:LOOP AGAIN
FACTORIAL PROC
HASDKJFj
basdjbjk
FACTORIAL ENDP
CODE ENDS
DATA SEGMENT
NUM1 DB 00H
NUM2 DB 02H
SUM DB 00H
DATA ENDS
CODED SEGMENT
HIGHER PROC
HASDKJFj
basdjbjk
HIGHER ENDP
CODED ENDS
DATA SEGMENT
NUM1 DB 00H
NUM2 DB 02H
SUM DB 00H
DATA ENDS
Assembler Directives of 8086
Assembler Directives are keywords written along with the which provide additional information to the
assembler while it is converting the program written in Assembly Language to Machine Language.
Assembler Directives are not Assembly Language Instructions.
1. ORG
2. DB, DW, DD, DT
3. SEGMENT, ENDS
4. PROC, ENDP
6. ASSUME
7. PTR
8. PUBLIC
9. STACK
10. NEAR, FAR
Assembler Directives of 8086
1. ORG - This directive is used at the time of assigning starting address for a module or segment.
2. DB, DW, DD– Define variable as Byte, Word (2 Bytes), Double Word
3. SEGMENT, ENDS – Used to indicate the start and end of a Segment
4. PROC, ENDP – Used to indicate the start (PROC) and end of (ENDP) a procedure i.e. sub-routine
6. ASSUME – Provides information to the assembler regarding the name of the program or data segment for
that particular segment.
7. PTR - This directive shows information regarding the size of the operand.
8. PUBLIC -This directive is used to provide a declaration to variables that are common for different program
modules.
9. STACK- Indicates presence of Stack Segment
10. NEAR, FAR – Calling procedure within the segment (NEAR) or in some other segment (FAR)
Interrupt Architecture of 8086 – Hardware
Interrupts
Hardware Interrupts
NMI (Non Maskable Interrupt) - This is a non-mask-able, edge triggered, high priority interrupt.
• On receiving an interrupt on NMI line, the microprocessor executes INT
• Microprocessor obtains the ISR address from location 2 x 4 = 00008H from the IVT.
• It reads 4 locations starting from this address to get the values for IP and CS to execute the ISR.
INTR - This is a mask-able, level triggered, low priority interrupt.
• On receiving an interrupt on INTR line, the microprocessor executes 2 INTA/ pulses.
1st INTA/ pulse – The interrupting device calculates (prepares to send) the vector number.
2nd INTA/ pulse – The interrupting device sends the vector number ‘N’ to the microprocessor.
• Now microprocessor multiplies N x 4 and goes to the corresponding location in the IVT to obtain the ISR
address. INTR is a mask-able interrupt.
• It is masked by making IF = 0 by software through CLI instruction.
• It is unmasked by making IF = 1 by software through STI instruction.
Interrupt Architecture of 8086 – Software Interrupts
Software interruptThese interrupts are caused by writing the software interrupt instruction INT n where ‘n’ can be any value
from 0 to 255 (00H to FFH). Hence all 256 interrupts can be invoked by software. E.g. INT 21
Interrupt Vector Table
Interrupt Vector Table
The interrupt vector (or interrupt pointer) table is the link between an interrupt type code and the procedure that has
been designated to service interrupts associated with that code. 8086 supports total 256 types i.e. 00H to FFH.
For each type it has to reserve four bytes i.e. double word. This double word pointer contains the address of the
procedure that is to service interrupts of that type.
The higher addressed word of the pointer contains the base address of the segment containing the procedure. This
base address of the segment is normally referred as NEW CS.
The lower addressed word contains the procedure’s offset from the beginning of the segment. This offset is normally
referred as NEW IP.
Thus NEW CS: NEW IP provides NEW physical address from where user ISR routine will start.
As for each type, four bytes (2 for NEW CS and 2 for NEW IP) are required; therefore interrupt pointer table occupies
up to the first 1k bytes (i.e. 256 x 4 = 1024 bytes) of low memory.
The total interrupt vector table is divided into three groups namely,
1.A. Dedicated interrupts (INT 0…..INT 4)
2.B. Reserved interrupts (INT 5…..INT 31)
3.C. Available interrupts (INT 32…..INT 225)
Dedicated Interrupts
1.INT 0 (Divide Error)-
1. This interrupt occurs whenever there is division error i.e. when the result of a division is too large to be stored. This condition normally
occurs when the divisor is very small as compared to the dividend or the divisor is zero.
2. Its ISR address is stored at location 0 x 4 = 00000H in the IVT.
2.INT 1 (Single Step)-
1. The microprocessor executes this interrupt after every instruction if the TF is set.
2. It puts microprocessor in single stepping mode i.e. the microprocessor pauses after executing every instruction. This is very useful during
debugging.
3. Its ISR generally displays contents of all registers. Its ISR address is stored at location 1 x 4 = 00004H in the IVT.
3.INT 2 (Non mask-able Interrupt)-
1. The microprocessor executes this ISR in response to an interrupt on the NMI (Non mask-able Interrupt) line.
2. Its ISR address is stored at location 2 x 4 = 00008H in the IVT.
4.INT 3 (Breakpoint Interrupt)-
1. This interrupt is used to cause breakpoints in the program. It is caused by writing the instruction INT 03H or simply INT.
2. It is useful in debugging large programs where single stepping is efficient.
3. Its ISR is used to display the contents of all registers on the screen. Its ISR address is stored at location 3 x 4 = 0000CH in the IVT.
5.INT 4 (Overflow Interrupt)-
1. This interrupt occurs if the overflow flag is set and the microprocessor executes the INTO (Interrupt on Overflow) instruction.
2. It is used to detect overflow error in signed arithmetic operations.
3. Its ISR address is stored at location 4 x 4 = 00010H in the IVT.
Reserved Interrupts
Reserved interrupts (INT 5…..INT 31):
1.These levels are reserved by Intel to be used in higher processors like 80386, Pentium etc. They are not
available to the user.
Available Interrupts
Available interrupts (INT 32…..INT 255):
1.These are user defined, software interrupts.
2.ISRs for these interrupts are written by the users to service various user defined conditions.
3.These interrupts are invoked by writing the instruction INT n. Its ISR address is obtained by the
microprocessor from location n x 4 in the IVT.
Response of 8086 on Interrupt
ColdFire™ 32 Bit MPU
Freescale™ Micro-controller & Microprocessor
Evolution
8 bit MCU / MPU
◦ 68HC05 series / 68HCS08 series / 68HC11 series And MC6800 MPU (1974)
16 bit MCU
◦ 68HC12 series / 68HCS12 series / MC9S12 series / 68HC16 series / S12X series &
MC68000 MPU (1980)
32 bit MCU
◦ Power Architecure™ Processors
◦ ColdFire Processors & Controllers
◦ ARM™ Processors
Freescale™ ColdFire ™ 32 bit MCU / MPU Series
The ColdFire series has been in existence since 1994
The series consists of both 32 bit Micro-controllers as well as Microprocessors
ColdFire Series has been designed for high end applications which require fast
computations as well as various modes of connectivity
Evolution of ColdFire™ Core
Evolution of ColdFire™ Core
V1 ColdFire Core
V2 ColdFire Core
V3 ColdFire Core: Single-Issue + Pipelined Local Bus
V4 ColdFire Core: Limited Superscalar
V4e ColdFire Core: Limited Superscalar
V5 ColdFire Core: Full Superscalar
ColdFire™ Core Architecture
ColdFire core is based on Variable Length RISC Architecture
Instructions are of size 16 bit, 32 bit or 48 bits
All cores (V1 till V5) share same core architecture as well as Instruction
set thus maintaining upward compatibility
ColdFire™ Core V1 Architecture
ColdFire™ Core Features
V1 ColdFire Core - Up to 150 MHz in 130-nm process technology
Multiply Accumulate Module, Hardware Division
External bus interface (16- or 32-bit)
Range of cache and local memory sizes, pipeline options
Single-pin BDM interface
Integrated peripherals
◦
◦
◦
◦
◦
◦
◦
◦
◦
◦
16-channel Direct Memory Access (DMA)
Fast Ethernet Controller
Multi-master Crossbar Switch
FlexBus for external interface
Interrupt Controller
4 32-bit DMA Timers
3 UARTs
Queued SPI
I2C
On-platform peripheral expansion bus
ColdFire™ MCF5223X Series Block Diagram
ColdFire™ V2 Core Architecture
ColdFire™ V2 Core Architecture
Two main units:
◦ Instruction Fetch Pipeline – Responsible for pre-fetching of instructions
◦ Operand Execution Pipeline – Responsible for decoding of instruction, fetching of operands and
execution of instructions
ColdFire™ V2 Core Architecture
Instruction Fetch Pipeline
◦ Instruction Address Generation Cycle
◦ Instruction Fetch Cycle
◦ Instruction Buffer Cycle
◦ The instruction Buffer serves as the FIFO type of queue for storage of instructions
which have been pre-fetched. It has the ability to store 03 nos. 32 bit longword.
ColdFire™ V2 Core Architecture
If Instruction Buffer is empty then Instruction fetched is immediately passed to Operand
Execution Pipeline for execution.
As instructions are pre-fetched, they are stored into the Instruction buffer and passed on to the
OEP as and when required.
ColdFire™ V2 Core Architecture
Operand Execution Pipeline is implemented in two stages:
◦ Decode & Select/Operand Cycle (DSOC) – Decode instructions and Select operands
◦ Address Generation/Execute Cycle (AGEX) – Performs instruction execution besides
the task of calculating the effective address of operand if needed.
V2 ColdFire SPP