Interface (Data Transmission)
Texas Instruments Incorporated
系统级
电路保护设计考虑因素
DesignESD
considerations
for system-level
ESD circuit protection
作者：Roger Liang，
By Roger Liang
德州仪器
系统工程师
(TI)
Systems Engineer
电击，而最近出台的小型器件静电规定更是低至
strikes only to a 2-kV HBM, while lower-geometry devices
500V。
引言
Introduction
As technology has evolved, mobile electronic devices have
随着技术的发展，移动电子设备已成为我们生活和文化
also evolved to become an integral part of people’s lives
的重要组成部分。平板电脑和智能手机触摸技术的应
and cultures. The advent of haptics for tablets and smartphones has encouraged increasing interaction with these
用，让我们能够与这些设备进行更多的互动。它构成了
devices. This creates the perfect environment for electro一个完整的静电放电 (ESD) 危险环境，即人体皮肤对设
static discharge (ESD) hazards, or the discharge of static
备产生的静电放电。例如，在使用消费类电子设备时，
electricity from a body surface to a device. In the case of
consumer electronics, for USB
example,
can occur
between
在用户手指和平板电脑
或者ESD
接口之间会发
HDMI
a user’s finger and a tablet’s USB or HDMI connector and
生 ESD，从而对平板电脑产生不可逆的损坏，例如：峰
cause irreversible damage to the tablet, such as spiked
值待机电流或者永久性系统失效。
standby current or permanent system failure.
This article explains the difference between system-
本文将为您解释系统级
现象和器件级
现象之
ESD
ESD
level and device-level ESD
phenomena
and offers
systemlevel design techniques that are targeted
to protect
间的差异，并向您介绍一些提供
ESD 事件保护的系统级
against everyday ESD events.
设计方法。
System-level versus device-level ESD protection
系统级
保护的对比
ESD保护与器件级
ESD damage
to ICs can occurESD
at any
time, from assembly
to board-level soldering to end-user interactions. The
的 ESD
损坏可发生在任何时候，从装配到板级焊
IC
incidence
of ESD-related
damage dates back to the dawn
of semiconductors, but it didn’t ESD
become
a prevalent prob接，再到终端用户人机互动。
相关损坏最早可追溯
lem
until
the
1970s
with
the
introduction
of the microchip
到半导体发展之初，但在 20 世纪 70 年代微芯片和薄栅
and thin-gate-oxide FETs for highly integrated ICs. All ICs
氧化
FET 应用于高集成
IC 以后，它才成为一个普遍的
have built-in
device-level ESD
structures that protect the
问题。所有
都有一些嵌入式器件级
ESD 结构，用于
IC events
IC against ESD
during the manufacturing
phase.
These events are simulated
by
three
different
device-level
在制造阶段保护
免受
事件的损坏。这些事件可
IC
ESD
models: the human-body model (HBM), the machine model
由三个不同的器件级模型进行模拟：人体模型 (HBM)、
(MM), and the charged-device model (CDM). The HBM is
机器模型
和带电器件模型
用于模
(CDM)
HBMhanintended to(MM)
emulate
ESD events caused
by。
human
dling,
the
MM
to
emulate
ESD
events
caused
by
automated
拟用户操作引起的 ESD 事件，MM 用于模拟自动操作
handling, and the CDM to emulate ESD events caused by
引起的
ESD 事件，而 CDM 则模拟产品充电/放电所引
product charging/discharging. These models are used for
起的
事件。这些模型都用于制造环境下的测试。在
ESD
testing
in the
manufacturing environment, where assembly, final testing, and board-level soldering are performed
这种环境下，装配、最终测试和板级焊接工作均在受控
in controlled
ESD environments that limit the level of ESD
环境下完成，从而减小暴露器件所承受的
ESD
ESD 应
stress to which the device is exposed. In the manufactur力。在制造环境下，
一般仅能承受
IC usually specified
2-kV
HBM 的
ESD
ing environment, ICs are
to survive
ESD
have recently been specified to as low as 500 V.
尽管在厂房受控
环境下器件级模型通常已足够，但
While device-level
are usually sufficient for the
ESDmodels
controlled
ESD
environment
of the factory floor, they are
在系统级测试中它们却差得很远。在终端用户环境下，电
completely inad equate for system-level testing. The levels
压和电流的
电击强度要高得多。因此，工业环境使用
ESDfrom
of ESD strikes
both voltages and currents can be
另一种方法进行系统级
测试，其由 For
ESD environment.
IECthis
61000-4-2
much greater in the end-user
reason,
the industry uses a different
method
for system-level
ESD
标准定义。器件级
和CDM
测试的目的都是
HBM、MM
testing, defined by the IEC 61000-4-2 standard. Device保证 IC 在制造过程中不受损坏；IEC 61000-4-2规定的系
level HBM, MM, and CDM tests are intended to ensure
统级测试用于模拟现实世界中的终端用户
ESD事件。
only that ICs survive the manufacturing process;
systemlevel tests specified by IEC 61000-4-2 are intended to
规定了两种系统级测试：接触放电和非接触放电。
IEC
simulate
end-user ESD events in the real world.
There
two方types
tests
specified
使用
接 触are
放电
法 时of，system-level
测试模拟器
电极
与 受 测by器 件
the IEC: contact discharge and air-gap discharge. In the
(DUT) 保持接触。非接触放电时，模拟器的带电电极靠近
contact-discharge method, the test-simulator electrode is
DUT
DUT 之间产生的火花促使放电。
held，同
in contact
with the device under test (DUT). In airgap discharge, the charged electrode of the simulator
表approaches
标准规定的每种方法的测试级
1 列出了 IEC
61000-4-2
the DUT,
and a spark
to the DUT actuates
the discharge.
别范围。请注意，两种方法的每种测试级别的放电强度
The range of test levels specified in the IEC 61000-4-2
并不相同。我们通常在
4级（每种方法的最高官方标称级
standard for each method is given in Table 1. It is impor-
别）以上对应力水平进行逐级测试，直到发生故障点为
tant to note that the severity of each test level is not
equivalent between the two methods. Stress levels are
止。
usually incrementally tested above level 4 (the highest
official level for each method) until the point of failure.
Table
Test levels for contact-discharge and air-gap表 1 1.接触放电和非接触放电方法的测试电平
discharge methods
CONTACT接触式
DISCHARGE
放电电平
LEVEL
TEST VOLTAGE
±kV)
((±
kV)
测试电压
AIR-GAP非接触式
DISCHARGE
放电电平
LEVEL
TEST VOLTAGE
±kV)
((±
kV)
1
2
1
2
2
4
2
4
3
6
3
8
4
8
4
15
测试电压
28
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Texas Instruments Incorporated
表
2 2.器件级模型与
IEC 系统级模型比较
Table
Comparison of device-level
models and IEC system-level model
HUMAN-BODY MODEL
(HBM)
Definition
Test Levels (V)
MACHINE MODEL
(MM)
CHARGED-DEVICE MODEL
(CDM)
Human body discharging Robotic arm discharging
accumulated static
accumulated static
Charged device being
grounded
IEC 61000-4-2 MODEL
Real-world ESD events
500 to 2000
100 to 200
250 to 2000
2000 to 15000
~150
Pulse Width (ns)
~150
~80
~1
Peak Current at Applied 2 kV (APK)
1.33
—
~5
7.5
Rise Time
25 ns
—
< 400 ps
< 1 ns
2
2
2
20
Number of Voltage Strikes
器件级模型和系统级模型有一些明显的区
Device-level models and system-level
models have
some distinct differences,
as
别，表
2 列出了这些区别。表
2 中最后三
highlighted in Table 2. The last three
个参数（电流、上升时间和电击次数）需
parameters in Table 2—current, rise time,
特别注意：
and number of voltage strikes—are of par-
图
波形
1 器件级和
IEC 模型的 ESD
Figure
1. ESD waveforms
for device-level
and IEC models
48
2000-V CDM: 2 to 5 A PK (depending on package)
with 1-ns duration
2000-V HBM: 1.3 A PK with about 150-ns duration
Current, IPP (A)
ticular concern:
电流差对于 ESD 敏感型器件是否能够承
• The difference in current is critical to
36
受一次
事件至关重要。由于强电
whether ESD
the ESD-sensitive
device survives
流可引起结点损坏和栅氧化损坏，
8-kV
an ESD strike. Because high current levels
can
cause
junction
damage
and
gate-oxide
保护芯片（峰值电流
HBM
5.33A ）可
24
damage,
it
is
possible
that
a
chip
protected
能会因 2-kV IEC 模型电击（峰值电流
by an 8-kV HBM (with a peak current of
）而损坏。因此，系统设计人员不
7.5A
5.33 A) can be destroyed by a strike to a
能把
额定值同
HBM
2-kV IEC
model
(with aIEC
peak模型额定值混
current of
12
淆，这一点极为重要。
7.5 A). Thus, it is extremely important that
system designers do not confuse HBM
另一个差异存在于电压尖峰上升时间。
ratings with ratings for the IEC model.
的规定上升时间为
• HBM
Another
difference lies within
the。
rise
0
25ns
IEC 模
time
of
the
voltage
strikes.
The
rise
time
型脉冲上升时间小于 1ns，其在
最初
specified for an HBM is 25 ns. The pulse
3ns 消耗掉大部分能量。如果 HBM 额定
of the IEC model has a rise time of less
的器件需
来做出响应，则在其保护
25nsdissipates
than 1 ns and
most of its energy
电路激活以前器件就已被损坏。
in the first 30 ns. If an HBM-rated device
takes 25 ns to respond, the device can be destroyed
两种模型在测试期间所用的电击次数不同。
before its protection circuits are even activated.HBM 仅
要求测试一次正电击和一次负电击，而
模型却
• The number of strikes used during testing isIEC
different
要求
次负电击。可能出现的情况
between
the models. The
requires only a single
10 次正电击和
10 HBM
positive and single negative strike to be tested, whereas
是，器件能够承受第一次电击，但由于初次电击带来
the IEC model requires ten positive strikes and ten 显
的损坏仍然存在，其会在后续电击中失效。图
1
negative strikes. It is possible for a device to survive
示了
、
和
模型的
波形举例。很
CDM
IECsubsequent
ESD
the first
strikeHBM
but fail on
strikes due to
明显，相比所有器件级模型的脉冲，
模型的脉冲
IECFigure
damage sustained during the initial strike.
1
shows example ESD waveforms for a CDM, an HBM,
携带了更多的能量。
and the IEC model. It is apparent that the IEC model’s
pulse carries much more energy than the pulse of each
device-level model.
8000-V IEC model: 30 A PK with 1-ns
duration, plus a 16-A PK secondary
pulse with about 50-ns duration
50
100
Time (ns)
Connector I/O
图
2 系统级
TVS 布局 TVS placement
Figure
2. System-level
ESDSensitive
Device
TPD1E10B06
(4 Devices)
TVS 如何保护系统免受 ESD 事件的损害
How a TVS protects a system against ESD events
Instead
integrated structuresIEC
for ESD
protection,
the
与
标准规定
ESD of保护集成结构不同，
61000-4-2
model
specified
by
the
IEC
61000-4-2
standard
usually
的模型通常会使用离散式独立瞬态电压抑制二极管，
uses discrete stand-alone transient-voltage-suppressant
也即瞬态电压抑制器 (TVS)。相比电源管理或者微控制
diodes, or transient-voltage suppressors (TVSs). Compared
to ESD-protection
structures
integrated into
power器单元中集成的
保护结构，独立
ESD
TVSa 成本更低，
management or microcontroller
unit,
stand-alone
TVSs are
并且可以靠近系统
连接器放置，如图
所示。
I/O
2
low in cost and can be placed close to the system’s I/O
connector, as shown in Figure 2.
29
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立即沿这条通路接地。在单向
TVS 情况下，只要
D2 和
There are two types of TVSs: bidirectional
and unidirectional
(see
Figure
3).
The
Texas
Instruments
TPD1E10B06
都不进入其击穿区域，则电压信号会在接地电压以
Z1
is an example of a bidirectional
TVS
that can be变为正向偏
上摆动。当正
线路时，
ESD 电击击中 I/O
D1 placed on
a general-purpose data line for system-level ESD protec置，而
先于 D2 进入其击穿区域；通过
Z1 bidirectional
D1are和 Z1 形
tion. Both
and unidirectional TVSs
成一条接地通路，从而让
能量得到耗散。当发生负
designed to be an open circuit
normal operating
ESDduring
conditions,
and
a
short
to
ground
during
an ESD event.
In
事件时，
变为正向偏置，
ESD
D2
ESD能量通过
D2接地
the case of a bidirectional TVS, a voltage signal on the I/O
通路得到耗散。由于 D1 和 D2 尺寸可以更小、寄生电
line can swing above and below ground as long as neither
容更少，单向二极管可用于许多高速应用；
和 D2 可
D1 nor D2 enters its breakdown region. When D1
an ESD
strike
(positive
or
negative)
hits
the
I/O
line,
one
diode
以“隐藏”更大的齐纳二极管 Z1（大尺寸的原因是处理
becomes forward-biased and the other breaks down, creat击穿区域更多的电流）。
图
3 双向和单向
TVS and unidirectional TVSs
Figure
3. Bidirectional
I/O
D1
D1
I/O
Z1
D2
D2
GND
GND
Bidirectional
Unidirectional
ing a path in which ESD energy is immediately dumped to
ground. In the case of a uni系统级
directional
TVS,保护的关键
a voltage
ESD
图
4 TVS
Figure
4. 二极管电流与电压的关系
TVS diode’s current versus voltage
signal can swing above
器件参数
ground as long as neither
D2 4nor
Z1 enters
break图
显示了
IF
TVSits二极管电
down region. When a posiR DYN – Dynamic resistance
流与电压特性的对比情况。
VBR – Breakdown voltage
tive ESD strike hits the I/O
VRWM – Maximum working voltage
尽管
是一种简单的结
TVS
line, D1
becomes
forwardIRWM – Maximum working reverse
(leakage) current
biased and Z1 enters its
构，但是在系统级
ESD 保
VCL – Clamping voltage
breakdown region before D2
IPP – Peak pulse current
护设计过程中仍然需要注意
does; a path to ground is
V
V
V
几个重要的参数。这些参数
CL
BR
RWM
created through D1 and Z1
VR
VF
I RWM
in which ESD energy
is
dis、动态电
包括击穿电压
V BR
IR
VF – Forward voltage
sipated.、钳位电压
When a negative和电
阻
RDYN
VCL
IF – Forward current
ESD strike hits, D2 becomes
VR – Reverse voltage
容。
IR – Reverse current
forward-biased and ESD
R DYN
energy is dissipated through
I PP
D2 to ground. Unidirectional
diodes are implemented for
IR
击穿电压
high-speed applications
because D1 and D2 can be
正确选择
TVS
sized smaller
with的第一步是
less para研究击穿电压
线路的最大
sitic capacitance;
D1)。例如，如果受保护
and D2 in turn “hide” I/O
the bigger
(VBR
图
电流放电通路
5 ESD
Figure
5. ESD
current-discharge path
Zener
diode,
Z1,
which
is
sized
bigger
in
order
to
handle
工作电压 VRWM 为 5V，则在达到该最大电压以前
TVS 不
more current in its breakdown region.
Connector I/O
应进入其击穿区域。通常，TVS 产品说明书会包括具体
Key device
parameters
for system-level
，它让我们能够更加容易地选择正确的
漏电流的
V RWM
ESD。否则，我们可以选择一个
protection
TVS
VBR（min） 大于受保护 I/O
Figure 4 shows the characteristics of a TVS diode’s current
几伏的 TVS
。
线路
VRWM
versus
voltage. Even
though a TVS is a simple structure,
several important parameters should be considered in the
动态电阻
design of system-level ESD protection. These include
breakdown voltage, VBR ; dynamic resistance, RDYN; clamp是一种极速事件，也就是几纳秒的事情。在如此
ESD
ing voltage,
VCL; and capacitance.
ESD CurrentDischarge Path
TVS
ESDSensitive
Device
R DYN
+
VBR
–
短的时间内，TVS 传导接地通路不会立即建立起来，并
Breakdown voltage
且在通路中存在一定的电阻。这种电阻被称作动态电阻
The first step in selecting the appropriate TVS is looking
，如图 5 所示。
(RDYN)
at the breakdown
voltage (V ). For example, if the maxiBR
mum working voltage, VRWM, on the protected I/O line is
5 V, the TVS should not enter into its breakdown region
before reaching this maximum. More often than not, a TVS
datasheet includes VRWM at a specific leakage current,
which makes choosing the right TVS easy. If that is not the
case, a TVS can be selected whose VBR(min) is a couple of
volts higher than the VRWM of the protected I/O line.
Dynamic resistance
An ESD is an ultrafast event in the range of nanoseconds.
During such a short amount of time, the TVS conduction
path to ground is not established instantaneously and
there is some resistance in this path. This resistance,
known as dynamic resistance (RDYN), is shown in Figure 5.
30
High-Performance Analog Products
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4Q 2012
Analog Applications Journal
Interface (Data Transmission)
Texas Instruments Incorporated
理想情况下，
线路电压才能尽可
I/Ovoltage
Ideally, RDYNRshould
be zero so that
on the I/O
DYN 应为零，这样
；但是，这是不可能的事情。
能地接近
的最新
line can beVclamped
as close to the VBR as possible;
R DYN howBR
ever,
that
is
never
the
case.
The
industry’s
current
stan工业标准值为 1 Ω 或者 1 Ω 以下。利用传输线路脉冲测
dard value for RDYN is 1 Ω or less. RDYN can be captured
量技术可以得到
RDYN。使用这种技术时，通过 TVS 释放
by using transmission-line
pulse-measurement techniques,
电压，然后测量相应的电流。在得到不同电压的许多数
where a charged voltage is discharged through the TVS
据点以后，便可以绘制出如图
曲线，而斜线
6一样的 IV
and a corresponding current is measured.
After
many data
pointsRwith
different
charged
voltages
have
been
taken, an
便为
。图
显示了
的
6
TPD1E10B06
R
DYN
DYN，其典型
IV curve
like
the
one
in
Figure
6
can
be
drawn,
and
the
值为
。
~0.3 Ω
文件名称
Reference
For more information related to this article, you can downSSZB130B
load an Acrobat Reader file at www.ti.com/lit/litnumber
and replace “litnumber” with the TI Lit. # for the
materials listed below.
保护设计指南》
1、《系统级ESD/EMI
®
®
相关网站
Document Title
TI Lit. #
1. “System-level ESD/EMI protection guide”. . . SSZB130B
www.ti.com/esd
Related Web sites
slope is RDYN. Figure 6 shows the TPD1E10B06’s RDYN,
which has a typical value of ~0.3 Ω.
钳位电压
www.ti.com.cn/product/cn/TPD1E10B06
www.ti.com /esd
www.ti.com /product/TPD1E10B06
Clamping
voltage
由于
ESD 是一种极速瞬态事件，
I/O 线路的
VCL ≈ VBR + I PP × R DYN + IParasitic ×
dI PP
,
dt
(1)
把钳位电压波形下面的区域想像成能量。钳位
where IPP is the peak pulse current during an
the parasitic ESD
inducESD event, and IParasitic
性能越好，受保护
敏感型器件在
事件
ESDis
tance
of
the
trace
from
the
connector
through
中受到损坏的机率也就越小。由于钳位电压很
the TVS to ground.
小，一些 TVS 可承受 IEC 模型的 8kV 接触式放
Imagine the area under the clamping-voltage
电，但是“受保护”器件却被损坏了。
waveform as energy. The better the clamping
图
的 IV 特性
Figure
6. IV characteristic
of TPD1E10B06
6 TPD1E10B06
30
27
21
ESD
IC
护。我们应在系统级设计中使用独立
Conclusion
TVS。在
选择某个
As IC process-technology
nodes continue to
TVS 时，设计人员应注意一些重要
become smaller,
they
become
参数，例如：
、
、
和电容等。more
VBR RDYN VCLincreasingly
susceptible to ESD damage, both during the
manufacturing process and in the end-user
environment. Device-level ESD protection is not
参考文献
enough to protect ICs on a system level. Standalone TVSs should be used in a system-level
如
欲 了 解 本 文 更 多 详 情 ， 敬 请 访 问 w w w.
design. When selecting a TVS, the designer
（用下面列出的材料编号
ti.com/lit/litnumber
should pay careful attention
to parameters such
, and capacitance.
as VBR, RDYN, VCLlitnumber
替换地址中的“
”），下载Acrobat®
Reader 版文件。
®
15
12
6
3
0
0
10
20
30
40
50
Voltage (V)
图 7 8Kv
接触放电的clamping
Figure
7. ESD-event
with 8-kV contact discharge
ESD 事件钳位
100
90
80
70
Amplitude (V)
During normal operating conditions, the TVS
由于
ICan工艺技术节点变得越来越小，它也越
acts as
open circuit and has a parasitic来越容易受到
损坏的影响，不管是在制
capacitance shunt
to ground.
It is important
ESD
for the designer to take this capacitance into
造过程还是在终端用户使用环境下。器件级
account
in the signal chain’s bandwidth budget.
保护并不足以在系统层面为
提供保
18
9
performance is, the less likely it is that an ESD电容
sensitive device under protection will be damaged during an ESD event. Due to poor clamp在正常工作状态下，TVS为一个开路，并具有
ing voltage, some TVSs survive an IEC model’s
寄生电容分流接地。设计人员应在信号链带宽
8-kV contact discharge, but the “protected”
预算中考虑到这种电容。
device is destroyed.
Capacitance
结论
RDYN = 0.32 Ω
24
Current (A)
Since an ESD is an ultrafast transient
event, the
电压不能立即得到箝制。如图
7 所示，根据
voltage on the I/O line is not clamped instantaIEC 61000-4-2 标准，数千伏电压被箝制为数
neously. As shown in Figure 7, thousands of
十伏。如方程式
DYN 越小，钳位性
volts are clamped 1to 所示，
tens of Rvolts
according to
能也就越好：其中，
事件期间的
IPP 为As
ESD
the IEC 61000-4-2 standard.
indicated
by
the better
the接地
Equation 1, the lower
RDYN is, 为通过
峰值脉冲电流，而
Iparasitic
TVS
clamping performance will be:
来自连接器的线路寄生电感。
TI 文献编号
60
50
40
30
20
10
0
–10
–15 0
30
60
90
120
150
180
210
Time (ns)
31
Analog Applications Journal
4Q 2012
www.ti.com/aaj
High-Performance Analog Products
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