Chinese Journal of Electrical Engineering, Vol.4, No.2, June 2018
A New Active Gate Driver for MOSFET to
Suppress Turn-Off Spike and Oscillation
Yanfeng Jiang, Chao Feng, Zhichang Yang, Xingran Zhao, and Hong Li*
(School of Electrical Engineering, Beijing Jiaotong University, Beijing 100044, China)
Abstract: MOSFETs are widely used in power electronics converters. Due to the high di/dt and
dv/dt of the MOSFET and parasitic parameters in the circuit, drain voltage spikes and oscillations will
be generated during turn-off, which can affect the safety of the device and degrade the system's
electromagnetic compatibility. This paper first studies the relationship between drain voltage spike and
gate voltage during turn-off. Based on the effect of gate voltage on drain voltage spike, a new active
gate driver that optimizes gate voltage is proposed. The proposed active gate driver detects the slope of
the drain voltage and generates a positive pulse in the drain current fall phase to increase the gate
voltage, thereby suppressing drain voltage spike and oscillation. In order to verify the effectiveness of
the proposed active gate driver, a simulation circuit and an experimental platform are constructed and
compared with the conventional gate driver. Simulation and experimental results show that the new
active gate driver can effectively suppress the drain voltage spike and oscillation of MOSFETs, and can
effectively reduce high-frequency EMI.
Keywords: Active gate driver, electromagnetic interference, voltage spike, oscillation.
1
Introduction
In high frequency power converters, MOSFETs
generate severe voltage spikes and oscillations during
turn-off due to high dv/dt, di/dt, and circuit parasitic
parameters. Excessive voltage spikes and oscillations
can not only damage the MOSFET, increase switching
losses, but also cause serious electromagnetic interference
(EMI)[1-3]. In order to suppress voltage spikes and
oscillations during turn-off, many methods have been
proposed in the existing literatures[4-9]. Among them, the
commonly used methods are active clamp circuit[4], soft
switches[5-6] and snubber circuit[7-9].However, additional
capacitance and inductance are needed in these methods,
which will reduce the switching frequency and increase
switching losses[10]. Compared to those methods, drive
circuit can be well balanced in switching losses and
electromagnetic compatibility(EMC), which is a good
choice to optimize the switching process[11].
Conventional gate driver(CGD) reduce voltage
spikes and oscillations by increasing drive resistance,
but the switching losses will increase significantly[12].
Based on the problem of CGD, active gate driver(AGD)
is proposed to suppress voltage spikes and oscillations,
which has little effect on MOSFET switching speed and
losses of MOSFET[13]. Due to the advantages of AGD, it
has been studied by many scholars.
There are many active drive schemes reported in
literatures. By changing the gate resistance in different
switching phases, the charging and discharging speeds
of MOSFET during the switching process can be
controlled. Thereby, the voltage spikes and oscillations
can be effectively suppressed[14-17]. However, the range
*Corresponding Author, E-mail:hli@bjtu.edu.cn.
Supported in part by the General Program of National Natural Science
Foundation of China under Grant 51577010, 51777012, in part by the
Fundamental Research Funds for the Central Universities under Grant
2017JBM054.
of values of the drive resistors is limited, so the
suppression effect of voltage spikes and oscillations is
limited. Although the drive resistance is continuously
adjustable in [18], the high-speed clock is required in
these circuit, which increases the cost of the drive
circuit.
On the other hand, the switching speed of the
MOSFET can be controlled effectively by controlling
the drive current. The di/dt of MOSFET can be reduced
by appropriately reducing the drive current during the
drain current fall phase[19-21]. However, control process
of the controllable current source driving circuit is
complicated. Compared to the analog current source
circuits, a digital current source drive is proposed in [22],
whose control process is easy. But the speed of ADC or
DAC to collect the switching information makes it
difficult to use in high-frequency converters.
In addition to controlling the drive resistance and
drive current, the switching transition can also be
controlled by controlling the gate voltage[21-29]. The
influence of the gate voltage on the drain voltage spike
and oscillation is deduced theoretically in [23], but the
corresponding solution are not given. The active
closed-loop voltage gate drive in [24] makes up for the
shortcomings of [23]. But the value of the passive
devices is difficult to determine. The closed-loop
controller is designed in [25-27], which uses the error of
the drain voltage and the reference voltage to make the
switching waveform close to idea voltage. However, it is
difficult to perform well under different DC bus voltages
at fixed reference voltage. Contrary to the closed loop
control, the multi–level drive pulses to improve the
switching characteristics has been studied in [28-29].
However, this circuit in [28] can only be used for
switches with a drive level of -5V to 15V.
In order to overcome the shortcomings of the
above-mentioned active drive circuit, a new active gate
driver(NAGD) is designed based on the causes of
voltage spike and oscillation. The general principle of
44
Chinese Journal of Electrical Engineering, Vol.4, No.2, June 2018
the NAGD is that, by detecting the dvd /dt, the gate
voltage is raised at a certain point during the rise of the
drain voltage and held until the end of the MOSFET is
turned off to suppress voltage spike and oscillation. The
gate-source voltage is raised at a certain point during the
rise of the drain-source voltage The NAGD has a simple
control process, requires fewer components, and is easy
to implement in the actual circuit.
2
Analysis of MOSFET turn-off process
The causes of the voltage spike and oscillation
during turn-off process are analyzed based on a chopper
circuit, as shown in Fig.1. The MOSFET in the Fig.1
consists of an ideal MOSFET, gate-drain capacitance Cgd,
gate-source capacitance Cgs, drain-source capacitance
Cds, and an internal diode; Ld is the parasitic inductance
of the MOSFET; Lf is the parasitic inductance of the
freewheeling diode(FWD); L and R are inductive loads;
Rg is the drive resistance; Udc is the DC bus voltage.
According to the behavior of the voltage and current, the
turn-off process is divided into four phases, as shown in
Fig.2.
Phase 1: the turn-off delay phase (t0~ t1)
At this phase, the gate-source capacitance Cgs of the
MOSFET is discharged through the gate resistor. And
the gate-source voltage begins to decrease until t1.
According to Kirchhoff law, the expression of the
gate-source voltage and current are shown in equation
(1)~(2):
ugt  Rg ig  U gs  0
Theoretical analysis of voltage spike and
oscillation in turn-off process
This part analyzes the turn-off process of the
MOSFET and gives the mathematical equations of
voltage spike and oscillation. Based on the causes of
the voltage spike and oscillation, a method of
suppressing the voltage spike and oscillation is proposed.
2.1
2.1.1
ig  Cgs
2.1.2
dU gs
(1)
(2)
dt
Phase 2: the voltage rise phase(t1~ t2)
This phase is also called miller plateau phase. The
MOSFET gate-source voltage remains unchanged, and
the drain-source voltage begins to rise until it equals the
DC bus voltage. During this process, Cgd starts reverse
charging after completing discharge and the MOSFET
enters the saturation region from the linear resistive
region.
2.1.3
Phase 3:the current fall phase(t2~ t3)
At this phase, the drain current begins to fall and
the load current is transferred from the MOSFET to the
FWD. At this time, MOSFTE operates in the saturation
region, and the value of the drain current depends on the
gate-source voltage, as shown in equation (3):
id  g m (U gs  U th )
(3)
The first derivative of equation (3) is equation (4):
dU gs
did
 gm
dt
dt
(4)
where gm is the admittance of the MOSFET.
Equation (5) can be derived from equation (1)~
(4)[23]:
Fig.1
Chopper circuit with inductive load
id
 U th  U gt
did
gm

C
dt
Rg iss
gm
(5)
According to Kirchhoff voltage law, the KVL
equation of the power loop can be obtained, as shown in
equation (6):
U dc  U dc  ( Ld  Lf )
did
 U FWD
dt
(6)
where UFWD is the forward conduction voltage of the
freewheeling diod. Since the did /dt is less than zero, the
–(Ld +Lf)·did /dt is greater than zero. Therefore, the
voltage spike expression due to the parasitic inductance
can be obtained as shown in (7):
Fig.2
Schematic of turning off process
U ds  U dc  ( Ld  Lf )
did
 U FWD
dt
(7)
Y. Jiang et al.: A New Active Gate Driver for MOSFET to Suppress Turn-Off Spike and Oscillation
2.1.4
Phase 4: the oscillation phase(t3~ t4)
At this phase, since the gate-source voltage drops
below the threshold voltage, the MOSFET will be
completely turned off. Because of the presence of
parasitic parameters in the power loop, the drain current
forms a damping oscillation. Accordingly, the drain
voltage will form a damping oscillation according to
(7)[23].
Based on the above analysis, large did/dt in the
current fall phase is the cause of voltage spike and
oscillation during the turn-off process of the MOSFET,
which makes that a large voltage spike is formed on
the circuit parasitic inductance. A damping oscillation of
the current is caused by the parasitic inductance, which
causes the drain-source voltage forming a damping
oscillation.
2.2
Method of suppressing spike and oscillation
The magnitude of the voltage spike is determined
by the did /dt of the current fall phase and the parasitic
inductance of the circuit. For a particular circuit, the
circuit inductance is fixed. So reducing voltage spike
can be achieved by reducing the did /dt. From equation
(5), it can be seen that, under the threshold of the gate
voltage, the did/dt can be reduced by raising the
gate-source voltage. According to the cause of the
voltage oscillation during the turn-off process, reducing
the did /dt in the current fall phase can also suppress
voltage oscillation effectively.
3
45
Active drive circuit design
According to the method of suppressing voltage
spike and oscillation and as far as possible without
affecting turn-off loss, the normal gate-source voltage
should be maintained during the turn-off delay phase,
and the gate-source voltage should be raised to suppress
the did /dt during the current fall and voltage oscillation
phase. However, the current fall phase is too fast to
respond to in time. Considering the delay time of the
detection circuit, a positive pulse can be generated by
detecting the rise of the drain-source voltage and the
amplitude of it should be held until the end of the
voltage oscillation phase[30]. Based on the above analysis,
a NAGD is proposed to suppress voltage spike and
oscillation, which mainly consists of three parts: slope
detection of drain-source voltage part[22]; proportional
amplification circuit; push- pull circuit .
(1) Detection circuit of voltage slope[22]: it contains
a differentiator AMP1 and a comparator Comp. AMP1
is used to detect the dvd /dt. The output voltage of the
AMP1 is compared with the reference voltage Vref of the
Comp after being divided by the resistor. The value of
Vref should be a little than the voltage of R4 when
MOSFET is completely turned on or off. The output
voltage waveform of the Amp1 is shaped by the
comparator to generate a positive pulse during the
current fall phase. The output voltage of the AMP1 is
determined by equation (8):
U Amp1-out  Vcm
dU ds
 R2 C1
dt
(8)
Fig.3
Active drive gate circuit schematic
(2) Proportional amplification circuit: this part is
used to further amplify the output pulse amplitude of the
comparator so that Bipolar Junction Transistor(BJT) in
the push-pull circuit works in the cutoff or saturation
region. The amplification of the proportional amplifier
circuit is shown in equation(9).
U AMP2-ou t
R
 1 6
U AMP2-in
R5
(9)
(3) Push-pull circuit: it is used to isolate the front
stage circuit and raise the gate voltage when the
comparator outputs a positive pulse. The maximum
value of its output voltage is determined by the supply
voltage VCC of Push-pull circuit when it working in the
switching state. The higher the value of VCC is, the
higher the amplitude of the gate voltage is raised and the
better the suppression of voltage spike and oscillation
will be.
Fig.4 shows the simulated waveform of the NAGD
in the simulation software PSpice. It can be seen that the
gate-source voltage of the turn-off process is divided
into three parts. In the first part, the output voltage of the
comparators is low and the MOSFET maintains normal
turn off. In the second part, during the period from the
drain drain-source rise to the oscillation phase, the
output voltage of differentiator is the dvd /dt, and is
shaped by the comparator to generate a positive pulse.
The amplitude of the positive pulse is further amplified
through the proportional amplification circuit so that the
push-pull circuit operates in cutoff or saturation region.
Adjusting the voltage amplitude of VCC can get different
amplitude output voltages. The output voltage raises the
gate voltage through the push-pull circuit. The higher
the supply voltage of VCC is, the larger the value of the
gate voltage is raised, and the more obvious the effect on
suppression of the voltage spike and oscillation. In the
third part, the output voltage of the comparators is low
and the gate-source voltage is kept at zero potential to
ensure the MOSFET is reliably turned off.
4
Simulation verification
In this section, a CGD and a NAGD circuit are built
in PSpice to verify the effectiveness of the NAGD for
improving the dynamic characteristics of MOSFET. The
46
Chinese Journal of Electrical Engineering, Vol.4, No.2, June 2018
Fig.4
Simulation waveform of NAGD
amplifier and comparator adopt the TI high-speed device,
which are respectively THS3062 and TLV3501. The
MOSFET is IRF620 and diode is HAF25TB60. The
simulation models are all provided by the official
website. The parameters of simulation circuit are shown
in Table 1.
According to the analysis of the push-pull circuit in
the NAGD, the suppression effect of voltage spike and
oscillation depends on the magnitude of the gate-source
voltage being raised. The gate-source and drain-source
voltage waveforms are shown in Fig.5 and Fig.6 under
CGD and NAGD. It can been seen that the gate-source
voltage is raised to 2.701V, the drain-source voltage
spike amplitude decreases by 23.64% and the oscillation
is significantly reduced.
Table 1
Parameters of simulation circuit
Parameters
DC bus voltage Udc /V
Load inductance L/H
Load Resistance R/
Drive resistance Rg/
Switching fs/kHz
Supply voltage of push-pull circuit VCC/V
MOSFET drain parasitic inductance Ld/nH
Freewheeling diode parasitic inductance Lf /nH
Fig.5
Fig.6
In order to verify that under the threshold voltage,
the higher the gate-source voltage is, the better
suppression of voltage spike and oscillation is, Fig.7
shows the gate-source and the drain-source voltage
waveform when the VCC is increased from 5V to 8V.
Compared to Fig.6, the gate-source voltage increases
from 2.701V to 3.07V, and the voltage spike decreases
by 12.27%. It proves that under the threshold voltage,
the higher the gate-source voltage is, the better the
suppression effect of voltage spike and oscillation will be.
It is necessary to verify that the NAGD can still
effectively suppress voltage spike and oscillation with
large parasitic inductance. The parasitic inductance Ld is
increased from 60nH to 112nH, and the V C C is
maintained at 8V. The gate-source and drain-source
voltage waveform are shown in Fig.8 and Fig.9 under
CGD and NAGD. It can been seen that the gate-source
voltage is raised to 3.201V, and the voltage spike
amplitude decreases by 38.75%, which proves that the
NAGD can still suppress the voltage spike and
oscillation effectively under large parasitic inductance.
It is so common for power converters to change DC
bus voltage. Accordingly, it is necessary to verify that
the NAGD can work well at different DC bus voltages.
The DC bus voltage increases from 60V to 100V, and
Value
60
330
10
10
100
5
60
10
Fig.7
U ds and U gs voltage waveform of NAGD at VCC=8V
U ds and U gs voltage waveform of CGD at Udc=60V
Fig.8
U ds and U gs voltage waveform of CGD at L d =112nH
U ds and U gs voltage waveform of NAGD at Udc=60V
Fig.9
Uds and Ugs voltage waveform of NAGD at Ld=112nH
Y. Jiang et al.: A New Active Gate Driver for MOSFET to Suppress Turn-Off Spike and Oscillation
the VCC maintains 8V. The gate-source and drain-source
voltage waveform are shown in Fig.10 and Fig.11 under
CGD and NAGD. It can been seen that the gate-source is
raised to 3.201V, and the voltage spike amplitude
decreases by 42.29% and the oscillation is suppressed
effectively.
In order to show the effectiveness of NAGD more
intuitively, the drain-source voltage waveforms of the
CGD and NAGD are compared when the parasitic
inductance Ld = 60nH and the VCC=8V, as shown in
Fig.12. Fig.13 shows the spectrum waveform comparison
result of the drain-source voltage under CGD and
NAGD. From Fig.12, it is known that the frequency of
the drain-source voltage oscillation obtained by
calculation is 50MHz. From Fig.13 it can be seen that
the spectrum peak of the drain-source voltage is 51MHz,
which is basically consistent with the frequency of the
drain-source voltage oscillation. Compared to CGD,
NAGD reduces the EMI 19.4dBμV caused by voltage
spike and oscillation during turn-off. The amplitude of
the spectrum is effectively reduced from 30MHz to
80MHz. Simulation results show that NAGD has a good
effect on the suppression of EMI in high frequency.
Fig.10
Uds and Ugs voltage waveform of CGD at Udc=100V
Fig.11
Uds and Ugs voltage waveform of NAGD at Udc=100V
Fig.12
Comparison of U ds between CGD and NAGD
Fig.13
5
47
Spectrum waveform comparison of U ds between
CGD and NAGD
Experimental verification
The experiment platform of chopper circuit with
inductive load is built to verify the effectiveness of
the NAGD for the suppression of voltage spike and
oscillation, as shown in Fig.14 The setting of
experimental parameters is consistent with the simulation.
The gate-source and the drain-source voltage
waveform are shown in Fig.15 and Fig.16 when the VCC
is 0V and 5V. It can been seen that the gate-source
voltage is raised to 2.7V, the drain-source voltage spike
amplitude decreases by 27.27%, and the oscillation is
suppressed effectively.
Compared to Fig.16, the VCC in Fig.17 is increased
from 5V to 8V. It can been seen that the gate-source
voltage increases from 2.7V to 3.6V and the voltage
spike decreases by 7.28%, which proves that under the
threshold voltage, the higher the gate-source voltage is,
the better the suppression effect of voltage spike and
oscillation will be.
This section is used to verify that the NAGD can
work well in large parasitic inductance. The parasitic
inductance Ld is increased from 60nH to 112nH. The
gate-source and drain-source voltage waveform are
shown in Fig.18 and Fig.19 under CGD and NAGD.
Fig.14
Fig.15
Experiment platform of chopper circuit
U ds and U gs voltage waveform of CGD at U dc =60V
48
Chinese Journal of Electrical Engineering, Vol.4, No.2, June 2018
Time(200ns/div)
Fig.16
Uds and Ugs voltage waveform of NAGD at Udc=60V
Time(200ns/div)
Fig.20
Uds and Ugs voltage waveform of CGD at Udc=100V
Fig.21
Uds and Ugs voltage waveform of NAGD at Udc=100V
Time(200ns/div)
Time(200ns/div)
Fig.17
Uds and Ugs voltage waveform of NAGD at VCC=8V
Time(100ns/div)
Fig.18
Uds and Ugs voltage waveform of CGD at L d =112nH
6
Conclusion
In order to solve the problem of voltage spikes and
oscillations caused by the high frequency switching of
MOSFETs in power electronic converters, the NAGD is
proposed to suppress voltage spikes and oscillations in
the turn-off process. The simulation and experimental
results show that under the threshold of the gate voltage,
the higher the gate voltage is, the better the suppression
effect of voltage spike and oscillation will be. At the
same time, for higher parasitic inductance and bus
voltage, not only can voltage spike and oscillation be
effectively suppressed, EMI at high frequencies can also
be effectively suppressed. In addition, the control of
the NAGD is simple and requires fewer additional
components, which is beneficial to the realization of the
circuit.
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Time(100ns/div)
Fig.19
Uds and Ugs voltage waveform of NAGD at Ld=112nH
It can been seen that the gate-source voltage is raised to
3.201V, and the voltage spike amplitude decreases by
44.87%, which proves that the NAGD can still suppress
the voltage spike oscillation effectively under large
parasitic inductance.
Fig.20 shows the gate-source voltage and drainsource voltage waveform under CGD when the DC bus
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Fig.21 is the gate-source and the drain-source voltage
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voltage spike oscillation under large DC bus voltage
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Yanfeng Jiang was born in Anhui province,
China, in 1993. He received the B.S. degree in
electrical engineering from North University
of China, Taiyuan, China, in 2017. He is
currently working toward the M.S. degree in
electrical engineering at the School of Electrical
Engineering, Beijing Jiaotong University,
Beijing, China. His current research interests
is electromagnetic compatibility in power
electronics.
Chao Feng was born in Shanxi province,
China, in 1993. He received the B.S. degree in
electrical engineering from Taiyuan University
of Technology, Taiyuan, China, in 2016. He
is currently working toward the M.S. degree
in electrical engineering at the School of
Electrical Engineering, Beijing Jiaotong
University, Beijing, China. His current research
interests is electromagnetic compatibility in
power electronics.
Zhichang Yang(S’15) was born in Chifeng,
China, in 1991. He received the B.S. degree in
electrical engineering from Beijing Jiaotong
University, Beijinng, China, in 2013, where is
currently working toward the Ph.D. degree
in electrical engineering in the School of
Electrical Engineering. His current research
interests include power electronics, electromagnetic interference, and chaos control and
its applications.
Xingran Zhao was born in Hebei province,
China, in 1994. She received the B.S. degree in
electrical engineering from Beijing Jiaotong
University, Beijing, China, in 2016. She is
currently working toward the M.S. degree
in electrical engineering at the School of
Electrical Engineering, Beijing Jiaotong
University, Beijing, China. Her research
interest is simulation and modeling of wide
band gap power devices.
Hong Li (S’07-M’09-SM’18) received her
B.Sc., M.Sc., and Ph.D. degrees from Taiyuan
University of Technology, South China
University of Technology, and FernUniversität
in Hagen, Germany, in 2002, 2005 and 2009,
respectively.
Currently, she is a Professor of Electrical
Engineering School, Beijing Jiaotong University,
China. Her research interests include nonlinear
modeling, analysis and its applications, EMI
suppressing methods for power electronic systems, wide band gap
power devices and applications. She is Associate Editor of IEEE
Transactions on Industrial Electronics, Associate Editor of the Chinese
Journal of Electrical Engineering, Vice Chairman of Electromagnetic
Compatibility Specialized Committee in China Power Supply Society.
She has published 1 book, 30 journal papers, and 39 conference papers.
She has also applied 20 patents.