Chapter 2 Exercise Solutions
2.1 (Testability Analysis)
Fig. 1: The SCOAP controllability and observability measures for a 3-input XOR gate
Fig. 2: SCOAP measures for a 3-input XOR gate using NAND-NOR implementation
2.2 (Testability Analysis)
A
B
C
0.5/0.5/0.5
0.5/0.5/0.5
0.5/0.5/0.5
0.5/0.5/1
Z
Fig. 3: The probability-based testability measures for a 3-input XNOR gate
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Fig. 4: probability-based measures for a 3-input XNOR gate using NAND-NOR implementation
2.3 (Testability Analysis)
Fig. 5: The probability-based testability measures for the full-adder circuit
2.4 (Testability Analysis)
Fig. 6: A ripple-carry adder composed of n full adders
Si = C i + A i + B i ,
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Ci+1 = Ci(Ai + Bi) + AiBi
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2.5 (Ad Hoc Technique)
Fig. 7: An example of a combinational feedback loop in a combinational circuit
Figure 7 shows an example of a combinational feedback loop. In this example, when A = 1, B = 0, and
C = 1, the circuit acts as an oscillator, which prevents us from being able to predict a valid value at G.
This will reduce the fault coverage of the circuit and could damage the chip.
2.6 (Test Point Insertion)
Fig. 8: A single observation point insertion
2.7 (Clocked-Scan Cell)
Fig.9 A gate-level implementation of the clocked-scan cell
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2.8 (LSSD Scan Cell)
Fig. 10: A CMOS implementation of the LSSD scan cell
2.9 (Full-Scan Design)
Fig. 11: Test Operations
We know that ATE performs scan testing on scan chains in parallel, so test time is related to the
number of scan test vectors N. From Figure 11, we can see that one vector would take L cycles during
shift operation, 1 cycle during hold operation to observe PO values, 1 cycle during capture operation
to capture values to scan cells, and 1 cycle to observe all PPO values. Also, at the end of scan testing,
L-1 cycles are required to shift out the final capture values of the scan cells. Thus, the total test time
required to test the scan design with N test vectors is:
N(L + 3) + L – 1 = NL + 3N + L – 1
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2.10 (Full-Scan Design)
1. In an LSSD single-latch design, the output of the master latch L1 is used to drive combinational
logic, and the slave latch L2 is used for scan shift. While in an LSSD double-latch design, the
output of slave latch L2 is used for driving both combinational logic and scan shift.
2. In an LSSD single-latch design, at least two system clocks C1 and C2 must be used as C clocks to
prevent combinational feedback loops from occurring. In an LSSD double-latch design, only C1 is
used as C clock, and C2 is used as B clock.
2.11 (Random-Access Scan)
(1) Clock cycles required for a full-scan design
For there are n storage elements and m balanced scan chains in the full-scan design, the longest scan
chain length L is equal to the upper bound integer of n/m.
L = ┌n/m┐
Thus, the number of clock cycles required to shift in the test vector vi+1 is L.
(2) Clock cycles required for a RAS design
Since vi+1 and the response of vi are different in d bits, in order to apply vi+1, these d bits have to be
udpated. Assuming that the clock cycles to specify an address is T, then
T = ┌log2n┐
Because one additional cycle is needed to update the specified scan cell, the total number of clock cycles
required to update d bits will become d(1+T).
2.12 (Combinational Feedback Loop)
The sequential circuit can be treated as a directed graph. We can easily identify whether it contains
combinational feedback loops or not with the DFS algorithm. An implementation is listed as follows:
typedef struct {int v; int w} EDGE; // Edge v->w
int count;
// a counter
int ivertex[Vcount];
// Record if a vertex is visited or not
// Vcount is the count of vertexes in the graph
int iparent[Vcount];
// Record the parent of one vertex in current search
//print out the found loop
void print_loop(int w, int v)
{
int t;
printf("Loop: %d", v);
t = w;
while( t != v )
{
printf(" %d", t);
t = iparent[w];
}
printf(" %d\n", v);
return;
}
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//DFS
void search(Graph G, EDGE e)
{
link t;
int w;
w = e.w;
ivertex[w] = count;
iparent[w] = e.v;
//Adjacency-list implementation of graph
//Traverse all child vertex(es) of w
for(t = G->adj[w]; t != NULL; t = t->next)
{
//skip sequential logic
if(logic_type(t->v) == SEQUENTIAL)
continue;
if(ivertex[t->v] == -1) //unvisited
{
search(G, EDGE(w, t->v));
}
else if(ivertex[t->v] != count)
{
//visited by previous search process, continue
}
else
{
print_loop(w, t->v);
//loop is found, print it out
}
}
return;
}
//main program
void loop_identify(Graph G)
{
int v;
count = 0;
//initial all elements in the visit array as -1
for(v = 0; v < Vcount; v++)
ivertex[v] = -1;
//traverse all vertexes in the graph
for(v = 0; v < Vcount; v++)
{
//skip sequential logic
if(logic_type(v) == SEQUENTIAL)
continue;
if(ivertex[v] == -1)
{
count++;
search(G, EDGE(v, v));
}
}
return;
}
2.13 (Lock-Up Latch)
Between SFF2 and SFF3, there is a clock skew, so do SFF4 and SFF5. The clock skew may cause this
failure. To fix this problem, adding one lock-up latch before SFF3 and another lock-up latch before
SFF5. Below is the modified schematic:
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Fig. 12: Circuit structure fixed by using a lock-up latch
2.14 (Lock-Up Latch)
In this case SFF1 is positive-edge-triggered DFF and SFF2 is negative-edge-triggered DFF. Below is
the waveform:
Fig. 13: The waveform of the scan chain
To stitch the two cross-clock-domain scan cells into one single chain, a lock-up latch should be added
before the first negative-edge-triggered scan cell. The waveform is like below:
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SI
Q1
SFF1
X
SO
Q2
SFF2
lock-up
latch
CLK1
CLK1
D1
Q1
D2
D1
X
D3
D2
D1
Q2
D4
D3
D2
D5
D4
D3
D4
Fig. 14: Stitching of the scan chain
2.15 (Lock-Up Latch)
A lock-up latch cannot stitch the two cross-clock-domain scan cells into one single scan chain. A
lock-up flip-flop can do it. The lock-up flip-flop uses CK2 as its clock.
SCp
Lockup FF
SCq
CLK1
CLK2
CLK1
CLK2
Fig. 15: Circuit structure and Timing diagram
2.16 (Scan Stitching)
Once the physical implementation of the scan design is completed, including placement and routing of
all the cells of the design, it may cause errors during shift operation between adjacent scan cells. If
two neighboring scan cells in the chain are too close, the data path delay from the output of a driving
scan cell to the scan input of the following scan cell is smaller than the clock skew that exists between
the clocks driving the two scan cells (we suppose that the two scan cells are driven by the same clock).
Finally, both scan cells will always incorrectly contain the same value at the end of each shift clock
cycle.
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Fig. 16: Circuit structure
CK
CK+delay
X, X’
Y
D1
D1
D2
D2
D3
D3
Fig. 17: Timing diagram
To fix the clock skew problem, we can insert a lock-up latch between adjacent scan cells as shown
below:
Fig. 18: A lock-up latch circuit structure
If the distance between two neighboring scan cells in the scan chain is very far, then the data path
delay from the Q output of a driving scan cell to the scan input SI of the next scan cell could be one
clock cycle longer than the clock skew that exists between the clocks driving the two scan cells. In this
case, data at the scan chain will be lost due to hold time violation. One may add pipelined flip-flops
between these two scan cells or lower the scan shift frequency.
2.17 (Test Signal)
During scan testing, the test mode signal (TM) is set to 1, in order to turn on all test-related fixes. In
order to operate the circuit in shift mode, the scan enable signal (SE) is first set to 1, so the scan cells
are reconfigured as scan chains, which allows us to shift in any desired logic values into the scan
chains. In capture mode, SE is set to 0, and the scan cells are used to capture the test response from the
combinational logic when capture clock(s) are applied.
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2.18 (Clock Grouping)
Initialize clock info. and mark CCDs of
all clocks. Set all clocks ungroup
Select one clock from ungrouped clocks
and build one group
Check next clock from ungrouped clocks
whether there is any CCD with clocks in
the group
Y
N
Add into group
Y
Is there any clock that is not checked
in ungroup?
N
Y
Is there any clock left in ungroup?
N
END
Fig. 19: An algorithm to find the smallest number of clock groups in clocking grouping
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2.19 (RTL Testability Enhancement)
The original schematic:
Q
DFF
CLK
tri_en[3]
Q
d4
tri_en[2]
dbus
DFF
1'b ’
CLK
d3
tri_en[1]
1 'b ’
DFF
CLK
d2
bus_sel[0]
bus_sel[1]
tri_en[0]
1'b ’
DFF
d1
CLK
Fig.20 The original schematic
When more than two bus drivers’ Enable signals are set to 1, bus contention may occur. Therefore,
modification must be made in order to ensure only one driver controls the bus.
The modified RTL code is:
reg[3:0] tri_en;
always @(posedge clk)
begin
case(bus_sel)
0:tri_en[0] = 1’b1;
1:tri_en[1] = 1’b1;
2:tri_en[2] = 1’b1;
3:tri_en[3] = 1’b1;
endcase
end
assign dbus = (tri_en[0]_fix)?d1:8’bz;
assign dbus = (tri_en[1]_fix)?d2:8’bz;
assign dbus = (tri_en[2]_fix)?d3:8’bz;
assign dbus = (tri_en[3]_fix)?d4:8’bz;
or (tri_en[0]_fix, tri_en[0], SE);
not ( SE , SE);
and (tri_en[1]_fix, SE , tri_en[1]);
and (tri_en[2]_fix, SE , tri_en[2]);
and (tri_en[3]_fix, SE , tri_en[3]);
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The modified schematic:
Fig. 21: The modified schematic
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