People’s Democratic Republic of Algeria
Ministry of Higher Education and Scientific Research
Institute of Electrical and Electronic Engineering
EE222 Digital Systems
LABORATORY REPORT #7
Registers & Shift Registers and Applications
Done by:
AMOUR Fatma
BOULEGROUN Amin
BOUTITE Ramzi
Group:
L2 Group 08
Instructor:
Y.AZZOUGUI
Date:
30/05/2023
Introduction
The Registers & Shift Registers and Applications laboratory experiment aims to provide
us with a practical understanding of the design and implementation of various registers and
shift registers using VHDL. This lab explores the fundamental concepts of digital circuit design
using discrete ICs and the proto-board, and investigates different applications of registers and
shift registers. Through hands-on experience and the use of Quartus II software and the DE2
board, will learn how to verify the operations of these circuits and gain a deeper appreciation
for the importance and versatility of registers and shift registers in digital circuit design.
Objectives
The objective of this laboratory experiment is to design and implement various registers
and shift registers using VHDL. Also, investigates certain applications using these devices and
verify their operations using Quartus II software development software and the DE2 board.
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Part I: Implementation Using Discrete ICs and the ProtoBoard
1.1
Problem Statement:
The problem statement involves building and testing three different circuits in Part I using
discrete ICs and a proto-board. The first circuit is a 4-bit PIPO register using a 7474 Dual Dtype positive-edge triggered Flip-Flop with asynchronous Clear and Preset. The second circuit
involves modifying the PIPO circuit to act as a 4-bit SISO shift right shift register using one
of the pulsers as a clock. The third circuit involves testing the 4 modes of the 74194, a 4-bit
Universal shift register.
1.2
Design approach:
1. PIPO:
To create a PIPO register, use two 7474 ICs. Connect the input lines directly to each
register input and the output lines to the LED outputs.Without forgetting to connect the
power, clock signal, and reset.
2. SISO: To create a SISO register, use the same configuration as the PIPO register but
remove all the inputs except for the first one. Replace the removed inputs with the
output of the previous register.
3. Universal Shift Register: To create a universal shift register using the 74194 IC, connect
the pins to their corresponding input/output lines. The IC will take care of the shift
register functionality, making the process simpler.
1.3
Testing results:
We ensured that each circuit was functioning correctly by testing it with various outputs
and ensuring that the expected output was received. In the case of the 74194, we can achieve
multiple functionalities by following the table and adjusting the S0 and S1 inputs as needed.
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Part II: Register & Shift Registers Using Schematic Capture Design Entry
2.1
Problem Statement:
The problem requires the construction of two different 4-bit registers using D-type flipflops (DFFs) using capture design entry. The first register is a parallel-in, parallel-out (PIPO)
register. The second register is a serial-in, parallel-out (SIPO) shift register. Both come with
a means to reset them at any instant of time and with all outputs available.
2.2
Design approach:
A serial-in, serial-out (SISO) shift register can be constructed using DFFs as building
blocksby: The first DFF is connected to the input, and each subsequent DFF takes its input from the output of the previous DFF. The register’s output is taken from the outputs of
all the DFFs. A common clock is used to synchronize the operation of all the DFFs, and the
register can be reset by providing a reset signal to all the DFFs.
To construct a PIPO register using DFFs, we can connect the data inputs of all DFFs to the
provided inputs. Each DFF takes its clock input from a common clock signal and the outputs
of each DFF are connected to the outputs. To reset the register, a reset signal can be applied
to all DFFs simultaneously.
2.3
Design Schematics:
Table 1: PIPO and SISO shift registers made with capture design entry .
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2.4
Simulation Results:
After designing simulation waveforms for the inputs, each circuit is tested. Based on the
results, their functionality is correct.
Table 2: PIPO and SISO shift registers simulated inputs and outputs .
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Part III: Implementation of Registers and Shift Registers
Using VHDL:
3.1
Problem Statement:
The problem is to write VHDL code for three different registers: a parallel-in, parallel-out
(PIPO) register, a serial-in, parallel-out (SIPO) register, and a universal shift register, all with
4-bit capacities. The registers should have clock and reset buttons. The input to the registers
will be taken from four switches, and the output will be displayed on four red LEDs.
3.2
Design approach:
To design the PIPO, SIsO, and universal shift registers, VHDL code is used to implement
their functionality. Each register has a set number of bits, clock and reset buttons, and takes
input from four switches. The code provided for the PIPO register uses a process block to check
the clock and reset signals and update the output accordingly, which can be extended to the
SISO and universal shift registers with appropriate modifications. The goal is to implement
these digital circuits in hardware using VHDL code and ensure that they function as intended
in the overall system.
3.3
VHDL Code:
1. PIPO register code
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library ieee;
use ieee.std_logic_1164.all;
entity part3 is--pipo
port(
clk,res : in std_logic;
I : in std_logic_vector(3 downto 0);
O : out std_logic_vector(3 downto 0)
);
end part3;
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architecture marimo of part3 is
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begin
process(clk,res)
begin
if(res ='0') then O <= "0000";
elsif (clk'event and clk ='1') then o<=i;
end if;
end process;
end marimo;
2. SIPO register code
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library ieee;
use ieee.std_logic_1164.all;
entity sipo is
port(
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clk,res : in std_logic;
i : in std_logic;
o0,o1,o2,o3 : out std_logic
);
end sipo;
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architecture marimo of sipo is
signal state : std_logic_vector(3 downto 0);
begin
process (clk, res)
begin
if(res='0') then state <="0000";
elsif(clk'event and clk='1') then state <= i & state(3 downto 1);
end if;
end process;
o0 <= state(0);
o1 <= state(1);
o2 <= state(2);
o3 <= state(3);
end marimo;
3. Universal Shift register code
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library ieee;
use ieee.std_logic_1164.all;
entity uni is
port(
clk,res,iR,iL : in std_logic;
s : std_logic_vector(1 downto 0);
load : in std_logic_vector(3 downto 0);
o: out std_logic_vector(3 downto 0));
end uni;
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architecture marimo of uni is
signal state : std_logic_vector(3 downto 0);
begin
process(clk,res)
begin
if res ='0' then state <="0000";
elsif(clk'event and clk = '1') then
case s is
when "00" => state <= state;
when "01" => state <= iR & state(3 downto 1);--right
when "10" => state <= state(2 downto 0) &iL;--left
when "11" => state <= load;
end case;
end if;
end process;
o<=state;
end marimo;
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3.4
Simulation Results:
1. PIPO register simulation
2. SIPO register simulation
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Part IV: Particular Registers:
4.1
Problem Statement:
Write VHDL code for a 4-bit ring counter, a 4-bit Johnson counter, and a 4-bit nearmaximum linear feedback shift register. Simulate each design and download onto the DE2
board using a push-button as a clock generator.
4.2
Design approach:
The approach to designing the three register circuits includes creating a shift register using
D flip-flops, adding feedback loops to produce the desired counter behavior, and implementing
the designs in VHDL. Each design will be simulated and then downloaded onto the DE2 board
using a push-button as a clock generator.
4.3
VHDL Code:
1. Ring counter code
2. Johnson counter code
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3. Linear feedback shift register code
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4.4
Simulation Results:
1. Ring counter simulation
2. Johnson counter simulation
3. Linear feedback shift register simulation
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Part V: Applications of Registers and Shift Registers:
5.1
Problem Statement:
The problem is to design and implement four LED circuits using VHDL code on the DE2
board. These circuits include a chasing LED system, a collision LED circuit, a circuit to
circulate square patterns on the seven-segment display, and a rotating LED banner circuit.
The VHDL implementations should be efficient and accurate, and their operation should be
verified on the DE2 board at a rate slow enough for visual inspection.
5.2
VHDL Code:
1. Chasing code
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity chasing is
port(
clk,res,dir : in std_logic;
speed:in std_logic_vector(1 downto 0);
leds : out std_logic_vector(15 downto 0)
);
end chasing;
architecture marimo of chasing is
signal state : std_logic_vector(15 downto 0);
signal clk_low : std_logic;--4 speeds from clk div
signal clk_div : unsigned(27 downto 0);--0.25,0.5,1,2 HZ
begin
process(clk)
begin
if(clk'event and clk='1') then clk_div <= clk_div +1;
end if;
end process;
process(speed)--speed select
begin
case speed is
when "00" =>clk_low<=clk_div(27) ;
when "01" =>clk_low<=clk_div(26) ;
when "10" =>clk_low<=clk_div(25) ;
when "11" =>clk_low<=clk_div(24) ;
end case;
end process;
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process(clk,res,dir)
begin
if res='0' then state <="1000000000000000";
elsif(clk_low'event and clk_low='1' and dir ='0') then
state <= state(0)&state(15 downto 1);
elsif(clk_low'event and clk_low='1' and dir ='1') then
state <= state(14 downto 0)&state(15);
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end if;
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end process;
leds<= state;
end marimo;
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2. Collision code
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
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Entity Collision_LEDs is
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Port(
CLK:
LEDR:
LEDG:
in std_logic;
out std_logic_vector(15 downto 0);
out std_logic_vector(7 downto 0) );
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End Collision_LEDs;
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Architecture Logic of Collision_LEDs is
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signal CLK_slow:
std_logic;
signal state_driver: std_logic_vector(24 downto 0);
signal state_Red:
std_logic_vector(15 downto 0);
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Begin
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Clock_driver: Process(CLK)
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begin
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if Rising_Edge(CLK) then
state_driver <= state_driver + '1' ;
end if;
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End Process Clock_driver;
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CLK_slow <= state_driver(8) ;
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Collision_Action: Process(CLK_slow)
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Begin
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if state_Red = X"0000" then
state_Red <= X"0180" ;
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elsif Rising_edge(CLK_slow) then
state_Red <= ( state_Red(14 downto 8) & state_Red(15)
) & ( state_Red(0) & state_Red(7 downto 1) ) ;
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End if;
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End Process Collision_Action ;
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LEDG <= state_Red(15 downto 8) ;
LEDR <= state_Red ;
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end Logic;
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3. Rotating Square code
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
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entity Rotating_Square_Ciruit is
port(
CLK:
in std_logic;
En,Cw: in std_logic;
HEX_0,HEX_1,HEX_2,HEX_3:
);
end Rotating_Square_Ciruit;
out std_logic_vector(6 downto 0)
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architecture Logic of Rotating_Square_Ciruit is
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signal CLK_slow:
std_logic;
the simple eye
signal state_driver: std_logic_vector(24 downto 0);
signal disp_halfs:
std_logic_vector(7 downto 0);
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begin
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Clock_driver: process(CLK)
begin
if Rising_Edge(CLK) then
state_driver <= state_driver + '1' ;
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end process Clock_driver;
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CLK_slow <= state_driver(8) ;
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Rotating_Action: process(clk_slow)
begin
if disp_halfs = "00000000" then
disp_halfs <= "10000000" ;
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elsif En = '0' then
disp_halfs <= disp_halfs ;
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elsif Rising_Edge(CLK_slow) then
case Cw is
when '0' =>
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disp_halfs <= disp_halfs(0) & disp_halfs(7 downto 1) ;
when '1' =>
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disp_halfs <= disp_halfs(6 downto 0) & disp_halfs(7) ;
when others =>
disp_halfs <= disp_halfs ;
end case;
end if;
end process Rotating_Action;
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HEX_0 <= not ( ( disp_halfs(4) OR disp_halfs(3) ) & disp_halfs(4)
& disp_halfs(3) & disp_halfs(3) & disp_halfs(3) & disp_halfs(4) & disp_halfs(4));
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HEX_1 <= not ( ( disp_halfs(5) OR disp_halfs(2) ) & disp_halfs(5)
& disp_halfs(2) & disp_halfs(2) & disp_halfs(2) & disp_halfs(5) & disp_halfs(5));
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HEX_2 <= not ( ( disp_halfs(6) OR disp_halfs(1) ) & disp_halfs(6)
& disp_halfs(1) & disp_halfs(1) & disp_halfs(1) & disp_halfs(6) & disp_halfs(6));
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HEX_3 <= not ( ( disp_halfs(7) OR disp_halfs(0) ) & disp_halfs(7)
& disp_halfs(0) & disp_halfs(0) & disp_halfs(0) & disp_halfs(7) & disp_halfs(7));
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end Logic;
4. Rotating LED banner code
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
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entity banner is
port(
clk,res :in std_logic;
HEX0,HEX1,HEX2,HEX3 : out std_logic_vector(6 downto 0)
);
end banner;
architecture marimo of banner is
signal counter: unsigned(3 downto 0);
--signal lowclk: std_logic;
begin
--counting the state of our banner-- mod10 up
process(clk)
begin
if (counter = "1010") then counter <= "0000";
elsif (clk'event and clk ='1')then counter <= counter + 1;
end if;
end process;
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--process to switch between states
process (clk,res)
begin
if res='0' then -- turn off
HEX0<="1111111";
HEX1<="1111111";
HEX2<="1111111";
HEX3<="1111111";
else
case counter is
when"0000" =>
HEX0<="1000000";
HEX1<="1111001";
HEX2<="0100100";
HEX3<="0110000";
when"0001" =>
HEX0<="1111001";
HEX1<="0100100";
HEX2<="0110000";
HEX3<="0011001";
when"0010" =>
HEX0<="0100100";
HEX1<="0110000";
HEX2<="0011001";
HEX3<="0010010";
when"0011" =>
HEX0<="0110000";
HEX1<="0011001";
HEX2<="0010010";
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HEX3<="0000010";
when"0100" =>
HEX0<="0011001";
HEX1<="0010010";
HEX2<="0000010";
HEX3<="1111000";
when"0101" =>
HEX0<="0010010";
HEX1<="0000010";
HEX2<="1111000";
HEX3<="0000000";
when"0110" =>
HEX0<="0000100";
HEX1<="1111000";
HEX2<="0000000";
HEX3<="0010000";
when"0111" =>
HEX0<="1111000";
HEX1<="0000000";
HEX2<="0010000";
HEX3<="1000000";
when"1000" =>
HEX0<="0000000";
HEX1<="0010000";
HEX2<="1000000";
HEX3<="1001111";
when others =>
HEX0<="1111111";
HEX1<="1111111";
HEX2<="1111111";
HEX3<="1111111";
end case;
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end if; end process; end marimo;
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Conclusion
In conclusion, the Registers/Shift Registers and Applications lab provided a comprehensive
understanding of the design and implementation of circuits using discrete ICs and the protoboard, as well as the use of VHDL to design and implement registers and shift registers. The
lab explored various applications of registers and shift registers. Through hands-on experience
and careful consideration of input signals and hardware components, the lab demonstrated the
importance and versatility of registers and shift registers in digital circuit design.
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