1.10 Availability is the most important consideration for designing servers, followed closely by scalability
and throughput.
a. [10] We have a single processor with a failure in time (FIT) of 100. What is the mean time to failure
(MTTF) for this system?
Ans: 10^9/100 = 10^7
NOTE :(It is expected from the students that to explain why they have used 10^9)
As a metric, MTTF represents how long a product can reasonably be expected to perform in the field based
on specific testing.
10^9 represent billion. Generally reported as failures per billion hours of operation or Failure in Time (FIT)
b. If it takes one day to get the system running again, what is the availability of the system?
Ans: The calculated mean time to failure is 10^7 then we can calculate the availability of the system.
10^7/10^7 + 24 = 1 failure Mean Time to Failure is a reliability measure; the reciprocal of MTTF is a rate
of failures. Generally reported as failures per billion hours of operation or Failure In Time (FIT).
NOTE: It is expected from the students to explain how they have calculated
c. Imagine that the government, to cut costs, is going to build a supercomputer out of inexpensive
computers rather than expensive, reliable computers. What is the MTTF for a system with 1000
processors? Assume that if one fails, they all fail.
Ans: Since there are a thousand processors with MTTF of 10^7 hours, the net MTTF is 10^7/1000 or
10^4 hours.
NOTE: It is expected from the students to explain how they have calculated
1.15: Your company has just bought a new 22-core processor, and you have been tasked with optimizing
your software for this processor. You will run four applications on this system, but the resource
requirements are not equal. Assume the system and application characteristics listed in Table 1.1.
The percentage of resources of assuming they are all run in serial. Assume that when you parallelize a
portion of the program by X, the speedup for that portion is X.
a. How much speedup would result from running application A on the entire 22-core processor, as
compared to running it serially?
Ans: 1/(0.5 + 0.5/22)=1.91
NOTE : Amdahl’s Law definition is expected from students.
b. How much speedup would result from running application D on the entire 22-core processor, as
compared to running it serially?
Ans: 1/(0.1 + 0.90/22)=7.10
NOTE : Amdahl’s Law definition is expected from students.
c. Given that application A requires 41% of the resources, if we statically assign it 41% of the cores,
what is the overall speedup if A is run parallelized but everything else is run serially?
Ans: Two possible ways :
First as given in solution book:
41% * 22=9. A runs on 9 cores. Speedup of A on 9 cores: 1/(0.5 + 0.5/9)= 1.8
Overall speedup if 9 cores have 1.8 speedup, others none: 1/(0.6+ 0.4/1.8) =1.22
Second Approach:
Cores by A = 41% of 22 = 9 cores
NOTE: Students can use either technique but second one is tricky
d. What is the overall speedup if all four applications are statically assigned some of the cores, relative
to their percentage of resource needs, and all run parallelized?
Ans: This answer seems to be wrong in solution book. As per our understanding below should be the
answer:
e. Given acceleration through parallelization, what new percentage of the resources are the
applications receiving, considering only active time on their statically-assigned cores?
Ans: This also seems to be wrong in solution book. As per our understanding below should be the
answer:
Appendix
A.9 For the following, we consider instruction encoding for instruction set architectures.
a. Consider the case of a processor with an instruction length of 14 bits and with 64 general-purpose
registers, so the size of the address fields is 6 bits. Is it possible to have instruction encodings for the
following?
■ 3 two-address instructions
■ 63 one-address instructions
■ 45 zero-address instructions
Ans: a. Consider the case of a processor with an instruction length of 14 bits and with 64 generalpurpose registers so the size of the address fields is 6 bits. Is it possible to have instruction encodings
for the following?
3 two-address instructions
63 one-address instructions
45 zero-address instructions
Key: We need to fit the instruction in 14 bits. We have 64 registers, we need 6 bits encode each register
number.
If we have two register addresses, they take up 12 bits, and it leaves us only 2 bits for OPCODE
but we can encode 4 instructions with 2-bit opcode We can use 3 of these opcodes.
The fourth (say 11) is to indicate something other than 2 register address instruction If we have
only one address, we are left with 8 bits for opcode and can encode 256 instructions
But if we are assuming that we have both 2 address and one address We use 2 bits as before and
that leaves only 6 bits for opcode, and we can have 64 instructions
Again, we can use 63 for one address and leave one say (111111) to indicate that it is not a one address
instruction If we have zero addresses, then we can encode 214 different instructions but if have 2 and
one address instructions, we already used 8 bits for opcode leaving 6 bits for zero address instructions à
we can have 64 of them
b. Assuming the same instruction length and address field sizes as above, determine if it is possible to
have
■ 3 two-address instructions
Can be referred to part a
■ 65 one-address instructions
Can be referred to part a
■ 35 zero-address instructions Explain your answer.
Ans: Solution Book
c. Assume the same instruction length and address field sizes as above. Further assume there are
already 3 two-address and 24 zero-address instructions. What is the maximum number of one-address
instructions that can be encoded for this processor?
Ans: Solution Book
d. Assume the same instruction length and address field sizes as above. Further assume there are
already 3 two-address and 65 zero-address instructions. What is the maximum number of one-address
instructions that can be encoded for this processor?
Ans: Solution Book