1. With what you have learnt already and with reference to the manual what
then are DSCH and Microwind programmes, how would you describe
these tools to another electronic engineer ? i.e. what does each do and
how do their functionality and capabilities differ from the information given
in the manual?
根据当前网页内容，DSCH 和 Microwind 是两个不同的计算机程序，它们用于设计和
模拟集成电路。DSCH 是一个逻辑编辑器，用于设计和模拟数字电路。而 Microwind 则
是一个用于设计和模拟微电子器件的程序，它可以模拟 CMOS、双极型和双极 CMOS
（BiCMOS）技术。因此，DSCH 和 Microwind 的主要区别在于它们的功能和应用领
域。DSCH 和 Microwind 可以协同工作，以设计和模拟集成电路。首先，可以使用
DSCH 逻辑编辑器来设计数字电路，并模拟其行为。然后，可以使用 Microwind 来设
计和模拟微电子器件，以实现 DSCH 中设计的数字电路。这样，DSCH 和 Microwind
可以协同工作，以提供一个完整的集成电路设计和模拟解决方案。
2. What advantages and disadvantages would you expect of these two different tools?
As design tools in the hierarchical view if IC design?
根据当前网页内容，DSCH 和 Microwind 作为集成电路设计工具，在分层视图中具有
各自的优缺点。DSCH 作为一个逻辑编辑器，它的优点在于能够快速设计和模拟数字
电路，帮助工程师验证电路设计的正确性。然而，它并不能直接模拟微电子器件，因
此无法提供关于器件物理特性的信息。
相比之下，Microwind 作为一个用于设计和模拟微电子器件的程序，它的优点在于能够
模拟 CMOS、双极型和双极 CMOS（BiCMOS）技术，提供关于器件物理特性的详细
信息。然而，它并不直接支持数字电路设计，因此需要与 DSCH 等逻辑编辑器配合使
用。
总之，DSCH 和 Microwind 作为集成电路设计工具，在分层视图中各有优缺点。它们
可以协同工作，以提供一个完整的集成电路设计和模拟解决方案。
3. Minimum gate length of default 45nm is 0.04 um.
Electrical characteristics of 180 nm:
Electrical characteristics of 65 nm:
Electrical characteristics of 45 nm:
Electrical characteristics of 22 nm:
Comment: with the increase of the technology length, the corresponding Id increases
for the same applied voltage on the gate.
4. The transistor characteristics using the default parameters (45nm):
W=0.58 um, L=0.04 um
W=0.30 um, L=0.04 um
W=1.16 um, L=0.04 um
W=0.58 um, L =0.08 um
W=0.58 um, L =0.16 um
Comment: The larger length and smaller width will produce a higher Id under the same
gate voltage case.
5. The higher gate voltage will produce a higher source/drain current, and this property
will not be altered at different gate width situation.
6. Vth = 0.38 V, T = 27
Vth = 0.30 V, T = 27
Vth = 0.21 V, T = 27
T = 47, Vth = 0.21 V,
T = 87, Vth = 0.21 V
T = 147, Vth = 0.21 V
Comment: The lower the Vth, and Lower the temperature, the higher the maximum Id
current.
7. Tox = 3.5, Vth = 0.19, low leakage
Tox = 3.5, Vth = 0.19, high speed
Tox = 1.5, Vth = 0.19, low leakage
Tox = 1.5, Vth = 0.19, high speed
Tox = 7.5, Vth = 0.19, low leakage
Tox = 7.5, Vth = 0.19, high speed
8. Horizontal cross-section
9. transient characteristics:
For W=0.58 um, L=0.04 um
Comment: When vgate is at zero, no channel exists so the node vsource is
disconnected from the drain. When the gate is on (vgate=1.0 V), the source copies the
drain. It can be observed that the nMOS device drives well at zero but poorly at the
high voltage. The highest value of vsource is around 0.6 V, that is VDD minus the
threshold voltage. This means that the n-channel MOS device does not drives well
logic signal 1
22n Foundry
45n Foundry
65n Foundry
018 Foundry
10. Apply different gate and drain voltages:
a)
b)
c)
11. Apply the Vdd =1v to drain side:
Comment: the max voltage achieved at the source side is 0.681V, which is the Vdd
minus Vth
12. different math models:
Level 1:
Level 3:
BSim4:
13. Physical cross-section layout of PMOS.
14. DC characteristics
Transient characteristics:
Comment: Note that the pMOS gives approximately half of the maximum current given
by the nMOS with the same device size. The highest current is obtained with the lowest
possible gate voltage, that is 0. From the simulation of figure above, we see that the
pMOS device is able to pass well the logic level 1. But the logic level 0 is transformed
into a positive voltage, equal to the threshold voltage of the MOS device (0.35 V).
15. Nand2:
Enlarge the length of N channel twice:
Enlarge the length of P channel twice:
Enlarge the width of P channel twice:
Enlarge the width of N channel twice:
16. InvNmos:
DC characteristics:
Nmos_1
Nmos_2
Transient characteristics: