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A Review on Power Supply Induced Jitter
Article in IEEE Transactions on Components, Packaging, and Manufacturing Technology · October 2018
DOI: 10.1109/TCPMT.2018.2872608
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IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 9, NO. 3, MARCH 2019
511
A Review on Power Supply Induced Jitter
Jai Narayan Tripathi , Senior Member, IEEE, Vijender Kumar Sharma, Graduate Student Member, IEEE,
and Hitesh Shrimali, Senior Member, IEEE
Abstract— The primary focus of this paper is to discuss the
modeling of jitter caused by power supply noise (PSN), named
power supply induced jitter (PSIJ). A holistic discussion is
presented from the basics of power delivery networks to PSN
and eventually to the modeling of PSIJ. The in-depth details and
a review of several methodologies available in the literature for
the estimation of PSIJ are presented.
Index Terms— Power delivery network (PDN), power
integrity (PI), power supply induced jitter (PSIJ), power supply
noise (PSN), signal integrity (SI), time interval error (TIE).
I. I NTRODUCTION
N THE present high-speed systems, operating frequencies
can attain values up to tens of GHz. Considering the scaled
down supply voltages and the higher switching speeds, one
of the most challenging tasks for the system designers is
to maintain the integrity of power and signal in the deepsubmicrometer technologies. Moreover, due to interconnects,
the large amount of switching current flowing through the
circuits along with the scaled supply voltages may cause substantial impact on signal integrity (SI) and power integrity (PI).
The high-speed systems consist of several subsystems. Apart
from the on-chip circuits, various off-chip blocks, such as
voltage regulator modules (VRMs), boards, packages, etc., are
primarily responsible for noise in the power supply. In system
level SI/PI simulations, these subsystems/blocks are simulated
together to estimate the mutual effects of their switching and
loading on common factors such as noise in power supplies.
These kinds of SI/PI analyses are required for characterizing
high-speed analog and mixed-signal systems.
SI and PI correspond to the quality of signal and the quality
of the power supply, respectively. In SI analysis of a system,
the impact of the electrical properties of the interconnects
on signals are analyzed to ensure an efficient propagation
of signals. In PI analysis, the quality of power delivery
in the system (throughout the board, package and chip) is
analyzed [1]–[3]. The detailed discussion of SI and PI
problems at the system level is presented in [4]–[8]. The
I
Manuscript received February 8, 2018; revised June 14, 2018 and
August 10, 2018; accepted September 9, 2018. Date of publication October 1,
2018; date of current version March 13, 2019. This work was funded
by MeitY, Government of India under SMDP-C2SD project and Visvesvaraya PhD Scheme. Recommended for publication by Associate Editor
M. Cases upon evaluation of reviewers’ comments. (Jai Narayan Tripathi
and Vijender Kumar Sharma are co-first authors.) (Corresponding author:
Jai Narayan Tripathi.)
J. N. Tripathi is with STMicroelectronics Pvt. Ltd., Greater Noida, U. P.,
201308, India (e-mail: jainarayan.tripathi@st.com).
V. K. Sharma and H. Shrimali are with the School of Computing and
Electrical Engineering, IIT Mandi, Himachal Pradesh 175005, India (e-mail:
vijender_s@students.iitmandi.ac.in; hitesh@iitmandi.ac.in).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCPMT.2018.2872608
major SI/PI issues are insertion loss, reflection, crosstalk,
electromagnetic interference (EMI), intersymbol interference,
ground bounce, simultaneous switching noise (SSN), etc.
Power supply noise (PSN) in a system occurs due to SSN,
ground bounce, EMI noise, etc. PSN is one of the major
contributing factors for degradation in the circuit performance.
The power supply fluctuations cause timing variations in the
output response of the circuit. Higher supply noise increases
the signal distortion and hence increases the probability of
higher bit error rate (BER).
Jitter is one of the important timing metrics in high-speed
systems. It can be defined in terms of the timing variations in
the transition edges from their ideal positions. Total jitter in a
circuit or system can be categorized into two major categories
as random jitter (RJ) and deterministic jitter (DJ) [9]. A
component of jitter induced because of the PSN and the
substrate noise is called power supply induced jitter (PSIJ).
The PSIJ can be classified as a subcategory of DJ if the
overall supply noise is having a negligible contribution from
the thermal noise. It is desired to minimize the PSIJ to achieve
strict jitter budgets in high-speed data links viz., USB, MIPI,
DDR, PCIe, etc. [10]. For postsilicon validation, jitter can be
measured by various commercial instruments available, such
as a mixed-mode sampling oscilloscope, a jitter analyzer, a
spectrum analyzer, and a BER tester [11], [12]. For pre-silicon
validations, system level SI/PI simulations are required to
estimate it.
In this paper, various analytical, semianalytical, statistical,
and numerical methods available in the literature for modeling
of PSIJ are discussed. A brief introduction of a power delivery
network (PDN) and its limitations for providing constant
power supply to the load are also presented. Also, the basic
important factors responsible for power supply variations are
highlighted.
The rest of this paper is organized as follows. In Section II,
a common and widely used model of the PDN and its
design considerations are discussed. Also, main causes of
PSIJ, the contributing factors for PSN, different PSN modeling
techniques, and the effects of PSN on output are discussed
briefly. In Section III, PSIJ is discussed in detail with various
modeling techniques available in the literature to estimate it.
Section IV concludes this paper.
II. N OISE IN P OWER D ELIVERY N ETWORKS
In this section, the basics of PDN and PSN are discussed.
The basic building blocks of the PDNs are discussed using a
typical PDN model. Next, PSN and its impact on the output
response are discussed. The techniques for modeling PSN are
also mentioned.
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Fig. 1.
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 9, NO. 3, MARCH 2019
A typical PDN [15].
A. Power Delivery Network
The primary objective of a PDN is to deliver a constant
power to all the switching devices of a system under varying
load conditions [2]. The robust design of PDNs has become
a challenging task for the system designers in the present
scenario of the constantly scaling technologies. The higher
speed of operation, increased power consumption, and higher
current transition density cause the fluctuations in a power
supply [13], [14]. In addition to these, the high average
current densities and reduction in switching speeds (due to
electromigration as well as the excessive IR drop in the power
supply) also affect the performance of a PDN.
A typical PDN consists of a VRM, a package, a printed
circuit board (PCB), and on-chip components (interconnects
and loads), as shown in Fig. 1. The AC–DC rectification circuit
converts an ac power supply to a DC power supply as an input
for the VRM, which is usually the initial block of a PDN in
the electronic systems. The major building blocks of a PDN
are as follows.
1) Voltage Regulator Module: The VRM is commonly a
DC–DC buck converter designed to provide a constant and
regulated power supply. A conventional VRM consists of
a power MOSFET (M0 ), a freewheeling diode (DVRM ), an
inductor (LVRM ), a capacitor (CVRM ), a load, and a pulsewidth
modulator circuitry, as shown in Fig. 1. The VRM has lower
impedance at lower frequencies and is capable of delivering
required transient current in these frequency ranges. On the
other hand, at higher frequencies, it has high impedance
because of inductive nature and fails to fulfill instantaneous
current requirements [16].
2) Boards and Packages: The packages and the boards are
dominant in midfrequency ranges in the overall impedance of
the PDN. The DC resistance of package and PCB traces causes
a voltage drop (IR drop) across the package and the board.
However, the effect of resistance may be negligible in some
of the cases, but electromagnetic resonant cavities formed due
to power and ground planes can cause some serious concerns.
At their resonant frequencies, the power planes are the major
sources of noise in the board and the packages [17]. As
shown in Fig. 1, package and board can be modeled by their
equivalent lumped models.
3) On-Chip Interconnects: The interconnects are present
throughout the chip and are used to connect different on-chip
components. Due to resistance and inductance of these interconnects, a voltage drop is developed across them when the
current is drawn by the load. Additionally, these interconnects
create radiated emissions because of the excessive current and
high-frequency noise, which can cause EMI/EMC issues [18].
Fig. 2.
The self-impedance of a practical PDN.
In Fig. 1, the on-chip interconnects are shown by a lumped
RLC model.
4) Decoupling Capacitors: The decoupling capacitors or
bypass capacitors are used in the PDN to decouple the
voltage regulator from the switching circuits. The decoupling
capacitors are placed on the board and on the package as well
as are designed on-chip as well. These capacitors facilitate an
alternative way to reduce the output impedance to get desired
impedance profile of the PDN. These capacitors typically have
a small resistance called the equivalent series resistance (ESR)
of the capacitor. Because of the magnetic field produced
by varying current, an inductive effect is present that can
be represented by an equivalent series inductance (ESL).
The ESL may form a resonant condition by interacting with
capacitance, causing the supply fluctuations at the resonant
frequency. Another type of decoupling capacitors that are
having very high capacitance, which prevent supply output
drop when the current is unavailable, is called bulk decoupling
capacitors. Typically, the bulk capacitors have high ESR values
(2–100 m) [2].
An example is shown in Fig. 2 to depict the self-impedance,
seen at the on-chip, of a practical PDN in a high-speed system
designed in STMicroelectronics. This impedance consists of
lumped models of VRM, S-parameters of a board as well as of
a package, the on-board decoupling capacitors, the on-package
decoupling capacitors, and the chip power module. As it can
be seen in Fig. 2, there are various inductive and capacitive
effects due to the nonideal behavior of the system. At the very
low frequencies, the behavior of impedance profile is resistive,
and at the higher frequencies, it is dominantly capacitive. To
minimize the effect of noise, the impedance is desired to be
as low as possible.
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TRIPATHI et al.: REVIEW ON POWER SUPPLY INDUCED JITTER
513
Fig. 3. An example of power delivery to an inverter through a PDN having
RP , LP , and CP as the equivalent lumped parameters.
B. Noise in PDN
Due to the nonideal impedance of the practical PDNs
(as shown in Fig. 2) and several other factors, there are fluctuations in power supply in the form of the ripples, which is called
PSN. The PSN is primarily dependent on the input bit patterns
and rise/fall times of the switching devices in the system. The
factors, such as increment in data rate, an increased number
of I/O pins on the ICs, and faster rise/fall times, lead to
higher PSN in the system. Analog circuits are comparatively
more sensitive to supply noise, and their responses vary with
frequency of noise. Therefore, PSN analysis is important for
characterization and optimization of high-speed mixed-signal
systems. In general, the PSN mainly consists of the IR drop
and the L di
dt noise [19].
1) IR-Drop: The IR-drop is the DC voltage drop across
a conductor due to its electrical resistance. It is linearly
dependent on the magnitude of the current. The IR drop exists
primarily because of the highly resistive on-chip wires in the
on-chip power grids. The DC resistance of the PDN can cause
detrimental effects on PI. The voltage drop across the PDN,
denoted by Vdrop, can be calculated by its impedance at 0 Hz
and multiplied by the average dc current of the system. In the
low-voltage applications, this effect is very crucial.
2) Simultaneous Switching Noise: The SSN is mainly
because of the switching activities of millions of transistors in
the core circuit. The on-chip circuits generate high-frequency
noise depending upon their input data rates. The switching of
different blocks in a system creates fluctuations in power supply due to di
dt effects. These fluctuations are more prominent
when multiple blocks switch simultaneously for a very short
duration of time. The SSN is dynamic in nature.
To demonstrate an insight of noise due to switching in
a system, an example is shown in Fig. 3. In Fig. 3, a
CMOS inverter is getting a power supply (VDD ) through a
PDN (having RP , LP , and CP as lumped parameters), hence
acting as a load for the PDN. The input terminal of the inverter
is at node IN, and the corresponding output terminal is at node
OUT. Based on the input data pattern and current requirements
of the transistor, there are fluctuations in the supply (VDD )
(or in other words, PSN), which are shown in Fig. 4. Also,
a zoomed-in image of a sample time interval is shown to
demonstrate the fluctuations clearly. As can be seen, there is a
noise due to switching, which depends on the values of lumped
components of the PDN.
Fig. 4. Noise at supply (VDD ) in the PDN of Fig. 3 due to the switching
of the inverter.
C. Impact of Power Supply Noise on Output
As mentioned earlier, PSN may cause performance degradation in a high-speed system. Because of the PSN, jitter, power
supply rejection ratio, and noise margins may not be able to
sustain themselves within the defined tolerance limits. In the
present deep submicrometer technologies, the tolerance limits
are typically ±5% to ±10% for the supply voltages, including
the dc offset, ripples, and external noise (EMI).
Because of the PSN, the major effects on output are as
follows.
1) Propagation Delay: Propagation delay of a circuit can
change because of its intrinsic capacitors. The charging and
discharging times of these capacitors change with power
supply fluctuations, and hence, the propagation delays are
changed due to the PSN.
2) Output Slope: The rising and the falling edges of a circuit
are largely affected by the PSN. Delay, rising/falling time, and
the slope of the output signal are dependent on the RC timeconstant and power supply of the circuit.
3) Bias Point: The variations in the power supply voltage
can disturb the biasing point of the transistors, which can result
in threshold voltage variations. The duty cycle of the output
signal is dependent on the threshold voltages of the transistors.
4) Time Interval Error: The time interval error (TIE) is
the difference between an ideal transition edge and an actual
transition edge at the zero crossover point, as shown in Fig. 5.
The main causes of the TIE are the changes in output delay
and transition edge slope, shift in bias point of transistors, etc.
Due to the TIE, the timing margins are affected and there may
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514
Fig. 5.
IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 9, NO. 3, MARCH 2019
An example of TIE and peak-to-peak jitter.
Fig. 6. An example of power supply fluctuation due to the PDN on the load
output.
Fig. 7. An example exhibiting the impact of PDN noise on the output of
the circuit shown in Fig. 6 [46].
be violations in setup/hold times of the system. The TIE can
be analytically calculated by modeling the output response of
the circuit [20], [21].
An example is shown in Fig. 6 to demonstrate the effects
of PSN on the output. A differential driver is considered in
this example, which is widely used for scalable low-voltage
signaling applications. This driver is having complementary
differential inputs (DP and DN), and the differential output is
denoted by v Rn (t). As shown in Fig. 6, it is sharing the power
supply with another subsystem, which is drawing a current
d
i (t)
i (t) from the same power supply. Because of the PDN, dt
effects will cause the voltage fluctuations at VDD , which will
eventually affect the output of the differential driver. Fig. 7
shows PSN and its effects on output for this case, where v n (t)
represents the fluctuations in VDD (also called PSN). The right
y-axis, dotted line represents the noisy supply (VDD + v n (t))
and the left-y axis, solid line represents the differential output
(v Rn (t)) in the presence of noise.
After modeling the PSN, the estimation of the PSIJ can be
done using various methodologies available in the literature.
The knowledge of the characteristics of the PSN in the system
can subsequently be used to model the PSIJ. Some of the PSIJ
estimation techniques are discussed in Section III.
D. Methods to Model Power Supply Fluctuations
As shown in Fig. 7, PSN affects the output of a circuit.
This effect can be in terms of both the amplitude (as shown
in the zoomed-in image of Fig. 7) and timing (rise/fall
times) of the output. The variations in rise/fall times (or
jitter) induced by power supply variations can be estimated
by knowing the characteristics of these fluctuations in the
PDN [10]. Various methods have been introduced in the literature to model PSN. These methods are the finite-difference
method [22]–[24], the linear programing method [25], methods
based on frequency- and time-domain formulations [26]–[28],
radial basis function modeling [29]–[31], spline function
based on finite-difference methods [32], adaptive circuit
block methodology [33], recurrent neural network models [34], [35], and the vector based approach [36]. For the
scope of this paper, the details of these methods are not
discussed.
III. P OWER S UPPLY I NDUCED J ITTER
In this section, various methods to estimate PSIJ are discussed in detail, using corresponding analytical/semianalytical
relationships and the details of statistical and numerical techniques. Also, some flowcharts are presented for the purpose
of a quick understanding for the readers.
A. Frequency-Domain Analysis
Frequency-domain analysis is explained in [37]–[40] based
on two factors. The first one is the switching activitydependent supply noise spectral content (V ( f )), and the
second one is the operating mode dependent jitter sensitivity
profile (S( f )). The jitter spectrum J ( f ) can be expressed
as [39]
J ( f ) = V ( f ) · S( f ).
(1)
The supply noise spectrum V ( f ) is a product of the current
spectrum Inoise ( f ) and the PDN impedance profile Z PDN ( f )
V ( f ) = Z PDN ( f ) · Inoise ( f ).
(2)
The impedance of off-chip PDN can be extracted by EM
tools as Z-parameters, and the on-chip PDN can be modeled
either by the lumped modeling or by the distributed modeling.
Furthermore, the current profile is extracted by simulating the
circuit in the nominal power supply conditions. The extracted
current profile is used as the current sources to provoke the
PDN of the system.
Fig. 8 explains (2) by demonstrating this for a practical system on chip (SoC). This SoC was designed in
STMicroelectronics and was having multiple power supplies.
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TRIPATHI et al.: REVIEW ON POWER SUPPLY INDUCED JITTER
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Fig. 10.
Steps used for the extraction of jitter sensitivity at a frequency f 1 .
Fig. 11.
Frequency-domain analysis-based method for the PSIJ estimation.
Fig. 8. A practical case study using an SoC to demonstrate (a) impedance of
the PDN, (b) current spectrum of a subsystem in the SoC, (c) corresponding
noise spectrum, and (d) noise in time domain.
Fig. 9. Output of the SoC without PSN (solid) and with noise (dotted) for
two sample bits.
Fig. 8(a) shows the impedance of the PDN for one of the
power supplies from 10 MHz to 500 MHz, and Fig. 8(b) shows
the current profile of a subsystem of the SoC using the same
power supply. The current profile in Fig. 8(b) is extracted in a
nominal or ideal power supply condition and can eventually be
used to estimate the PSN in the PDN by multiplying itself with
the impedance of the PDN. This helps in saving the design
cycle of the SoC by providing an estimation of the PDN noise
if there is any change in the PDN design. Fig. 8(c) shows
the PDN noise in frequency domain corresponding to the
switching activity [see Fig. 8(b)] and the PDN impedance [see
Fig. 8(a)]. Supply noise in time domain, as shown in Fig. 8(d),
can be obtained by applying IFFT to this spectrum.
To further demonstrate the impact of supply noise on TIE,
Fig. 9 shows the output of the SoC without supply noise and
with supply noise of Fig. 8(d) for two sample bits. It can
be seen that in addition to the amplitude noise, the supply
noise also introduces variations in the rising/falling edges of
the output causing TIE at midpoints, which can be collectively
called PSIJ.
Fig. 10 shows a flowchart to explain the traditional approach
to determine the jitter sensitivity profile S( f ). In this approach,
a low-amplitude sinusoidal signal of a particular frequency
is applied at the voltage supply node over a DC supply.
The maximum TIE obtained at output is recorded for that
particular frequency. Similarly, this procedure is repeated for
various frequencies, and S( f ) is obtained in terms of ps/mV.
Fig. 11 shows the steps involved in frequency-domain
approach to predict the PSIJ. The supply noise spectrum
indicates the highest effects of jitter over the frequency range.
The worst peak-to-peak jitter that can be derived from the jitter
spectrum profile is given as [39]
∞
J ( f )d f .
(3)
jpp = 2
0
The accumulated jitter percentage, which can be used to
evaluate the highest jitter components over the frequency
range, can be given as
f
η( f ) = 0∞
0
J ( f )d f
J ( f )d f
× 100%.
(4)
Next, time-domain jitter j (t) can be derived by taking IFFT
of (1) as
∞
j (t) =
J ( f )e j 2π f t d f .
(5)
0
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Fig. 13.
Fig. 12.
Jitter sensitivity calculation based on propagation delay.
rising edge. Next, the magnitude jitter sensitivity is given as
TP,max,dc + TP,min,dc |S( f )| = β × sinc π f
2
B. Delay Based Methods
As discussed in Section II, due to PSN, there are variations in the switching transitions of the circuits. Using this
phenomenon, a few methods are introduced in the literature,
which will be covered in this section. The basic idea behind
all delay based methods is to model the perturbation in the
rising/falling edges due to supply noise.
1) Jitter Sensitivity Based on Propagation Delay: A method
for the calculation of PSIJ sensitivity function based on the
propagation delay is discussed in [41] and is explained by a
flowchart in Fig. 12. The jitter sensitivity (S( f )) is used to
calculate the PSIJ using (1).
Reference [41] discusses the power supply jitter sensitivity
calculation despite knowing the architecture of the buffer chain
and its electrical parameters. A chain of buffers is considered
as a test case. The total delay of the buffer chain is given
in [41]
(6)
where T P0 refers to the nominal propagation delay and is
obtained by an equivalent RC model of the buffer [42]. T P ,
VDD , and K buff are the delay change, supply variations, and
a static coefficient, respectively.
The estimation of T P is based on a small-signal equivalent
delay gain model. It is assumed that the delay of each stage is
constant and the buffer chain is modeled by N small sections.
Since the total delay is a function of propagation delays of each
of the small sections, the propagation delay can be expressed
as [41], [43]
N
N
K buff
T P0
+ θ)
T P0,i +
TP ≈
Vn cos ω(i − 1)
N
N
i=1
β =
TP,max,dc − TP,min,dc
VDD,max − VDD,min
i=1
(7)
where Vn represents the supply noise amplitude, ω is the noise
angular frequency, and θ is the phase of noise present at input
(8)
where f corresponds to the frequency of input signal of the
buffer chain, and TP,max,dc and TP,min,dc are the propagation
delays for the maximum and the minimum dc supply voltages,
respectively. Reference [41] concludes that jitter depends on
the propagation delay. Having the higher number of stages,
jitter is increased by the same factor of PSN. The minimum
and maximum propagation delays occur at the maximum and
the minimum values of the PSN, respectively.
2) α-Factor Method: This method incorporates the evaluation of a normalized factor (called α-factor) derived from the
circuit simulations. An α-factor is the “ratio of the normalized
delay and supply voltage variation” [44]. Thus, α can be
expressed as
α=
T P = T P0 + T P
T P = K buff VDD
PSIJ calculation based on the α-factor method.
td /td
VDD /VDD
(9)
where td is the propagation delay of the circuit at nominal
supply voltage, VDD is the offset voltage to nominal supply,
and td is the change in propagation delay because of a small
variation in the supply voltage. This is also a dependent parameter of technology and device. The PSIJ can be calculated
for DC offset to nominal power supply and for ac noise, at
low frequencies. It can be expressed as
VDD
PSIJ = αtd
V
t +tDD
d V
DD (t) PSIJ = α
dt
VDD
t =t
(10)
where VDD (t) is the magnitude of noise signal. The complete flow is shown in Fig. 13. This method is best suitable
for noise with low frequencies (below GHz) and smaller
amplitudes (less than 10% of the supply). However, transistor
nonlinearities increase at high frequency and add further
inaccuracy in the model.
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TRIPATHI et al.: REVIEW ON POWER SUPPLY INDUCED JITTER
517
The final expression (11) of Jr is a function of the timeconstant (τ ), β( f ), v n (t), and VOH .
4) PSIJ Model Based on Recursive Expressions: A recursive method for the PSIJ modeling has been developed in
[47] and [48]. A simplified clock distribution topology of
spine-based global binary clock tree architecture [49] is used
for the analysis. The propagation delay for a single cell of
clock tree architecture is calculated by two quadratic equations
as follows:
t p L H (Vn ) = aVn2 + bVn + t p L Hn
t p H L (Vn ) = cVn2 + dVn + t p H L n
Fig. 14.
Midpoint delay based estimation of TIE.
3) Midpoint Delay Based Estimation of Time Interval Error:
As discussed in Section II, the TIE is the instantaneous jitter
at a particular edge (refer to Fig. 5). Based on TIE calculation,
a semianalytical relationship between TIE and PDN noise,
depending on the midpoint delays at the transition edges of the
output response, is derived in [45]. A linear and approximated
relationship between periodic PDN noise and the TIE is
derived for differential signaling as a function of magnitude
of PDN noise. The approximated expression is given as
TIE = Jr ≈
∞
τ (βi pi sin (2π fi t))tm
VOH
(11)
i=0
where τ is the effective time constant of rising and falling
edges (assuming same rise and fall times), βi represents the
transfer function corresponding to the i th frequency component
of the PDN noise, VOH is output HIGH across the differential
output terminals, and pi refers to the Fourier coefficient of i th
frequency component ( f i ).
The expression for TIE, as mentioned in (11), is derived
for a current-mode driver circuit. The expression is
validated in different technologies, such as 130-nm BiCMOS
technology, 55-nm triple-gate oxide BiCMOS technology,
and 28-nm FD-SOI technology (all technologies from
STMicroelectronics). Also, it is shown that both the delaybased method [45] and the slope based method [efficient
modeling of power supply induced jitter (EMPSIJ)] [46] are
fundamentally and analytically same in the case of small
values of noise.
Fig. 14 shows a flowchart to obtain the relationship between
TIE and noise, as mentioned in (11). The TIE at the midpoint
of a transition edge is calculated by both large-signal and
small-signal analyses. The output response without PDN noise
(v R (t)) is a function of time, device/circuit parameters (β), and
load (Z L ). It has been obtained using 1-bit simulation of the
circuit. The noise at output (vrn (t)) is obtained by a transfer
function (β( f )) from power supply to the output using smallsignal analysis.
(12)
where t p L H (Vn ) and t p H L (Vn ) are the propagation delays
because of supply noise (represented by Vn ) for low-to-high
and high-to-low transition edges, respectively. The coefficients (a, b, c, and d) in the equation are calculated using the
least square error method (by curve fitting of SPICE results).
The propagation delays at nominal supply for both low-to-high
and high-to-low edges are denoted as t p L Hn and t p H L n . The
n th period jitter (or in other words, cycle-to-cycle jitter) at the
k th stage of the clock is given by
PSIJn,k = tn+1,k − tn,k
(13)
where tn+1,k and tn,k are the arrival time of the (n+1)th and n th
leading edges at the k th clock stage, respectively. The arrival
time is estimated on the basis of propagation delay. The arrival
time of the n th and (n + 1)th leading clock edge for a k stage
clock distribution is expressed as
tn,k = t p L H (v n (tn,k−1 )) + · · · + t p H L (v n (tn,1 )) + tn,1 (14)
tn+1,k = t p L H (v n (tn+1,k−1 ))+· · ·+t p H L (v n (tn+1,1 ))+tn+1,1
(15)
where t p L H (v n (tn,k−1 )) and t p L H (v n (tn+1,k−1 )) are the propagation delays due to power supply variation of the n th and
(n + 1)th leading edges at the (k − 1)th clock edge.
5) α-Power Law Model Based Approach for Inverters:
For modeling the delay of inverters, an extensive literature is
available [50]–[58]. From the very initial development in 1952
by Burns [50] to the recently developed models incorporating
short-channel effects of present technologies, the modeling
of inverter delay has been of interest to the researchers. The
α-power law1 based models are very effective for modeling
the delay of the short channel devices [60], [62].
As mentioned in Section II, the propagation delay of any
circuit is affected by the power supply fluctuations [59].
Moreover, the optimal stages of the circuit majorly depend
on the buffer delay, clock, and timing circuit (which may be
affected by supply fluctuations). Therefore, higher fluctuations
may affect the optimal solution for the circuit. The high-tolow propagation delay (t p H L ) and the low-to-high propagation
delay (t p L H ) for a single buffer based on the α-power law
1 The α-power law is the analytical formulation of drain-current of short
channel MOSFETs. This method is the extension of Shockleys’ method [57]
with the inclusion of velocity saturation effects of carriers.
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model can be expressed as [55]
1 1 − vT
C L VDD
−
tpH L , tpL H =
tT +
2
1+α
2IDD
VTH
vT =
(16)
VDD
where the propagation delays are the linear combination of
the output capacitance (C L ) of the CMOS inverter and the
input waveform transition time (tT ). Differential mode noise,
common mode noise, and the loading effects are some of the
factors that affect the propagation delay [59].
The change in buffer delays depending on the polarity of
the power and ground noise (VDD and VSS , respectively)
is given as [59], [60]
t p H L = K 3n VDD + K 4n VSS
CL
tr
(17)
K 3n =
, K 4n =
I D0
VDD (1 + α)
t p L H = K 3 p VDD + K 4 p VSS
CL
tr
(18)
K3 p = −
, K4 p = −
I D0
VDD (1 + α)
where I D0 , tr , and α are the drain current (at VGS = VDS =
VDD ), input transition time, and velocity saturation index,
respectively. The above mentioned equations are valid for
small power supply variations and nondominant nonlinear
effects of transistor.
C. Statistical Methods
1) Probability Density Functions Based Methods: The BER
of an I/O link is dependent on the supply voltage in terms
of amplitude uncertainty and timing variations in the output
response. An analytical approach to obtain output amplitude
uncertainty probability density function (PDF) because of
supply fluctuations for single-ended buffers has been presented
in [61] and [62]. The obtained PDF helps in the calculation of standard deviation, which is used for the root mean
square (rms) jitter calculation. In [62], the effects of external
load (i.e., parasitic inductance because of wire bond or solder
bumps) are also included.
In [63], analytical expressions for output response and
PSIJ estimation derived in [62] are extended to two-stage
buffers. The modeling and calculation of output response have
been done using a stage by stage approach with appropriate load considerations. This analysis is also based on the
I−V characteristics of MOSFETs in both saturation and linear
regions of operations. Nonlinear MOSFETs in both the stages
are modeled as piecewise linear models. In the saturation
region, the drain current (I D p (t) and I Dn (t)) for both the
pMOS and nMOS transistors can be modeled as a linear
function of gate-to-source (VGS ) and drain-to-source (VDS )
voltages as [61]
I D p (t) = G mp VGS + gmp v GS (t) + λ p VDS (t)
(19)
I Dn (t) = G mn VGS + gmn v GS (t) + λn VDS (t)
(20)
where the commonly used modeling parameters, such as
G mp , gmp , G mn , gmn , λ p , and λn , are procured by SPICE
simulations. In the linear region of operation, both the
nMOS and the pMOS can be modeled by their ON-resistance
ronn and ron p , respectively.
For an analysis in the first stage, the input capacitance of
the second stage is combined with the load capacitance of the
first stage. For the calculation of the input capacitance of the
second stage, several sinusoidal sources ranging from 0 V
to VDD with different oscillating frequencies are applied to
the gate terminal. The equivalent input gate current (Ia ) and
voltage (Va ) waveforms at different frequencies are used to
obtain the value of capacitance (C). The equivalent capacitor (Ceq ) is the average value of C at different oscillating
frequencies as
C=
Ia
.
2π f Va
(21)
Both the low-to-high transient response using a pullup network and the high-to-low transient response using
a pull-down network are calculated using the following
expressions [61], [62].
Expression 1: The low-to-high transient response (V L H1 (t))
for the first stage can be derived by modeling the buffer in
both saturation and triode regions, separately as
V L H1 (t) = VDD +
Vnp1 cos(ω(t + ts ) + φ p1 − ψ
2 r2
2
Ceq
on p1 ω + 1
ψ = arctan 2(Ceqron p1 ω, 1))
(22)
(23)
where Vng1 , Vnp1 and φg1 , φ p1 are the peak-to-peak amplitude
and phase of the ground and PSN, respectively.
Expression 2: The high-to-low transient response (V H L 1 (t))
for the first stage can be derived by modeling the buffer in both
saturation and triode regions, separately as
V H L 1 (t) =
Vng1 cos(ω(t + ts )+φg1 −a tan 2(Ceqronn1 ω, 1))
2 r 2 ω2 + 1
Ceq
onn1
(24)
where ts and t refer to the input transition time and the time
elapsed after ts , respectively.
These voltages (V H L 1 (t), V L H1 (t)) are the input transitions
for the second stage. In the second stage, the input voltage
fluctuations because of the first stage along with the power
and ground fluctuations are considered. The output response
analysis is the same as that of the first stage with inclusion
of input voltage fluctuations. t p H L 1 and t p L H1 , which are the
input delays for the second stage, have been calculated and
used for the second-stage delay analysis. Finally, PSIJ can be
estimated using the PDF plot of last-stage delay variations at
0.5 VDD . The complete flow of the methodology is shown
in Fig. 15.
2) Latin Hypercube Sampling: The Latin hypercube sampling (LHS) is a statistical method to generate controlled
random samples. The response surface methodology (RSM)
is a set of mathematical and statistical techniques that helps
for optimization and modeling of the output response [64]. The
LHS method combined with the RSM is used to characterize
and to model the PSIJ in [65]. The LHS method is used to
get jitter values at different sampling points. Resulting jitter
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TRIPATHI et al.: REVIEW ON POWER SUPPLY INDUCED JITTER
519
Fig. 16.
Slope based EMPSIJ method.
a result of PSN is determined using (25). The LHS method
is widely used as a tool to compute the uncertainties in the
computer models [67], [68].
D. Slope Based Methods
As described in Section II, one of the effects of PSN on
output signal is a change in the slope of its output voltage.
Thus, the slope can also be used to model the PSIJ. A couple
of methodologies to model PSIJ based on the slope of the
rising/falling edge are discussed in this section.
1) Efficient Modeling of Power Supply Induced Jitter: A
recently introduced methodology based on the calculation of
the slope of the output, named EMPSIJ, is explained in [46].
This methodology is based on the separate analyses for largesignal and small-signal voltages and subsequently by adding
them to get the system response in the presence of PDN noise.
Using 1-bit simulation, an accurate value of the slope at the
midpoint is evaluated, which is used for the estimation of TIE
(represented by Jr ), by the following relationship:
Jr =
Fig. 15.
Output response and PDF calculation for a two stage buffer.
values are used to model the response surface model on these
sampling points.
A second-order response surface model (RSM) can be
represented as [66]
y = a0 +
n
i=1
ai x i +
n
i=1
aii x i2
+
n
n ai j x i x j
(25)
n=1 j =1
where x i and x j are the input design variables and a and
n are the tuning parameter and the number of independent
input variables, respectively. The input variables (x i ,x j ) in
(25), such as power supply, power supply standard deviation,
and ground supply standard deviation, can be obtained
by applying the LHS method to system input parameters.
Considering these input variables, total built-in-jitter (rms) as
(vrn )tm
γ
(26)
where γ is the slope of the output rising or falling edge without
any PSN and (vrn )tm is the amplitude of the small-signal noise
response at midpoint. Next, the PSIJ can be calculated as
the difference between the maximum and minimum values of
TIE as
PSIJ = max Jrk
n
k=1
− min Jrk
n
k=1
(27)
where Jrk is the TIE at the k th rising/falling edge.
In [46], the details of the derivation of the above relationship
are provided with the physics-based insights of the PSIJ. The
expressions are derived for a voltage-mode (VM) driver circuit
but are not limited to VM driver circuit and can be used for
other circuits as well. The complete flow of the slope-based
EMPSIJ method is shown by a flowchart in Fig. 16.
In [69]–[71], EMPSIJ is extended and validated, including
the effects of ground bounce and transmission media on PSIJ.
It is also extended and validated for substrate noise-induced
jitter in [72].
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2) Slope Based PSIJ Calculation for an Inverter: In [73],
an analysis of the PSIJ for a single-ended inverter is discussed.
The supply-to-jitter transfer function is obtained analytically.
The analysis for low-to-high and high-to-low transitions is
based on I–V characteristics in the saturation region of pMOS
and nMOS transistors, respectively. The output voltage (Vout )
is a sum of the voltage at nominal VDD and the voltage at ac
fluctuations as
Vout (t) = Vout,0 (t) + Vout,n (t)
(28)
where Vout,0 (t) and Vout,n (t) are the output voltages at nominal VDD and at the sinusoidal supply fluctuations, respectively.
The small-signal analysis is used to calculate the supply
fluctuations response (Voutn (t)) and the large-signal analysis
is used to calculate the output response (Vouto (t)) due to the
dc voltage (VDD ). The output response of an inverter can be
expressed as
λ
Gm
Vout,o (t) = VDD 1 +
1 − exp − t
(29)
λ
C
λ + gm
Vout,n (t) = 2
Vn0 (A(t) cos ωtdk + B(t) sin ωtdk )
λ + C 2 ω2
(30)
λ
A(t) = λ sin ωt − Cω cos ωt + Cω exp − t
C
λ
B(t) = λ cos ωt + Cω sin ωt − λ exp − t
(31)
C
where G m , gm , λ, ω, Vn0 , C, and tdk are the large-signal gain,
small-signal gain, transconductance gain, angular frequency,
amplitude of supply noise, load capacitor, and the timing offset
between circuit transition and PSN, respectively.
A straightforward calculation of peak-to-peak jitter can be
obtained by estimating multiple low-to-high transitions with
respect to time. At low-to-high transition edges, the maximal
difference at the midcrossing voltage is peak-to-peak jitter
Vout,n
(32)
Slope
Vout,n (t p L H ) = max(Vout,n (t p L H )) − min(Vout,n (t p L H )).
Jitter =
(33)
PSIJ can be calculated using (32) only when the magnitude
of Vout,n is trivial compared to 0.5 VDD . Finally, the jitter
transfer function (Hjitter( f )) can be obtained as
Jitter Hjitter( f ) = (34)
Vn0 where Vn0 denotes the amplitude of PSN.
A complete flowchart for the PSIJ estimation for the singleended buffer by the method described in [73] is shown
in Fig. 17. The supply fluctuations are considered as white
noise. It is assumed that supply fluctuation has the same effect
on both the rise and fall times.
E. Piecewise Linear/Nonlinear Modeling
The PSIJ can also be estimated by piecewise linear or
nonlinear modeling of MOSFET I–V characteristics [21], [74],
[75]. As discussed in Section II, the TIE is calculated at the
Fig. 17.
Slope based PSIJ calculation for single-ended buffer.
Fig. 18. Piecewise nonlinear modeling of the output rising edge for a voltagemode transmitter driver circuit in ideal power supply.
midpoint of the output transition edges. Hence, the output
transition edges (both rise and fall) can be modeled in pieces
using different polynomials for each time interval. This makes
the nonlinear output response modeled into the approximate
piecewise linear/nonlinear response.
In [21], a VM driver is used for the PSIJ analysis. The
output response is considered to be a sum of the noise
response and the large-signal response [refer to (28)]. The
midpoint calculation for PSIJ is based on both the small-signal
and the large-signal analysis. The voltage contributed by the
noise source at midpoint is calculated using the small-signal
analysis. The large-signal analysis is used to model output
response in the absence of supply noise. Next, a piecewise
nonlinear model or polynomial is used to fit the rising edge at
nominal supply voltage. Fig. 18 shows the piecewise nonlinear
modeling of the differential output voltage (rising edge) for a
VM driver circuit [46]. The modeling of a rising edge is done
using five different quadratic polynomials. For PSIJ calculation, the particular polynomial having the midpoint (tm 0 ) in
its time range is considered for further calculations. Next, the
midpoint (tm 0 = (tmid )v in =0 ) of the output rising edge can be
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TRIPATHI et al.: REVIEW ON POWER SUPPLY INDUCED JITTER
obtained as
(tmid )v in =0 = −
a1 ±
521
a12 − 4a0 a2
.
(35)
2a2
Similarly, the midpoint of the rising edge in the presence of
PSN can be evaluated as
a1 + a12 − 4a2 (a0 + βv in )
tmid = −
.
(36)
2a2
Finally, peak-to-peak PSIJ can be calculated using the
following expressions:
Jr = (tmid )v in =0 − tmid
2
a1 − 4a0 a2 ± a12 −4a0a2 − 4a2 βv in
ttotal =
n
tn
(39)
1
I D = pVGS + qv GS + sv DS
k
tm(n+1)
(37)
1
±
(38)
2a2
where a0 , a1 , and a2 are the polynomial coefficients, β corresponds to the noise transfer function, v in is the input noise
source voltage, and tmid and (tmid )v in =0 are the midpoints of
the output rising edge with and without PSN, respectively.
In [74] and [75], MOSFET I − V curve is modeled by a
piecewise linear (PWL) approximation. A chain of inverters,
having linear delay, is used for the analysis. The transfer
function of PSIJ for a single-stage inverter is calculated by
the PWL approximation of the MOSFET I − V curve. The
complete transfer function of PSIJ for a chain of inverters is
then obtained by accumulating PSIJ of all the stages. The total
delay of the number of inverters is given by [74]
Jr =
supply to output transfer function at f = f n , Td corresponds
the bit period of input data, ã = pi |β( f )| f i , φi = ( β( f )) fi ,
and pi is the Fourier coefficient of the i th frequency component
of the supply noise.
Note that, F(t) in (41) represents the modeling for just
a rising/falling edge, where the first two terms represent the
large-signal response and the third term represents the smallsignal response. Now, based on the root-finding approach, the
roots of (41) are evaluated for different transition edges. The
expression for evaluation is as follows:
(40)
where p, q, and s are the coefficients of different operating
modes for an MOSFET, tn corresponds to the single stage
inverter, VGS is large-signal gate-to-source voltage, and v GS
and v DS are the small-signal gate-to-source and drain-tosource voltage, respectively. Using (40), the rising and falling
edges of each inverter stage are modeled for their respective
operating modes. Finally, the peak-to-peak PSIJ is calculated
as a difference of maximum and minimum delay of the inverter
chain, which is a function of phase and a particular frequency
of the supply noise.
i=1
Bi edi (t −2(k−1)Td ) +
k
F tm(n)
∞
(41)
where A, Bi , and di are the constants, k is the k th bit,
f i corresponds to the frequency of noise, β( f ) represents
(43)
G. IBIS Model Based Approach
The input/output buffer information specification (IBIS)
models are the standard models used to provide the electrical
characteristics of an intellectual property without disclosing
other details of it, such as the schematic, process information,
etc. [77]. The IBIS model based method to estimate the jitter
transfer function is introduced in [78] by assuming that the
characteristics of supply noise are known in advance. In [78],
based on the I/V characteristics and pin package parameters
of the I/O buffer, a second-order differential equation is used
to formulate the jitter transfer function. The formulation of the
second-order differential equations can be accomplished using
nodal analysis and IBIS model files for a given circuit. The
expressions for both low-to-high and high-to-low transitions
in the presence of power and ground voltage fluctuations are
obtained by solving the second-order differential equations.
The low-to-high transition (Vout(t L H )) for an inverter (with
inclusion of package parameters) can be expressed as
(44)
where Vout0 (t) is the output response without power/ground
noise and is a function of VDD , pull-up I/V fitting parameters (Pu1 /Pu0 , Pd1 /Pd0 ), switching time (ts ), device, and
package parameters (R, L, and C).
The approximated solution for Vout0 (t) can be expressed as
Vout0 (t) ≈
ã sin(2π f i t + φi )
i=0
(42)
k
k
and tm(n)
are the (n + 1)th and n th iterations,
where tm(n+1)
k
respectively. F(tm(n) ) is the output response because of the
k
. After a few iterations, TIE at the k th
PSN at t = tm(n)
bit is calculated, which can eventually be used for the PSIJ
estimation by (27).
Vout (t L H ) = Vout0 (t) + Voutn (t)
Recently, a numerical method is proposed to estimate the
PSIJ using a root-finding approach by classical Newton’s
method [76]. In this paper, an equivalent circuit of the VM
driver is analyzed as an example. A function for differential
output response of the VM driver (the same circuit as used
in [46]) is formulated. The driver output in the presence of a
noise with single tone is modeled as
3
−
k
F tm(n)
Jrk = tmk 0 − tmk
F. Numerical Method
F(t) = A +
=
k
tm(n)
s p2 (Vout(ts )) − VDD − pu0 / pu1 s p1 t
e
s p2 − s p1
+ (VDD + pu0 / pu1 )
(45)
where
s p1, p2 =
(C/ pu1 − RC) ±
(RC − C/ pu1 )2 − 4LC
. (46)
2LC
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Finally, TIE due to ground and power supply fluctuations
can be calculated as
ground
TIE L H (ω) = H L H
ground
H L H (ω)
power
(ω)Vg (ω) + H L H (ω)V p (ω)
(53)
power
H L H (ω)
and
are the jitter transfer funcwhere
tion for low-to-high output transition edge with ground and
ground
power
PSN, respectively. H L H (ω) and H L H (ω) can be obtained
by solving (51) and (52). Vg (ω) and V p (ω) are the spectrum of
ground and PSN, respectively. Likewise, TIE for high-to-low
transitions can be determined in the same way.
A complete flowchart of TIE estimation methodology using
the IBIS model is shown in Fig. 19. Unlike previous methods,
this method is useful for large systems even without knowing
their circuit details.
IV. C ONCLUSION
Fig. 19.
This paper discusses the basics of PSIJ and its modeling
approaches available in the literature. The relevant discussions
on PDNs, PSN, and their effects on the output are also presented. Various PSIJ modeling techniques, such as frequencydomain analysis, delay based techniques, statistical methods,
recursive methods, slope based methods, numerical methods,
and IBIS model based methods, are discussed.
IBIS model based PSIJ calculation for single-ended buffer.
Similarly, Voutn (t) can be expressed as
Voutn (t) ≈
Vnp (A(t) cos(ϕ) + B(t) sin(ϕ))
(s p1 − s p2 ) (1 − LCω2 )2 + (RC − C/ pu1)2 ω2
(47)
where
A(t) = s p2 es p1 t + s p1 cos(ωt) − s p2 cos(ωt)
B(t) = ωes p1 t − s p1 sin(ωt) − s p2 sin(ωt)
ϕ = ωts + φ p − arctan 2((RC − C/ pu1 )ω, 1 − LCω2 ).
The TIE at 0.5 VDD for low-to-high transition edge due to
ground fluctuations can be obtained by
ground
TIE L H
= tpL H − tpL H0
(48)
where t p L H and t p L H 0 are the propagation delay with ground
fluctuation at 0.5 VDD and can be expressed as
(0.5VDD + pu0 / pu1 )(s p2 − s p1 )
1
(49)
tpL H =
ln
s p1
s p2 (VDD + pu0 / pu1 − Vout(ts ))
(0.5VDD + pu0 / pu1 )(s p2 − s p1 )
1
tpL H0 =
ln
(50)
s p1
s p2 (VDD + pu0 / pu1 )
cos(ωts + φg − θ )
ground
TIE L H =
(1 − LCω2 )2 + (RC + C/ pd1 )2 ω2
Vng
(51)
×
s p1 (VDD + pu0 / pu1 )
where Vnp , Vng and φ p , φg are the amplitude of power
fluctuations, ground fluctuations, and phase of both the power
and ground fluctuations, respectively.
Similarly, TIE due to power supply fluctuations can be
evaluated as
V
A(t p L H 0 )2 + B(t p L H 0 )2
np
power
TIE L H =
s p1 (s p1 − s p2 )(0.5VDD + puo / pu1)
cos(ωts + φ p − θ )
. (52)
×
(1 − LCω2 )2 + (RC − C/ pu1 )2 ω2
ACKNOWLEDGMENT
The authors would like to thank Prof. R. Achar from
Carleton
University,
Ottawa,
ON,
Canada,
Prof. M. Swaminathan from the Georgia Institute of
Technology, Atlanta, GA, USA, and Prof. J. E. Schutt-Aine
from the University of Illinois at Urbana–Champaign, IL,
USA, for their valuable suggestions to improve this paper.
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Jai Narayan Tripathi (S’07–M’14–SM’18) was
born in Gangapur (Bhilwara), Rajasthan, India.
He received the B.E. degree in electronics and
communication engineering from the Manikya
Lal Verma Textile and Government Engineering
College, Bhilwara, in 2007, the M.Tech. degree in
information and communication technology from
the Dhirubhai Ambani Institute of Information and
Communication Technology, Gandhinagar, India,
in 2009, and the Ph.D. degree in electrical engineering from IIT Bombay, Mumbai, India, in 2014.
He was a Visiting Scientist with the Politecnico di Torino, Turin, Italy,
in 2016 and 2017, where he was also a Visiting Post-Doctoral Fellow in 2016.
He is currently a Technical Leader with STMicroelectronics, Greater Noida,
India, where he has been involved in the design issues of high-speed systems,
such as serial links. He has authored/coauthored over 50 research papers in
refereed journals and proceedings of international conferences. His current
research interests include signal integrity, power integrity, electromagnetic
interference/electromagnetic compatibility, metaheuristic optimization, and
RF circuits.
Dr. Tripathi has also served as a TPC member for several international
conferences. He was a recipient of the Young Investigator Training Program Research Award by the Associazione di Fondazioni e di Casse di
Risparmio Spa, Italy, in 2016 and 2017, consecutively. He is currently serving
as a TPC Co-Chair for IEEE EDAPS 2018. He was an Invited Speaker
at IEEE Electrical Design of Advanced Packaging and Systems 2015 held
in Seoul, South Korea, where he also served as a Session Co-Chair for
the session High-Speed Channels and Interconnects. He has served as a
reviewer for many international journals, such as IEEE T RANSACTIONS ON
V ERY L ARGE S CALE I NTEGRATION S YSTEMS , Progress in Electromagnetics
Research, IEEE T RANSACTIONS ON E LECTROMAGNETIC C OMPATIBILITY,
IEEE T RANSACTIONS ON P OWER E LECTRONICS , and Microelectronics Journal. He has delivered invited talks at various universities, including IIT
Bombay, IIT Mandi, IIT BHU, and IIIT Delhi.
Vijender Kumar Sharma (S’13–GS’13) received
the B.Tech. degree from Rajasthan Technical University, Kota, India, in 2011, and the M.Tech. degree
from the Indraprastha Institute of Information Technology Delhi, New Delhi, India, in 2014.
He is currently a Ph.D. Research Scholar at IIT
Mandi, Himachal Pradesh, India, in collaboration
with STMicroelectronics, Greater Noida, India. He
has authored/coauthored 10 papers in IEEE conferences. His current research interests include jitter,
signal integrity, and high-speed serial links.
Mr. Sharma was one of the recipients of the Best Poster Award at
the 14th International System-On-Chip Conference 2017 held in Seoul,
South Korea.
Hitesh Shrimali (S’09–M’13–SM’18) was born in
Ahmedabad, India. He received the B.E. degree in
instrumentation engineering from the Nirma Institute
of Technology, Ahmedabad, the M.Tech. degree in
instrumentation engineering from IIT Kharagpur,
Kharagpur, India, and the Ph.D. degree in mixed signal VLSI design from IIT Delhi, New Delhi, India.
After completing his education, he was a Senior
Design Engineer with the Analog-to-Digital Converter (ADC) Team, STMicroelectronics, Greater
Noida, India. He was also a Post-Doctorate
Researcher with the Università degli Studi di Milan, Milan, Italy, from 2013 to
2014. Since 2014, he has been serving as an Assistant Professor with IIT
Mandi, Himachal Pradesh, India. His areas of expertise include design and
testing of radiation hard circuits (CMOS silicon detectors), analog and mixed
signal VLSI design (ADCs), modeling of radiation effects on analog and
mixed signal circuits, and on-chip instrumentation.
Dr. Shrimali has served as an Organizing Committee Member and a TPC
Member for IEEE EDAPS 2018. He was a recipient of the Distinguished
Alumni Award in 2017 for the Instrumentation Engineering Department,
Nirma University, Ahmedabad. He has served as a Reviewer for IEEE T RANS ACTIONS ON V ERY L ARGE S CALE I NTEGRATION S YSTEMS , the Journal of
Circuits, Systems and Signal Processing (Springer), IETE, IEEE ISCAS, IEEE
EDAPS, IEEE VLSID, and MWSCAS.
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