By SYED MUHEEB ULLA
Cell-Aware Test (CAT) - An advanced fault model
1. Background
Traditional IC test-pattern generation, including stuck-at, transition, small delay, and bridge, produces high-quality
tests that detect most defects. All of these tests use fault models that define fault sites at IC gate boundaries.
However, a significant population of defects (perhaps up to 50%) occurs within the gates, or cells. Many cellinternal defects can be detected with traditional test methods, but some require a unique set of stimulus to excite
and observe the defect. It is important for applications that require near-zero defects to properly define fault models
that target these cell-internal defects.
The basic premise of IC test is to deliver specified test patterns to a chip. Subsequently, we detect defects within
the chip upon observing its responses to those patterns. We generate test patterns from fault models that represent
potential defects with simple properties. We achieve access to internal nodes of the chip through scan chains. The
scan structures turn sequential logic into shift registers, which are control-and-observe points that can be loaded
and observed from tester equipment.
Fault models in common usage include stuck-at (stuck-at-zero, stuck-at-one), transition, small delay defects,
deterministic bridge, and multiple detect. These fault models are based on observations of silicon defect behavior
and are developed by the electronic software design automation (EDA) vendors. They are commonly available to
anyone using the test pattern generation software.
However, these tests all look for defects only at the boundary of standard cells, or gates, and not the defects that
occur within the standard cells.
2. Introduction to Cell Aware Test
A recent approach, called cell-aware test, targets specific shorts, opens and other physical defects internal to each
cell by modeling it at the transistor level. Analog simulations are performed to characterize the effects of potential
short and open defects. Based on the analog simulation results, a cell-aware fault model is created that directs ATPG
to generate patterns targeting these internal cell defects. There have been multiple studies that show that tests
generated using cell-aware fault models find defects that the normal test methods miss. One such study by AMD
found that after 400,000 die had been tested, 880 defective die per million passed the standard manufacturing test,
but were detected by the cell-aware tests.
A key component of cell-aware test is the ability to create user-defined fault models (UDFM). UDFMs provide
users the ability to define new fault models without waiting for them to be built into commercial test tools. It allows
users to define the stimulus requirements that must be met in order for test patterns to detect a specific defect. The
UDFM model is text based, and incorporates the standard fault models provided with ATPG tools.
Cell “MUX2” {
Fault “Z1” {
test {StaticFault “Z'=1; Condition “D0'=0, “D1'=0, “S'=0;}
test {StaticFault “Z'=1; Condition “D0'=0, “D1'=1, “S'=0;}
test {StaticFault “Z'=1; Condition “D0'=0, “D1'=0, “S'=1;}
}
}
The UDFM above specifies that ATPG must produce one of the three listed input patterns in order to detect fault
Z1. This fault model provides a lot of flexibility and can specify any number of test cycles and can utilize library
models, instances, and hierarchical paths within the design.
3. Why do we need CAT approach?
The goal of silicon testing is to find defective parts before they are shipped to the customer. We measure our success
(or failure) to do this in defects-per-million (DPM), and the lower the number, the better the reliability. The usual
methods involve adding scan-test structures to the design, then applying fault models to pattern-generation tools
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By SYED MUHEEB ULLA
that represent issues such as stuck-at and transition defects. This provides high defect detection, but mostly for
faults at the gate (or cell) boundary, or between library cells. However, today’s fault models like stuck-at, transitionand path-delay are no longer sufficient for detecting all faults and especially defects within cells. With more recent
fabrication technologies, the number of defects occurring within cells is significant, perhaps amounting to roughly
half of all defects. Thus, it is important to ensure that you properly define fault models that target these ‘cellinternal’ or ‘cell-aware’ defects.
Test professionals can now use the physical design of cells as a way of understanding how to target the cell-internal
defects. This involves performing a library characterization to determine where defects can occur and how they
affect the operation of each cell.
Why cell-aware ATPG is so necessary for finding defects that stuck-at and transition patterns presumably miss?
That is a logical and valid question since production test based on stuck-at and transition has worked for many
years. Modern integrated circuits increasingly use highly complex cells, some with high drive strengths, which
mean more internal components such as transistors and resistors. It is no longer rare to find library cells with several
hundred parasitic resistors and coupling capacitors, which means there could be hundreds or thousands of locations
for defects in a cell. Neighboring interconnect lines also have to be considered as potential sources of resistive
bridge defects or shorts, and narrow lines can become open defects.
Without dedicated cell-aware ATPG, it is difficult to achieve the required low defect rates on designs using these
complex cells whose defects cannot be addressed sufficiently with traditional inter-cell-oriented fault models – thus
the need for test patterns for possible cell-internal defects.
The first published industrial results of using a cell-aware testing strategy showed large reductions in defect density.
Later reports have shown an 885 PPM improvement with cell-aware testing, as shown in Figure 1 PPM Improvement
with CAT, an important result for many production environments. Recent validation of these results through systemlevel-test has shown that cell-aware detected defects are uniquely detecting cell-internal defects.
Figure 1 PPM Improvement with CAT
Before stepping through the process of generating cell-aware patterns, let’s first look closer at why it is necessary.
A simple AND gate with two inputs and one output is very simple to understand and model. The logic model has
four possible input combinations: 00, 01, 10, and 11. The 11 combination produces a 1 at the output. All other
combinations produce a 0.
ATPG tools, though, will only use as many input combinations as necessary to detect all the faults at the logical
model. In the case of stuck-at fault models, there is a potential that any input or output is stuck at a 0 or 1. To test
for a stuck-at-0 at an input, a 1 is applied to that input with other inputs set to values that enable the input being
tested to dictate the value of the output.
In this example, we can detect all stuck-at faults if the 01, 10, and 11 input combinations are used. As far as the
logical model is concerned, there is no value in generating a pattern that produces a 00 input.
In the case of this simple AND gate, there isn’t an actual cell-internal defect that would be uniquely detected with
a 00 input. Cell-internal defects would be detected by one of the other combinations, so a cell-aware model would
not be necessary for this cell.
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By SYED MUHEEB ULLA
During normal ATPG, we produce thousands of patterns. So even if a traditional fault model did not target the
defect described above, it could be detected through random chance. But when considering millions of gates in a
design, it isn’t effective to rely on chance to detect these potential cell-internal defects at every gate. One option
would be to apply every possible combination of inputs at every gate. We call this fault model a gate-exhaustive
fault model. It could be effective in detecting many cell-internal defects because it would apply every possible
combination. However, it’s completely impractical to apply such an exhaustive set of patterns.
You might think that a logic model with eight inputs would require 2^8 (256) gate-exhaustive combinations. This
isn’t true because some gates can effectively produce a result at the output from a subset of its inputs.
When a gate is embedded in a real circuit, an input to the gate could be driven to an unknown state (X value) during
pattern generation and simulation. A two-state gate-exhaustive pattern would require every gate input to be at a 1
or 0 state.
An effective gate-exhaustive fault model would need to consider a third don’t-care state applied to inputs. Thus, an
eight-input logic model could require as many as 38, or 6561 patterns.
You could run simulations of these combinations to find the ones that are necessary and do not produce a value at
the output. As a result, you will still have between 28 and 38 combinations for the eight-input model. Many of the
gate-exhaustive combinations will not provide unique defect detection and will be wasted ATPG and patternapplication time.
Furthermore, some defects inside cells can manifest themselves as timing-related defects and are not detectable
using static tests. An efficient method is necessary to target static and dynamic cell-internal defects for low DPM
products. This is the objective of cell-aware ATPG.
4. CAT Architecture
The first step is to characterize each cell in a technology library. The transistor layout for each cell, typically in
GDSII format, is the starting point. An extraction tool is used to extract a transistor-level analog netlist, including
parasitic capacitors and resistors. The netlist is used to identify the location of possible bridge and open defects. To
model a potential cell internal bridge, the parasitic capacitor is replaced by a resistor model. Opens occur when
there is a gap in a connection. In this case, a parasitic resistor that describes connectivity is replaced by a highimpedance resistor.
Analog simulation is then performed to generate the cell-aware model. The analog simulation process iteratively
modifies each parasitic element in the netlist, performs the simulation, and compares the results to the fault-free
analog simulation to conclude if the inserted defect is detected or not. Defects are determined as “detected” when
the cell’s output voltage deviates from the “good circuit” voltage by a specified percentage (typically 50%).
However, not all bridge or open defects are detected by a static change in the output voltage. Some may result in a
delay in the output voltage swing. For these defects, a dual-cycle analog fault simulation is performed at-speed in
order to detect even small delays.
The final process in cell-aware characterization is to convert the list of input combinations into a set of the necessary
input values for each fault within each cell. Because this fault information is defined at the cell inputs as logic
values, it is basically a logic fault model representation of the analog defect simulation. This set of stimuli for each
cell represents the cell-aware fault model file for ATPG.
Within this file, a simulated defect (now a fault) can have one or more input combinations. An example is shown
below. For this example, fault ‘my_stuck_01’, ATPG will try to find any of the three input combinations when
targeting this fault in a design. If any one of the combinations can be applied to an instance of the cell and the fault
effect can be propagated to an observation point, then the fault is marked as detected for this instance; the other
combinations are no longer necessary.
udfm1.0 {
udfmtype'my_stuck_at” {
cell “XOR2” {
Fault “my_stuck_01” {
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By SYED MUHEEB ULLA
Test { StaticFault “Z” = 0; Condition “A” = 0; Condition “B” = 1; }
Test { StaticFault “Z” = 0; Condition “A” = 1; Condition “B” = 0; }
Test { StaticFault “Z” = 1; Condition “A” = 0; Condition “B” = 0; }
}
Because the cell characterization process is performed for all cells within a technology library, any design using
that technology can read in the same cell-aware fault model file. Characterization only needs to occur once, and
can then be applied to any design using that technology node library.
5. Diagrams
Figure 2 Cell Aware Test
1. Open: Any cell-internal open defect, such as an open in poly, metal, diffusion, or vias. In the extracted
SPICE netlist, these defects are matched to existing resistor elements by increasing their resistance values.
Different open resistor values are considered as necessary.
2. Bridge: Any cell-internal bridge defect such as bridges between adjacent objects in the same layer or
different layers. In the extracted SPICE netlist, these defects are matched to existing capacitor elements by
inserting resistors in parallel with them. Different bridge resistor values are considered as necessary.
3. T-leak: Any cell-internal transistor defect that will switch a transistor partially on with a certain resistive
value. Different leakage resistor values are considered as necessary.
4. T-drive: Any cell-internal defect that will switch a transistor partially off with a certain resistive value.
Different drive strength resistor values are considered as necessary.
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By SYED MUHEEB ULLA
5. Port-Bridge: A bridge between a port (e.g., D1) and VSS, VDD, or any other port of the cell. Different
bridge resistor values are considered as necessary.
6. Port-Open: A disconnected port (e.g., D1), to analyze the effect of cell-external disconnects to cell ports.
Different open resistor values are considered as necessary.
Figure 3 Cell Aware Test Process Flow
The CAT methodology consists of two major parts. The first part (see Figure 3 Cell Aware Test Process Flow)
is the technology-dependent CAT view generation flow, which is a one-time task that is
performed once for each technology library.
Figure 4 Cell Aware Model Generation Flow
The second major part is the well-known design flow (see Figure 4 Cell Aware Model Generation Flow) where we
use our CAT ATPG instead of a traditional ATPG. Our CAT ATPG is a defect-based ATPG that
uses the technology-dependent and transistor-level-based CAT view to generate high-quality test
patterns to significantly reduce the defect level of delivered ICs. The CAT ATPG is able to
generate patterns for very large multimillion gate designs. Current results achieved by this new
CAT methodology show a significant increase of the defect coverage and as such a significant
reduction of the defect rate measured in DPPM
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By SYED MUHEEB ULLA
Figure 5 Library Characterization Flow
The first step in the cell-aware methodology is to characterize each cell in a technology library. The flow is
illustrated in Figure 5 Library Characterization Flow. The transistor layout for each cell, typically in GDSII format,
is required as a starting point. An extraction tool, such as Calibre xRC, is used to extract a transistor-level analog
netlist, including parasitic capacitors and resistors, which are used to identify the location of possible bridge and
open defects, respectively. To model a potential cell internal bridge, then, the parasitic capacitor is replaced by a
resistor model. Opens occur when there is a gap in a connection. In this case, a parasitic resistor that describes
connectivity is replaced by a high-impedance resistor.
Analog simulation is then performed to generate the cell-aware model. The analog simulation process iteratively
modifies each parasitic element in the netlist, performs the simulation, and compares the results to the fault-free
analog simulation to conclude if the inserted defect is detected or not. Defects are determined as “detected” when
the cell’s output voltage deviates from the “good circuit” voltage by a specified percentage (typically 50%).
However, not all bridge or open defects are detected by a static change in the output voltage. Some may result in a
delay in the output voltage swing. For these defects, a dual-cycle analog fault simulation is performed at-speed in
order to detect even small delays.
6. Existing methodology/techniques
As the industry moves to increasingly smaller geometries, the existing fault models and associated test patterns are
becoming less effective for ensuring desired quality levels. Existing fault models only consider faults on cell inputs
and outputs, and on the interconnect lines between these cells. A growing number of defects occur within the cell
structures. With more recent fabrication technologies, the population of defects occurring within cells is significantas much 50% of all defects. A way to generate test patterns that efficiently target potential new defects at the
transistor level is required.
Figure 6 Comparison of Normal and Cell-aware tests
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By SYED MUHEEB ULLA
Figure 7 Normal ATPG process
Industry is facing increasingly tougher quality requirements for more complex ICs.To meet these quality
requirements, we need to improve the defect coverage. This paper presents a new methodology to significantly
increase the defect coverage of the test patterns generated by ATPG tools. The fault model used during the ATPG
is enhanced to directly target layout-based intra-cell faults. In contrast to previous techniques, such as GateExhaustive, N-Detect, or Embedded-Multi-Detect, which either are too complex for real-world designs or merely
improve the probability of detecting intra-cell defects, the new approach targets the actual root causes of intra-cell
defects. The newly proposed Cell-Aware-methodology has been evaluated for 90nm and 65nm technologies on
1671 library cells and on 10 real industrial designs with up to 50 million faults. The experimental results show an
average increase of 1.2% in defect coverage and a reduction of 420ppm in escape rate for a 50mm2 design. Figure 7
Normal ATPG process shows how the SA ATPG will generate a test for detecting a port fault; in this case, a SA 0 fault at
the cell input D0. In a traditional SA ATPG engine, the fault position (initial fault injection) and the condition for
the fault excitation is predefined for every ATPG primitive. In this example the SA ATPG would justify D0 = 1,
S0 = 0, and S1 = 0. The other inputs (D1 and D2) are not required.
Figure 8 CAT ATPG for an intracell bridge defect
The generation process of the CAT ATPG for the same multiplexer is shown in Figure 8 CAT ATPG for an intracell bridge defect.
In this case, an intracell bridge is assumed between two nets A and B as indicated in the layout. The initial fault
injection of a CAT defect is always at the cell output port. The condition for the fault excitation and its propagation
to the cell outputs is fully disconnected from any predefined ATPG primitive. It strictly applies the necessary
conditions at the input ports of the library cell as defined by the corresponding CAT model. Considering the bridge
B1 in the above example, the necessary assignments at the cell inputs are D0 = 1, D2 = 0, S0 = 0, and S1 = 0. That
means the CAT ATPG is forced to assign an additional cell input, which is in this case D2, in order to detect the
bridging defect B1. As described earlier, a traditional SA ATPG would only be forced to assign one data input. In
other words, in contrast to previous approaches, the CAT ATPG deterministically applies the conditions to detect
all detectable intracell defects. Traditional ATPGs, however, may detect them only by chance. To guarantee a very
compact set of test patterns, the CAT ATPG algorithm makes use of all possible conditions given by the CAT view
for detecting a certain defect.
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By SYED MUHEEB ULLA
7. Advantages and Disadvantages
Advantages:
Cell-aware testing will be very important for future integrated circuits. It is easy to apply (you only need to
characterize a library cell once for a certain process technology), it will not break your current test flow, and it will
add several percent to your defect coverage.
Figure 9 CAT 3-D FinFET transistor
The CAT methodology fully supports FinFET technologies. The CAT view generation process for FinFET
technologies is in principle the same as for other technologies. For FinFET. transistors the analog fault simulation
introduces transistor defects per fin, so that transistor drive-strength and leakage defects can be analyzed accurately
per fin. Because of the 3-D nature of a FinFET transistor as shown in Figure 9 CAT 3-D FinFET transistor, each fin of
the 3-D transistors can have defects on its own, which will result either in reduced drive strength because one or
more fins are not operating as they should, or in leakage current within one or more fins of the transistor. The
leakage defects are analyzed by CAT by inserting and simulating different leaking resistors from drain to source as
shown in Figure 10 FinFET leakage and drive-strength defects, indicated by the red resistors. Drive-strength defects are
analyzed by simulating different resistor values for the drain and source resistors as shown in Figure 10 FinFET leakage
and drive-strength defects, indicated by the green resistors R1 and R2.
The black falling edge in Figure 10 FinFET leakage and drive-strength defects represents a fault-free cell output waveform.
Depending on the severity of a leakage or drive strength defect, a larger delay will be observed at the cell output
(see the green falling edges), and in addition the final settled state may not reach the required low or high state in
case of a leakage defect (see the red falling edges). Simulating drive strength and leakage defects accurately per fin
ensures that the CAT ATPG is forced to generate all needed cell input conditions to fully test the drive-strength
and leakage defects for FinFET technologies.
Figure 10 FinFET leakage and drive-strength defects
Disadvantages:
Test length is longer than traditional test.
Needs layout extraction and SPICE simulation for library cells
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8. Data/Metrics if available.
Figure 11 DESIGN DATA/RESULTS OF INDUSTRIAL DESIGNS
Figure 12 CELL-AWARE DEFECT SCORING TABLE
Figure 13 Measured PPM reduction 350 nm design
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By SYED MUHEEB ULLA
Figure 14 CAT static defect coverage gain per cell type
Figure 15 CAT delay defect coverage gain per cell type
Figure 16 CAT-only detected defects per cell type
9. Summary
Some defects inside a standard cell might not be detected using common fault models. The cell-aware ATPG
characterization process can create a set of fault models based on the simulated behavior of defects within the cell
layout.
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By SYED MUHEEB ULLA
As a result, a higher-quality pattern set can be produced. Silicon results have already shown significant additional
defect detection beyond standard stuck-at and transition patterns when using cell-aware ATPG.
10. References:
Cell-Aware Test written by Friedrich Hapke, Member, IEEE, Wilfried Redemund, Member, IEEE, Andreas Glowatz, Member, IEEE, Janusz
Rajski, Fellow, IEEE, Michael Reese, Member, IEEE, Marek Hustava, Martin Keim, Member, IEEE, Juergen Schloeffel, Member, IEEE,
and Anja Fast
Cell-Aware Test - Semiconductor Engineering (semiengineering.com)
Why cell-aware testing is important - Tech Design Forum Techniques (techdesignforums.com)
(15) 18 4 Advanced Topics: N-detect, cell-aware tests - YouTube
Understanding Cell-Aware ATPG And User-Defined Fault Models
Feb. 23, 2012
https://www.electronicdesign.com/news/products/article/21794875/understanding-cellaware-atpg-and-userdefined-fault-models
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