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CMOS Inverter Analytical Delay Model Considering All Operating Regions
Conference Paper in Proceedings - IEEE International Symposium on Circuits and Systems · June 2014
DOI: 10.1109/ISCAS.2014.6865419
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CMOS Inverter Analytical Delay Model Considering
All Operating Regions
Felipe S. Marranghello, André I. Reis, Renato P. Ribas
PGMICRO, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil
{fsmarranghello,andreis,rpribas}@inf.ufrgs.br
Abstract — This paper presents an accurate analytical delay
model for CMOS inverter considering both subthreshold and
superthreshold operating regions. Previous related work are
either only valid for a specific operating condition or assume a
step input. Therefore, that is the first approach to consider both
different operating regions and input transition time.
Moreover, the proposed model also considers several second
order effects that influence the CMOS inverter dynamic
behavior. Compared to electrical simulations based on BSIM4
transistor model the proposed delay model presents an average
error of 2.3% and the worst case error of 6.6%.
I.
INTRODUCTION
The design of ultralow-power systems such as sensor
networks, portable devices and biomedical applications has
received great attention. Reduction of the supply voltage value
(Vdd) is a well-known technique to reduce power consumption
and increase energy efficiency. Even though better energy
efficiency is verified when the circuit operates below or near
the transistor threshold voltage, others factors such as timing
performance and robustness to process and environmental
variations are also major concerns when defining the operating
Vdd. In this context, analytical delay models that are valid over
a wide range of Vdd values are quite useful to overcome the
challenges related to circuit design that explore Vdd scaling.
Several analytical models for fast estimation of CMOS
gates delay have been proposed to perform analysis and
optimization of circuits [1]-[12]. The main goal of these
models is to explore a trade-off between accuracy and runtime
when compared to electrical simulations. In this context, the
CMOS inverter gate is of particular interest due to the
importance of I/O drivers and clock networks. The main
challenges in deriving an accurate delay model are related to
the complex behavior of MOS transistors and existent nonidealities.
Most proposed analytical delay models focus on the
inverter operating in superthreshold region, and neglect the
subthreshold current [1]-[5]. These models present accurate
results for sufficiently high Vdd values, but they lose accuracy
as Vdd is reduced. In a similar manner, models proposed for
near and sub threshold regions are only valid for sufficiently
small values of Vdd [6]-[9].
Since the best operating region for the circuit is a parameter
to be determined, it is desirable to have a delay model valid
over a wide range of Vdd values. One possibility is to combine
models for specific operating regions. However, this approach
can suffer from discontinuities and incoherencies at the
978-1-4799-3432-4/14/$31.00 ©2014 IEEE
transition among different models. These discontinuities and
incoherencies arise from different assumptions and
approximations used by different models. Thus, a single model
considering all operating regions represents a significant
improvement. Existing approaches that consider both
subthreshold and superthreshold regions are limited to step
input transitions [10][11].
This work proposes a novel delay model for CMOS
inverter valid for both subthreshold and superthreshold
operating regions considering the influence of input transition
time. Unlike previous works focusing only on superhtreshold
operation, the model proposed herein considers the
subthreshold current even for superthreshold operation.
Consequently, the proposed model does not lose accuracy as
Vdd is reduced, and the same approach used to model an
inverter operating in superthreshold is applied to subthreshold
operation. Hence, a continuous model with respect both to Vdd
and to input transition times is obtained. Finally, the proposed
model also considers channel length modulation, drain induced
barrier lowering (DIBL), velocity saturation and I/O coupling
capacitances.
II.
PROPOSED DELAY MODEL
The CMOS inverter gate delay can be defined as follows:
Td  Tout50  Tin / 2
(1)
where Tout50 and Tin are the time instants when the output
voltage (Vout) and the input voltage (Vin) attain Vdd/2,
respectively. Hereafter, the case for a rising input is considered,
while the analysis for falling input is symmetrical.
In this work, three different conditions of input signal slope
are taken into account for Tin: (1) fast input when Tin<Tout50;
(2) slow input when Tvthn<Tout50<Tin, being Tvthn the time
instant when Vin reaches the NMOS transistor threshold
voltage; and (3) very slow input when Tvthn>Tout50.
The superthreshold drain-to-source current (Ids) of
MOSFET is calculated based on the α-power transistor model
[1], and the subthreshold current is modeled as presented in
[12]. As result, Ids is given by:
 I 0.We( VgsVth ) / n.Ut ( 1  e Vds / Ut )
Vgs  Vth


Ids   Klin.W ( Vgs  Vth ) / 2 Vds  Isub
Vgs  Vth & Vds  Vdsat

Ksat.W ( Vgs  Vth ) ( 1   .Vds )  Isub Vgs  Vth &Vds  Vdsat


(2a)
(2b)
(2c)
where W is the effective transistor width, Klin and Ksat are
technology parameters. Vdsat, Vds, Vgs, Vth and Ut are
saturation, drain-to-source, gate-to-source, transistor threshold
and thermal voltages, respectively. I0 is a characteristic current,
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λ represents the channel length modulation parameter, n is the
subthreshold slope, and α is the velocity saturation index.
Hereafter, indexes n and p are used to refer to NMOS and
PMOS parameters, respectively. Isub is added to the α-power
transistor model to ensure that the estimated current behavior is
continuous with respect to Vgs between the subthreshold and
superthreshold regions. Isub is given by:
(3)
Isub  I 0.W (1  e Vds /Ut )
In order to include DIBL effect, Vth can be expressed as:
Vth  Vth0   .Vds
(4)
Where Vth0 is the threshold voltage when no bias is applied
and η is the coefficient to model the DIBL effect. The proposed
model uses a charge based approach, in which the main
principle is that the charge to be removed from the output node
equals the charge drained by the NMOS transistor. Both the
output charge and the NMOS drained charge can be written as
the sum of several components:
Qload  Qcm  Qsc  Qsubrise  Qsubhigh  Qstrrise  Qstrhigh
(5)
where Qsubrise and Qsubhigh are the charges drained through the
NMOS transistor, operating in the subthreshold region, for a
rising input signal and when the input voltage (Vin) equals Vdd,
respectively. In a similar way, Qstrrise and Qstrhigh are the
charges drained by the NMOS transistor for Vthn<Vin<Vdd
and when Vin=Vdd, respectively. Qload represents the charge
due to capacitances connected to the output node, Qcm is the
extra charge due to I/O coupling capacitance, and Qsc is an
equivalent charge that models the short circuit current (ISC)
influence.
The proposed inverter delay model calculates each
component individually, and then solves (6) to find Tout50 for
possible situations. Before presenting the calculation of the
charge components, some parameters are initially defined in
the following sections.
A. Inverter threshold voltage
As Tin increases, the transient behavior of inverter tends to
its DC behavior. In the DC transfer curve, there is a Vin value
such that Vout=Vdd/2. This Vin value is defined as the inverter
threshold voltage (Vtinv). Hence, to calculate Vtinv, Vout is set to
Vdd/2 and Ids currents of NMOS and PMOS transistors are
equated. Different cases are considered to calculate Vtinv:
(1) NMOS and PMOS operate in superthreshold region;
(2) NMOS operates in subthreshold region, and PMOS
operates in superthreshold region;
(3) PMOS operates in subthreshold region, and NMOS
operates in superthreshold region; and
(4) NMOS and PMOS operate in subthreshold region.
If the inverter operates in subthreshold region, then Vtinv is
determined by the fourth case. Otherwise, Vtinv is determined by
one of the other cases, depending on the Vdd value.
To determine which case must be taken into account to
calculate Vtinv, two PN ratios (PNref1 and PNref2) for CMOS
inverter are adopted as boundary values. If the PN ratio of the
evaluated inverter is smaller than PNref1, then Vtinv is determined
by case (2). If such inverter presents PN ratio between PNref1
and PNref2, then Vtinv lies either on case (1) or case (4),
depending on Vdd. Finally, case (3) determines Vtinv for inverter
gate with PN ratio higher than PNref2. Defining Vthp0p5 and
Vthn0p5 as the PMOS and NMOS threshold voltages for
|Vds|=Vdd/2, respectively, and Vov as Vdd-|Vthp0p5|- Vthn0p5,
PNref1 and PNref2 are given by:
I 0 n .eVov /( nn .Ut ) / I 0 p

PN ref 1  

I 0 n /( Ksat p .Vov p ( 1  0.5 p .Vdd ))
Vov<0
Vov>0
Ksat .Vov  n ( 1  0.5 .Vdd ) / I 0
n
n
p

PN ref 2  
Vov /( nnp .Ut )
I 0 n / I 0 p .e
Vov<0
Vov>0
(6a)
(6b)
(7a)
(7b)
The solution for case (4) is directly obtained from the
subthreshold current of both transistors. The remaining three
cases are solved using a first-order Taylor expansion around
Vin=V0 for both NMOS and PMOS currents. To ensure that
the proposed delay model is continuous with respect to PN
ratio, V0 is written as a function of PN ratio (PN), as follows:
Case (1):
V 0  Vthn0 p5  Vov
Case (2):
Case (3):
PN  PN ref 1
any Vov
(8a)
( Vdd  | Vth p 0 p5 |) PN / PN ref 1

V0  
Vthn0 p5 PN / PN ref 1

Vov<0
Vov>0
(8b)
(8c)
Vdd  ( Vdd  Vthn0 p5 ) PN ref 2 / PN

V0  
Vdd  ( Vdd  | Vth p 0 p5 |) PN ref 2 / PN


Vov<0
Vov>0
(8d)
(8e)
PN ref 2  PN ref 1
Defining Ip and In as the PMOS and NMOS currents,
respectively, for Vout=Vdd/2 and Vin=V0, and Ip’ and In’ as
the PMOS and NMOS current derivatives, respectively, when
Vout=Vdd/2 and Vin=V0, Vtinv can be written as:
Vtinv  V 0  ( Ip  In ) /( In'  Ip' )
(9)
B. Modeling DIBL and channel length modulation
One of the main challenges on developing an accurate
analytical gate delay model is to consider appropriately the
influence of Vds on the discharge current. If such influence is
explicitly considered, the differential equations become
difficult to be solved. Since the NMOS transistor is expected to
operate in saturation during the output transition to Vdd/2,
several works assume that the discharge current is constant in
respect to Vds, and the discharge current is calculated with
Vds=Vdd [2][4]. However, the influence of Vds on the
saturation current is verified through both channel length
modulation and DIBL, gaining importance in advanced CMOS
technology nodes. A simple way to consider the Vds impact on
the saturation current is to use an effective value (Vdseff), which
is defined by:
Vds eff  Vdd ( 1.5  Cme ff /( Cload  Cme ff )) / 2
(10)
where Cload is the lumped capacitance at the output node.
Cmeff is an effective I/O coupling capacitance value. Cmeff is the
sum of a PMOS component (Cgdp) and a NMOS component
(Cdgn). Cmp is given by:
 Cmlin p ( Vdd  | Vth p min |) | Vth p min | ( Cmlin p  Cmoff p )

Cgd p  
Vdd
Cmoff
p

|Vthpmin|<Vdd
(11a)
|Vthpmin|>Vdd
(11b)
where Vthpmin is the threshold voltage with |Vds|=Vdd. Cmoffp,
and Cmlinp are, respectively, coupling capacitances when the
transistor is turned-off and in linear region [14]. Cdgn is
calculated in the same manner replacing PMOS by NMOS
parameters. The effective values are used because both the
1453
input and output signal transitions have great influence on the
value of these capacitances.
C. Charges from output load and coupling capacitances
Qload is obtained from Cload. These capacitances have a
voltage drop of Vdd/2, which leads to:
(12)
Qload  ( Cload  Cmeff ).Vdd / 2
Qcm depends on the input transition time. For fast inputs,
all possible extra charge is transferred through the coupling
capacitance. For slow input, the charge transferred is reduced.
A simple way to consider this dependence is to write Qcm as:
Cmeff .Vdd
Qcm  
Cmeff .Vdd (Tinref / Tin)
Tin<Tinref
Tin>Tinref
(13a)
(13b)
where Tinref is the input transition time that defines the
boundary between fast and slow inputs. Accurate expressions
for Tinref are presented in Section II.F.
D. Short circuit current equivalent charge
Even though the influence of ISC on the CMOS inverter
dynamic behavior can be neglected for fast input transitions,
this component is important for slow inputs. The proposed
model considers the ISC through an equivalent charge Qsc. Qsc
is the product between the time during which ISC flows and an
average ISC value. It is considered that ISC flows during the
whole input transition except for the overshoot time (Tov).
Firstly, equating the Vout derivatives due to I/O coupling
capacitance and due to the NMOS current, the time instant
when the overshoot voltage reaches the maximum value
(Tmax) is estimated as:

Icm  Isubn
 Vthneff )
 Tin.(Vdd  Vthneff )(  n
I high  Isubn

Tmax  
Vdd

 Tin.( nn .Ut .ln( Icm / Isubn )  Vthneff )

Vdd
Icm>Isubn (14a)
Icm<Isubn (14b)
by:
(15)
Qsubhigh  I 0 n.Wn e
The average short circuit current corresponds to a
percentage of the DC current when Vin=Vtinv. This current is
referred as Ivtinv. This assumption is justified because the DC
behavior represents the worst case scenario when increasing
the input signal transition. As a result, Qsc can be expressed as:
Qsc  0.25Ivtinv (Tin  Tov)(1  Tinref / Tin)
(17)
E. NMOS drained charge
If Vin is smaller than Vthneff, from the starting of the input
transition until an arbitrary time t1, then Qsubrise can be
expressed as:
Vdd.t1/(Tin.nn .Ut )
Qsubrise  Tin.Ksubn .(e
 1)
)n n .Ut.e
Vdd
Vthneff /( nn .Ut )
(19)
(Vdd Vthneff ) /( nn .Ut )
(1  e
Vdseff / Ut
)(t1  Tin)
(20)
If Tvthn defines the time instant when Vin=Vthneff, then
Qstrrise from Tvthn to t1 is given by:
Qstrrise 
I high.Tin.(t1.Vdd / Tin  Vth neff ) 1
Vdd .(Vdd  Vth neff ) (  1)
(21)
 Qsub
where
(22)
Qsub  Isubn .( t1  Tvthn )
In order to guarantee that the proposed delay model is
continuous with respect to Tin, Qstrrise is calculated for both
α=1(Qstrrise1) and α=2 (Qstrrise2), and an average value is
considered, as follows:
Qstrrise  Qstrrise1( 2   n )  Qstrrise2 (  n  1 )
(23)
If Vdd>Vthneff, then the charge drained by NMOS transistor
from Tin until t1 is given by:
Qstrhigh  I high .( t1  Tin )
(24)
F. Output discharge for fast input transition
An input is considered fast when Tin<Tout50. If
Vdd>Vthneff, then Qsubhigh is null, whereas Qsubrise, Qstrrise and
Qstrhigh are calculated with t1=Tvthn, t1=Tin and t1=Tout50,
respectively. If Vdd<Vthneff, then both Qstrrise and Qstrhigh are
null, whereas Qsubhigh and Qsubrise are calculated with t1=Tin
and t1=Tout50, respectively. As result, Tout50 can be
calculated as follows:
Qcm  Qout  Qsubrise  Qstrrise
I high
(25)
The boundary between fast and slow inputs (Tinref) for
superthreshold and subthreshold operating conditions are given
by:
Tinref
(16)
In (16), if Tmax>Tin¸ then Tin is used instead of Tmax. A
first order Taylor expansion around t0=(Cmeff.Vdd/Isubn) is
used to calculate Tov when Isubn>Icm. This expansion is
required to calculate Tinrefslow, defined in Section II.G.
Vdseff / Ut
If Vdd<Vthneff and Vin=Vdd, Qsubhigh from Tin to t1 is given
Then, Tov is estimated as follows:
Tov  Tmax( 1  Vdd ( Cl  Cmeff ) /( I high.Tinref ))
I 0 n .Wn (1  e
Tout50  Tin 
where Vthneff is the NMOS transistor threshold voltage when
Vds=Vdseff, Ihigh is the NMOS current for Vgs=Vdd and
Vds=Vdseff and Icm is the current through the coupling
capacitance:
Icm  Cmeff .Vdd / Tin
Ksubn 
Vdd (   1 )( Qout  Qcm )

 ( I ( Vdd  Vth
neff )  Isubn ( Vdd  Vthneff  k1 ))
 high

Vdd ( Qout  Qcm )

 Isub ( eVdd /( nn .Ut )  1 )n Ut ( e Vthneff /( nn .Ut ) )
n
n

Vdd>Vthneff
(26a)
Vdd<Vthneff
(26b)
where
k1  nn .Ut(1  e
Vthneff /( nn .Ut )
)
(27)
G. Output discharge for slow and very slow input transitions
When the input is slow or very slow, the input voltage is
still rising at Tout50. Therefore, both Qsubhigh and Qstrhigh are
null. If Vdd>Vthneff, then Qsubrise, and Qstrrise are calculated
with t1=Tvthn and t1=Tout50, respectively. If Vdd>Vthneff, then
Qstrhighis null and Qsubrise is calculated with t1=Tout50. In the
superthreshold region, defining Tvthneff as the instant when
Vin=Vthneff and Δt=(Tout50-Tvthneff), Tout50 satisfies the
following expression:
(18)
where
1454
I high .Vdd  n ( t ) n 1
n
Tin ( Vdd  Vthneff ) n (  n  1 )
 Isubn .t  Qout  Qcm  Qsc  Qsubrise
(28)
TABLE I.
Equation (30) cannot be solved analytically unless αn=1 or
αn=2. Similar strategy used in (23) and (25) is applied to
determine Δt. For the subthreshold domain, Tout50 is given by:
Tout50 
nn .Ut.Tin Qout  Qcm  Qsc
ln(
 1)
Vdd
k.Tin
Power supply
(Vdd)
1.0 V
0.8 V
0.6 V
0.4 V
0.2 V
(29)
where
k
nn .Ut
Vth
Isubn .e neff
Vdd
/( nn .Ut )
(30)
In superthreshold domain, the input can also be classified as
very slow. In this case, Vout reaches Vdd/2 while the NMOS
transistor is in subthreshold. For this, it is required Vtinv <Vthneff
and Tout50 is similar to a slow input in subthreshold. The
boundary between slow and very slow inputs (Tinrefslow) is
found
considering
Qsubrise=Qout+Qcm+Qsc,
and
Tin=t1=Tinrefslow. Qsubhigh, Qstrrise and Qstrhigh are all zero.
Tinrefslow satisfies the quadratic equation:
2
a.Tinrefslow  b.Tinrefslow  c  0
(31)
where coefficients a, b and c are given by:
Vthneff /( nn .Ut )
)
(32)
b  0.25Ivt inv( Tinref ( 1  Tov' )  Tov0  Tov' t 0 )  Qout  Qcm
(33)
c  0.25Ivtinv .Tinref (Tov0  Tov'.t 0)
(34)
a  0.25Ivt inv ( 1  Tov' )  I 0.n.Wn.Ut .(1  e
being Tov0 and Tov’, respectively, the overshoot time and the
first-order derivative for Tin=t0, as described in Section II.D.
III.
MODEL VALIDATION
The proposed model has been validated using a 32 nm bulk
CMOS predictive technology model [13]. The supply voltage
values considered were 1 V, 0.8 V, 0.6 V, 0.4 V and 0.2 V, and
the operating temperatures considered were 25ºC and 125ºC.
For each pair of Vdd and temperature, 13200 different
configurations were evaluated. Each configuration is defined
by the transistor channel widths, output load and input
transition time. PN ratio was varied from 0.25 to 8. The fanout
applied lies in the interval from 0.25 to 256, and the input
transition time was changed from 5 ps to 1 ns with a 5 ps step.
Fig. 1 presents the dispersion of the relative error
considering all simulations performed. Half the cases are in the
interval [-2%,2%], 85% in [-4%,4%], and 97% in [-5%, 5%].
CONCLUSIONS
ACKNOWLEDGEMENTS
Research partially supported by Brazilian funding agencies
CAPES, CNPq and FAPERGS, under grant 11/2053-9
(Pronem).
REFERENCES
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[2]
[3]
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[6]
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[12]
[13]
[14]
1455
View publication stats
125ºC
AVG (%)
WC (%)
1.95
5.00
2.65
6.50
2.40
4.55
2.20
6.40
3.50
6.60
This work proposed an accurate analytical delay model that
is valid for all possible operating conditions, including different
effects that are important in the CMOS inverter transient
behavior. The proposed model is continuous and coherent for
different inverter characteristics and conditions, like PN ratio,
input transition time, output load and supply voltage values. A
second important contribution is the possibility to consider the
subthreshold current for inverter operating in superthreshold
region. Previous works focusing on superthreshold operation
lose accuracy as Vdd is reduced. Even though not discussed
herein, the model can be applied to variability analysis as
discussed in [2] and in [10].
[9]
Table I summarizes the relative average error (AVG) and
the absolute relative worst case error (WC) for different supply
voltages and temperatures. The overall average error is circa
2.3% and the worst case error is approximately 6.6%.
25ºC
AVG (%)
WC (%)
1.50
4.15
2.00
5.40
1.40
3.50
1.85
6.15
3.30
6.10
IV.
[8]
Fig. 1. Dispersion of relative error for the proposed inverter delay model.
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