Materials Science in Semiconductor Processing 84 (2018) 107–114 Contents lists available at ScienceDirect Materials Science in Semiconductor Processing journal homepage: www.elsevier.com/locate/mssp Optimization of nanometer bulk junctionless Trigate FET using gate and isolation dielectric engineering T ⁎ S. Priscilla Scarlet , R. Srinivasan Department of IT, SSN College of Engineering, Kalavakkam, India A R T I C LE I N FO A B S T R A C T Keywords: Bulk Junctionless Inversion Isolation Dielectric Trigate FET In this paper, the performance of bulk junctionless trigate FET is enhanced by optimizing the (WFISO) GateISO work function (GateISO is the portion of the gate above isolation dielectric), isolation dielectric permittivity (KISO), and GateFIN dielectric (GateFIN is the portion of the gate covering the fin) permittivity(KFIN). SiO2, Si3N4 and HfO2 dielectrics with gate work functions in the range of 4–5.6 eV are used in this study. The performance is enhanced in terms of ION, IOFF, is preferred for better ION, IOFF improve ION IOFF T ION IOFF FIN ISO ISO T ISO ( ) ratio. ION IOFF 1. Introduction Halo doping, Super steep retrograde channel doping, shallow source-drain extensions, high-K dielectric replacing the gate oxide, and metal gates instead of poly gates are some of the techniques to mitigate the short channel effects (SCE) faced by the conventional planar single gate MOSFET [1–6]. Building devices on Silicon on Insulator (SOI) substrate instead of bulk Silicon substrate, and mechanically stressed substrates are also some of the solutions [7,8]. Multigate structures like double gate FinFET, triple gate, quadruple gate, nanowires and nanotubes are some alternate advanced solutions to overcome the SCE [9]. Among these structures, FinFET is a potential alternative to the conventional planar structure [10–12]. From the fabrication point of view, junctionless structures have more scope at lower dimensions. Junctionless concept was introduced as trigate structure by Collinge et al., and had the source, channel and drain of the same doping species [13]. This solves the need of high doping concentration gradient in the junctions and thereby the annealing cost. Also the junctionless devices are not plagued by the surface scattering issue which is rampant in the junction based devices owing to the bulk mode of transport in junctionless devices. Similar to CMOS devices, the multi gate structures may be fabricated either on SOI or on bulk substrate [14,15]. While bulk CMOS devices use field oxide in the fabrication the bulk FinFET/trigate devices use field and isolation oxides [16,17]. While field oxide is sitting between two different devices the isolation oxide is ⁎ ( ) ratio, and f . High K brings up all the above parameters. While high K , and ( ) performance, low K is improves f . Moderate WF is suggested to Corresponding author. E-mail address: lillypushpam5@gmail.com (S.P. Scarlet). https://doi.org/10.1016/j.mssp.2018.05.009 Received 24 March 2018; Received in revised form 20 April 2018; Accepted 9 May 2018 1369-8001/ © 2018 Elsevier Ltd. All rights reserved. sitting within the same device. Fig. 1(a) shows (i) GateFIN, the portion of the gate running over the fin, and (ii) GateISO, the portion of the gate running over the isolation dielectric. The dielectrics sitting below GateFIN and GateISO have permittivity of KFIN and KISO, respectively. Similarly the gate electrode work functions associated with the GateFIN and GateISO are WFFIN and WFISO, respectively. We can improve the leakage current (IOFF), on current (ION) and ( ) ratio performance of the FinFET/trigate structure through opION IOFF timal selection of KFIN, KISO, and WFISO. Since the junctionless devices are claimed to have smaller ON currents compared to its junction-based counterpart [9] the above study would be more relevant for the junctionless devices. The usage of high K dielectrics is investigated in the literature for MOSFETs, FinFETs and junctionless transistors [18–21]. The same holds good for the work function engineering i.e. using metals for gates [22,23]. But, the usage of high K dielectric in the isolation dielectric region of bulk trigates/FinFETs is yet to be explored. Similarly dual metal gate work function technique is reported to improve the performance of the conventional planar FET devices [24]. But, this technique is not investigated in the isolation region of the bulk trigate/FinFET structures. In essence, the isolation region of the bulk trigate/FinFET structure is yet to be analyzed for performance enhancement. In this work, we have enhanced the performance of the bulk junctionless trigate device using the above technique, and the same has Materials Science in Semiconductor Processing 84 (2018) 107–114 S.P. Scarlet, R. Srinivasan So we hypothesize that the IOFF2 can be reduced without sacrificing ION ( ) ratio can be achieved through optimizaION IOFF significantly i.e. better tion of KISO and WFISO. 3. Methodology, device structure and ID-VG calibration Sentaurus TCAD simulator from Synopsys is used to perform the simulations. Sentaurus structure editor is used to create the device structure and to generate mesh for device simulation. Sentaurus device simulator is used to perform the DC and AC device simulations. Physics section includes appropriate models for doping dependency on mobility, effect of high and normal electric fields on mobility and velocity saturation. The physics models used in the device simulation are Shockley–Read–Hall (SRH) recombination model, extended Canali model and Lombardi model [13]. The drift diffusion mechanism based simulations have been carried out. The fitting parameters for the models used is given as below: SRH recombination model: (τmax − τdop (NA,0 + ND,0) = τmin + ( 1+ τmin ) NA,0 + ND,0 Nref ) γ , where τmin = 0 s, τmax = 1 × 10−5 s for electron and τmin = 0 s, τmax = 3 × 10−6 s for hole, γ = 1, Nref = 1 × 1016 cm−3. Extended Canali model: μ (F ) = ⎡1+ ⎣ ( μlow 1/ β μlow Fhfs β vsat ) , ⎤ ⎦ where Fig. 1. (a). Schematic of Bulk junctionless Trigate FET with the N-Type doped fin.(b). Schematic of Bulk junctionless Trigate FET with cut taken at centre of the fin. µlow is the low field mobility, β is the temperature dependant parameter, νsat is the saturation velocity, Fhfs is the driving field. been applied on the junction-based counterpart at the end of the study. This paper is organized into nine sections. Section 1 is the introduction and Section 2 deals with the proposal to minimize leakage current. Section 3 deals with the methodology, device structure and ID-VG calibration. Section 4 discusses the effect of WFISO in equilibrium, ON and OFF states. Section 5 deals with the effect of KISO on the currents. Section 6 discusses the effect of KISO, KFIN and WFISO on both DC and AC parameters. Section 7 deals with the analysis of leakage current in bulk junctionless Trigate FET. The effect of KISO, KFIN and WFISO on the DC parameters is studied in case of inversion based Trigate FET in Section 8. Finally the Conclusion section concludes this paper. Enhanced Lombardi model: 1 = μ μac = D + μac D μsr ⎛N + ND,0 + N2 ⎞ B A,0 + C⎜ ⎟ k T F⊥ ⎟ ⎜ F⊥1/3 300K ⎠ ⎝ ( ) and −1 2. Proposal to minimize leakage current (F⊥/ Fref ) A * F3 μsr = ⎜⎛ + ⊥ ⎟⎞ δ η⎠ ⎝ As already stated, the gate in a FinFET/Trigate with multiple fins has two different parts, (i) GateFIN, the portion of the gate covering the fin, and (ii) GateISO, the portion of the gate above isolation dielectric, as shown in Fig. 1(a). While the GateFIN interacts with the N type doped fin, the GateISO interacts with the P type doped substrate. So, this leads to two different leakage paths from drain to source as shown in Fig. 1(a) which can be categorized into, where, B= 3.6 × 107 cm s−1, A= 2.58, C = 1.7 × 104 cm5/3V−2/3 s−1, D = exp− x/lcrit, where x is the distance from the interface and lcrit = 10−6 (cm), η = 1.0e300V2 cm−1 s−1. The dimensions of the bulk junctionless Trigate FET is given in Table 1. It should be noted that there is no differentiation between KFIN and KISO in the calibrated device i.e. both use SiO2. The schematic of bulk junctionless Trigate FET along the GateISO (gate running over the isolation dielectric) and GateFIN (gate enclosing the fin region) is displayed in Fig. 1(a) and the corresponding 2D schematic for the device with the cut taken at centre of fin is displayed in Fig. 1(b). The TCAD (i) Fin region contributing to IOFF1(Refer Fig. 1(b)) (ii) All regions excluding Fin region contribute to IOFF2 (IOFF1 + IOFF2) gives the device's IOFF(Refer Fig. 1(b)) As already stated KFIN strongly controls the fin region whereas KISO and WFISO mostly control the substrate beneath the isolation dielectric. 108 Materials Science in Semiconductor Processing 84 (2018) 107–114 S.P. Scarlet, R. Srinivasan Table 1 Details of the device. Parameters Values Channel Length (nm) Tox (nm) TISO (nm) WFFIN (eV) WFISO (eV) Channel doping (atoms/cm3) Source/Drain doping (atoms/cm3) Substrate doping(atoms/cm3) 15 1 1 4.76 4.76 1.5 × 1019 1.5 × 1019 5 × 1018 Fig. 2. (a) Device Structure of Bulk junctionless Trigate FET(with gate oxide removed for clarity) (b)Various cuts of the device. Fig. 4. (a) Conduction Band Energy along MOS at equilibrium state for various WFISO with KFIN = 3.9 and KISO = 3.9. (b) Distance along MOS across the GateFIN and GateISO cuts. 4. Effect of WFISO In this section, the effect of WFISO on ID-VG characteristics is studied. The conduction band energy profiles at equilibrium state (i.e. VGS = VDS= 0 V) are plotted in Fig. 4(a), for two different WFISO. The profiles are shown at two different places, (i) perpendicular to GateISO -Isolation oxide-p substrate, and (ii) perpendicular to the GateFIN -Gate Oxide-fin/ channel (refer Fig. 4(b)). It can be observed from Fig. 4(a) that in the region below the GateISO, increase in WFISO from 4.76 eV to 5.6 eV changes the downward band bending into an upward band bending in both the regions under GateISO and GateFIN. Since the upward band bending does not favor electron accumulation, it cuts off the leakage path beneath the GateISO i.e. we can expect IOFF2 to go down (IOFF2 is discussed in Section 2). It should be kept in mind that the decrease in IOFF2 does not trade off with ION. The changes in the GateISO properties can also affect the fin/channel region to some extent. This can be studied by analyzing the MOS system present in the GateFIN region. The band profile in the GateFIN region is plotted Fig. 4(a), and we can notice that the increase in WFISO from 4.76 eV to 5.6 eV, shifts the band upwards in the pn junction region (formed by n channel and p substrate) i.e. the changes in the GateISO properties affect the fin/channel region. The profile in Fig. 4(a) suggests IOFF1 to go down but this will trade off with the ION. Fig. 3. ID-VG characteristics of bulk junctionless Trigate FET. simulated structure along with the directions along which the cuts for further analysis of the device performance will be taken are shown in Fig. 2(a) and Fig. 2(b) respectively. The ID-VG characteristic of the device is calibrated against [15] and displayed in Fig. 3. It can be observed from Fig. 3 that bulk junctionless Trigate FET has ION of 4.7 × 10−4 A/µm and IOFF of 1 × 10−9 A/µm. From the ID-VG characteristics, ION, IOFF and DIBL are extracted and similarly from the AC simulations, the fT is extracted. IOFF is the current with zero gate voltage and maximum drain voltage, ION is the current with maximum gate and drain voltage, and fT is the frequency at which Y21/Y11 ratio goes to 1, where Y21 and Y11 are the regular Y parameters. 109 Materials Science in Semiconductor Processing 84 (2018) 107–114 S.P. Scarlet, R. Srinivasan Fig. 5. Conduction Band Energy along MOS in OFF and ON state for various WFISO with KFIN = 3.9 and KISO = 3.9. Fig. 6. ION Vs KISO for various WFISO. Table 2 Normalised currents for various WFISO in junctionless Trigate FET. WFISO (eV) ION 4.76 5.6 488 427 (μA/μm) IOFF 1.5 0.4 (nA/μm) ION IOFF 3.31 × 105 1.14 × 106 The OFF state, and ON state profiles are analyzed next. The OFF state (VGS = 0 V and VDS= 1 V) and ON state (VGS = VDS= 1 V) profiles corresponding to Fig. 4(a) are plotted in Fig. 5. The band diagrams in Fig. 5 suggest the IOFF to go down, with increase in WFISO, because the bands under both the regions under GateISO and GateFIN, go up with increase in WFISO in the regions under GateISO (implying IOFF2 decrease) and under GateMAIN (implying IOFF1 decrease). Similarly the GateFIN ON state profiles depicted in Fig. 5, for WFISO = 4.76 eV, and WFISO to 5.6 eV, suggest that the ION might go down but not significantly i.e. ( ) I better I ON ratio is achieved (refer Table 2) conforming the hypothesis OFF given in Section 2. The reason for IOFF reduction is nothing but the threshold voltage reduction with increase in WFISO. When the WFISO increases from 4.76 eV to 5.6 eV, the threshold voltage under the GateISO increases from 2.86 V to 3.7 V which is calculated from the formula VTH = Fig. 7. IOFF Vs KISO for various WFISO. − QD +2ΦF + VFB CI GateFIN (ii) going through GateISO. During ON state the increase in KISO from 3.9 to 25 increases the average electron mobility along the channel from 67.8 cm2/(Vs) to 90.2 cm2/(Vs) thereby increasing ION. where, QD is the charge per unit area in the depletion region, CI is the MOS capacitance, ΦF is the fermi potential and VFB is the flatband voltage. Thus the result obtained in this section confirms the proposed idea of Section 2. With respect to ( ) ratio, at lower WF ION IOFF ISO, the performance degrades at higher KISO, as depicted in Fig. 8. But at higher WFISO (5.6 eV), as KISO increases, ION and IOFF decrease whereas 5. Effect of KISO ( ) performance improves, as can be seen from Figs. 6–8. At ION IOFF higher WFISO, as the KISO increases the barrier between source and channel increases in the regions under GateFIN and under GateISO as observed from Fig. 10 (The profiles along the channel for higher WFISO case are shown in Fig. 10), and this trend is opposite to the lower WFISO case. Since the source-channel barrier increases in the regions under GateFIN (implying IOFF1 decrease) and under GateISO (implying IOFF2 decrease), at high KISO one can expect the IOFF to go down at high KISO. During ON state the increase in KFIN from 3.9 to 25 decreases the average electron mobility along the channel from 45.4 cm2/(Vs) to 42.7 cm2/(Vs) thereby decreasing ION. With respect to IOFF, at lower In this section, the impact of isolation dielectric permittivity (KISO) is studied, for various GateISO work function (WFISO). Figs. 6 and 7 show ION Vs KISO and IOFF Vs KISO, for various WFISO respectively. It can be observed that, at lower WFISO (4 eV), as KISO increases, both ION and IOFF increase. We can understand this by studying the band profile along the channel (Fig. 2b). At lower WFISO as the KISO decreases, the barrier between source and channel increases under GateFIN and GateISO (implying both IOFF1 & IOFF2 decrease) as observed from Fig. 9 thereby decreasing IOFF. Two profiles are shown in Fig. 9, (i) going through 110 Materials Science in Semiconductor Processing 84 (2018) 107–114 S.P. Scarlet, R. Srinivasan Fig. 10. Conduction band energy along the channel for WFISO = 5.6 eV during OFF state. Fig. 8. ION/IOFF Vs KISO for various WFISO. Fig. 11. IOFF Vs KISO and KFIN for various WFISO. and Table 3 that both IOFF and ION improve with increase in KFIN. Fig. 12 provides the OFF state band profile detail, along the channel for two different KFIN values. We can see from the OFF state band diagram (refer Fig. 12) for WFISO = 5.6 eV and KISO = 3.9, that the source-channel barrier increases with KFIN in the GateFIN (implying IOFF1 decrease) and the GateISO regions (implying IOFF2 decrease) which will decrease the IOFF. The corresponding average mobility value in the channel increases from 57.5 cm2/(Vs) for KFIN = 3.9–74.9 cm2/(Vs) for KFIN = 25 thereby in- Fig. 9. Conduction Band Energy along the channel for WFISO = 4 eV during OFF state. WFISO lower KISO is preferable and at higher WFISO higher KISO is preferable. On the contrary, for ION the conclusion is opposite to that of IOFF. We have a third interesting case which uses WFISO as 4.76 eV which is in between 4 eV (lower WFISO) and 5.6 eV (higher WFISO). For this case, as KISO increases, both ION and IOFF performance improves i.e. ION increases and IOFF decreases slightly. This is favorable for the device performance which enhances the creases the ION. Hence the ( ) ratio increases with K ION IOFF FIN. More data mining can be done from Table 3 which tabulates ION, ( ) ratio also. All these results can ION IOFF IOFF, be observed from Figs. 6–8, for the WFISO = 4.76 eV. ( ), DIBL, f , g ION IOFF T m and CGG, for various WFISO, KISO, KFIN values. Totally there are 27 different combinations are studied and are tabulated in Table 3. Based on the above simulations a set of optimized 6. Effect of KFIN, KISO, and WFISO devices with respect to IOFF, ION and ( ) ratio have been proposed ION IOFF and these are bold faced in the Table 3. The following summary is extracted from the optimized set of devices, In order to further enhance the device performance in addtition to KISO and WFISO, a third parameter namely GateFIN dielectric permittivity (KFIN) is considered in this section. Fig. 11 shows the variation of IOFF as a function of KISO and KFIN, for various WFISO, and Table 3 enlists the corresponding IOFF and ION values. It can be observed from Fig. 11 • High K • High K 111 ISO ISO + High KFIN + High WFISO leads to minimum IOFF + High KFIN + Low WFISO leads to maximum ION Materials Science in Semiconductor Processing 84 (2018) 107–114 S.P. Scarlet, R. Srinivasan Table 3 DC AND AC parameters of Trigate junctionless FET. S.No. KFIN KISO WFISO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 3.9 3.9 3.9 7.5 7.5 7.5 25 25 25 3.9 3.9 3.9 7.5 7.5 7.5 25 25 25 3.9 3.9 3.9 7.5 7.5 7.5 25 25 25 3.9 7.5 25 3.9 7.5 25 3.9 7.5 25 3.9 7.5 25 3.9 7.5 25 3.9 7.5 25 3.9 7.5 25 3.9 7.5 25 3.9 7.5 25 4 4 4 4 4 4 4 4 4 4.76 4.76 4.76 4.76 4.76 4.76 4.76 4.76 4.76 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 5.6 (eV) ION (μA/μm) 549 592 706 560 599 709 577 611 716 488 504 560 502 517 569 525 537 585 427 415 395 445 433 411 472 460 437 IOFF (pA/μm) 7869.8 2.27 × 104 2.93 × 105 313.6 749 1.31 × 104 31.9 32.3 345.3 1472.1 1302.2 1096.3 97 84.7 71.9 29.7 21.6 12.3 374.7 175.6 60.1 53.8 36.7 20.7 29.7 23.1 15.8 ( ) fT (GHz) gm (μA/V) CGG (aF) 6.98 × 104 2.61 × 104 2.41 × 103 1.79 × 106 8.00 × 105 5.41 × 104 1.81 × 107 1.89 × 107 2.07 × 106 3.31 × 105 3.87 × 105 5.11 × 105 5.18 × 106 6.10 × 106 7.92 × 106 1.77 × 107 2.48 × 107 4.74 × 107 1.14 × 106 2.36 × 106 6.57 × 106 8.26 × 106 1.18 × 107 1.99 × 107 1.59 × 107 1.99 × 107 2.77 × 107 427 384 257 450 402 270 452 416 288 400 373 320 424 398 346 431 411 366 356 308 234 382 338 264 392 355 287 33.72 34.79 36.23 42.41 43.23 43.02 53.92 54.31 54.4 31.15 31.89 34.37 38.64 39.32 41.95 49.45 49.83 52.13 28.17 27.71 26.42 34.56 33.71 32.14 44.38 43.02 40.64 7.22 14.42 22.78 10.09 11.31 18.32 11.02 12.12 19.56 9.36 10.65 15.23 10.07 11.32 14.65 10.96 12.15 15.32 9.68 11.72 14.93 10.37 12.83 16.03 11.22 12.26 17.96 ION IOFF Optimum fT Optimum ION Optimum ION/IOFF Optimum IOFF better DC performance but on the other hand high KISO increases the parasitic capacitance resulting in fT reduction. 7. Analysis of the leakage current In this section, the effect of WFISO on IOFF is analyzed. As stated previously, we have two IOFF components known as IOFF1 and IOFF2. The electron current density across the device cross section is shown in Figs. 13 and 14, for two different WFISO (4 eV and 5.6 eV) with KISO = 25 and KFIN = 25. These figures are obtained by taking a cut at the centre of the channel. The current flow in these figures are perpendicular to the page. IOFF1is achieved by integrating the current density over the cross section of the fin, and IOFF2 is calculated by integrating the current density over the entire device excluding the fin as shown in Figs. 13 and 14. Fig. 12. Conduction band energy along the channel for WFISO = 5.6 eV and KISO = 3.9 during OFF state. • High K ratio • Low K ISO ISO + High KFIN + Moderate WFISO leads to maximum ( ) ION IOFF + High KFIN + Low WFISO leads to maximum fT The inferences from the above summary are, • High K • High K • Low K FIN ISO ISO improves both DC and AC performance is needed to improve the DC performance is preferable for AC performance Since high KFIN improves transconductance (gm) as depicted in Table 3, both DC and AC characteristics are enhanced. On one hand, the high KISO eliminates the leakage path (with high WFISO) resulting in Fig. 13. Electron current density across the device cross section for WFISO = 4 eV, KISO = 25 and KFIN =25 during OFF state. 112 Materials Science in Semiconductor Processing 84 (2018) 107–114 S.P. Scarlet, R. Srinivasan Table 6 IOFF1 and IOFF2 for various WFISO WITH KISO = 25 and KFIN = 25 in inversion mode Trigate FET. WFISO (eV) IOFF1(A) IOFF2(A) 4 5.6 2 × 10−9 2.78 × 10−10 2.9 × 10−10 1.54 × 10–19 8. Effect of WFISO, KFIN and KISO in inversion mode Trigate FET The technique discussed in the above sections holds true for the junction-based devices/the inversion mode Trigate FET. For this we took the device details from ref [25] which has a channel length of 20 nm and a gate workfunction of 4.37 eV and the corresponding currents of the calibrated device are given in Table 5. All the studies tabulated in Table 3 are repeated on this device, and the set of optimized devices with respect to ION, IOFF, and IOFF2(A) 3.35 × 10–12 1.57 × 10–19 9. Conclusion Table 4 IOFF1 and IOFF2 for various WFISO with KISO = 25 and KFIN = 25 in junctionless Trigate Fet. IOFF1(A) –12 4 5.6 6.95 × 10 1.89 × 10–14 ION IOFF junctionless device holds good in junction-based devices too. Similar to IOFF1 and IOFF2 calculation, in Section 7 the analysis was repeated for inversion mode trigate FET. Table 6 shows the computed IOFF1 and IOFF2 values for two different WFISO. It can be observed from Table 6 that increase in WFISO reduces IOFF1 from 2 × 10−9 A to 2.78 × 10−10 A. On the other hand the corresponding IOFF2 is brought down to 1.54 × 10–19 A from 2.9 × 10−10 A. In other words at WFISO= 4 eV, IOFF1 contributes 87.3% and IOFF2 contributes 12.7% to the net leakage. But at WFISO= 5.6 eV, IOFF1 contribution is 99.99% with IOFF2 contribution being insignificant. Fig. 14. Electron current density across the device cross section for WFISO = 5.6 eV, KISO = 25 and KFIN = 25 during OFF state. WFISO (eV) ( ) ratio are given in Table 5. The inferences given for the The gate in the bulk FinFET/Trigate structure has been seen as, (i) GateFIN, the portion of the gate covering the fin, and (ii) GateISO, the portion of the gate above isolation dielectric. This view is exploited to improve the device performance. This is done by manipulating the GateISO work function (WFISO), isolation dielectric permittivity (KISO), and GateFIN dielectric permittivity (KFIN). The device was optimized separately for ION, IOFF, ( ) ratio, and f . Both DC and AC perforION IOFF T mance demand high KFIN. High WFISO and high KISO improves IOFF performance but the AC performance demands low WFISO and low KISO. Moderate WFISO along with high KISO give maximum Table 5 DC parameters of trigate inversion FET. References KFIN KISO WFISO (eV) ION (mA/ μm) IOFF (nA/ μm) ION/IOFF 3.9 3.9 4.37 0.81 18.6 4.34 × 104 25 25 25 5.6 4 5.6 3.26 3.79 3.26 5.31 41.84 5.31 ION IOFF techniques followed have been applied to junction-based Trigate FET and proved to be useful. Fig. 15. IOFF1 and IOFF2 distribution for KISO = 25 and KFIN = 25. 25 25 25 ( ) ratio. The 5 6.1 × 10 9.1 × 104 6.1 × 105 [1] C.F. Codella, S. Ogura, "Halo doping effects in submicron DI-LDD device design," in: Proceedings of the 1985 International Electron Devices Meeting, Washington, DC, USA, 1985, pp. 230–233. [2] I. De and C. M. Osburn, “Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices,” vol. 46, no. 8, pp. 1711–1717, 1999. [3] M. Bohr, “High-k + metal gate transistor breakthrough on 45 nm microprocessors risk factors,” pp. 1–30, 2007. [4] G. Baum, H. Beneking, Drift velocity saturation in MOS transistors, IEEE Trans. Electron Devices 17 (6) (1970) 481–482. [5] M.J. Deen, Z.X. Yan, ‘DIBL in Short-Channel NMOS Devices’, IEEE Trans. Electron Devices 39 (4) (1992) 908–915. [6] M.J. Deen Z.X. Yan “DIBL in Short-Channel DIBL Short.-Channel NMOS Devices 39 4 1992. [7] Surya Veeraraghavan and Jerry G. Fossum, “Short-Channel Effects in SO1 MOSFET ’ s t,” vol. 36, no. 3, pp. 522–528, 1989. [8] T. Vogelsang and K. R. Hofmann, “Electron transport in strained Si layers on Si1x Ge x substrates Electron transport in strained Si layers on Sil-, Ge, substrates,” vol. 186, no. 1993, pp. 61–64, 1996. [9] J.P. Colinge, Finfets and Other Multigate Transistors, Springer, Berlin, 2007. [10] D. Hisamoto, et al., FinFET-A self-aligned double-gate MOSFET scalable to 20 nm, IEEE Trans. Electron Devices 47 (12) (2000) 2320–2325. [11] C.R. Manoj, M. Nagpal, D. Varghese, V.R. Rao, ‘Device design and optimization considerations for bulk FinFETs’, IEEE Trans. Electron Devices 55 (2) (2008) 609–615. Calibrated device Optimum IOFF Optimum ION Optimum ION/ IOFF Table 4 shows the computed IOFF1 and IOFF2 values for two different WFISO. It can be observed from Table 4 that increase in WFISO reduces IOFF1 from 6.95 × 10–12 A to 1.89 × 10–14 A. On the other hand the corresponding IOFF2 is brought down to 1.57 × 10–19 A from 3.35 × 10–12 A. In other words at WFISO= 4 eV, IOFF1 contributes 67.5% and IOFF2 contributes 32.5% to the net leakage current as shown in Fig. 15. But at WFISO= 5.6 eV, IOFF1 contribution is 99.99% with IOFF2 contribution being insignificant, as shown in Fig. 15. 113 Materials Science in Semiconductor Processing 84 (2018) 107–114 S.P. Scarlet, R. Srinivasan [18] S. Kong, F. Application, and P. Data, MOSFET device having high-K dielectric layer, U.S. Patent 6504214, Jan. 7, 2003. [19] P. Haffner, S. Venkataraman, CMOS transistor having dual high-K dielectric, U.S. Patent 0199914, Aug. 9, 2012. [20] C.C. Wu, et al., High performance 22/20 nm FinFET CMOS devices with advanced high-K/metal gate scheme, Tech. Dig. - Int. Electron Devices Meet. IEDM (2010) 600–603. [21] S. Gundapaneni, S. Ganguly, A. Kottantharayil, Enhanced electrostatic integrity of short-channel junctionless transistor with high-k spacers, IEEE Electron Device Lett. 32 (10) (2011) 1325–1327. [22] B. Lakshmi, R. Srinivasan, Performance analysis of dual metal gate work function in junctionless transistors, J. Comput. Theor. Nanosci. 10 (6) (2013) 1354–1358. [23] P. Alto, B. Doyle, S. Jose, S. Jose, Work function tuning for MOSFET gate electrodes, U.S. Patent 0151074 vol. 1, no. 19, Aug. 14, 2003. [24] W. Long, H. Ou, J. Kuo, K.K. Chin, Dual-material gate ( DMG) field effect transistor, IEEE Trans. Electron Devices 46 (5) (1999) 865–870. [25] X. Sun et al., Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate, vol. 58, no. 10, pp. 3294–3299,201. [12] P. Scarlet, K.K. Nagarajan, R. Srinivasan, Optimization of doping profile and isolation oxide thickness in bulk FinFETs using TCAD simulations, in: Proceedings of IEEE International Conference on Circuit, Power and Computing Technologies, ICCPCT 2013, 2013. [13] J.-P. Colinge, et al., Nanowire transistors without junctions, Nat. Nanotechnol. 5 (3) (2010) 225–229. [14] C.R. Manoj, N. Meenakshi, V. Dhanya, and V. Ramgopal Rao, Device optimization of bulk FinFETs and its comparison with SOI FinFETs, in Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD, 2007, pp. 134–137. [15] M.H. Han, C.Y. Chang, H. Bin Chen, J.J. Wu, Y.C. Cheng, Y.C. Wu, Performance comparison between bulk and SOI junctionless transistors, IEEE Electron Device Lett. 34 (2) (2013) 169–171. [16] A. Bryant, W. Hansch, T. Mii, "Characteristics of CMOS device isolation for the ULSI age," in: Proceedings of 1994 IEEE International Electron Devices Meeting, San Francisco, CA, USA, 1994, pp. 671–674. [17] T. Baldauf et al., "Strained isolation oxide as novel overall stress element for TriGate transistors of 22nm CMOS and beyond," in: Proceedings of the International Semiconductor Conference Dresden-Grenoble (ISCDG), Grenoble, 2012, pp. 61–63. 114