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逻辑与计算机设计基础答案

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Problem Solutions – Chapter 1
CHAPTER 1
1-1.
39
2
© 2016 Pearson Education, Inc.
(a)
(1) Calm:
68
or
05
(2) 10 mph
:
69
(3) 100 mph
料
群
(b) The microcomputer requires a table or equation for converting from rotations/second to miles/hour. The pulses produced
by the rotating disk must be counted over a known period of time, and the table or equation used to convert the binary count
to miles per hour.
资
1-2.
–34° quantizes to –30° => 1 V => 0001
+31° quantizes to +30° => 7 V => 0111
试
+77° quantizes to +80° => 12 V => 1100
考
+108° quantizes to +110° => 15 V => 1111
1-3.*
17
18
19
20
大
Bin
16
21
22
23
24
25
26
27
28
29
1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101
20
21
22
Hex
10
11
12
23
13
湖
Oct
14
30
31
1 1110
1 1111
25
26
27
30
31
32
33
34
35
36
37
15
16
17
18
19
1A
1B
1C
1D
1E
1F
128K  128  210  131,072 Bits
32M  32  220  33,554,432 Bits
8G  8  230  8,589,934,592 Bits
欢
迎
加
入
1-4.
24
南
Dec
学
Decimal, Binary, Octal and Hexadecimal Numbers from (16)10 to (31)10
1
Problem Solutions – Chapter 1
1-5.
39
2
220 = (1,000,00010 + d) where d = 48,576
1Tb = 240 = (220)2 = (1,000,000 + d)2
= (1,000,000)2 + 2(1,000,000) d + d2
97,152,000,000
+
2,359,627,776
68
= 1,000,000,000,000
+
05
= 1,099,511,627,776
:
69
1-6.
11 1 Bits  211  1  2047
群
25 1 Bits  225  1  33, 554, 431
(1001101) 2  26  23  22  20  77
料
1-7.*
(1010011.101) 2  26  24  21  20  21  23  83.625
资
(10101110.1001) 2  27  25  23  22  21  21  24  174.5625
10111011
学
考
1
1
0
1
1
1
0
1
2|2014
2|1007
2|503
2|251
2|125
2|62
2|31
2|15
2|7
2|3
2|1
0
0
1
1
1
1
0
1
1
1
1
1
11111011110
欢
迎
加
入
湖
南
大
2|187
2| 93
2| 46
2| 23
2| 11
2| 5
2| 2
2|1
0
试
1-8.
2
2|891
2|445
2|222
2|111
2|55
2|17
2|13
2|6
2|3
2|1
0
1
1
0
1
1
1
1
0
1
1
2|20486
2|10243
2|5121
2|2560
2|1280
2|640
2|320
2|160
2|80
2|40
2|20
2|10
2|5
2|2
2|1
0
1101111011
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
101 0000 0000 0110
Problem Solutions – Chapter 1
39
2
1-9.*
Binary
Octal
Hexadecimal
369.3125
101110001.0101
561.24
171.5
189.625
10111101.101
275.5
BD.A
214.625
11010110.101
326.5
62407.625
1111001111000111.101
171707.5
68
Decimal
D6.A
05
F3C7.A
:
69
1-10.*
a)
0.45 × 8 = 3.6 =>
0.60 × 8 = 4.8 =>
0.80 × 8 = 6.4 =>
0.20 × 8 = 3.2 =>
(1938.257)10 = (792.41CB)16
(175.175)10 = (10101111.001011)2
(673.6)8
=
(110 111 011.110)2
考
a)
试
1-11.*
b)
(E7C.B)16
=
(1110 0111 1100.1011)2
=
(7174.54)8
(310.2)4
大
c)
南
=
(11 01 00.10)2
=
(64.4)8
1010
b)
×1100
0110
×1001
0000
0110
0000
0000
1010
0000
1010
0110
1111000
0110110
c)
1111001
×011101
1111001
000000
1111001
1111001
1111001
0000000
迎
加
入
湖
a)
(1BB.C)16
学
=
1-12.
3463
资
c)
3
4
6
3
料
b)
群
8|7562 2
16612
8|945 1
8|118 6
8|14 6
8|1 1
0
(7562.45)10 = (16612.3463)8
欢
110110110101
3
Problem Solutions – Chapter 1
10001
101 1010110
101
000
 000
001
000
011
 000
110
101
1
39
2
1-13.+
Quotient = 10001
群
:
69
05
68
Remainder = 1
1-14.
6 × 123 + 8 × 122 + 7 × 121 + 4 = 11608
12|7569 9
446912
12|630 6
12|52 4
12|4 4
0
试
资
料
(a)
(b)
0
1
A
B
2
3
4
5
6
7
8
9
C
D
E
F
G
H
I
J
学
a)
考
1-15.
大
b)
20|2007 7
20|100 0
20|5 5
0
50720
南
c) ( BCI .G)20  11 202  12  201  18  200  16  201  (4658.8)10
欢
迎
加
入
湖
1-16.*
a)
(BEE)r = (2699)10
11  r 2  14  r1  14  r 0  2699
11  r 2  14  r  2685  0
By the quadratic equation: r = 15 or ≈ –16.27
ANSWER: r = 15
b)
(365)r = (194)10
3  r 2  6  r1  5  r 0  194
3  r 2  6  r  189  0
By the quadratic equation: r = – 9 or 7
ANSWER: r = 7
4
Problem Solutions – Chapter 1
39
2
1-17.
Errata: The text has an error: 1480 should be 1460. This will be corrected in future printings.
Noting the order of operations, first add (34)r and (24)r
(24) r  2  r1  4  r 0
(34) r  (24) r  5  r1  8  r 0
Now, multiply the result by (21)r
Next, set the result equal to (1480)r and reorganize.
10  r 2  21  r1  8  1  r 3  4  r 2  6  r1
1  r 3  6  r 2  15  r1  8  r 0  0
群
Finally, find the roots of this cubic polynomial.
:
69
(2  r1  1 r 0 )  (5  r1  8  r 0 )  10  r 2  21 r1  8
Solutions are: r = 8, – 1, – 1
资
料
ANSWER: The chicken has 4 toes on each foot (half of 8).
试
1-18.*
考
a) (0100 1000 0110 0111)BCD
学
b) (0011 0111 1000.0111 0101)BCD
南
大
1-19.*
(4867)10
=
(1001100000011)2
=
(378.75)10
=
(101111010.11)2
(694)10
=
(0110 1001 0100)BCD
(835)10
=
(1000 0011 0101)BCD
湖
1
0001
1001
0100
+1000
+0011
+0101
1111
1100
1001
+0110
+0110
+0000
0101
1 0010
1001
欢
迎
加
入
=
0110
5
05
68
(34) r  3  r1  4  r 0
Problem Solutions – Chapter 1
101 100
0111 1000
011 1100
−0011
011 1001
−0011
01 1001
0 1100
−0011
0 1001
0100
010
01
0
Move R
Subtract 3
Move R
Move R
Move R
Move R
Move R
Subtract 3
大
料
考
学
Move R
Move R
Move R
试
0
Move R
Move R
Move R
Subtract 3
1-21.
欢
迎
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入
湖
南
(a)
1st Move L
2nd Move L
3rd Move L
Add 3
4th Move L
Add 3
5th Move L
6th Move L
Add 3
7th Move L
(b)
102
101
100 column > 0111
110
1110
01110
001110
1001110 Leftmost 1 in BCD number
shifted out: Finished
资
00
0
Move R
Subtract 3
110
101
100
1001
0111
1100
1011
−0011 -0011
1001 1000
1100 1100
−0011 −0011
1001 1001
0100 1100
−0011
0100 1001
0010 0100
001 0010
00
1001
−0011
00 0110
0 0011
0001
000
001
00
Move R
Subtract 3
0
1
101 and 100 columns > 0111
1
01
101 and 100 columns > 0111
01
101
100 column > 0111
群
102
0011
001
(b)
100 column > 0111
68
Subtract 3
0
05
Move R
Subtract 3
:
69
(a)
39
2
1-20.*
1101
01101
001101 100 column > 0111
001101
0001101
10001101
110001101 Leftmost 1 in BCD
number shifted out: Finished
100
1111000
1 111000
11 11000
111 1000
100 column > 100
0011
1010 1000
100 column > 100
1 0101 000
0011
1 1000 000
11 0000 00
110 00000 101 column > 100
0011
1001 0000 0
1 0001 00000 Least significant bit in binary number moved in:Finished
103
102
101
1st Move L
2nd Move L
3rd Move L
4th Move L
Add 3
100
0
01
011
0111
0011
6
01110010111
1110010111
110010111
10010111
0010111
100 column > 100
Problem Solutions – Chapter 1
10th Move L
Add 3
11th Move L
10 0010
100 0101
0011
100 1000
1001 0001
10111
0111
101 & 100 columns > 100
0111
111
11
100 column > 100
11
1
101 &100 columns > 100
39
2
100 column > 100
68
8th Move L
9th Move L
Add 3
10
101
0011
1000
1 0001
10 0010
0010111
010111
10111
05
7th Move L
Add 3
1010
0100
1000
0011
1011
0111
0011
1010
0100
1001
0011
1100
1001
0011
1100
1001
1
10
1
Least significant bit in binary number moved in: Finished
:
69
5th Move L
6th Move L
Add 3
1-22.
群
From Table 1-5, complementing the bit B6 will switch an uppercase letter to a lower case letter and vice versa.
1-23.
0101
0101
0010
0100
0100
资
B
N
M
L
V
A
0100
0010
0010
0100
0100
0101
0000
0000
0100
1110
1101
0010
1100
0101
1110
1101
0100
1010
0000
0100
1101
0010
1110
1010
0000
1100
1100
1100
0101
0100
0100
0101
0110
1100
1001
0100
1110
0100
0001
考
0010
大
湖
入
加
迎
欢
R
T
.
E
I
0100
1000111
G
1101111
o
南
1-24.
0010
0100
1110
0101
1001
0100
学
b)
0010
1110
1101
1100
0110
0001
试
0100
0100
0100
0100
0101
0100
料
a) The name used is Brent M. Ledvina. An alternative answer: use both upper and lower case letters.
E
(SP)
(SP)
D
N
0100000
1000011
C
1100001
a
1110010
r
1100100
d
1101001
i
1101110
n
1100001
a (Errata: This number appears as 110001, which would be “1”)
1101100
l
1110011
s
0100001
!
7
Problem Solutions – Chapter 1
a)
(11111111)2
b)
(0010 0101 0101)BCD
39
2
1-25.*
011 0010
011 0101
011 0101ASCII
d)
0011 0010
1011 0101
1011 0101ASCII with Odd Parity
05
68
c)
a)
U+0040 = 01000000
b)
U+00A2 = 11000010 10100010
c)
U+20AC = 11100010 10000010 10101100
d)
U+1F6B2 = 11110000
群
10011111 10011010 10110010
Binary Numbers from (32)10 to (47)10 with Odd and Even Parity
32
33
34
35
(a) Odd
100000 0
100001 1
100010 1
(b) Even
100000 1
100001 0
100010 0
42
101001 0
101010 0
(b) Even
101000 0
101001 1
101010 1
38
39
100011 0
100100 1
100101 0
100110 0
100111 1
100011 1
100100 0
100101 1
100110 1
100111 0
43
44
45
46
47
101011 1
101100 0
101101 1
101110 1
101111 0
101011 0
101100 1
101101 0
101110 0
101111 1
试
41
101000 1
37
学
考
40
(a) Odd
36
资
Decimal
料
1-27.
Decimal
:
69
1-26.
大
1-28.
Gray Code for Hexadecimal Digits
1
2
0001
0011
迎
加
入
1-29.
欢
3
4
南
0
0000
0010
湖
Hex
Gray
0110
5
6
7
8
9
A
B
C
D
E
F
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
(a) Wind Direction Gray Code
Direction
Code Word
N
000
S
110
E
011
W
101
NW
100
NE
001
SW
111
SE
010
8
Problem Solutions – Chapter 1
000
NE
001
E
011
SE
010
S
110
SW
111
W
101
NW
100
68
N
05
Code Word
:
69
Direction
39
2
(b) Wind Direction Gray Code (directions in adjacent order)
As the wind direction changes, the codes change in the order of the rows of this table, assuming that the bottom row is “next
to” the top row. From the table, the codes that result due to a wind direction change always change in a single bit.
群
1-30.+
The percentage of power consumed by the Gray code counter compared to a binary code counter equals:
料
Number of bit changes using Gray code
Number of bit changes using binary code
资
As shown in Table 1-6, and by definition, the number of bit changes per cycle of an n-bit Gray code counter is 1 per count =
2n.
试
Number of bit changes using Gray code = 2n
考
For a binary counter, notice that the least significant bit changes on every increment. The second least significant bit
changes on every other increment. The third digit changes on every fourth increment of the counter, and so on. As shown
in Table 1-6, the most significant digit changes twice per cycle of the binary counter.
Number of bit changes using binary code 2n  2n1 
学
n
 n 
  2i   2i   1  (2( n 1)  1)  1  2n 1  2
i 1
 i 0 
2
2n
( n1)
2
 100
欢
迎
加
入
湖
南
大
% Power 
9
 21
Problem Solutions – Chapter 2
CHAPTER 2
39
2
© 2016 Pearson Education, Inc.
2-1.*
b)
Y
Z
XYZ
XYZ
X Y  Z
0
0
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
1
1
0
0
0
1
1
1
0
1
0
1
1
1
1
0
0
1
1
1
1
1
1
0
0
:
69
05
X
X  YZ  ( X  Y )  ( X  Z )
Y
Z
YZ
X + YZ
X+Y
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
学
考
资
0
0
YZ
XZ
XY  YZ  XZ
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
0
1
1
0
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
0
1
1
湖
南
0
YZ
0
0
0
0
1
1
1
0
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
入
加
迎
欢
1
1
XY
XY
1
0
XY  YZ  XZ
Z
1
0
XZ
Y
1
0
XY  YZ  XZ  XY  YZ  XZ
X
1
(X + Y)(X + Z)
大
c)
X+Z
试
X
料
The Second Distributive Law
2-2.*
68
XYZ  X  Y  Z
Verification of DeMorgan’s Theorem
群
a)
a)
X Y  XY  XY
=
 ( X Y  X Y )  ( XY  XY )
 X (Y  Y )  Y ( X  X )
 X Y
1
X Y
b)
AB  BC  AB  BC
=
1
=
X Y  Z
=
:
69
Problem Solutions – Chapter 2
 ( AB  AB)  ( BC  BC )
39
2
 B( A  A)  B (C  C )
B  B 1
c)
Y  XZ  XY
68
 Y  XY  XZ
 (Y  X )(Y  Y )  XZ
05
 Y  X  XZ
 Y  ( X  X )( X  Z )
 X Y  Z
d)
XY  Y Z  XZ  XY  YZ
 XY  YZ ( X  X )  XZ  XY  YZ
 XY  XYZ  XYZ  XZ  XY  YZ
群
 XY (1  Z )  XYZ  XZ  XY  YZ
 XY  XZ (1  Y )  XY  YZ
 XY  XZ (1  Y )  YZ
ABC  BCD  BC  CD
=
B  CD
考
a)
试
2-3.+
资
 XY  XZ  YZ
料
 XY  XZ  XY ( Z  Z )  YZ
 XY  XZ  XYZ  YZ (1  X )
X Y  XZ  YZ
 ABC  ABC  BC  BCD  BCD  CD
学
 AB(C  C )  BC ( D  D)  BC  CD
 AB  BC  BC  CD
大
 B  AB  CD
 B  CD
欢
迎
加
入
湖
南
b)
WY  WYZ  WXZ  WXY
=
WY  WXZ  XYZ  XYZ
 (WY  WXYZ )  (WXYZ  WXYZ )  (WXYZ  WXYZ )  (WXYZ  WXY Z )
 (WY  WXYZ )  (WXYZ  WXY Z )  (WXYZ  WXYZ )  (WXYZ  WXYZ )
 WY  WXZ (Y  Y )  XYZ (W  W )  XYZ (W  W )
 WY  WXZ  XYZ  XYZ
c)
AD  AB  CD  BC
=
( A  B  C  D)( A  B  C  D)
 AD  AB  CD  BC
 ( A  D)( A  B )(C  D)( B  C )
 ( AB  AD  BD)( BC  BD  CD)
 ABCD  ABCD
 ( A  B  C  D)( A  B  C  D )  ( A  B  C  D )( A  B  C  D )
2
Problem Solutions – Chapter 2
Given:
A  B  0, A  B  1
Prove:
( A  C)( A  B)( B  C)
=
 AB  AC  BC
05
 0  C ( A  B)
 C ( A  B )(0)
 C ( A  B )( A  B )
:
69
 C ( AB  AB  B
 BC
2-5.+
(A3, A2, A1, A0)
B
=
(B3, B2, B1, B0)
C
=
(C3, C2, C1, C0)
Define OR1, AND1 and NOT1 so that they conform to the definitions of AND, OR and NOT
presented in Table 2-1.
资
Step 2:
=
群
Define all elements of the algebra as four bit vectors such as A, B and C:
A
料
Step 1:
A + B = C is defined such that for all i, i = 0, ... ,3, Ci equals the OR1 of Ai and Bi.
b)
A B = C is defined such that for all i, i = 0, ... ,3, Ci equals the AND1 of Ai and Bi.
c)
The element 0 is defined such that for A = “0”, for all i, i = 0, ... ,3, Ai equals logical 0.
d)
The element 1 is defined such that for A = “1”, for all i, i = 0, ... ,3, Ai equals logical 1.
e)
For any element A, A is defined such that for all i, i = 0, ... ,3, Ai equals the NOT1 of Ai.
AC  ABC  BC  AC  ABC  ( ABC  BC)
大
a)
学
考
试
a)
2-6.
 AC  ( ABC  ABC  BC
南
 ( AC  AC )  BC  A  BC
迎
加
入
湖
b)
欢
BC
68
 ( AB  AC  BC )( B  C )
39
2
2-4.+
( A  B  C )( ABC )
 AABC  ABBC  ABCC
 ( AA) BC  A( BB )C  AB (CC )
 ABC  ABC  ABC  ABC
c)
ABC  AC  A( BC  C )  A( B  C )
d)
ABD  ACD  BD
 ( AB  B  AC ) D
 ( A  AC  B) D
 ( A  B) D
e)
( A  B)( A  C )( ABC )
 AAABC  ACABC  BAABC  BCABC
 ABC
3
Problem Solutions – Chapter 2
2-7.*
 ( X  Y )( X  Z )  X  YZ
X  Y ( Z  X  Z )  X  Y ( Z  XZ )  X  Y (Z  X )(Z  Z )  X  YZ  XY
b)
WX ( Z  YZ )  X (W  WYZ )  WXZ  WXYZ  WX  WXYZ
c)
 WXZ  WXZ  WX  WX  WX  X
68
 ( X  X )( X  Y )  YZ  X  Y  YZ  X  Y
39
2
XY  XYZ  XY  X  XYZ  ( X  XY )( X  Z )  ( X  X )( X  Y )( X  Z )
a)
05
( AB  AB)(CD  CD)  AC  ABCD  ABCD  ABCD  ABCD  A  C
d)
:
69
 ABCD  A  C  A  C  A( BCD)  A  C  C ( BD)  A  C  BD
2-8.
F  ABC  AC  AB
a)
F  ABC  AC  AB
b)
料
群
 ( A  B  C )  ( A  C )  ( A  B)
c) Same as part b.
资
2-9.*
F  ( A  B)( A  B)
b)
F  ((V  W ) X  Y )Z
c)
F  [W  X  (Y  Z )(Y  Z )][W  X  YZ  YZ ]
d)
F  ABC  ( A  B)C  A( B  C )
学
考
试
a)
2-10.*
X
Y
Z
a
A
B
C
b
W
X
Y
Z
c
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
1
0
1
1
1
0
1
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
欢
迎
加
入
湖
南
大
Truth Tables a, b, c
4
 ( ABC )( AC )( AB)
Problem Solutions – Chapter 2
a)
Sum of Minterms:
XYZ  XYZ  XYZ  XYZ
b)
Sum of Minterms:
ABC  ABC  ABC  ABC
Product of Maxterms: ( A  B  C )( A  B  C )( A  B  C )( A  B  C )
Sum of Minterms:
WXYZ  WXYZ  WXYZ  WXY Z  WXYZ  WXYZ  WXYZ
68
c)
39
2
Product of Maxterms: ( X  Y  Z )( X  Y  Z )( X  Y  Z )( X  Y  Z )
Product of Maxterms: (W  X  Y  Z )(W  X  Y  Z )(W  X  Y  Z )
05
(W  X  Y  Z )(W  X  Y  Z )(W  X  Y  Z )
:
69
(W  X  Y  Z )(W  X  Y  Z )(W  X  Y  Z )
2-11.
a)
E  m(1, 2, 4, 6)  M (0, 3, 5, 7),
b)
E  m(0, 3, 5, 7),
c)
E  F  m(0, 1, 2, 4, 6, 7),
d)
E  XYZ  XYZ  XY Z  XYZ ,
e)
E  Z ( X  Y )  XYZ ,
a)
( AB  C )( B  CD)  AB  ABCD  BC  AB  BC s.o.p.
F  m(1, 3, 5, 6)
群
F  XY Z  XYZ  XY Z  XYZ
料
F  Z ( X  Y )  XYZ
试
b)
E  F  m(2, 4)
资
2-12.*
 B( A  C ) p.o.s.
F  m(0, 2, 4, 7)  M (1, 3, 5, 6)
X  X ( X  Y )(Y  Z )  ( X  X )( X  ( X  Y )(Y  Z ))
考
 ( X  X  Y )( X  Y  Z ) p.o.s.
 (1  Y )( X  Y  Z )  X  Y  Z s.o.p.
( A  BC  CD)( B  EF )  ( A  B  C )( A  B  D)( A  C  D)( B  EF )
学
c)
 ( A  B  C )( A  B  D)( A  C  D)( B  E )( B  F ) p.o.s.
大
( A  BC  CD)( B  EF )  A( B  EF )  BC ( B  EF )  CD( B  EF )
2-13.
a)
A
入
B
湖
南
 AB  AEF  BCEF  BCD  CDEF s.o.p.
b)
c)
Y
Z
A
Z
加
C
D
C
Y
A
X
B
W
C
A
C
B
D
A
Y
C
X
Z
欢
迎
B
5
B
Problem Solutions – Chapter 2
2-14.
X 1
1
1
X 1 1
Z
XY + XZ + YZ
1 1
C
C + AB
1
1 1
1
1
C
AB + AC + BC
BC + AB + AC
or
2-15.*
1
1
1
1
1
1
1
c)
1
1
A
C
CB
AA+CB
1 1
1
A 1 1
1
C
BB+CC
资
Z
XZ
XZ 
+ XY
B
料
X
B
b)
群
Y
a)
:
69
05
Z
X Y + YZ+XYZ
1
1
A 1
1
1
A 1
B
d)
B
c)
39
2
1
1
Y
b)
68
Y
a)
a)
b)
C
1
B
1
1
1 1
学
A
大
D
Y
1
1
1
1
1
1
1
A
1
B
X
1 1
W
1
1
1
1
1
D
Z
AC AD ABC
X Z  Y Z  WXY  W XYZ
南
BD  ABC  ACD
c)
C
1
考
1
1 1
试
2-16.
湖
2-17.
Y
a)
1
1
W
C
1
X
1
1
1
1
A
1
Z
1
1
1 1
1
B
1 1
D
F  BC  ACD  ABD  ABC  ( ABD or ACD)
F  XZ  Y Z  W XY  W XYZ
欢
迎
加
入
1 1
b)
6
Problem Solutions – Chapter 2
b)
1
1
W
Z
m  3 5 6 7 
m(3, 5, 6, 7)
1
1
1
1 1
X
A
1
b) Prime  CD, AC, BD, ABD, BC
c)
Essential  AC , BD, ABD
Prime  AB, AC, AD, BC , BD, CD
Essential  AC, BC , BD
2-20.
b) Prime  WY , XY ,WXZ ,W X , XYZ ,WYZ
料
a) Prime  BD, ACD, ABC, ABC, ACD
Essential  WY , XY
Redundant  BD
Redundant  W X , XYZ ,WYZ
F  ACD  ABC  ABC  ACD
F  WY  XY  WXZ
考
Essential  W Z , X Z
Redundant =W XY ,W XZ ,WXY
a)
F
大
2-21.
Y
0
0
0
0
C
0
X
A
湖
W
0
F
b)
南
0
0
学
F  W Z  X Z  WYZ  XYZ
试
资
Essential  ACD, ABC, ABC, ACD
Prime  W Z , X Z ,WYZ , XYZ ,W XY ,W XZ ,WXY
c)
1
B
群
Essential  XZ , XZ
1
1
D
m  0 2 6 7 8 10 13 15
m(0, 2, 6, 7, 8, 10, 13, 15)
Z
m  3 4 5 7 9 13 14 15
m(3, 4, 5, 7, 9, 13, 14, 15)
2-19.*
a) Prime  XZ , WX , XZ , WZ
1
1
1
05
X
1
:
69
1
C
1
1
1
Y
1
c)
Y
68
a)
39
2
2-18.*
0
0
0 0
B
0 0
0
0
D
入
Z
0
0
F  m(0, 2, 6, 7, 8, 9, 10, 12, 14, 15)
加
F  m(3,4,5,6,7,9,11,13)
F  BD  BC  ABC  AD
F  (W  X )(W  Y  Z )( X  Y  Z )
F  ( B  D)( B  C)( A  B  C )( A  D)
迎
F  W X  WYZ  XYZ
欢
2-22.*
a) s.o.p.
p.o.s.
CD  AC  BD
(C  D)( A  D)( A  B  C )
b) s.o.p.
p.o.s.
AC  BD  AD
(C  D)( A  D)( A  B  C )
7
c) s.o.p.
p.o.s.
BD  ABD  ( ABC or ACD)
( A  B)( B  D)( B  C  D)
Problem Solutions – Chapter 2
2-23.
ABD  ABC  ABD  ABC
b) s.o.p.
or
ACD  BCD  ACD  BCD
p.o.s.
X  YZ  W Z
( X  Y  Z )(W  X  Z )
( A  B  D)( A  B  C )( A  B  D)( A  B  C )
p.o.s.
68
or ( A  C  D)( B  C  D)( A  C  D)(B  C  D)
b)
1
X X
A 1 X
1 X
A
C
c)
C
B
X
1
X 1
1
B
1
1
D
X
X
X
1
群
Z
F  AD  ( ABD  BCD) or
F  AC
1
W
X X
X
Y
1
1
1 X X
:
69
a)
05
2-24.
F  XY Z W XY  WYZ  XYZ
料
( ACD  BCD) or ( ABD  ABC )
资
2-25.*
Y
b)
a)
A
1
1
1 X 1
W
考
X
C
a)(1)
入
1
0 1
X X
1 X
加
0
0 X
Z
迎
F  WY  Y Z 
WYZ  WX Z
1
1
X X
1
X
A
X
学
X
W
Y
X X
0 1
0 X
1
X X
1 X
0 1
0
0 X
b)(1)
C
b)(2)
X 0 X
0 1 X 0
B
0 1 1 0
A
Z
X
X 0
D
F  ( XY or X Z )  WYZ  WY Z  (WXZ or WYZ )
F  ((X Y) or (X+Z))(W+Y+Z)(W+Y+Z)
((W+X+Z) or (W+Y+Z))
8
1
1
1 X
1
X X
B
F  BD
X
C
X 0 X
0 1 X 0
B
0 1 1 0
X
X
X
X 1
D
Primes
C,AD
Primes
 AB=, AB
C, AD
BD BD
Essential
=
C

AD
Essential  C , AD
F = C + AD +  BD or AB 
F  C  AD( BD or AB)
大
0 X
X X
0 1
W
a)(2)
湖
Y
1
C
1
1 X
X
c)
Z
= ,XZ
 XZ, WXY
WXY, WXY
PrimesPrimes
 XZ , XZ
WXY
WY Z, WYZ
WYZ WYZ
Essential
Essential
 XZ = XZ
F = XZ + WXY + WXY
F  XZ  WXY  WXY
南
= ,AB
 AC
 BC ABC
PrimesPrimes
 AB, AC
BC
, ABC
Essential
= ,AB
 AC BC
Essential
 AB, AC
BC
F = AB + AC + BC
F  AB  AC  BC
2-26.
试
1
B
欢
39
2
a) s.o.p.
A
X
X 0
D
F BD
F  BD
X
Problem Solutions – Chapter 2
39
2
2-27.*
X  Y  XY  XY
Dual(X  Y )  Dual( XY  XY )
68
 ( X  Y )( X  Y )
 XY  XY
05
 XY  XY
:
69
 X Y
2-28.
ABCD  AD  AD  ABCD  ( A  D)
群
Note that X  Y  ( X  Y )  XY
Letting X  ABCD and Y  A  D,
料
We can observe from the map below or determine algebraically that XY is equal to 0.
C
1
1
试
1
1
考
A
1
资
1
1
1
B
1
D
For this situation,
学
X  Y  ( X  Y )  XY
 ( X Y )  0
大
 X Y
南
So, we can write F ( A, B, C, D)  X  Y  ABCD  ( A  D)
A
B
F
加
The longest path is from input C or D.
0.073 ns + 0.073 ns + 0.048 ns + 0.073 ns = 0.267 ns
欢
迎
2-29.*
C
入
湖
D
9
Problem Solutions – Chapter 2
39
2
2-30.
68
a)
05
b)
0
1.0
2.0
4.0
3.0
5.0
7.0
6.0
2-31.
t PLH-C, D to F  2t PHL  2t PLH  2(0.20)  2(0.36)  1.12 ns
t PHL-B to F  2t PHL  t PLH  2(0.20)  (0.36)  0.76 ns
t PLH-B to F  2t PHL  t PLH  2(0.36)  (0.20)  0.92 ns
b) t pd-C, D to F  4 t pd  4(0.28)  1.12 ns
t pd-B to F  3 t pd  3(0.28)  0.78 ns
资
学
t pd-A, B, C to F  2 t pd  2(0.28)  0.56 ns
考
t pd-A, B, C to F  0.56 ns
试
t PHL-A, B, C to F  t PLH  t PHL  0.36  0.20  0.56 ns
t PLH-A, B, C to F  t PHL  t PLH  0.20  0.36  0.56 ns
9.0 ns
料
t pd  1.12 ns
t pd-B to F  0.76  0.92  0.84 ns
8.0
群
a) t PHL-C, D to F  2t PLH  2 t PHL  2(0.36)  2(0.20)  1.12 ns
:
69
c)
大
c) For paths through an odd number of inverting gates with unequal gate tPHL and tPLH, path tPHL, tPLH, and tpd are different.
For paths through an even number of inverting gates, path tPHL, tPLH, and tpd are equal.
南
2-32.
欢
迎
加
入
湖
If the rejection time for inertial delays is greater than the propagation delay, then an output change can occur before it
can be predicted whether or not it is to occur due to the rejection time.
For example, with a delay of 2 ns and a rejection time of 3 ns, for a 2.5 ns pulse, the initial edge will have already
appeared at the output before the 3 ns has elapsed at which whether to reject or not is to be determined.
10
Problem Solutions – Chapter 2
39
2
2-33.+
68
a) The propagation delay is tpd  max(tPHL  0.05, tPLH  0.10)  0.10 ns.
a) The propagation delay istpd = max(
tPHL = 0.05, tPLH = 0.10) = 0.10 ns.
a) The
tPHLpulse,
= 0.05,
= 0.10)
= 0.10occurs:
ns.
Assuming that the
gatepropagation
is an inverter,delay
for aistpositive
output
thet following
actually
pd = max(
Assuming that the gate is an inv, erter
f or
a positiv ePLH
output pulse, the f ollowing actually occurs:
Assuming that the gate is an inv, erter
f or a positiv e output pulse, the f ollowing actually occurs:
05
0.05 ns
0.10 ns0.05 ns
0.10 ns
:
69
If the input pulse is narrower than 0.05 ns, no output pulse occurs so the rejection time is 0.05 ns.
If the
input pulse
is narrower the
thanf ollowing
0.05 ns,results,
no output
pulse
occurs
so the delay
rejection
time
The
resulting
model
which
f erdif
ftime
rom
behav
, ioris 0.05 ns.
If the input pulse
is narrower
than
0.05predicts
ns, no output pulse
occurs so the rejection
isthe
0.05actual
ns. The resulting
model
The
resulting
model
predicts
the
f
ollowing
results,
which
f
er
dif
f
rom
the
actual
delay
behav
but models
rejection
behav
: delay behavior, but models the rejection behavior: : , ior
predicts the following
results,the
which
differ from
theior:
actual
but models the rejection behav ior: :
群
0.10 ns
0.10 ns 0.10 ns
0.10 ns
料
b) For a negative output pulse, the following actually occurs:
b) For a negative output pulse, the following actually occurs:
b) For a negative output pulse, the following actually occurs:
考
试
资
0.05 ns
0.15 ns 0.050.10
ns ns
0.10 ns
0.15 ns
The model predicts the f ollowing results, which
f ers
dif f rom the actual delay behav ior and f rom
The model predicts the following results, which differs from the actual delay behavior and from the actual rejection
the
actual
rejection
behavior:
The
model
predicts
the
f
ollowing
results,
which
f
ers
dif
f rom the actual delay behav ior and f rom
behavior:
the actual rejection behavior:
南
大
学
0.10 ns0.10 ns
0.10 ns0.10 ns
Overall, the model is inaccurate for both cases a and b, and provides a faulty rejection
model fthe
or model
case b.
Using anfor
avboth
erage
of
and
t b,
f or
t provides
would improv
e rejection
the delay
Overall,
is inaccurate
cases
at and
and
a faulty
PHL
PLH
pd
Overall, the model is inaccurate
for
both
and
b, and
provides
aof
faulty
rejection
model
for
case
b.fails.
Using
an
accuracy
thecases
model
for circuit
applications,
but
the
rejection
model
still
model
f orof
case
b. a Using
an av
erage
and
t
t
f
or
t
would
improv
e
the
delay
PHL
PLH
pd
average of tPHL and tPLH for
t
would
improve
the
delay
accuracy
of
the
model
for
circuit
applications,
but
the
rejection
pd
accuracy of the model for circuit applications, but the rejection model still fails.
model still fails.
X1
N1
N2
X2
N6
N3
N4
X3
N5
X4
迎
2-35.
加
入
湖
2-34.*
欢
-- Figure 4-40: Structural VHDL Description
library ieee;
use ieee.std_logic_1164.all;
entity nand2 is
port(in1, in2: in std_logic;
out1 : out std_logic);
end nand2;
11
f
Problem Solutions – Chapter 2
39
2
architecture concurrent of nand2 is
begin
out1 <= not (in1 and in2);
end architecture;
architecture concurrent of nand3 is
begin
out1 <= not (in1 and in2 and in3);
end concurrent;
料
群
library ieee;
use ieee.std_logic_1164.all;
entity nand4 is
port(in1, in2, in3, in4: in std_logic;
out1 : out std_logic);
end nand4;
-- The code above this point could be eliminated by using the library, func_prims.
:
69
05
68
library ieee;
use ieee.std_logic_1164.all;
entity nand3 is
port(in1, in2, in3 : in std_logic;
out1 : out std_logic);
end nand3;
考
试
资
library ieee;
use ieee.std_logic_1164.all;
entity fig440 is
port(X: in std_logic_vector(2 to 0);
f: out std_logic);
end fig440;
architecture structural_2 of fig440 is
南
component NAND3
port(in1, in2, in3: in std_logic;
out1: out std_logic);
end component;
大
学
component NAND2
port(in1, in2: in std_logic;
out1: out std_logic);
end component;
加
入
湖
signal T: std_logic_vector(0 to 4);
begin
g0: NAND2 port map (X(2),X(1),T(0));
g1: NAND2 port map (X(2),T(0),T(1));
g2: NAND2 port map (X(1),T(0),T(2));
g3: NAND3 port map (X(1),T(1),T(2),T(3));
g4: NAND2 port map (X(1),T(2),T(4));
g5: NAND2 port map (T(3),T(4),f);
end structural_2;
欢
迎
F =X0X 2 + X 1X 2
F  X0X2  X1X0
12
Problem Solutions – Chapter 2
2-36.begin
X = D + BC
g0: begin
NOT _1 port map (D, x1);
Y = A BCD
g1: AND_2
map (B,
C,map
x2);
g0: port
NOT_1
port
2-38.*
料
资
g
大
学
begin
F <= (X and Z) or ((not Y) and Z);
end;
f
考
a
b
a
c
b
c
b
a
c
d
试
2-37.
群
:
69
05
68
39
2
X  D  BC
Y  ABCD
(D, x1);
g2: NOR_2
map (A,
x1,map
x3); (B, C, x2);
g1: port
AND_2
port
g3: NAND_2
port mapport
(x1, x3,
x4);
g2: NOR_2
map
(A, x1, x3);
g4: OR_2
port
map
(x1,
x2,
x5);
g3: NAND_2 port map (x1, x3, x4);
g4: port
OR_2
g5: AND_2
mapport
(x4, map
x5, X);(x1, x2, x5);
g5: port
AND_2
portx5,map
g6: AND_2
map (x3,
Y); (x4, x5, X);
g6: AND_2 port map (x3, x5, Y);
end structural_1;
end structural_1;
南
2-39.*
X1
N1
N2
N6
N3
N4
X3
N5
X4
欢
迎
加
入
湖
X2
13
f
Problem Solutions – Chapter 2
2-40.
39
2
module circuit_4_50(A, B, C, D, X, Y);
input A, B, C, D;
output X, Y;
68
wire n1, n2, n3, n4, n5;
05
not
go(n1, D);
:
69
nand
g1(n4, n1, n3);
群
and
g2(n2, B, C),
g3(X, n4, n5),
g4(Y, n3, n5);
or
料
g5(n5, n1, n2);
nor
资
g6(n3, n1, A);
欢
迎
加
入
湖
南
大
学
考
试
endmodule
14
Problem Solutions – Chapter 2
2-41.
39
2
module circuit_4_51(X, F);
input [2:0]
module circuit_4_51(X,
F);X;
output
F;
input [2:0]
X;
output F;
[0:4] T;
nand
nand
g0(T[0],X[0],X[1]),
g0(T [0],X[0],X[1]),
g1(Tg1(T[1],X[0],T[0]),
[1],X[0],T [0]),
g2(Tg2(T[2],X[1],T[0]),
[2],X[1],T [0]),
g3(Tg3(T[3],X[2],T[1],T[2]),
[3],X[2],T [1],T [2]),
g4(T [4],X[2],T [2]),
g4(T[4],X[2],T[2]),
g5(F
,T [3],T [4]);
endmodule g5(F,T[3],T[4]);
endmodule
料
群
:
69
05
68
wire [0:4]wire
T;
试
考
a
b
a
c
b
c
b
a
c
d
资
2-42.
学
g
大
2-43.*
f
欢
迎
加
入
湖
南
module circuit_4_53(X, Y, Z, F);
input X, Y, Z;
output F;
assign F = (X & Z) | (Z & ~Y);
endmodule
15
Problem Solutions – Chapter 3
CHAPTER 3
39
2
© 2016 Pearson Education, Inc.
3-1.
05
68
Place a 1 in each K-map cell where 2 or more inputs are equal to 1.
Place a 1 in each K-map cell where 2 or more inputs are equal to 1.
Y
This is the same function as the carry
1
This is the same function as the
= XZ
F =FXZ
+ XY+ +XY
YZ+ YZ
for the full adder.
carry f or the f ull adder
.
1
1
1
X
:
69
Z
3-2.*
1
B
1 1
F = AB + AC
料
1
A
群
C
1 1
资
D
试
3-3.
G1G0
00 01 11 10
00 01 11 10
G3G2
00
01 1
1 1
10 X X
X X
X X
G1G0
G1G0
00 01 11 10
G3G2
00
01 1
10 X X
B2  G3G2
1 1
00
01 1
X X
X X
11
1
11
00 01 11 10
G3G2
B1  G2G1  G3G2 G1
1
1
1
1 X X
10 X X X X
B0  G3G0  G2G1G0  G2G1 G0
 G2 G1G0  G3G2 G1 G0
入
B3  G3
1
11
南
10 X X
X X
X X
湖
11 1 1
大
00
01
学
G1G0
G3G2
考
Assuming inputs G3, G2, G1, G0 and outputs B3, B2, B1, B0, with G3 and B3 being the most significant bits, and treating the invalid
input combinations as don’t cares:
3-4.
加
a) For the 3 x 3 pattern, there are exactly three row, three column and two diagonal combinations that represent a win for the X
player: W = X1 X2 X3 + X4 X5 X6 + X7 X8 X9 + X1 X4 X7 + X2 X5 X8 + X3 X6 X9 + X1 X5 X9 + X3 X5 X7 Gate Input cost = 32
迎
b) W = X5 (X1 X9 + X2 X8 + X3 X7 + X4 X6) + X1 X2 X3 + X1 X4 X7 + X7 X8 X9 + X3 X6 X9 Gate Input Cost = 30
3-5.
欢
a) For the 4 x 4 pattern, there are exactly four row, four column and two diagonal combinations that represent a win for the X
player: W = X1 X2 X3 X4 + X5 X6 X7 X8 + X9 X10 X11 X12 + X13 X14 X15 X16 + X1 X5 X9 X13 X2 X6 X10 X14 + X3 X7 X11
X15 + X4 X8 X12 X16 + X1 X6 X11 X16 + X4 X7 X10 X13 Gate Input cost = 50
b) W = X1(X2 X3 X4 + X5 X9 X13 + X6 X11 X15) + X7(X5 X6 X8 + X3 X11 X15 + X4 X10 X13) + X9 X10 X 11 X12
+ X13 X14 X15 X16 + X2 X6 X10 X14 + X4 X8 X12 X16 Gate Input Cost = 48
1
Problem Solutions – Chapter 3
1
0110
1
0111
1
0101
0
0100
0
1100
0
1101
0
1111
0
1110
0
1010
0
1011
0
1001
0
1000
0
0
1
0
0
GNS
GNS
GNS
GNS = AC + AB
GNSGNS
 AC= AC
AB+ AB
GNS = AC + AB
A
A
B
A
B
C
B
C
D
C
D
D
料
1
0010
资
1
0011
试
0001
考
1
B
B
B
A
A
A
C
C
C
YNS
YNS
YNS
YNS = ABCD
YNS = ABCD
YNS
= ABCD
YNS
 ABCD
B
B
C
B
C
D
C
D
A
D
A
A
RNS
RNS
RNS
+ BCD
RNS = A
RNS = A + BCD
RNS = A + BCD
RNS  A  BCD
学
0000
YNS RNS
YEW REW
YNS ABCD
RNS GNS
GEW
YEWGEWREW
ABCD
GNS
REW
0000
1 YNS
0 RNS
0 0 GEW
0 YEW
1
0 ABCD
0 GNS
0
10 REW
YNS
RNS
GEW
0000
1
0
0
0 YEW
0
1
0001
1
0
0
0
0
1
0000
11 0 00
00 0 00
11
0
0
100
0001
0011
1
0
0
0
0
1
0001
11 0 00
00 0 00
11
0011
0
0
0
100
0010
1
0
0
0
1
0011
11
0
00
00
00
11
0010
0110
1 00
0
00 0
1
0
0
10
0010
11
0
00
00
00
11
0110
01110
1 00
0
00 0
0
1
0
1
0110
11
00
00
00
00
11
0111
0101
0
1
0
0
0
1
0
0
100
0111
10 0 01
00 0 00
11
0101
0100
0
0
1
0
0
1
0101
00 0 10
01 0 00
11
0100
0
1
0
100
1100
0
0
1
1
0
0100
00
0
11
01
00
10
1100
1101
0 00
0
10 1
0
0
1
10
1100
00
0
11
11
00
00
1101
11111
0 10
0
10 1
0
0
0
0
1101
00
00
11
11
00
00
1111
1110
0
0
1
1
0
0
0
000
1111
00 1 00
11 0 11
00
11101
1010
0
0
1
1
0
0
1110
00 1 00
11 0 11
00
0
1
000
1010
0
1011
0
0
1
1
0
1010
00
0
11
11
00
00
1011
0
1
01
1001
0 10
0
10 0
0
1011
00
0
11
10
01
00
1001
1000
0 10
0
10 0
0
1
0
1
0
1001
00
00
11
00
10
01
1000
0
1
1
0
0
1000
0
0
1
0
0
1
0
1
0
1
0
1
大
GNS
群
3-7.+
ABCD
B
C
S5 S4 S3 S2 S1 S0
S0  C
0
0
0
0
0
0
0
0
0
S1  0
0
0
1
0
0
0
0
0
1
S2  ABC  ABC
0
1
0
0
0
0
1
0
0
S3  ABC  ABC
0
1
1
0
0
1
0
0
1
S4  AB  AC
1
0
0
0
1
0
0
0
0
S5  AB
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
1
0
0
1
1
1
1
1
0
0
0
1
欢
迎
加
入
A
湖
南
3-8.
2
68
If odd parity is chosen, then an
alternative result for Z is:
Z  X1  X 2  X 3
Z
0
1
1
0
1
0
0
1
:
69
X1 X2 X3
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
05
a) Detecting a change in one-out-ofthree inputs can be done using a parity
function as Z. The truth table shown is
for even parity. For this case,
Z  X1  X 2  X 3
39
2
3-6.
B
B
B
GEW
A
GEW
A
GEW
A
C
C GEW = AB + AC
CGEW
GEW
= AB
 AB
AC+ AC
A
A
B
A
B
C
B
C
D
C
D
D
B
B
C
B
C
D
C
D
A
D
A
A
GEW = AB + AC
YEW
YEW
YEW
YEW = ABCD
YEW = ABCD
YEW
= ABCD
YEW
 ABCD
REW = A + BCD
REW = A + BCD
REW = A + BCD
REW  A  BCD
Problem Solutions – Chapter 3
A
B
C
D
S2
S1
S0
0
0
0
0
0
0
0
S0  BCD  BCD  AB  ACD  ABCD
0
0
0
1
0
0
1
0
0
1
0
0
0
1
S1  AB  AB  ACD  BCD
0
0
1
1
0
1
0
0
1
0
0
0
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
1
1
0
1
0
0
1
1
1
0
1
1
0
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
0
1
1
1
1
1
0
0
A
B
C
D
W
X
Y
Z
W  AC  BD  BD
0
0
0
0
0
0
1
1
X  BCD  BC+BD
0
0
0
1
0
1
0
0
0
0
1
0
Y  CD +CD
0
0
1
1
0
1
0
0
0
1
0
0
1
1
0
1
1
1
05
:
69
群
料
资
考
试
3-10.
1
0
1
0
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
1
1
0
1
0
0
0
0
1
0
1
1
0
0
1
1
1
0
0
南
大
学
0
1010 to
XXXX
欢
迎
加
入
湖
1111
68
S2  ABC  ABD
39
2
3-9.+
3
ZD
Problem Solutions – Chapter 3
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
0
1
1
1
1
1
0
0
RL
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
PL  PS
LL = PSLS RS+ PSLS RR
LL  PS LS RS  PS LS RR
RL = PSLS RS + PSRS RR
RL  PS LS RS  PS RS RR
b)
1
1
1
1
C
1
1
1
1 1
1
1
B
A
1
1
1
D
B
A
a
1
1
1
1
1 1
1
1
C
1
南
1
1
入
D
e
C
1
A
A
1
1
1
B
1
D
c
d
C
1 1
B
A
1
1
1
1
D
C
1
1
1
B
1
B
湖
1
A
大
b
a
C
1
学
D
1
考
1
试
C
a)
资
3-12.
A
PL = PS
39
2
PL LL
0 0
LL RL
0 0
0 00
0
0 00
0
0
0 11
0
0 11
0 0
1
0
0 1
1
1 00
0 01
1
1
1 00
1
0 00
1 0
0
0
1 0
0
1 00
0 00
1
0
0
68
RR
0
PL
1
00
01
00
01
0
0
1
00
01
00
11
0
1
1
10
11
1
LS
05
PS LS RS
0 0 0
RS RR
0 0 0
0 0 0 01
0 0 0 11
0 1 1 00
0 1 1 10
0 1 1
0
0
0 1 1
0
1 0 10
1 1 0 00
1 1 0 11
1 0 0 01
1 1 0
0
1
1 1 0
1
1 1 01
1 1 1 11
0
0
PS
料
a)
:
69
a)
群
3-11.
1
1
1
1
1
D
D
f
g
B
加
b)
ab)
= AC + ABD + ABD + ABC
ba=
=AC
AB
++
ACD
+ +ABC
BD
ABD++ACD
AB C
迎
cb=
= AB
AB ++ BC
B C++AD
A C D + ACD
欢
B+ B +
A
C ABC
+ AD+ ABD + ABC + ACD
dc=
= ABCD
BCD ++ACD
A
AB C + A B D + A BC + ACD
ed=
= BCD
D+
+ ABD
ACD + ABC + ACD
fe=
=BC
ABC
f=
AB
C
+
A
BD
++A
BC ++ ACD
ACD
g = ABC + ABC
ABC
g=ABC + ABC + A BC + ACD
c)c)The
following
input
counts
include
input
inverters
and and
shareshare
ANDAND
gates.
The
followinggate
gate
input
counts
include
input
inverters
gates.
Total gate inputs for this solutions = 74. Total gate inputs for book solution is 70. The book solution is better by 4 gate inputs.
Total gate inputs for this solutions = 74. Total gate inputs for book solution is 70. The book solution is better by 4 gate inputs.
4
Problem Solutions – Chapter 3
X
Hierarchy
Y
X
Y
Z
W=XZ + YZ
39
2
3-13.
W
Z
W
W
G = B(CE + DE) + BC
3-14.
H
BC+BD
Hierarchy
3-15.+
BC+BD
c)
c)
Part b requires 6 fewer gates.
Part b requires 6 f ewer gates.
b)
欢
迎
加
入
湖
南
大
学
a)
= ABC + ABD + ABC + ABD
= ABC + ABD + ABC + ABD
试
H
考
X
Y
Z
G = A(BC
BD) + A(BC
+ BD)
G
A(BC+ +BD)+
A(BC
+BD)
资
X
Y
Z
H
料
Hierarchy
群
Hierarchy
X
Y
Z
:
69
X
Y
Z
05
F = A(CE + DE) + AD
Hierarchy
Hierarchy
X
Y
Z
W
68
Hierarchy
X
Y
Z
5
Problem Solutions – Chapter 3
GG
AA
BB
CC
A
B
C
DD
EE
FF
D
E
F
G
A
B
C
DD
EE
FF
D
E
F
b)b)Replacement
with
b) Replacement
withalents
equiv
Replacement
withequiv
equiv
alentsalents
b) Replacement with equivalents
GG
c)c)Cancel
inv
c) Cancel
inv erters
Cancel
inverters
erters
c) Cancel inverters
G
B
C
D
G
E
E
F
F
F
c) Manipulate inv erters
c) Manipulate inv erters
c) Manipulate inv erters
c) Manipulate inv erters
c) Manipulate inverters
G
E
F
F
F
A
A
B
A
BC
BG CD G
GC DE
D
E
E
F
F
F
欢
迎
加
入
湖
F
学
B
C
D
大
B
C
D
A
A
A
B
BC
CD
D
E
E
南
A
考
a) Original
circuit
a) Original
circuit
a) Original circuit
a) Original circuit
a) Original circuit
A
B
C
D
资
G
G
A
A
A
B
BC
CD
D
E
E
试
A
B
C
D
E
F
A
AB
BC
CD
DE
EF
F
料
3-17.
A
B
C
D
E
F
G
群
AA
BB
CC
G
05
a)a)Original
circuit
a) Original
Original
circuitcircuit
a) Original circuit
GG
68
A
B
C
D
E
F
:
69
AA
BB
CC
DD
EE
FF
39
2
3-16.
6
E
G
G
G
G
F
b) Replacement with equiv alents
b) Replacement with equiv alents
b)
Replacement
withequiv
equivalents
b) Replacement with
alents
b)BReplacement with equiv alents
A
C
D
G
G
E
G
F
d) Cancel inv erters
d) Cancel inv erters
d) Cancel inv erters
d) Cancel inverters
d) Cancel inv erters
G
Problem Solutions – Chapter 3
3-18.
:
69
05
68
39
2
a) Using Inverter, 2NAND, 3NAND and 4NAND gates.
试
资
料
群
1) Original circuit using AND, OR, Inverter
考
2) Mapped to Inverter, 2NAND, 3NAND, and 4NAND
欢
迎
加
入
湖
南
大
two literals become available ( AB,BC )
学
b) Using Inverter and 2NAND gates. There is not a one to one correspondence to the above schematics because common terms with only
7
Problem Solutions – Chapter 3
3-19.
群
:
69
05
68
39
2
For original circuit, see 3-18 part (a) above.
a) Mapped to Inverter, 2NOR, 3NOR, and 4NOR
南
大
学
考
试
资
料
b) Mapped to 2NOR and Inverter
3-20.
湖
X
T2
T1
F
T3
欢
加
Y0 = ABCE
Y1 = ABCE
G1
Y 0 = ABCE
Y2 = ABCE
G2A
迎
3-21.
入
Y
G2B
E
=EG1
 G2A
 G2B
= G1
 G2A
 G2B
E
Y 1= ABCE
Y3 = ABCE
Y2
ABCE
Y4
==
ABCE
Y5
==
ABCE
Y3
ABCE
Y6 = ABCE
Y 4 = ABCE
Y7 = ABCE
Y 5 = ABCE
Y 6 = ABCE
Y 7 = ABCE
8
T 1  XY T1 = X Y
T2 = X Y
T 2  XY T3 = X Y
T 3  XY F = XY + X Y
F  XY  XY
Except f or G1 = 1 and G2A and G2B = 0,
Y 0 through Y 7 are all 1’s. Oth
Except forthe
G1 outputs
= 1 and G2A
and G2B =
erwise,
one
of Y7
Y 0are
through
0, the outputs Y0 through
all 1’s. Y 7 is equal to 0
with
all
others
equal
to
Oth-erwise, one of Y0 through Y71.isThe output that is
0 hasequal
index
i =The
decimal v alue of
equal to 0 equal
with alltoothers
to 1.
aluestoof0 has
(A,B,C)
output thatthe
is vequal
indexini binary
= . E.g., if
(A,B,C)
= (1,1,0),
Y 6 = 0.
decimal value
of the
values ofthen
(A,B,C)
in binary. E.g., if (A,B,C) = (1,1,0), then
Y6 = 0.
Problem Solutions – Chapter 3
:
69
05
68
39
2
3-22.
3-23.
试
资
料
群
a)
Treating the input values 1010-1111 as don’t cares changes the behavior for those values:
a  A  C  BD  BD, b  B  CD  CD, c  B  C  D, d  A  CD  BC  BD  BCD,
欢
迎
加
3-24. *
入
湖
The equations in this case are:
南
大
学
考
b)
e  BD  CD, f  A  CD  BC  BD, g  A  BC  BC  CD
a)
b)
VDD
F7
A
G7
F6
A
G6
F5
0
G5
F4
1
G4
F3
A
G3
F2
A
G2
F1
1
G1
F0
1
G0
9
Problem Solutions – Chapter 3
3-25.
a)
b)
F7
2
F
F4
G6
G5
8
G4
F3
G3
1
0
F2
G2
G1
F0
G0
05
F1
3-26.
a)
12
5
4
3
2
1
0
6
G(3:0)
G
F(3:0)
M
考
3-28.
DECODER
A0
A1
A2
0
1
2
3
4
5
6
7
D0
D1
D2
D3
D4
南
大
学
A0
A1
A2
D5
DECODER
A0
A1
A2
D8
0
1
2
3
4
5
6
7
D9
D 10
D 11
D 12
欢
迎
加
入
湖
D6
D7
A3
8
H
L
V
C
试
( S  S  S 2 M
S3  S 4  S 5  M
V = A =  S0  S1 V
 S2 AS
3  S04  S1 5  +
C V
C = V
S5
S4
S3
S2
S1
S0
3:0
资
 S3  S4  S5  M
A =  S 0  S1  S 2  SA3 S( S40 SS51  S+2 M
L

A
L = A
7:4
4
料
3-27.
)
4
群
F
b)
11
9
7
5
3
1
68
F5
:
69
A
G7
3
F6
39
2
VDD
VDD
D 13
D 14
D 15
10
Problem Solutions – Chapter 3
3-29.
DECODER
DECODER
A0
A1
EN
EN
En
0
1
2
3
0
1
2
3
D0
D1
D2
D3
DECODER
A0
A1
A0
A1
En
0
1
2
3
D4
D5
D6
D7
68
A2
A3
A0
A1
39
2
A0
A1
En
0
1
2
3
D8
D9
D10
D11
DECODER
A0
A1
A0
A1
D12
D13
D14
D15
群
En
0
1
2
3
:
69
A0
A1
05
DECODER
A0
A1
欢
迎
加
入
湖
南
大
学
考
试
资
料
3-30.*
11
Problem Solutions – Chapter 3
3-31.
(Errata: Replace “4” with “3” in “4-to-6-line decoder”)
DECODER
A0
A1
0
1
2
3
D0
39
2
A0
A1
D1
DECODER
A2
A0
68
D2
D3
0
1
05
D4
料
群
:
69
D5
a) The Truth Table:
Note: a = g, b = f , and c = e.
Note: a = g, b = f, and c = e.
资
f
d
0
g
0
d
0
0
1
1
1
1
d
1g
1d
10
1
d
1
1
1
1
d
g
d
0
1
1
1
1
1
d
DECODER
学
大
A
X2
Note: a = g, b
XX0
B
A0
A1
A2
X1
X2
d
X2
1
1
1
d
0
1
2
3
4
5
6
=7 f ,
a
g
b
f
c
e
and c = e.
0 C
1
d
2
3
4
5
1
6X
7 2
DECODER
0
X1
1
D
d
B = X1 + X2
C = X1X 2
C
X0
X0
B
Gate input cost: b = 4 compared to a = 27 + 11 = 38
1
d
d
d
1 1
1
1
A
A = XX00
X1
X2
1
d
X1
1
1X+1 X2X 2
BB
=X
X2 1
d
X1
X1
CC
=
X1X
X12X 2
Gate input cost: b = 4 compared to a = 27 + 11 = 38
Gate input cost: b = 4 compared to a = 27 + 11 = 38
12
X0
a
g
d
X0
d
d
X0
A = X0
欢
迎
加
入
湖
b) A = {d}
B = {a,g}
C = {c. e}
D = {b, f}
南
D = {b, f}
A0
A1
A2
X0
X1
X2
考
X 2Truth
X 1 Table:
X0 a b c d e
a) The
0 0 0 d d d d d
X2 X01 X00 1
a 0
b 0c 0
d 1
e 0f
0 0
0 1
0 0
d 1
d 0
d 0
d 0
d 0
d
0 1 1 1 0 0 1 0
0 0 1 0 0 0 1 0 0
1 0 0 1 1 0 0 0
0 1
1 0
0 1
1 1
0 1
0 0
0 1
0 0
0
a)
0 The
1 1
0 1
0 1 0 1
0
1 Truth
1 Table:
0
1X 2 1
0X 1 1
0X 0 1
1a d
1b d
0c d
0d d
0e d
1f
10 00 10 1d 1d 0d 1d 0d 1d
b) A = {d}
X
1 10 10 A
1 0 1 0B =0{a,g}
1 0 0 1 01 0 1 0
0 1C = {c.
0 e} 1 0 0 d 01 0 0
1 1 D =1{b, f}d d d d d d
0 1 1 1 0 0 1 0 0
1 0 0 1 1 0 01 0 1
b) 1A =0{d}1 1 1 0 1 d 0X 1 1
1B =1{a,g}
0 1 1X 2 1 0 1 1
C
=
{c.e}
1 1 1 d d d d1 d d
试
3-32.
X2
b
f
c
e1
d
d1
1
X1
D = X2
X0
D
d
X2 1 d
1
1
DD = X
X22
X1
Problem Solutions – Chapter 3
A0
D0
A1
:
69
D4
D5
D6
D7
群
EN
料
3-34.
K-Map for GE5: BCD = (C3,C2, C1, C0)
1
d
1
1
d
d
试
1
d
C2
考
C3
1
资
C1
d
C0
C2
GE5
C3
欢
迎
加
入
湖
南
Equations for output logic:
P0 = D0 + GE5·D1
P1 = D2 + GE5·D1
P2 = D3 + GE5·D4
P3 = D5 + GE5·D4
P4 = D6 + GE5·D7
P5 = D8 + GE5·D7
P6 = D9 + GE5·D10
P7 = D11 + GE5·D10
P8 = D12+ GE5·D13
P9 = D14 + D15 + GE5·D13
大
C1
C0
学
GE5 = C3 + C2 (C1 + C0)
05
D3
A2
68
D1
D2
d
39
2
3-33.
13
Problem Solutions – Chapter 3
X
X
1
A1
D0
X0
01
0
0
0
10
A
A 10
XX
00
0
1
1
10
V
A0
X0
01
1
1
0
11
D1
A1
V
0
1
1
1
1
D0
D1
X
1
D3
D2
1
1
D0
0
V
= 0D 0 +0 D1 1+ D 21+ D13
V A
D00 = DD
D32 
1 
0 D21+D
D2
A0
V
A0
D3
D3
D1
1
1
X
A0 AD
1 0 (=D1D0 D 12
A1  D0 D1
A1
68
X
D D
D3 1D2 D0 1
0 0 0 0 00
X X X X 1X
X X 1
X 1
0
X 1 0
1 1 0 0 00
1
1
1
D2
群
D0
05
0
D2
:
69
D3
39
2
3-35.*
料
3-36.
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
X
0
0
0
1
3-37.
入
a)
A3
A2
A1
A0
V
0
X
X
X
X
0
0
1
0
0
0
0
1
0
1
X
0
0
0
1
1
0
1
X
X
0
0
1
0
1
1
X
X
X
0
0
1
1
1
1
X
X
X
X
0
1
0
0
1
X
X
X
X
X
0
1
0
1
1
X
X
X
X
X
0
1
1
0
1
大
0
学
考
0
1
X
X
X
X
X
X
X
0
1
1
1
1
X
X
X
X
X
X
X
X
1
0
0
0
1
X
X
X
X
X
X
X
1
0
0
1
1
S2
S
0
1
南
X
1
X
湖
1
0
试
9
Binary Outputs
资
Decimal Inputs
b)
DECODER
欢
迎
加
S0
S1
S2
A0
A1
A2
0
1
2
3
4
5
6
7
I0
4x1 MUX
S0
S1
I0
I1
I2
I3
I1
I2
I3
S0
S1
0
1
2
3
Y
Y
4x1 MUX
I4
S0
S1
I4
I5
I6
I7
I5
I6
S0
S1
0
1
2
3
2x1 MUX
Y
Y
Y
I7
14
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently
exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
Problem Solutions – Chapter 3
3-39.
试
资
T
a his
th nd wo
o eir is rk
w r sa co pro is
ill le u vi pr
de o rse de ot
st f a s d s ec
ro n an o te
y y p d le d
th a a ly by
e rt ss fo U
in o e r
te f t ss th nite
gr hi in e
ity s w g us d S
of or stu e o tat
th k ( de f i es
e in nt ns co
w cl le tr p
or ud a uc y
r
k
an ing rnin tors igh
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is
w
D
no the iss tea s
t p W em ch
er or in ing
m ld a
itt W tio
ed id n
.
e
W
eb
)
料
群
:
69
05
68
39
2
3-38.
0
1
2
3
4
5
6
7
欢
迎
加
入
湖
南
大
学
A0
A1
A2
考
DECODER
S0
S1
S2
IA0
IA1
IA2
IA3
YA
IA4
IA5
IA6
IA7
IB0
IB1
IB2
IB3
YB
IB4
IB5
IB6
IB7
15
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently
exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.
Problem Solutions – Chapter 3
料
群
:
69
05
68
39
2
3-40.
欢
迎
3-42.*
加
入
湖
南
大
学
考
试
资
3-41.
8x1 MUX
D(7:0)
D(7:0) Y
0
A(2:0)
S(2:0)
8x1 MUX
D(14:8)
D(6:0) Y
0
D(7)
S(2:0)
A(3)
3 OR gates
16
Problem Solutions – Chapter 3
D0
D1
D2
D3
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
0
0
0
1
0
1
0
0
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
Consider E as the data input and A0, A1 as the
select lines. For a given combination on (A1,
A0), the value of E is distributed to the
corre-sponding D output. For example for
(A1, A0) = (10), the value of E appears on D2,
while all other outputs have value 0.
68
E
0
05
A0
0
3-44.
DECODER
0
1
2
3
4
5
6
7
F1
F2
群
A0
A1
A2
F3
料
X
Y
Z
a) LR = LT·BL + LT·BR + EM·BL = BL·(LT + EM) + LT·BR
RR = R
+ RT·BR
+ EM·BL
= BR·(R
+ EM)
+ RT·BR
a) LR  LT·BL
T·BL
LT·BR
 EM·BL
 BL·(LT
TEM)
 LT·BR
0
0
0
1
1
1
1
1
1
1
1
1
1
0
10
01
10
0
1
1
0
1
1
0
0
1
1
1
1
考
LR
For For
RR, RR,
samesame
circuit
with L
Twith
replace
by RT. by RT.
circuit
LT replace
欢
迎
1
11
00
11
0
1
1
01
大
0
南
0
0
0
1
1
0
1
1
1
0
1
0
1
0
1
0
1
湖
0
0
LR
10
0
0
1
01
入
0
0
BR0 BL
0
0
00
0 1
0
1
0 1
1 1 00
1 1 10
0 1 01
0 1 11
0 0
1
0
0 0
1 0 11
0 0 01
0 1 10
1 1 00
1 1
1
1
1 1
0
0
加
0
EM 0
0 0
0
0
0
0 0
0 0
1 0
1 0
1
1
1
1 1
0 1
0 1
0 1
1
0
1
1
学
b) Maximum
of four inputs on OR gates assumed.
LT EM BR BL LR
试
RR b)RT·BL+RT·BR
 EM·BL
 EM)
 RT·BR
Maximum of four
inputsonBR·(RT
ORgates
assumed.
资
3-45.
LT
:
69
A1
39
2
3-43.*
17
Problem Solutions – Chapter 3
F
F
0
0
00
11
0
0
1
01
10
0
1
0
10
10
1
1
0
01
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
C
B
A
F0
F=0
FF=DD
D
VDD
F =D
FD
F =D
FD
F=D
FF = D
1
F=0
F 1
01
F
=D
1
D0
D1
D2
D3
D4
D5
D6
D7
Y
F
F0
FD
资
0
8 x 1 MUX
S0
S1
S2
68
D
C D
0
0 0
011
100
1 1
1
0 0
001
110
1 1
0
0 0
011
100
1 1
1
0 0
001
110
1 1
0
05
C
B
0
0
00
10
0
1
1
01
01
1
1
0
10
00
0
0
1
11
11
1
0
:
69
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
群
B
料
A
39
2
3-46.
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
试
0
0
F
0
1
F=D
0F  D
1
1
0
F=C D
0
0
F0  CD
0
F=C D
0
1
1
F1  CD
F=1
1
1
C
D
考
0
AC B D C FD
00 0 0 0 00
0 0 0 1
0
1
1
0 0 1 0
1
0
0 0 1 01
01 1 1 0 10
0 1 0 1
0
0
1
0 1 1 0
0
1
0 1 1 01
11 0 0 0 00
11 0 1 0 01
1 0 1 0
0
0
0
1 0 1 1
10 1 1 0 00
11 1 0 0 01
1 1 1 0
1
1
1
1 1 1 1
0
0
1
B
A
VDD
F 1
欢
迎
加
南
大
学
B
入
A
湖
3-47.*
18
4 x 1 MUX
S0
S1
D0
D1
D2
D3
Y
F
Problem Solutions – Chapter 3
39
2
3-48.
DECODER
A
0
1
2
3
4
5
6
7
A0
A1
A2
EN
F
DECODER
EN
05
0
1
2
3
4
5
6
7
A0
A1
A2
:
69
D
C
B
68
D
C
B
群
3-49.
C1  C0 A0  A0 B0  C0 B0
S1  C1 A1 B1  C1 A1 B1  C1 A1B1  C1 A1B1
C2  C1 A1  A1B1  C1B1
S1  C0 A0 A1 B1  A0 B0 A1 B1  C0 B0 A1 B1
C2  C0 A0 A1  A0 B0 A1  C0 B0 A1
C0 A0 A1B1  A0 B0 A1B1  C0 B0 A1B1
试
C0 A0 A1B1  A0 B0 A1B1  C0 B0 A1B1
C0 A0 B1  A0 B0 B1  C0 B0 B1  A1B1
资
 C0 A0 A1 B1  A0 B0 A1 B1  C0 B0 A1 B1
料
S0  C0 A0 B0  C0 A0 B0  C0 A0 B0  C0 A0 B0
考
* These are the three equations for the outputs. The logic diagram consists of a sum-of-products implementation of these equations.
学
3-50.*
C1  A0 B0  A0C0  B0C0
大
C1  T3  T2  T1C0  T2  A0 B0 C0  A0  B0  ( A0  B0 )C0  A0 B0  ( A0 B0  C0 )( A0  B0 )
S0  C0  T4  C0  TT
1 2  C0  A0 B0 ( A0  B0 )  C0  ( A0  B0 )( A0  B0 )  C0  A0 B0  A0 B0
湖
南
S0  A0  B0  C0
T3
入
T1
T4
迎
加
T2
欢
3-51.*
Unsigned
1’s Complement
2’s Complement
1001 1100
0110 0011
0110 0100
1001 1101
0110 0010
0110 0011
19
1010 1000
0101 0111
0101 1000
0000 0000
1111 1111
0000 0000
1000 0000
0111 1111
1000 0000
Problem Solutions – Chapter 3
3-52.
11010
+ 01111
01001
b)
11010
b)
11110
+ 10010
10000
c)
1111110
+ 0000010
0000000
d)
11110
c)
1111110
+ 0000010
0000000
d)
101001
+ 111011
100100
39
2
a)
+ 01111
+ 00010
01001
00000
+36 = 0100100
- 24 = 1101000
36
+(–24)
+
= 12
=
0100100
1101000
10001100
0001100
料
+
=
3-55.
+
11
-26
-15
学
3-56.+
湖
Cin
0
1
0
1
S
0
1
1
0
Cout
0
1
1
1
S  Bit  Cin
Cout  Bit  Cin
欢
迎
加
入
Bit
0
0
1
1
南
大
a) H  D
G C D
F  BC  BD  BCD
E  AB  ABCD  AC  AD
b)
1110101
c)
0010011
100110
110001
试
-25
-7
-32
考
+
b)
100111
111001
100000
1011101
0011000
资
= –11
a)
群
- 35 = 1011101
–35
- (–24)
101100
:
69
3-54.*
101001
+ 000011
+
05
a)
68
3-53.
d)
110001 -15
101110 -18
011111 -33
Overflow
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
101110
001001
110111
+
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
E
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
-18
9
-9
F
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
G
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
c) Using shared inverters, XOR cost = 6. Gate input cost for a = 4 + 0 + 6 + 10 + 14 = 34 Gate input cost for
b = 4 x (2 + 6 + 2) = 40 In terms of gate cost, a is the better design.
20
H
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Problem Solutions – Chapter 3
3-57.
A2
A1
A0
C4
S3
05
68
39
2
A3
S1
S2
B0  1
:
69
3-58.
S0
Cin  0
S0  A0  1  0  A0
C0  A0  1  0( A0  1) A0
群
B1  S
B2  S
B
A
Cout FA Cin
S
B
A
C out FA Cin
S
S6
S5
S7
A3
S
A2
B
A
Cout FA Cin
S
B
A
Cout FA Cin
S
B
A
Cout FA C in
S
S4
S3
S2
大
3-59.
A4
考
A
FA Cin
S
A5
学
B
A6
试
A7
资
料
B3 7  S
Bits 1-6 use regular full adder/subtractor logic. For bit 7, the carry logic is omitted.
A1
A0
B
A
Cout FA Cin
S
S1
S0
Proceeding from MSB to LSB: A  B if Ai  Bi ( Ai Bi  1) and for all j  i, Aj  B j ( Aj B j  Aj B j  1) Based on the above,
南
X  A3 B3  ( A3 B3  A3 B3 ) A2 B2  ( A3 B3  A3 B3 )( A2 B2  A2 B2 ) A1B1
欢
迎
加
入
湖
( A3 B3  A3 B3 )( A2 B2  A2 B2 )( A1B1  A1B1 ) A0 B0
21
Problem Solutions – Chapter 3
3-60.+
A
B
Cin
Cin
A3
B3
C4
A2
B2
C3
A1
B1
C2
05
X
Cout
68
Cout
A0
B0
Logic 0
C1
+
:
69
B
39
2
A
3-61.
Bi
Ai
Bri+1
Bri
B2
A2
B1
A1
试
A3
Bi
Ai
Bri+1
Bri
Bi
A0
B0
Ai
Bri+1
Bri
考
X
B3
资
料
群
In a subtractor, the sum is replaced by the difference and the carry is replaced by the borrow. The borrow at
A B
given point
is asum
1 onlyisifreplaced
in the LSB
thatthe
point,
Inany
a subtractor
, the
bydirection
the
f erence
dif fromand
carry
is. replaced by the .borrow
Only
borrow
logic
is
needed
to
produce
X,
so
the
difference
logic
is
discarded
The remaining
The borrow at any given point is a 1 only if in the LSB direction from that point,in
A <contraction.
B.
equation for borrow into the i + 1 position is: Bri 1  Ai Bi  Ai Bri  Bi Bri for i = 0,1,2,3. Br0  0 giving
Only borrow logic is needed to produce X, so the diff erence logic is discarded in contrac
 B.i +Thus,
Br1  A0remaining
B0 When the
borrowforBrborrow
X = Bris:
using
tion.The
equation
intoAthe
1 position
Br
Ai Bi + Acircuit
4. The
i+ 1 =resulting
i Bri +B
i Bri the borrow logic
4  1, then
for
i
=
0,1,2,3.
Br
=
0
giving
Br
=
A
B
When
the
borrow
Br
=
1,
then
A
<
B.
Thus,
0
is:
4
0
1
0
X = Br 4 . The resulting circuit using the borrow logic is:
学
3-62.+
南
大
This problem requires two decisions: Is A > B? Is A = B? Two “carry” lines are required to build an iterative
circuit, Gi and Ei. These carries are assumed to pass through the circuit from right to left with G0 = 0 and E0 = 1.
Each cell has inputs Ai, Bi, Gi, and Ei and outputs Gi+1 and Ei+1. Using K-maps, cell equations are:
Ei 1  Ai Bi Ei  Ai Bi Ei
湖
Gi 1  Ai Bi Ei  ( Ai  Bi ) Ei
Using multilevel circuit techniques, the cost can be reduced by sharing terms:
B3
E4
G4
Ei+1 Bi
Gi+1
A3
B2
Ai E
Gi
Ei+1 Bi
Gi+1
欢
迎
加
入
Ei 1  ( Ai Bi  Ai Bi ) Ei
Ei+1 = (Ai Bi + Ai Bi ) Ei
Gi 1  ( Ai Bi  ( Ai Bi )Gi
Gi+1 = (Ai Bi + (Ai Bi ) Gi
22
A2
B1
Ai E
i
Gi
Ei+1 Bi
Gi+1
A1
B0
Ai Ei
Gi
Ei+1 Bi
Gi+1
A0
Ai Ei
Gi
E0 = 1
G0 = 0
Problem Solutions – Chapter 3
39
2
3-63.+
Circuit Diagram:
4-bit Adder
S3 S2 S1 S0
Control Logic
ResultCorrection
SignA
Sub
Corr
Cout
Sign
Cin
2’s Complementer
S4 S3 S2 S1 S0
S/ASignA
 SignA
SignB
Sub Sub
= S/
A 
 
SignB
Sub Cout
Corr Corr
= SubCout
 SignA
 Corr
Sign Sign
= SignA
 Corr
群
Control Logic
Truth Tables
Control
Logic Truth Tables
Overflow
Cout
Sub Cout
Overflow
= Sub
试
资
料
Inputs
Inputs Inputs
Over
SignB
Sub
Sub
SignA
Cout
Corr
Sign
Overflow
S/A SignA SignB Sub Sub SignA Cout Corr Sign
flow0
0
0
0
0
0
0
0
1
00
00
0
01
0 0 0
01 0 0 0
01
0
10
10
0
01
1 0 1
00 1 0 0
10
1
10
11
0
10
0 0 1
11 0 0 0
01
0
00
11
0
11
1 1 0
10 1 1 0
10
1
01
01
1
00
0 1 1
01 0 0 1
00
0
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
1
0
1
0
1
1
0
0
1
1
0
1
0
0
1
1
1
1
1
1
1
0
1
0
考
Inputs
Sign A
0
0
1
1
0
0
1
1
0
3-64.*
A
0111
0100
1101
0111
0001
学
S
0
1
1
0
1
B
0111
0111
1010
1010
1000
C4
0
0
1
1
0
欢
迎
加
入
湖
南
大
a)
b)
c)
d)
e)
68
2’s Complementer
Cout
S/A
0
0
0
0
1
1
1
1
Adder/Subtractor
05
S/A
B3 B2 B1 B0
:
69
A4
B4
A 3 A2 A1 A 0
Control Logic
Add/Subtract
SignA
Sub
SignB
Sub/Add
23
S3
1
1
0
0
1
S2
1
1
0
0
0
S1
1
0
1
0
0
S0
0
1
1
1
1
Problem Solutions – Chapter 3
欢
迎
加
入
湖
南
大
学
考
试
资
料
群
68
05
:
69
-- Full Adder: Structural VHDL Description
-- (See Figure 4-28 for logic diagram)
library ieee, lcdf_vhdl;
use ieee.std_logic_1164.all, lcdf_vhdl.func_prims.all; --X is input vector (A0, B0, C0).
entity full_adder_st is
port(X: in std_logic_vector(0 to 2);
C1, S0: out std_logic);
end;
architecture logic of full_adder_st is
component NOT1
port(in1: in std_logic;
out1: out std_logic);
end component;
component NAND2
port(in1, in2: in std_logic;
out1: out std_logic);
end component;
component NOR2
port(in1, in2: in std_logic;
out1: out std_logic);
end component;
component AND2
port(in1, in2: in std_logic;
out1: out std_logic);
end component;
component XOR2
port(in1, in2: in std_logic;
out1: out std_logic);
end component;
signal S: std_logic_vector(0 to 6); -- S(0 to 6) is the vector of six gate output signals
-- from upper left to lower right.
--The following is the circuit netlist.
begin
g0: NAND2 port map (X(1), X(0), S(0));
g1: NOR2 port map (X(1), X(0), S(1));
g2: NOT1 port map (X(2), S(2));
g3: AND2 port map (S(0), S(2), S(3));
g4: NOT1 port map (S(1), S(4));
g5: NOT1 port map (S(2), S(5));
g6: AND2 port map (S(0), S(4), S(6));
g7: NOR2 port map (S(1), S(3), Z(1));
g8: XOR2 port map (S(6), S(5), Z(0));
end logic;
39
2
3-65.
24
Problem Solutions – Chapter 3
群
:
69
05
68
39
2
3-66.
料
The solution
is very
thorough
it checks
each
of the carry
connections
between
adjacentbetween
cells transferring
Thegiven
solution
giv en
is v erysince
thorough
since
it checks
each
of the carry
connections
adjacent 0cells
0 and
1. In contrast
testAapplying
C0 B
= 1=and
A = 15allow
with B
0 would
allowofa incorrect
whole connections
and 1. In transferring
contrast a test
applying
C0 = 1aand
= 15 with
0 would
a=
whole
variety
variety
of would
incorrect
between cells
that
notconnections
be detected.between cells that would not be detected.
南
大
学
考
试
资
3-67.*
欢
迎
加
入
湖
The solution given is very thorough since it checks each of the carry connections between adjacent cells transferring 0
and 1. In contrast a test applying C0 = 1 and A = 15 with B = 0 would allow a whole variety of incorrect connections
between cells that would not be detected.
25
Problem Solutions – Chapter 3
欢
迎
68
05
:
69
加
入
湖
南
大
学
考
试
资
料
群
-- prob_4-30 adder-subtractor with overflow detection
library ieee;
use ieee.std_logic_1164.all, ieee.std_logic_unsigned.all;
entity addsubov is
port(A,B: in std_logic_vector(3 downto 0);
S: in std_logic;
SD: out std_logic_vector(3 downto 0);
C, V: out std_logic);
end addsubov;
architecture behavior of addsubov is
signal Y: std_logic_vector(3 downto 0);
signal temp4: std_logic_vector(3 downto 0);
signal temp2: std_logic_vector(4 downto 3);
signal CI: std_logic_vector(4 downto 3);
begin
with S select
Y(2 downto 0) <= B(2 downto 0) when '0',
not B(2 downto 0) when '1',
"XXX" when others;
with S select
Y(3) <= B(3) when '0',
not B(3) when '1',
'X' when others;
temp4 <= ('0' & A(2 downto 0)) + ('0' & Y(2 downto 0)) + ("000" & S);
CI(3) <= temp4(3);
temp2 <= ('0' & A(3)) + ('0' & Y(3)) + ('0' & CI(3));
CI(4) <= temp2(4);
SD <= (temp2(3) & temp4(2 downto 0));
C <= CI(4);
V <= CI(4) xor CI (3);
end behavior;
39
2
3-68.+
The solution given is very thorough since it checks each of the carry connections between adjacent cellstransferring 0 and 1.
In contrast a test applying C0 = 1 and A = 15 with B = 0 would allow a whole variety of incorrect connections between cells
that would not be detected.
26
Problem Solutions – Chapter 3
3-69.
学
考
试
资
料
群
:
69
05
68
39
2
// Full Adder: Structural Verilog Description
// (See Figure 4-28 for logic diagram)
module full_adder_st(C1, S0, X);
input [2:0] X; //X is the vector of inputs (A0, B0, C0).
output C1, S0;
wire [0:6] N; //N[0:6] is the six bit vector of gate
//outputs from upper left to lower right.
//The netlist for the gate types:
nand
gna(N[0],X[1],X[0]);
nor
gno1(N[1],X[1],X[0]),
gno2(C1,N[1],N[3]);
not
gn0(N[2], X[2]),
gn1(N[4], N[1]),
gn2(N[5], N[2]);
and
ga0(N[3], N[0], N[2]),
ga1(N[6], N[0], N[4]);
xor
gx(S0, N[5], N[6]);
endmodule
欢
迎
加
入
湖
南
大
3-70.
27
Problem Solutions – Chapter 3
:
69
05
68
39
2
3-71.*
料
群
The solution given is very thorough since it checks each of the carry connections between adjacent cellstransferring 0
and 1. In contrast a test applying C0 = 1 and A = 15 with B = 0 would allow a whole variety of incorrect connections
between cells that would not be detected.
3-72.
试
考
欢
迎
加
入
湖
南
大
学
assign {C4, SD} = S?(A - B):(A + B);
endmodule
资
// Adder-Subtractor Behavioral Model
module addsub_4b_v (S, A, B, SD, C4);
input[3:0] A, B;
input S;
output[3:0] SD;
output C4;
28
Problem Solutions – Chapter 4
CHAPTER 4
39
2
© 2016 Pearson Education, Inc.
:
69
05
68
4-1.
试
资
料
群
4-2.
南
大
学
考
4-3.
欢
迎
加
入
湖
4-4.
1
Problem Solutions – Chapter 4
Y
39
2
4-5.
A
D
Z
B
D
68
Clock C
Output
B
Y
A
B
Z
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
S0
1
0
S3
0
1
1
0
1
S1
0
1
1/1
考
d) This machine is a Moore machine.
大
学
4-6.
南
X
A
Clock C
D
Clock C
欢
迎
加
入
湖
Y
D
2
B
X
0
1
S2
0
试
资
A
:
69
Input
S0 - 00
S1 - 01
S2 - 10
S3 - 11
群
Next
state
料
Present
state
05
Clock C
Z
Problem Solutions – Chapter 4
B
X
Y
A
B
Z
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
0
0
0
1
0
1
1
1
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
X1/0, 1X/0
1X/0
00 /0
01/1
S2
1X/0
S3
00 /0
00/1, 1X/0
料
Inputs
Inputs
X
Y
0 X0 Y
0
1
1 00 0
1
1
0 00 1
0 11 0
1 10 1
1 01 0
0
1
1
0
1
1
迎
加
Present state
Present state
Q
0 Q
0
0 0
0 0
1
1 0
1 0
1 1
1
1
1
Next state
Next state
Q
0 Q
1
1 0
0
1 1
0 1
0 0
1 1
0
0
1
试
100
001
考
0
00
00
00
1
10
11
11
01
0
01
00
10
10
1
10
1
1
1
1
资
000
CC
110
010
011
111
101
X=1
学
AA BB
1
0
01 00
00 00
10 00
0
0
11 00
10 00
01 00
11 10
0
1
00 10
11 11
00 11
10 11
1
1
01 11
0
1
1
1
1
1
0
1
X=0
大
XX
0
10
01
10
0
11
00
11
00
1
01
10
01
10
0
11
0
1
0
1
Next
state
Next
state
湖
C
C
0
00
01
11
0
10
01
01
10
0
11
01
00
10
1
11
0
0
1
1
入
B
B
0
00
00
00
1
01
11
11
10
0
10
00
01
01
1
01
1
1
1
1
Input
Input
南
Present
state
Present state
欢
00 /1
01/0
4-7.*
4-8.
S1
S0
d) This machine is a Mealy machine.
A
A
0
00
00
00
0
00
00
00
01
1
01
11
11
11
1
11
1
1
1
1
01/1
群
A
39
2
Output
68
Inputs
S0 - 00
S1 - 01
S2 - 10
S3 - 11
Format: XY/Z (X = unspecified)
05
Next
state
:
69
Present
state
001
100
010
101
000
011
111
110
Statediagram
diagram is
is the
of of
thethe
above
two two
diagrams.
State
the combination
combination
above
diagrams.
01/1, 10/1
Output
Output
S
0 S
0
0 0
0
1 0
1 0
1 0
1 1
1
1
1
00/1, 11/1
00/0, 11/0
1
0
01/0, 10/0
Format: XY /S
3
Problem Solutions – Chapter 4
00
01
00
00
01
11
00
01
11
10
10
Input
1
0
0
1
1
0
1
1
1
1
0
Output
0
1
0
0
0
1
0
0
0
0
1
Next State
01
00
00
01
11
00
01
11
10
10
00
68
Present State
39
2
4-9.
01/0
10/1
11/0
05
4-10.
:
69
00/1
1
0
00/0
01/1
10/0
11/1 01/0
01/1, 10/0
10/1
3
群
00/0
2
11/1
11 /0
料
00/1
资
Format: XY/Z
DA  B
SA = B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
0
0
1
1
0
0
1
1
考
B
学
B
南
0
0
0
0
1
1
1
1
Next state
A
B
0
0
1
1
0
0
1
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
Output
1/1
0/0
Y
0
1
1
0
1
0
0
1
加
迎
欢
4
0
1
1
0
1
0
0
1
1
0
Output Y
入
0
0
0
0
1
1
1
1
Input X
湖
A
X  state
A
Input R B = Next
大
RA = B
Present state
Present
A state B
DB =X  A
SB = X  A
试
4-11.
1/0
0/1
0/1
1/0
2
3
0/0
Format: X/Y
1/1
Problem Solutions – Chapter 4
4-12.
a)
:
69
05
68
39
2
Vdd
群
Vdd
X
料
b)
A
D
C
资
A
试
Reset
考
D
B
C
B
学
Clock
南
大
Y
湖
4-13.*
Present
Present state Input Input
state
A
B
X
欢
迎
加
0
0
0
0
1
1
1
1
0B
0
0
0
0
0
1
1
1
10
10
11
1
入
A
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DA
Next state
Next
state
A
B
A
0
1
0
0
1
1
1
0
0B
1
00
00
1
1
0
1
0
11
01
DB
B
B
1
1
A 1
0
0
1
0
0
1
1
1
1
1
1
A
5
1
X
X
D  AX  BX
DAA = AX + BX
DB  AX  BX
DB = AX + BX
Logic diagram not given.
Logic diagram not giv en.
1
1
Problem Solutions – Chapter 4
4-14.
欢
迎
加
入
湖
南
大
学
考
试
资
料
群
:
69
05
68
39
2
For part a) results, replace codes in table below with state name, e.g., 00 with A.
6
Problem Solutions – Chapter 4
d)
A
X1
B
X1
S
A
X1
X2
A
X1
X2
D
X1
X2
D
X1
X2
D
X1
X2
D
X1
X2
C
X2
D
X2
D
X1
B
群
料
资
C
试
C
X1
欢
迎
加
入
湖
南
大
学
考
B
X1
7
68
C
X1
39
2
A
X1
X2
05
X2
A
X1
X2
A
X1
X2
:
69
X1
D
Problem Solutions – Chapter 4
加
入
湖
南
大
学
考
试
资
料
群
:
69
05
68
39
2
4-15.
d) Using equations for the circuit rather than a schematic:
DB  AX
DC  BX  DX  E X  BX DX E X
DD  AX  B X  AX B X
DE  EX  F X  EX F X
DF  CX  DX  FX  CX DX FX
欢
迎
DA  CX
Z  D  E  F  DEF
To enter state A on reset, flip-flop A should have its set input S connected to Reset and flip-flops B-F should have their reset
inputs R connected to Reset.
8
.
Problem Solutions – Chapter 4
欢
迎
加
入
湖
南
大
学
考
试
资
料
群
:
69
05
68
39
2
4-16.
9
Problem Solutions – Chapter 4
欢
迎
加
入
湖
南
大
学
考
试
资
料
群
:
69
05
68
39
2
4-17.
10
Problem Solutions – Chapter 4
4-18.*
Q(t)
X
YQ(t)
Q(t+1)X
Y
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
10/1
0
0
0
0
1
1
1
1
考
试
资
// state register: implements positive edge-triggered
// state storage with asynchronous reset.
always @(posedge CLK or posedge RESET)
begin
if (RESET)
state <= state0;
else
state <= next_state;
end
料
// Serial 2s complementer: Verilog Process Description
// problem 4-18 c, 5th edition
module serial_2s_complementer(CLK, RESET, X, Y, Z);
input CLK, RESET, X, Y;
output Z;
reg state, next_state;
parameter state0 = 1'b0, state1 = 1'b1;
reg Z;
群
c)
南
大
学
// next state function: implements next state as function
// of X, Y and state
always @(X, Y or state)
begin
case (state)
state0: next_state = ({X,Y} == 2'b10) ? state1: state0;
state1: next_state = Y ? state0 : state1;
endcase
end
欢
迎
加
入
湖
// output function: implements output as function
// of X, Y, and state
always @(X or Y or state)
begin
case (state)
state0:
case ({X,Y})
2'b00: Z = 1'b0;
2'b10: Z = 1'b1;
default: Z = 1'bx;
endcase
state1:
case ({X,Y})
2'b00: Z = 1'b1;
2'b10: Z = 1'b0;
default: Z = 1'bx;
endcase
endcase
end
endmodule
11
0
0
1
0
1
0
1
0
Output
Next state
39
2
00/1
10/0
Next
state
Inputs
ZQ(t+1)
0
X
1
X
1
X
0
X
0
0
1
0
1
0
1
0
68
00/0
x1/x
Inputs
Present state
05
x1/x
Present
state
:
69
Format: XY /Z (x = unspecif ied)
Format: XY/Z (x = unspecified)
Output
Z
0
X
1
X
1
X
0
X
Problem Solutions – Chapter 4
Present
state
X
Y
Q(t+1)
Z
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
X
0
X
0
X
1
X
00/0
1
0
10/0
考
试
资
// state register: implements positive edge-triggered
// state storage with asynchronous reset.
always @(posedge CLK or posedge RESET)
begin
if (RESET)
state <= state0;
else
state <= next_state;
end
料
// Serial odd parity generator: Verilog Process Description
// problem 4-19 c, 5th edition
module serial_odd_parity_generator (CLK, RESET, X, Y, Z);
input CLK, RESET, X, Y;
output Z;
reg state, next_state;
parameter state0 = 1'b0, state1 = 1'b1;
reg Z;
南
大
学
// next state function: implements next state as function
// of X, Y and state
always @(X, Y or state)
begin
case (state)
state0: next_state = ({X,Y} == 2'b10) ? state1: state0;
state1: next_state = ({X,Y} == 2'b00) ? state1: state0;
endcase
end
欢
迎
加
入
湖
// output function: implements output as function
// of X, Y, and state
always @(X or Y or state)
begin
case (state)
state0:
case ({X,Y})
2'b00: Z = 1'b1;
2'b10: Z = 1'b0;
default: Z = 1'bx;
endcase
state1:
case ({X,Y})
2'b00: Z = 1'b0;
2'b10: Z = 1'b1;
default: Z = 1'bx;
endcase
endcase
end
endmodule
12
群
c)
68
00/1
x1/x
Q(t)
05
10/1
x1/x
Output
:
69
Format: XY/Z (x = unspecified)
Next
state
Inputs
39
2
4-19.
Problem Solutions – Chapter 4
4-20.
1/0
2/0
4/0
3/0
6/0
5/0
7/1
E=1
0
0
0
0
0
0
0
1
68
05
001
D2D1 D0
010
000 011
001 100
010
011 101
100 110
101 111
110
111
0
0
0
0
0
1
:
69
Present state
000
E=0
E=1
Next State
For Input
001
001
E=0 010 E=1 010
011
011
001 100 001 100
010
010
011 101 011 101
100 110 100 110
101 111 101 111
110 111 110 000
111
111
111
000
群
D2D1D0
The state assignment could be different. E. g.,
state 7 could be 000 with state 0 001. This would
permit use of R inputs on the D flip-flops for
RESET.
Z
The state assignment could be
f erent.
dif
E.
g.,
state
7
could
be
000
with
state 0
Output
0 001. This would permit use of R inputs
Z 0 on the D f lip-f lops f or RESET
.
Output
料
Next State
For Input
Present state
资
D0
E
试
D1
考
Z
欢
迎
加
入
湖
南
CLK
大
学
D2
39
2
E=0
0/0
13
Problem Solutions – Chapter 4
4-21.
1/1
2/1
4/1
3/1
6/1
5/1
7/0
E=1
Z
001
010
011
100
101
110
111
111
0
1
1
1
1
1
1
0
001
Z 010
011
100
0 101
1 110
111
1 000
1
1
1
1
0
05
E=0
OutputE=1
资
料
000
001
010
011
100
101
110
111
Output
Assumes
for E = 0, the output remains at 0.
:
69
000
E=0 001E=1
010
011
001 100 001
010 101 010
011 110
111 011
100
100
101
101
110
110
111
111
111
000
D2D1D0
Next State
For Input
群
Present
state
Present state
Next State
D2D
For
Input
1 D0
CLK
欢
迎
加
入
湖
南
大
学
考
试
E
14
68
Assumes f or E = 0, the output remains
at 0.
39
2
E=0
0/0
Z
Problem Solutions – Chapter 4
4-22. +
X=0/
Z=0,S=0
C
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
X=1/
Z=1,S=0
X=1/Z=1,S=0
A
0X
0
0
00
01
0
00
01
10
11
1
10
1
0
1
0
1
3
B
0
0
0
0
1
1
1
1
0
0
0
0
C
A0
0
1
01
00
0
01
01
00
00
1
01
1
0
1
0
0
Next
state
Output
A
0
0
0
0
0
0
0
1
0
1
0
0
料
4
B
2
X=0/
Z=0,S=0
X=1/
Z=1,S=0
A
Next
Input
state
X
B
0C
1
0
1 0
0 1
0
1
0
0 0
0
1 0
0 0
1
1 1
0
0
1
1 0
0
0
0
0
0
1
0
0
0
Z
试
资
X
B
Z0
0
0
0 1
1 0
1
0 0
1 0
0 0
1 0
0
0 0
1
0
1
0
0
大
学
考
S
CLK
X=1 / Z=0
X=0 / Z=0
4-23.
0
1
南
X=1 / Z=1
Present
state
X=0 / Z=1
X=1 / Z=1
X=1 / Z=0
X=0 / Z=0
湖
A
0Present
0 state
1
1 A
1
入
0
X=0 / Z=1
迎
加
0
0
1
1
CLK
欢
Z
R
CLK
X
Present
0
state
1 Input
0
1A X
0
0
1
1
RESET
R
Next
state
Input
Z
RESET
15
0
1
0
1
A
Output
Next
1Input
0 state
0
1 XA
Z
Next
0
state
1Output
1
0A Z
1
00
0
11
0
1
0
1 1
1
0 0
0
1
C
S0
1
0
00
00
1
00
00
00
01
0
00
0
0
0
1
1
Output
Z
0
1
1
0
Output
Z
S
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
68
X=1/
Z=1,S=0
Present
Input state
05
X=0/
Z=0,
S=0
5
Present state
群
1
X=0/Z=0,S=0
:
69
X=1/Z=1,S=0
0
X=x/
Z=0,S=1
39
2
X=0/Z=0,S=0
X=0 / Z=1
Problem
Present Solutions – Chapter
Next 4
+
1
state
Input
state
Output
A
X
A
Z
X=0 / Z=0
X=1 / Z=1
0
0
Present
0
1
Present
1
0
state
1 state
1 Input
X=0 / Z=1
X=1 / Z=0
0
1
A
X=0 / Z=0
A
0
0
Z1
1
X
CLK
X
0
0
1
1
1
0
1 Next
Input
0 state
0
Next
1
1
state
0 Output
XA
1
0 0
1 1
0 0
1
A Z
0
1 1
0 1
1 0
0
X
0
1
0
1
Output
Z
0
1
1
0
05
4-24.
0
RESET
:
69
Z
4-25.
CLK
Format: RA/E (x = unspecif ied)
RESET
xx/1
x1/1
10/0
1x/1
11/0
10/0
01/0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
4-26.
加
Present state
APresent
state
0
0A
0
00
10
10
10
1
1
1
1
1
迎
欢
0
1
0
1
0
1
湖
C
B
D
E
0
0
1
0
D0
0
01
00
10
01
00
00
0
1
Output
0
1
E1
1
00
10
01
10
11
10
B
0
1
0
1
1
1
0
0
1
0
1
0
入
B
0
0
0D
0
00
00
00
00
01
01
C
0
0
Next
1
0
state
Input
X
0
0
1
1
0
0
1
1
0
1
1
1
0
0
1
0
1
0
C
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
1
1
0
0
1
0
0
资
A
Present state
Inputs
Next state
B
R
B
C
0
0
1
1
1
1
1
1
0
0
1
1
0Next
0 state
0
0
D
0B 0C
0
0
00 0 0
0
00 0 1
1
C
D
0
1
1
0
1
1
Present
0
1 state
1
0
1
1
B1
C
0
0D
1
0
0
01
01
10
01
01
10
试
R
0
0
0
0
Inputs
0
1
0
1
A0
1R
1
0
01
10
11
10
01
00
01
10
00
01
00
11
考
D
0
0
0
0
0
0
0
0
1
1
1
1
Output
学
C
大
B
Present 0
state 0
Next state
南
Inputs
0
0
1
1
1
1
0
0
1
0
1
0
Next state
Output
A
Z
01/0
料
11/0
00/0
Present state
x0/1
群
0x/1
00/0
Reset
39
2
X=1 / Z=0
68
X=1 / Z=1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
A
0
1
Inputs
0
1
R0 A
1
0 0 0
0 1 1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
Output
D
E
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
Next state
A
0
0
1
0
1
0
1
0
0
0
1
1
0
0
0
0
16
E
0
0
1
1
1
1
1
1
Format: XY /Z (x = unspecif ied)
Format: XY/Z (x = unspecified)
Y
Input
0
X 1
Y
0
0 1
0
0 0
1
1 1
0
1 0
1
0
0
1
0
1
1
0
1
1
Output
Output
Z
0
0
1
1
0
0
0
0
11/1
0x/0
10/1
x0/0
1
0
x1/0
Problem Solutions – Chapter 4
4-27.*
To use a one-hot assignment, the two flip-flops A and B
No Reset
State Specified.
No Reset State Specif
ied.
D1  Y1  X·Y1  X·Y4
need to be replaced with f our f lip-f lops Y 4, Y 3, Y 2. Y 1.
0
0 00
0 0
0
0 1
0
0 1
1 00
1 00
1 11
1 11
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
10
0
0
0
0
0
00
00
01
01
0
0
0
0
1
1
0
0
X A’ B"
0
1
1
1
0
0
1
0
0
0
1
0
0
0
0
1
0
1
0
1
0
0
0
1
1
0
0
0
0 1
0
1
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
Output
Output
A’ B”Y4’Y3’Y2’Y1
Y4’Y3’Y2’Y1 Z
Z
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
1
00
0
1
0
0
0
01
00
01
00
0
10
0
0
0
0
1
00
01
00
10
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
1
D1 =D2
Y 1’=
+ X·Y
4
 Y2X·Y
X·Y1
 X·Y2
  X·Y2
D2 =D3
Y2’=Y3
X·Y1
+ X·Y
2
 X·Y3
68
Y4BY3 Y2 Y1
A
Y4 Y3 Y2 X
Y1
0
0
0
0
1
1
1
1
Next State
Next State
D3 =D4
Y 3’
= X·Y
2 + X·Y
3
  X·Y3
 Y4
 X·Y4
D4 = Y4’ = X·Y3 + X·Y 4
05
AB
Input
:
69
Present State
Present State
Input
料
群
X
Y1
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D
C
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Clock
欢
Y3
C
D
17
Y2
C
D
39
2
To use a one-hot assignment, the two flip-flops A and B need to be replaced with four flip-flops Y4, Y3, Y2. Y1.
Y4
Y
Problem Solutions – Chapter 4
4-28.
Input
Next state
Output
AB
X
A B
Z
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
1
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
05
0
0
0
1
1
0
1
1
:
69
0
0
1
1
0
0
1
1
68
Present state
资
Z
试
C
B
料
A
C
D
群
X
D
39
2
Using a Gray code assignment of 00, 01, 11, 10 for states 00, 01, 10, 11, respectively, in the diagram:
4-29.+
学
a) D A  C
考
Clock
Next State
DB  A
ABC
ABC
DC  B
000
001
010
011
100
101
110
111
100
000
XXX
001
110
XXX
111
011
大
Present
State
Clear B  Reset
Clear C  Reset
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b) Clear A  Reset
18
c, d, e, f) The circuit is suitable for child’s toy, but not
for life critical applications. In the case of the
child’s toy, it is the cheapest implementation.
If an error occurs the child just needs to reset
it. In life critical applications, the immediate
detection of errors is critical. The circuit above
enters invalid states for some errors. For a life
critical application, additional circuitry is
needed for immediate detection of the error
(Error  ABC  ABC). This circuit using the
design in a), does return from the invalid states
to a valid state automatically after one or two
clock periods.
Problem Solutions – Chapter 4
05
68
39
2
4-30.
01/0
10/1
11/0
00/1
1
0
00/0
1
9 01/100/0
13 10/0
11/1 01/0
16
3
11/1
4
14
群
17
7
01/1, 10/0
6 11
10/1
料
RESET
2
5 10
3 00/1
11 /0
2
资
8
12
15
:
69
4-31.*
试
Format: XY/Z
Reset, 00, 11, 00, 11, 10, 01, 00, 01, 01, 10, 10, 10, 10, 01, 11, 11, 00
考
X’s can be used for transitions 8/15 and 9/16, but using X’s would not decrease the length of the sequence.
学
4-32.
DA  AB  ABX  AXY  B X Y
大
DB  ABY  ABY  AB X  BX Y  AB X Y
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Z  ABY  ABY  ABX  AB X
19
Problem Solutions – Chapter 4
4-33.
1
0
1
b)
1
0
1
DA  AB  BY  ABY
0
DB  AY
0
Z  AB  AB
68
0
39
2
a)
2
0
1
0
:
69
3
1
05
1
Format is
State
Output value
试
资
料
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4-34.
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入
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学
考
4-35.
20
.
Problem Solutions – Chapter 4
4-36.
Implementing the state-machine diagram from 4-35 using a one-hot state assignment:
39
2
DA  AX  BY  CX
DB  AX
Z  B X  CY  D
Flip-flop A should be set to a 1 on reset, while flip-flops B, C, and D should be reset to 0 on reset.
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69
4-37.
05
DD  C X  DX Y  D XY
68
DC  BY  DXY  D X Y
21
Problem Solutions – Chapter 4
料
群
:
69
05
68
39
2
4-38.*
4-39.
(a)
No_Change
D
资
D
DR
DR
DR
DR
试
LT2Q
D
NoCh
DR
Q
25c
Q
50c
Q
75c
Q
Q
考
Q
100c
学
Init
Reset
DR
CLOR
D
125c
Q
150c
200c
Return_2_Quarters
LED
DR
R
Disp_Cola
Disp_Lemon
南
Disp_Orange
Disp_Root_Beer
大
C
L
O
欢
迎
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入
湖
(b) Some possible changes to the specification follow. 1. Provide appropriate change and dispense soda for the cases in which
75 cents and 125 cents followed by a dollar have been deposited. Provide a coin return button for the event that the user is out
of quarters and dollars before the 150c state is reached. 3. Change the No Change warning to cover all added cases in 1.
22
Problem Solutions – Chapter 4
4-40.
39
2
The schematic in Figure 4-49 does not include a reset signal. The model below includes a reset to make the model simulate
correctly.
library ieee, lcdf_vhdl;
use ieee.std_logic_1164.all, lcdf_vhdl.func_prims.all;
05
68
entity problem440 is
port (Clock, Reset, X: in std_logic;
Y: out std_logic);
end problem440;
:
69
architecture structural of problem440 is
component xor2
port(in1, in2: in std_logic;
out1: out std_logic);
end component;
群
component dff
port(CLK, RESET, D : in std_logic;
Q : out std_logic);
end component;
signal A, B, AxorX, AxorX_n: std_logic;
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考
试
begin
g0: dff port map(Clock, Reset, B, A);
g1: dff port map(Clock, Reset, AxorX_n, B);
g2: xor2 port map(A, X, AxorX);
g3: not1 port map(AxorX, AxorX_n);
g4: xor2 port map(B, AxorX, Y);
end structural;
资
料
component NOT1
port(in1: in std_logic;
out1: out std_logic);
end component;
23
Problem Solutions – Chapter 4
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试
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68
:
69
05
library ieee;
use ieee.std_logic_1164.all;
entity problem441 is
port(Clock, X, Reset: in std_logic;
Y: out std_logic);
end problem441;
architecture process_style of problem441 is
type state_type is (state0, state1, state2, state3);
signal state, next_state : state_type;
begin
-- Process 1 - state_register: implements positive edge-triggered state
state_register: process (Clock, Reset)
begin
if (Reset = '1') then state <= state0;
elsif (Clock'event and Clock = '1') then state <= next_state;
end if;
end process;
---- Process 2 - next_state_function: implements next state as function of input X and state.
next_state_func: process (X, state)
begin
case state is
when state0 =>
if X = '1' then
next_state <= state0;
else
next_state <= state1;
end if;
when state1 =>
if X = '1' then
next_state <= state2;
else
next_state <= state3;
end if;
when state2 =>
if X = '1' then
next_state <= state1;
else
next_state <= state0;
end if;
when state3 =>
if X = '1' then
next_state <= state3;
else
next_state <= state2;
end if;
end case;
end process;
-- Process 3 - output_function: implements output as function of input X and state.
output_func: process (X, state)
begin
case state is
when state0 =>
if X = '1' then
Y <= '1';
else
Y <= '0';
end if;
when state1 =>
if X = '0' then
Y <= '1';
else
Y <= '0';
end if;
when state2 =>
if X = '0' then
Y <= '1';
else
Y <= '0';
end if;
when state3 =>
if X = '1' then
Y <= '1';
else
Y <= '0';
end if;
end case;
end process;
end;
39
2
4-41.
24
Problem Solutions – Chapter 4
architecture mux_4to1_arch of mux_4to1 is
begin
entity mux_4to1 is
port (
S: in STD_LOGIC_VECTOR (1 downto 0);
D: in STD_LOGIC_VECTOR (3 downto 0);
Y: out STD_LOGIC
);
end mux_4to1;
process (S, D)
begin
case S is
when “00” => Y <= D(0);
when “01” => Y <= D(1);
when “10” => Y <= D(2);
when “11” => Y <= D(3);
when others => null;
end case;
end process;
end mux_4to1_arch;
群
4-43.
05
:
69
-- (continued in the next column)
68
library IEEE;
use IEEE.std_logic_1164.all;
architecture mux_4to1_arch of mux_4to1 is
begin
entity mux_4to1 is
port (
S: in STD_LOGIC_VECTOR (1 downto 0);
D: in STD_LOGIC_VECTOR (3 downto 0);
Y: out STD_LOGIC
);
end mux_4to1;
process (S, D)
begin
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library IEEE;
use IEEE.std_logic_1164.all;
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-- (continued in the next column)
if S = “00” then Y <= D(0);
elsif S = “01” then Y <= D(1);
elsif S = “10” then Y <= D(2);
elsif S = “11” then Y <= D(3);
else null;
end if;
25
end process;
end mux_4to1_arch;
39
2
4-42.*
Problem Solutions – Chapter 4
4-44.+
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26
68
05
:
69
-- Process 3 -output function
output_func: process (X, state)
begin
case state is
when Init =>
if (X = ‘0’) then
Z <= ‘1’;
else
Z <= ‘0’;
end if;
when B10 =>
if (X = ‘0’) then
Z <= ‘1’;else
Z<= ‘0’;
end if;
when B11 =>
Z <= X;
when B20 =>
Z <= X;
when B21 =>
if (X = ‘0’) then
Z <= ‘1’;
else
Z <= ‘0’;
end if;
when B2X =>
if (X = ‘0’) then
Z <= ‘1’;
else
Z <= ‘0’;
end if;
when B3X0 =>
Z <= X;
when B31 =>
Z <= ‘1’;
end case;
end process;
资
architecture process_3 of serial_BCD_Ex3 is
type state_type is (Init, B10, B11, B20, B21, B2X, B3X0, B31);
signal state, next_state: state_type;
begin
-- Process 1 - state register
state_register: process (clk, reset)
begin
if (reset = ‘1’) then
state <= Init;
else if (CLK’event and CLK= ‘1’) then
state <= next_state;
end if;
end if;
end process;
-- Process 2 - next state function
next_state_func: process (X, state)
begin
case state is
when Init =>
if (X = ‘0’) then
next_state <= B10;
else
next_state <= B11;
end if;
when B10 =>
if (X = ‘0’) then
next_state <= B20;
else
next_state <= B21;
end if;
when B11 =>
next_state <= B2X;
when B20 =>
next_state <= B3X0;
when B21 =>
if (X = ‘0’) then
next_state <= B3X0; else
next_state <= B31;
end if;
when B2X =>
if (X = ‘0’) then
next_state <= B3X0;
-- (continued in the next column)
next_state <= B31;
end if;
when B3X0 =>
next_state <= Init;
when B31 =>
next_state <= Init;
end case;
end process;
39
2
else
料
library IEEE;
use IEEE.std_logic_1164.all;
entity serial_BCD_Ex3 is
port (clk, reset, X : in STD_LOGIC;
Z : out STD_LOGIC);
end serial_BCD_Ex3;
end process_3;
Problem Solutions – Chapter 4
architecture process_3 of prob_5_43 is
type state_type is (A, B, C, D);
signal next_state, state : state_type;
begin
-- Process 1 - state register
state_register: process (clk, reset)
begin
if (reset = ‘1’) then
state <= A;
elsif (clk’event and clk = ‘1’) then
state <= next_state;
end if;
end process;
:
69
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入
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大
-- Process 2 - next state function
next_state_func: process (X, state)
begin
case state is
when A =>
case X is
when “00” =>
next_state <= A;
when “01” =>
next_state <= B;
when “10” =>
next_state <= B;
when “11” =>
next_state <= A;
when others => next_state <= A;
end case;
when B =>
case X is
when “00” =>
next_state <= A;
when “01” =>
next_state <= A;
when “10” =>
next_state <= D;
when “11” =>
next_state <= D;
when others => next_state <= A;
end case;
when C =>
case X is
when “00” =>
next_state <= A;
when “01” =>
next_state <= A;
when “10” =>
next_state <= C;
when “11” =>
next_state <= C;
when others => next_state <= A;
end case;
-- Process 3 -output function
output_func: process (X, state)
begin
case state is
when A =>
case X is
when “00” =>
Z <= ‘0’;
when “01” =>
Z <= ‘0’;
when “10” =>
Z <= ‘1’;
when “11” =>
Z <= ‘0’;
when others => Z <= ‘X’;
end case;
when B =>
case X is
when “00” =>
Z <= ‘0’;
when “01” =>
Z <= ‘0’;
when “10” =>
Z <= ‘1’;
when “11” =>
Z <= ‘1’;
when others => Z <= ‘X’;
end case;
when C =>
case X is
when “00” =>
Z <= ‘1’;
when “01” =>
Z <= ‘0’;
when “10” =>
Z <= ‘1’;
when “11” =>
Z <= ‘0’;
when others => Z <= ‘X’;
end case;
when D =>
case X is
when “00” =>
Z <= ‘1’;
when “01” =>
Z <= ‘1’;
when “10” =>
Z <= ‘0’;
when “11” =>
Z <= ‘1’;
when others => Z <= ‘X’;
end case;
end case;
end process;
end process_3;
68
when D =>
case X is
when “00” =>
next_state <= C;
when “01” =>
next_state <= B;
when “10” =>
next_state <= B;
when “11” =>
next_state <= C;
when others => next_state <= A;
end case;
end case;
end process;
05
library IEEE;
use IEEE.std_logic_1164.all;
entity prob_5_43 is
port (clk, reset : in STD_LOGIC;
X : in STD_LOGIC_VECTOR(2 downto 1) ;
Z : out STD_LOGIC);
end prob_5_43;
39
2
4-45.
欢
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加
--Continued in next column
27
Problem Solutions – Chapter 4
:
69
architecture process_3 of prob_5_44 is
type state_type is (A, B, C, D, E, F);
signal state, next_state: state_type;
begin
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湖
-- Process 3 -output function
output_func: process (X, state)
begin
case state is
when A =>
Z <= ‘0’;
when B =>
Z <= ‘0’;
when C =>
Z <= ‘0’;
when D =>
Z <= ‘1’;
when E =>
-- Continued in next page
end case;
end process;
end process_3;
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Z <= ‘1’;
when F =>
Z <= ‘1’;
-- Continued in next column
群
-- Process 1 - state register
state_register: process (clk, reset)
begin
if (reset = ‘1’) then
state <= A;
else if (CLK’event and CLK= ‘1’) then
state <= next_state;
end if;
end if;
end process;
-- Process 2 - next state function
next_state_func: process (X, state)
begin
case state is
when A =>
if X = ‘0’ then
next_state <= B;
else
next_state <= D;
end if;
when B =>
if X = ‘0’ then
next_state <= D;
else
next_state <= C;
end if;
-- Continued in next column
68
when C =>
if X = ‘0’ then
next_state <= A;
else
next_state <= F;
end if;
when D =>
if X = ‘0’ then
next_state <= F;
else
next_state <= C;
end if;
when E =>
if X = ‘0’ then
next_state <= C;
else
next_state <= E;
end if;
when F =>
if X = ‘0’ then
next_state <= E;
else
next_state <= F;
end if;
end case;
end process;
05
library IEEE;
use IEEE.std_logic_1164.all;
entity prob_5_44 is
port (clk, reset,
X : in STD_LOGIC;
Z : out STD_LOGIC);
end prob_5_44;
39
2
4-46.
28
Problem Solutions – Chapter 4
when Fill_3 =>
if L3 = ‘1’ then
next_state <= Mix;
else
next_state <= Fill_3;
end if;
when Mix =>
if TZ = ‘1’ then
next_state <= Empty;
else
next_state <= Mix;
end if;
when Empty =>
if L0 = ‘1’ then
next_state <= Init;
else
next_state <= Empty;
end if;
end case;
end if;
end process;
05
architecture process_3 of prob_5_46 is
type state_type is (Init, Fill_1, Fill_2, Fill_3, Mix, Empty);
signal state, next_state: state_type;
begin
68
library IEEE;
use IEEE.std_logic_1164.all;
entity prob_5_46 is
port (clk, reset, NI, Start, Stop, L0, L1, L2, L3, TZ : in
STD_LOGIC;
MX, PST, TM, V1, V2, V3, VE : out STD_-LOGIC);
end prob_5_46;
39
2
4-47.
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-- Process 3 - output function
output_func: process (L2, L3, NI, TZ, Stop, state)
begin
MX <= ‘0’;
PST <= ‘0’;
TM <= ‘0’;
V1 <= ‘0’;
V2 <= ‘0’;
V3 <= ‘0’;
VE <= ‘0’;
case state is
when Init =>
when Fill_1 =>
V1 <= ‘1’;
when Fill_2 =>
V2 <= ‘1’;
if ((L2 and not NI and not Stop) = ‘1’) then
PST <= ‘1’;
end if;
when Fill_3 =>
V3 <= ‘1’;
if ((L3 and not Stop) = ‘1’) then
PST <= ‘1’;
end if;
when Mix =>
MX <= ‘1’;
if ((not TZ and not Stop) = ‘1’) then
TM <= ‘1’;
end if;
when Empty =>
VE <= ‘1’;
end case;
end process;
end process_3;
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-- Process 2 - next state function
next_state_func: process (NI, Start, Stop, L0, L1, L2, L3, TZ, state)
begin
if Stop = ‘1’ then
next_state <= Init;
else
case state is
when Init =>
if Start = ‘1’ then
next_state <= Fill_1;
else
next_state <= Init;
end if;
when Fill_1 =>
if L1 = ‘1’ then
next_state <= Fill_2;
else
next_state <= Fill_1;
end if;
when Fill_2 =>
if L2 = ‘1’ then
if NI = ‘1’then
next_state <= Fill_3;
else
next_state <= Mix;
end if;
else
next_state <= Fill_2;
end if;
-- Continued in next column
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:
69
-- Process 1 - state register
state_register: process (clk, reset)
begin
if (reset = ‘1’) then
state <= Init;
else if (CLK’event and CLK= ‘1’) then
state <= next_state;
end if;
end if;
end process;
29
Problem Solutions – Chapter 4
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考
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-- Process 1 - state register
state_register: process (clk, reset)
begin
if (reset = ‘1’) then
state <= S0;
else if (CLK’event and CLK= ‘1’) then
state <= next_state;
end if;
end if;
end process;
-- Process 2 - next state function
next_state_func: process (CR, N, D, Q, state)
begin
case state is
when S0 =>
if N = ‘1’ then
next_state <= S5;
elsif D = ‘1’ then
next_state <= S10;
elsif Q = ‘1’ then
next_state <= S25;
else
next_state <= S0;
end if;
when S5 =>
if CR = ‘1’ then
next_state <= RT;
elsif N = ‘1’ then
next_state <= S10;
elsif D = ‘1’ then
next_state <= S15;
elsif Q = ‘1’ then
next_state <= S25;
else
next_state <= S5;
end if;
when S10 =>
if CR = ‘1’ then
next_state <= RT;
elsif N = ‘1’ then
next_state <= S10;
end if;
-- Continued in next column
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-- Process 3 - output function
output_func: process (CR, N, D, Q, state)
begin
DJ <= ‘0’;
RC <= ‘0’;
case state is
when S25 =>
DJ <= ‘1’;
when RT =>
RC <= ‘1’;
when others => null;
end case;
end process;
end process_3;
30
.
68
:
69
architecture process_3 of prob_5_47 is
type state_type is (S0, S5, S10, S15, S20, S25, RT);
signal state, next_state: state_type;
begin
next_state <= S15;
elsif D = ‘1’ then
next_state <= S20;
elsif Q = ‘1’ then
next_state <= S25;
else
when S15 =>
if CR = ‘1’ then
next_state <= RT;
elsif N = ‘1’ then
next_state <= S20;
elsif D = ‘1’ then
next_state <= S25;
elsif Q = ‘1’ then
next_state <= S25;
else
next_state <= S15;
end if;
when S20 =>
if CR = ‘1’ then
next_state <= RT;
elsif N = ‘1’ then
next_state <= S25;
elsif D = ‘1’ then
next_state <= S25;
elsif Q = ‘1’ then
next_state <= S25;
else
next_state <= S20;
end if;
when S25 =>
next_state <= S0;
when RT =>
next_state <= S0;
end case;
end process;
05
library IEEE;
use IEEE.std_logic_1164.all;
entity prob_5_47 is
port (clk, reset, CR, N, D, Q : in STD_LOGIC;
DJ, RC : out STD_LOGIC);
end prob_5_47;
39
2
4-48.
Problem Solutions – Chapter 4
4-49.
39
2
The schematic in Figure 4-49 does not include a reset signal. The model below includes a reset to make the model simulate
correctly.
module problem449(Clock, Reset, X, Y);
input Clock, Reset, X;
output Y;
68
wire A, B, AxorX, AxorX_n;
:
69
05
dff g0(Clock, Reset, B, A);
dff g1(Clock, Reset, AxorX_n, B);
xor g2(AxorX, A, X);
not g3(AxorX_n, AxorX);
xor g4(Y, B, AxorX);
endmodule
4-50.
群
The schematic in Figure 4-49 does not include a reset signal. The model below includes a reset to make the model simulate
correctly.
料
module problem450(Clock, Reset, X, Y);
input Clock, Reset, X;
output Y;
试
考
state0 : state1;
state2 : state3;
state1 : state0;
state3: state2;
大
?
?
?
?
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X)
X
X
X
X
=
=
=
=
X;
~X;
~X;
X;
加
入
always @(state or
begin
case (state)
state0: Y
state1: Y
state2: Y
state3: Y
endcase
end
=
=
=
=
南
always @(state or X)
begin
case (state)
state0: next_state
state1: next_state
state2: next_state
state3: next_state
endcase
end
学
always @(posedge Clock or posedge Reset)
begin
if (Reset)
state <= state0;
else
state <= next_state;
end
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reg state, next_state;
parameter state0 = 2'b00, state1 = 2'b01, state2 = 2'b10, state3 = 2'b11;
reg Y;
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endmodule
31
Problem Solutions – Chapter 4
input [1:0] S ;
input [3:0] D ;
output Y;
reg Y ;
:
69
// (continued in the next column)
4-52.*
module problem_6_39 (S, D, Y) ;
always @(S or D)
begin
if (S == 2′ b00) Y <= D[0];
else if (S == 2′ b01) Y <=
D[1];
else if (S == 2′ b10) Y <= D[2];
else Y <= D[3];
// (continued in the next column)
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end
endmodule
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input [1:0] S ;
input [3:0] D ;
output Y;
reg Y ;
68
always @(S or D)
begin
case (S)
2′ b00 : Y <= D[0] ;
2′ b01 : Y <= D[1] ;
2′ b10 : Y <= D[2] ;
2′ b11 : Y <= D[3] ;
endcase;
end
endmodule
05
module problem_6_38 (S, D, Y) ;
39
2
4-51.
32
Problem Solutions – Chapter 4
4-53.+
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// Next StateFunction
always@(X or state)
begin
case (state)
Init: if (X == 0)
next_state <= B10;
else
next_state <= B11;
B10: if (X == 0)
next_state <= B20;
else
next_state <= B21;
B11: next_state <= B2X;
B20: next_state <= B3X0;
B21: if (X == 0)
next_state <= B3X0;
else
next_state <= B31;
// (continued in the next column)
// Output Function
always@(X or state)
begin
case (state)
Init: if (X == 0)
Z <= 1;
else
Z <= 0;
B10: if (X == 0)
Z <= 1 ;
else
Z <= 0;
B11: Z <= X;
B20: Z <= X;
B21: if (X == 0)
Z <= 1;
else
Z <= 0;
B2X: if (X == 0)
Z <= 1;
else
Z <= 0;
B3X0: Z <= X;
B31: Z <= 1;
endcase
end
endmodule
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// State Register
always@(posedge clk or posedge reset)
begin
if (reset == 1)
state <= Init;
else
state <= next_state;
end
33
39
2
68
B3X0: next_state <= Init;
B31: next_state <= Init;
endcase
end
:
69
reg[2:0] state, next_state;
parameter Init = 3′ b000, B10 = 3′ b001,
B11=3’b011, B20= 3′ b010, B21 = 3′
b110,
B2X = 3′ b111, B3X0 = 3′b100, B31 = 3′
b101;
reg Z;
B2X: if (X ==0)
next_state <= B3X0;
else
next_state <= B31;
05
//Serial BCD to Excess 3 Converter
module serial_BCD_Ex3(clk, reset, X, Z);
input clk, reset, X;
output Z;
Problem Solutions – Chapter 4
4-54.
// State Diagram in Figure 5-40 using Verilog
module prob_5_51 (clk, reset, X, Z);
input clk, reset;
input[1:2] X;
output Z;
next_state <= A;
// Output Function
always@(X or state)
begin
case (state)
A: if (X == 2′ b01 | X == 2′
Z <= 0;
else
Z <= 1;
B: if (X == 2′ b10 | X == 2′
Z <= 1;
else
Z <= 0;
C: if (X == 2′ b00 | X == 2′
Z <= 1;
else
Z <= 0;
D: if (X == 2′ b00 | X == 2′
Z <= 1;
else
Z = 0;
endcase
end
endmodule
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// Next StateFunction
always@(X or state)
begin
case (state)
A: if (X == 2′ b01 | X == 2′ b10)
next_state <= B;
else
next_state <= A;
B: if (X == 2′ b10 | X == 2′ b11)
next_state <= D;
else
next_state <= A;
C: if (X == 2′ b00 | X == 2′ b01)
// (continued in the next column)
68
end
:
69
// State Register
always@(posedge clk or posedge reset)
begin
if (reset == 1)
state <= A;
else
state <= next_state;
end
next_state <= C;
D: if (X == 2’b00 | X == 2’b11)
next_state <= C;
else
next_state <= B;
endcase
05
reg[1:0] state, next_state;
parameter A = 2′b00, B = 2′ b01, C = 2′ b11, D = 2’b10;
reg Z;
39
2
else
34
b00 | X == 2′ b11)
b11)
b10)
b11 | X == 01)
Problem Solutions – Chapter 4
4-55.
39
2
next_state <= F;
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05
:
69
next_state <= A;
D: if (X == 1)
next_state <= C;
else
next_state <= F;
E: if (X == 1)
next_state <= E;
else
next_state <= C;
F: if (X == 1)
next_state <= F;
else
next_state <= E;
endcase
68
else
end
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料
// Output Function
always@(X or state)
begin
case (state)
A: Z <= 0;
B: Z <= 0;
C: Z <= 0;
D: Z <= 1;
E: Z <= 1;
F: Z <= 1;
endcase
end
endmodule
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// State Diagram in Figure 5-41 using Verilog
module prob_5_52 (clk, reset, X, Z);
input clk, reset;
input X;
output Z;
reg[2:0] state, next_state;
parameter A = 3’b000, B = 3’b001,
C = 3′ b010, D = 3′ b011, E = 3′ b100,
F = 3′ b101;
reg Z;
// State Register
always@(posedge clk or posedge reset)
begin
if (reset == 1)
state <= A;
else
state <= next_state;
end
// Next StateFunction
always@(X or state)
begin
case (state)
A: if (X == 1)
next_state <= D;
else
next_state <= B;
B: if (X == 1)
next_state <= C;
else
next_state <= D;
C: if (X == 1)
(continued in the next column)
35
Problem Solutions – Chapter 4
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68
end
// Output Function
always@(L2 or NI or STOP or L3 or TZ or state)
begin
case (state)
Fill_1: V1 <= 0;
Fill_2: begin
V2 <= 0;
if (L2 & ~ NI & ~STOP)
PST <= 1;
else
PST <= 0;
end
Fill_3: begin
V3 <= 0;
if (L3 & ~STOP)
PST <= 1;
else
PST <= 0;
end
Mix: begin
MX <= 1;
if (~TZ & ~STOP)
TM <= 1;
else
TM <= 0;
end
Empty: VE <= 1;
endcase
end
endmodule
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:
69
next_state <= Mix;
else
next_state <= Fill_2;
Mix: if (STOP == 1)
next_state <= Init;
else if (TZ == 1)
next_state <= Empty;
else
next_state <= Mix;
Empty: if (STOP == 1 | L0 == 1)
next_state <= Init;
else
next_state <= Empty;
endcase
考
// State Machine for Batch Mixing System (Figure 5-29)
module batch_mixing_system (clk, reset, START,
STOP, L0, L1, L2, L3, NI, TZ, V1, V2, V3, PST, MX,
TM, VE);
input clk, reset, START, STOP, L0, L1, L2, L3, NI, TZ;
output V1, V2, V3, PST, MX, TM, VE;
reg V1, V2, V3, PST, MX, TM, VE;
reg[2:0] state, next_state;
parameter Init = 3′ b000, Fill_1 = 3′ b001,
Fill_2 = 3′ b010, Fill_3 = 3′ b011, Mix = 3′ b100,
Empty = 3′ b101;
// State Register
always@(posedge clk or posedge reset)
begin
if (reset == 1)
state <= Init;
else
state <= next_state;
end
// Next StateFunction
always@( START or STOP or L0 or L1 or L2 or L3 or
TZ or state)
begin
case (state)
Init: if (START == 1 & STOP == 0)
next_state <= Fill_1;
else
next_state <= Init; // (continued on the next
page)
Fill_1: if (STOP == 1)
next_state <= Init;
else if (L1 == 1)
next_state <= Fill_2;
else
next_state <= Fill_1;
Fill_2: if (STOP == 1)
next_state <= Init;
else if (L2 == 1)
if (NI == 1)
next_state <= Fill_3;
else
next_state <= Mix;
else
next_state <= Fill_2;
Fill_3: if (STOP == 1)
next_state <= Init;
else if (L3 == 1)
// (continued in the next column)
39
2
4-56.
36
Problem Solutions – Chapter 4
4-57.
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4-58.
39
2
68
05
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// State Register
always@(posedge clk or posedge reset)
begin
if (reset == 1)
state <= Init;
else
state <= next_state;
end
// Next StateFunction
always@(CR or N or D or Q or state)
begin
case (state)
Init: if (N == 1)
next_state <= S5c;
else if (D == 1)
next_state <= S10c;
else if (Q == 1)
next_state <= Dispense;
else
next_state <= Init;
S5c: if (N == 1)
next_state <= S10c;
else if (D == 1)
next_state <= S15c;
else if (Q == 1)
next_state <= Dispense;
else if (CR == 1)
next_state <= Coin_Return;
else
next_state <= S5c;
// (continued in the next column)
S10c: if (N == 1)
next_state <= S15c;
else if (D == 1)
next_state <= S20c;
else if (Q == 1)
next_state <= Dispense;
else if (CR == 1)
next_state <= Coin_Return;
else
next_state <= S10c;
S15c: if (N == 1)
next_state <= S20c;
else if (D == 1)
next_state <= Dispense;
else if (Q == 1)
next_state <= Dispense;
else if (CR == 1)
next_state <= Coin_Return;
else
next_state <= S15c;
S20c: if (N == 1)
next_state <= Dispense;
else if (D == 1)
next_state <= Dispense;
else if (Q == 1)
next_state <= Dispense;
else if (CR == 1)
next_state <= Coin_Return;
else
next_state <= S20c;
Dispense: next_state <= Init;
Coin_Return: next_state <= Init;
endcase
end
// Output Function
always@(state)
begin
RC <= 0;
DJ <= 0;
case (state)
Dispense: DJ <= 1;
Coin_Return: RC <= 1;
endcase
end
endmodule
:
69
// State Machine for Jawbreaker Vending Machine
module jawbreaker_vending_machine (clk, reset, CR, N, D,
Q, RC, DJ);
input clk, reset, CR, N, D, Q;
output RC, DJ;
reg RC, DJ;
reg[6:0] state, next_state;
parameter Init = 7′ b0000001, S5c = 7′ b0000010,
S10c = 7′ b0000100, S15c = 7′ b0001000, S20c = 7′
b0010000,
Dispense = 7′ b0100000, Coin_Return = 7′ b1000000;
(Errata: Part a should read “signal D1 for flip-flop 1.”)
a)
b)
There is a setup time violation at 28ns.
There is a hold time violation at 16ns and a setup time violation at 24ns.
37
Problem Solutions – Chapter 4
4-59.*
39
2
a) The longest direct path delay is from input X through the two XOR gates to the output Y.
t delay  t pdXOR  t pdXOR  0.04  0.04  0.08 ns
68
b) The longest path from an external input to a positive clock edge is from input X through the XOR gate
and the inverter to the B Flip-flop.
05
t delay  t pdXOR  t pdINV  t sFF  0.04  0.01  0.02  0.07 ns
:
69
c) The longest path delay from the positive clock edge is from Flip-flop A through the two XOR gates to the
output Y.
t delay  t pdFF  2 t pdXOR  0.08  2(0.04)  0.16 ns
群
d) The longest path delay from positive clock edge to positive clock edge is from clock on Flip-flop A
through the XOR gate and inverter to clock on Flip-flop B.
料
t delay-clock edge to clock edge  t pdFF  t pdXOR  t pdINV  t sFF  0.08  0.04  0.01  0.02  0.15 ns
资
e) The maximum frequency is 1/tdelay- clock edge to clock edge. For this circuit, tdelay-clock edge to clock edge is 0.15 ns, so
the maximum frequency is 1/0.15 ns = 6.67 GHz.
试
Comment: The clock frequency may need to be lower due to other delay paths that pass outside of the circuit
into its environment. Calculation of this frequency cannot be performed in this case since data for paths
through the environment is not provided.
考
4-60.
a) The longest direct path delay is from input X through the four XOR gates to the output Y.
学
t delay  4 t pdXOR  4(0.04)  0.16 ns
大
b) The longest path from an external input to a positive clock edge is from input X through three XOR gates
and the inverter to the clock of the second B Flip-flop.
南
t delay  3 t pdXOR  t pd INV  t sFF  3(0.04)  0.01  0.02  0.15 ns
湖
c) The longest path delay from the positive clock edge is from the first Flip-flop A through the four XOR
gates to the output Y.
t delay  t pdFF  4 t pdXORR  0.08  4(0.04)  0.24 ns
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d) The longest path delay from positive clock edge to positive clock edge is from the first Flip-flop A
through three XOR gates and one inverter to the clock of the second Flip-flop B.
t delay-clock edge to clock edge  t pdFF  3 t pdXOR  t pdINV  t sFF  0.08  3(0.04)  0.01  0.02  0.23 ns
e) The maximum frequency is 1/tdelay-clock edge to clock edge. For this circuit, the delay is 0.23 ns so the maximum
frequency is 1/0.23 ns = 4.35 GHz.
Comment: The clock frequency may need to be lower due to other delay paths that pass outside of the circuit
into its environment. Calculation of this frequency cannot be performed in this case since data for paths
through the environment is not provided.
38
Problem Solutions – Chapter 4
4-61.
`timescale 1ps/1ps
module problem461_tb();
module problem461(Clock, Reset, X, Y);
input Clock, Reset, X;
output Y;
68
`timescale 1ps/1ps
39
2
There are a number of ways to model the timing behavior, but since the book has not gone into great detail
about modeling timing and some of the features of Verilog and VHDL for modeling timing (e.g., Verilog’s
$specify block) and checking for setup/hold time violations, the example below illustrates a simple approach
that does not require knowledge of these features.
05
reg x, clk, reset;
wire y;
// Set the period lower than 130 ps to
account for not checking the set up time
(20 ps).
parameter PERIOD = 125;
:
69
wire A, B, AxorX, AxorX_n;
dff_v g0(Clock, Reset, B, A);
dff_v g1(Clock, Reset, AxorX_n, B);
xor #40 g2(AxorX, A, X);
not #10 g3(AxorX_n, AxorX);
xor #40 g4(Y, B, AxorX);
endmodule
problem461 DUT(clk, reset, x, y);
群
initial
begin
x = 1'b1;
clk = 1'b0;
reset = 1'b1;
#PERIOD;
reset = 1'b0;
x = 1'b0;
end
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试
always
#(PERIOD/2) clk = ~clk;
endmodule
学
always @(posedge CLK or posedge RESET)
begin
if (RESET)
Q <= 1'b0;
else
Q <= #80 D;
end
endmodule
料
module dff_v(CLK, RESET, D, Q);
input CLK, RESET, D;
output Q;
reg Q;
入
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南
大
Incorrect behavior with the clock period set to 125 ps (Output y should toggle between 0 and 1 on every clock cycle with x
set to 0):
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Correct behavior with the clock period set to 175 ps:
39
Problem Solutions – Chapter 5
CHAPTER 5
39
2
© 2016 Pearson Education, Inc.
5-1.*
68
a) F  (A  B)CD
b) G  (A  B)(C  D)
b)gate
4-input
b) 4-input
NORNOR
+Vgate
b) 4-input
gate NOR
+V
A
B
B
C
C
A
B
B
C
C
D
D
资
欢
迎
加
入
湖
南
大
学
考
试
5-3.
1
+V
:
69
A
F
F
A
群
a) 3-input
NAND
gate gate
+V
a) 3-input
NAND
a) 3-input
NAND
gate
+V
+V
料
+V
05
5-2.
F
F
Problem Solutions – Chapter 5
5-4.
256 x 8 ROM
A(7:0)
8
256 x 8 ROM
8
Address
8
8
Address
DECODER
0
1
2
3
EN
EN
256 x 8 ROM
8
256 x 8 ROM
8
Address
8
EN
256 x 8 ROM
8
256 x 8 ROM
8
Address
8
Address
256 x 8 ROM
8
Address
256 x 8 ROM
8
Address
D(15:8)
资
D(7:0)
试
考
5-5.* (Errata: Change "32 X 8" to "64 X 8" ROM)
OUT
IN
OUT
IN
OUT
IN
OUT
000000
0000 0000
010000
000001
0000 0001
010001
0001 0110
0001 0111
100000
0011 0010
110000
0100 1000
100001
0011 0011
110001
0100 1001
000010
0000 0010
010010
0001 1000
100010
0011 0100
110010
0101 0000
000011
0000 0011
000100
0000 0100
010011
0001 1001
100011
0011 0101
110011
0101 0001
010100
0010 0000
100100
0011 0110
110100
0101 0010
000101
0000 0101
0010 0001
100101
0011 0111
110101
0101 0011
0000 0110
010110
0010 0010
100110
0011 1000
110110
0101 0100
010101
000111
南
大
学
IN
0000 0111
010111
0010 0011
100111
0011 1001
110111
0101 0101
001000
0000 1000
011000
0010 0100
101000
0100 0000
111000
0101 0110
001001
0000 1001
011001
0010 0101
101001
0100 0001
111001
0101 0111
001010
0001 0000
011010
0010 0110
101010
0100 0010
111010
0101 1000
001011
入
湖
000110
011011
0010 0111
101011
0100 0011
111011
0101 1001
0001 0010
011100
0010 1000
101100
0100 0100
111100
0110 0000
001101
0001 0011
011101
0010 1001
101101
0100 0101
111101
0110 0001
001110
0001 0100
011110
0011 0000
101110
0100 0110
111110
0110 0010
001111
0001 0101
011111
0011 0001
101111
0100 0111
111111
0110 0011
加
0001 0001
001100
欢
迎
8
EN
料
EN
b) 4K×32/(256×8) = 64 ROM chips
8
EN
群
EN
8
8
Address
:
69
EN
68
A0
A1
05
A8
A9
5-6.
a) 16 + 16 + 1 = 33 address bits and 16 + 1 = 17 output bits, 8G × 17
b) 8 + 8 + 1 + 1 = 18 address bits and 8 + 1 = 9 output bits, 256K×9
c) 4 × 4 = 16 address bits and 14 output bits are needed, 64K × 14
d) 4+4 = 8 address bits and 8 output bits, 256× 8
2
39
2
a)
Problem Solutions – Chapter 5
5-7.
Z
A
B
C
D
0
0
1
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
1
0
1
0
1
1
0
0
0
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
1
0
0
1
68
Y
0
05
X
39
2
Output
5-8.
1
1
1
1
X 1
1
X
C
1
Y
群
1
Y
B
1
X
Y
D
X
1
1
1
1 1
1 1
料
Y
A
:
69
Input
考
试
资
Z
Z
Z
Z
A = XY + XY + YZ
C = YZ + Z
C = YZ
B = XY + XY + YZ
 YZ by all f our f unctions.
C  YZ  Z
 XYA instead
XY  YZof A and
B
XY
 XYof
 YZ
ByAusing
ZY
instead
Y in D,Z Ycan beC shared
Further
,
since A is the complement of B, terms
Y andXXY can be shared betweenA and B. Thus, only f our
By
using Aterms
instead
and and
of Y in D,inversion
shared
by all four functions.
YZ Zinstead
YZ can be
product
Z,
Y of
XYA
, XY,
are required.An
must
be programmed
for A. Further, since A is the
complement of B, terms XY and XY can be shared between A and B. Thus, only four product terms
YZ, XY, XY, and Z are required. An inversion must be programmed for A.
5-9.
0
0
0
1
Z
Y00
00
1
01
1
10
101
00
0
01
1
11
10
A
Z00
01
0
10
1
00
100
01
0
10
1
00
11
B
A00
00
0
00
0
00
000
00
1
01
1
11
10
C
B00
00
0
00
0
00
011
11
0
10
1
01
10
D
C00
00
0
00
1
01
100
01
0
10
0
00
01
E
D00
00
0
01
0
10
000
00
0
01
0
10
00
F
E00
00
1
00
0
00
001
00
0
00
0
01
00
大
0
Y
X00
00
0
00
0
01
011
11
0
11
1
10
11
南
X
A
A
学
Find the truth table and K-maps:
Find the truth table and K-maps:
Find
X the
Y truth
Z Atable
B and
C DK-maps:
E F
F0
01
10
01
10
01
10
01
X
X
B
B
Y
Y
1 1
1
1
Z
A =Z XY
A  XY
D A = XY Y
D
Y
1
11
1
X
X
Y
Y
X 1 1 1
X 1 1 Z1
B = XZ+ YZ
B  X  YZ
EB = X + YZY
E
Y
C
C
X
X
Y
Y
1
1 1
1Z
Z
C  XY  XY  Z
F
Y
F
Y
1 1
1
1 11
X
1
X, XY, and Z are required. So we form the solution using five product terms: XY, YZ, XY, X, and Z. The solution is
described by the equations given with the six K-maps.
欢
迎
加
入
1
湖
X
1 Z1
X
X
Z
Z
D =ZYZ
EZ= 0
F=
1 1 1 1 1 0 0 0 1
ZZ
D = YZ
E=0
F= Z
Implementation of A, D, and E requiresDonly
Z. and
Straightf
Y
E  0 orward implementation
 YZtwo terms, XY
F ofZ B, C, and F
requires f our terms,
XYZ,
XYZ,
Z. By implementing
C,
F,Yonlyorward
three additional
terms of B, C, and F
Implementation
of A,,XY
D,
and
E and
requires
only two terms,B,XY
Z.and
and
Straightf
implementation
X, X Y, and
Z are
required.
So we
solution using
f ivand
e product
terms:
, YZ, additional
XXY
Y, X, andterms
Z. The solution
requires
f our
terms,
,XY
XYZ, XYZ,
andf orm
Z. Bythe
implementing
B, C,
F, only three
Implementation
of
A,
D,
and
E
requires
only
two
terms,
Straightforward
implementation
B, C,solution
and F
XY
and
YZ.
is
described
by
the
equations
giv
en
with
the
six
K-maps.
X, X Y, and Z are required. So we f orm the solution using f iv e product terms:
, YZ, XXY
Y, X, and Z.ofThe
requires
four terms,
XYZ, XYZ,giv
andenZ.with
By implementing
B, C, and F, only three additional terms
is described
by XY,
the equations
the six K-maps.
1
3
Problem Solutions – Chapter 5
5-10.
A
0 0
0 1 1
d d d
1
X
0
1
B
d
d
1
d
A
0 1
1 0
C
1 1
0 0
d
d
d
d
0
1 d
d
Y
B
A
1
1
0
0
1 0
1 0
d
d
d
d
1
0
d
d
B
A
C
1 0 0
1 0 0
1
1
d
d
d
d
1 0
d
d
D
D
D
Z
C
Z
Z = D
D
:
69
5-11.*
1
0 1 1
d d d
1
B
d
1
0
0 0
d
d
d
d
A
1
d
0
1
d
d
0 0
1
d
A
D
0
1
0
1
0
0
1
1
0
1 0
1
0
0
1
d
d
d
d
d
d
d
d
d
d
1 0
d
d
B
A
1
0
C
B
A
D
B
D
试
D
1
群
0
0
C
料
0
C
1 1
资
Assume
3-input
OR gates.
Assume
3-input
OR gates.
C
B
D
BC DBC
+ BC
+ BD
Y =CD
CD
WW= AAB
B + BC
D
BCD
X X =
BCD
 BD
Y
CD+ CD
In this case, shared terms are limited. One such term BC D is generated inW.
In this case, shared terms are limited. One such term BCD is generated in W.
W
68
0
C
05
W
39
2
The values given in the four K-maps come from Table 4-4 on page 224.
The v alues giv en in the f our K-maps come f rom Table 3-1 on page 99.
考
= BCDBC
+ BC
+ BD
Y
D
W =AA+BC
BC BD
+ BD X XBCD
ZZ=DD
 BD
Y=CD
CD+ C
CD
W
Each of the equations abov e is implemented using one 3-input OR gate. Four gates are used.
Each of the equations above is implemented using one 3-input OR gate. Four gates are used.
学
5-12.
1
1
1
南
X 1
大
Figure 5-10 uses 3-input OR gates.
Figure 6-23 uses 3-input OR gates.
A
B
Y
1
X
1
C
Y
1 1
X 1
1
Z
Y
D
1
1
1
1
Y
1 1
X
1
1
1
欢
迎
加
入
湖
Z
Z
Z
A
D = XY + Z
A = XZ + YZ + X YZ
B = XY + YZ + X Y
A  XZ  YZ  XYZ
B  XY  YZ  XY
D  XY  Z
C  A  XY
A, B, and D each require three or fewer product terms so can be implemented with 3-input ORgates.
C requires f our terms so cannot be implemented with a 3-input OR gate. But because
A L device
the f irst
output
P
A, B,
and as
D each
requiretothree
or fewerother
product
terms so can
be implemented
3-input
gates.
requires
can
used
an input
implement
f unctions
it can
be assignedwith
to A
and AOR
can
thenC be
usedfour
to implement C us
terms so
be implemented
inputs
of cannot
a 3-input
OR gate. with a 3-input OR gate. But because the first PAL device output can used as an input to
implement other functions it can be assigned to A and A can then be used to implement C using just two inputs of a 3input OR gate.
4
Problem Solutions – Chapter 5
5-13.
A
1 1 1
1 1
1
1
B
1
1
C
1
A
1
1 1
1
1
1
B
68
1
G
C
1
05
F
39
2
Figure 5-10 uses 3-input OR gates.
D
:
69
D
Straightforward implementation of F requires five prime implicants and of G requires four prime implicants, but only 3
inputs are available on the PAL OR gates. So sum-of-products that can be factored from F and G or both and
implemented by the other PAL cells are needed. A single sum of products that will work is H  ABC  BCD  BCD.
The terms of H are shown with dotted lines on the K-maps. Using H:
群
F  H  CD  AB
G  H  AB
资
料
There are other possible functions for H and corresponding results for F and H.
F ( A, B, C )  C ( AB  B) C ( AB  A)
b)
F ( A, B, C)  C( AB  AB) C( A  B)
考
a)
试
5-14.
学
5-15.
欢
迎
加
入
湖
南
大
a)
5
Problem Solutions – Chapter 5
Using Shannon’s expansion theorem, F ( A, B, C, D)  D(C( A  B) C(1))  D(C( A) C( A)) . Then using the 4LUT from part a, the function can be implemented as:
5-16.
资
MUX2: 0, MUX3: 1, MUX4: 0
MUX2: 1, MUX3: 1, MUX4: 1
MUX2: 1, MUX3: 1, MUX4: 0
试
a)
b)
c)
料
Assuming that the upper input of each mux is selected with a 0:
群
:
69
05
68
39
2
b)
5-17.
考
Invert the b input so that the upper 2-LUT is equal to f (a, b)  a  b and the lower 2-LUT is equal to f (a, b)  ab
学
5-18.
欢
迎
加
入
湖
南
大
The state machine is a Moore machine since the output Z depends only the current state. Using a state assignment of 0
for State0 and 1 for State1, then Z is the same as the state of the flip-flop.
Then the configuration bits 0:10 = 1001 0011 111 (assuming that the a input of the 2-LUTs is the most significant bit of
the address and that a = in1 and b = in2).
6
Problem Solutions – Chapter 6
CHAPTER 6
39
2
© 2016 Pearson Education, Inc.
6-1.
资
料
群
:
69
05
68
(a) R1 + 2’s complement of R2 = 2n + R1 - R2. If R1  R2, the result is  2n. The 2n gives C = 1.
R1 + 2’s complement of R2 = 2n + R1 - R2, if R1 < R2, the result is < 2n giving C = 0.
(b) If C = 1 then R1  R2 and there is no borrow.
If C = 0 then R1 < R2 and there is a borrow. Thus, the borrow is the complement of the C status bit.
(c) For signed numbers, the carry bit C does not indicate whether a borrow occurs. Instead, to tell if R1 is less than R2, one
must examine the sign (leftmost bit) of the result of R1-R2 and the overflow bit V. If the sign bit and the overflow bit V are
not equal to each other, then R1 is less than R2. To show that this condition is true, consider four cases based upon the signs
of R1 and R2:
1) Both R1 and R2 are positive. If R1 < R2, then the result R1-R2 is negative and no overflow occurs. If R1 ≥ R2,
then the result R1-R2 is non-negative and no overflow occurs.
2) Both R1 and R2 are negative. If R1 < R2, then the result R1-R2 is negative and no overflow occurs. If R1 ≥ R2,
then the result R1-R2 is non-negative and no overflow occurs.
3) R1 is positive, and R2 is negative. R1 > R2, but the result R1-R2 could be either positive (with no overflow) or
negative (with overflow).
4) R1 is negative, and R2 is positive. R1 < R2, but the result R1-R2 could be either negative (with no overflow) or
positive (with overflow).
In cases 1, 2, and 4, when R1 < R2, the sign of the result does not equal the overflow bit V. In all other cases, when R1 ≥ R2,
the sign of the result is equal to the overflow bit V.
6-2.*
试
1001 1001
1100 0011
考
1000 0001
学
1101 1011
0101 1010
6-3.
大
AND, 1010 1010 1010 1010
XOR, 1111 1111 0000 0000
(b)
OR
XOR
OR, 0000 0000 0000 1111
南
(a)
(c)
AND
sl 1001 0100
sr 0110 0101
入
湖
6-4.*
6-5.*
欢
迎
6-6.*
加
Qi remains connected to MUX data input 0. Connect Di to MUX data input 1 instead of Mux data input 3. Connect Qi−1 to MUX data
input 2 instead of MUX data input 1. Finally, 0 is connected to MUX data input 3.
a) 1000, 0100, 0010, 0001, 1000. ...
b) # States = n
1
Problem Solutions – Chapter 6
6-7.
39
2
a) 000, 100, 110, 111, 011, 001, 000, ...
b) # States = 2n
a) 8
b) 4
68
6-8.
c) 1
05
6-9.+
群
:
69
Examine an n-bit ripple counter and an n-bit synchronous counter. If
either of these counters cycles through all of its states, there are 2(2n) =
2n+1 transitions for the clock, and there are 2n+1– 2 total transitions for all
flip-flop outputs. For the ripple counter, the clock transitions occur on
the input of only one stage, the 0th stage. For the synchronous counter,
the clock transitions occur on the inputs to all of the n stages. Combining
the transition counts above, the ratio of the input + output transitions for
the synchronous counter compared to the ripple counter is:
料
[n 2n 1  2n 1  2]/[2n 1  2n 1  2]  (n  1)2n 1 /2(2n 1)  (n  1)/2
试
资
Thus, the power dissipated by the synchronous counter is at least as large
as that dissipated by the ripple counter in all cases and grows more rapidly
with the number of stages.
6-10.
学
考
a) Assuming there is an input “Up” for which the Gray code counter counts up when Up = 1 and down
when Up = 0, and that the counter outputs are G3, G2, G1, and G0, then the input equations for the
counter’s four flip-flops are the following:
大
D0  Up(G 3 G 2 G1  G 3G 2G1  G 3 G 2G1  G 3G 2 G1 )   Up(G 3 G 2G1  G 3G 2 G1  G 3G 2G1  G 3 G 2 G1)
D1 =G1 G 0 +Up(G 3 G 2G 0 +G 3G 2G 0 )+Up(G 3G 2G 0 +G 3 G 2G 0 )
D 2 =G 2 G1 +G 2G 0 +UpG 3G1 G 0 +UpG 3G1 G 0
南
D3 =G 3G 0 +G 3G1 +UpG 2 G1 G 0 +UpG 2 G1 G 0
入
湖
b) For an n-bit Gray code counter, there are 2n total transitions for the flip-flop outputs instead of
2n+1 -2 output transitions for the ripple and synchronous binary counters.
6-11.
加
CLK
Count
CT R 4
CT R 4
EN Q0
Q1
Q2
Q3
CO
EN Q0
Q1
Q2
Q3
CO
Q0-Q 3
欢
迎
3 x (CO delay) + (C1-C3 delay)
= 3 + 1 = 4 AND gates
CT R 4
EN Q0
Q1
Q2
Q3
CO
2
Q4-Q 7
Q8 -Q 11
CT R 4
EN Q0
Q1
Q2
Q3
CO
Q12-Q 15
Problem Solutions – Chapter 6
6-12.
Load
Count
D0 Q0
D1 Q1
D2 Q2
D3 Q3
CO
1
68
1
CTR 4
CLK
Load
Count
D0 Q0
D1 Q1
D2 Q2
D3 Q3
CO
39
2
CTR 4
CLK
05
6-13.
CTR 4
Load
Count
D4 Q4
D5 Q5
D6 Q6
D7 Q7
CO
群
1
CTR 4
Load
Count
D0 Q0
D1 Q1
D2 Q2
D3 Q3
CO
:
69
Clk
Init
料
6-14. *
The equations giv en on page
64-53 can be manipulated into SOP f orm as f ollows:
= D
The equations given on page 352 can be manipulated into SOP form as follows: D1  Q1, D2  Q2 1 Q1Q8  Q1Q2Q8  Q1Q2  Q2Q8 ,
Q1, D2 = Q2  Q1Q8 = Q1Q2Q8 + Q1Q2 + Q2Q8, D4 = Q4  Q1Q2 = Q1Q2Q4 + Q1Q4
资
D4  Q4  Q1Q2  Q1Q2Q
Q Q  Q28Q4 , (Q
D18Q8 Q
(Q Q  Q Q Q )  Q (Q Q  Q1Q
Q
+Q
+ 8Q
Q48))(Q
Q12  Q8 )(Q1  Q2  Q4 )  Q1Q2
4 
2Q
8 (Q
2Q4,1 D48 = Q
1Q2Q14) 8= Q81(Q21Q48+Q1Q82Q41) +8 Q8(Q
1+
1+
试
+ Q4) = The
Qequations
Qgiv
Qen
These
equations
are mapped
the
f or D
Table
on page
64-5
3
can
be manipulated
SOP
f the
ormK-maps
as f ollows:
2Q4Q8 +
1 the
8. K-maps
1=
Q4Q8  Q1Q8 . These equations
areQ1mapped
onto
for
Table
6-9 below into
andonto
meet
specifications
given by the maps and the
Q1and
, D2 =meet
Q2  the
Q1Q8specif
= Q1Q2ications
Q8 + Q1Qgiv
Q2Qby
Q1Q2table.
Q4 + Q1Q4
7-9 below
maps
and
2 + en
8, Dthe
4 = Q
4  Q1Q
2 = the
table.
+ Q2Q4, D8 = Q8  (Q1Q8 + Q1Q2Q4) = Q8(Q1Q8+Q1Q2Q4) + Q8(Q1 + Q8)(Q1 + Q2
Q Q + Q1 Q8D
. These equations are mapped onto the K-maps f or Table
D1 + Q4) = Q1Q
22 4 8
Q2
2
7-9 below and meet the specif ications giv en by the maps and the table.
0
X
0 1
X X X
1 0 X X
Q2
Q1
大
D4
0 0
Q
0 04 1
X
1 0 Q
2
00 01 1 0
Q4
X X X1 X
1 0 1
X
0 0
Q8 X X X X
Q10 0 X X
D4
1
1
湖
南
Q8
0 1
0 D21
0 1
0 1Q2
Q
1 0 14
0
Q8 X X X X
1
1
Q4
0 00 X X0
Q4
add
theenable,
enable, change D1
add
the
Q8 X
Q1 X X X ToTo
0 0 X X change
to:
D1
to:
D8
Q2
To add the enable,
Q1
D1 D
= Q1 Q
 EN.
 EN.
0 D 0 0 0Q
change
to:
1
1 D1
8
2
For
the
other
unc
For
threef functions,
D1 =the
Q1 other
 EN.three
0 00 10 00 0
AND
EN with
the
Q4 tions,
AND
EN
with
the
expression
For the other three f unc
X X0 X0 X1 0 expression
XORed
with
with
thewith
state
Q4 Q8
tions, AND
EN
the
Q4 XORed
state v The
ariable.
The
1Q 0X XX X
X X thevariable.
expression
XORed
with
circuit
below
8
the below
state vresults.
ariable. The
1Q1 0 X X circuit
results.
学
1
Q8 X X X1
1 0 X
Q8Q1X
Q2
考
1 0 0 1
1 D
01 0 1
Q1
Q1
入
D
D
EN
C
Q2
D
C
迎
加
Q1
D
C
EN
circuit below results.
Q1
D
欢
C
D
C
D
Q 4 Q4
C
D Q8
C
C
Clock
Clock
3
Q2
Q8
Y
Y
Problem Solutions – Chapter 6
6-15. *
0
0
0
0
1
1
0
0
1
0
1
0
0
0
1
1
0
0
0
1
0
1
0
1
A
0
0
0
1
1
0
B
C
0
1
0
1
0
0
0
1
1
0
0
0
1
0
1
0
1
0
DB  ABC  BC
DC  C
群
6-16.
DA  AB  AC  ABC
Present state
Next state
A
B
C
A
B
C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
料
DB  B
考
试
资
DC  BC  BC
学
6-17.
大
The basic
cell cell
of the
register
f ollows:
The basic
of the
registerisisas
as follows:
S1
S0
D
S1
S0
C
Clock
入
湖
南
S1
S0
In
X : R1  R 2
XY : R1  R3  R 4
迎
加
6-18.
欢
6-19.*
C3
Clock
39
2
C
DC  B C
68
B
b) DA  BC  AC
05
A
a) DB  C
Next
state
:
69
Present
state
R1
R2
Load
Load
4
Out
Problem Solutions – Chapter 6
R1
0
1
2
R1
1
R1
4-bit wide
2 to 1 mux
4-bit wide
4 to 1 mux
X
S1
资
R1
LOAD
C
学
C2 C1C0
考
6-22.*
Carry-in
试
4-bit adder
F
大
D0
D1
D2
D3
Q0
Q1
Q2
Q3
R2
南
LOAD
C
D0
D1
D2
D3
Q0
Q1
Q2
Q3
入
Clock
Assuming that C1 and C0 will not both be 1 simultaneously and using don’t cares for those cases:
Di  AC0  AB  BC1
欢
迎
加
Z
B
Carry-out
湖
3
S0
A
6-23.
1111
料
0
R2
群
R1
R2
:
69
6-21.
05
68
39
2
6-20.
5
W
Y
Problem Solutions – Chapter 6
39
2
6-24.
S1
D
R0
68
S0
D
R1
:
69
C
05
C
Clock
群
6-25.
D
Ci = S0 for lowest order bit.
料
C
Ci
CI
A S
D
B CO C(i +1)
C
试
资
S1
欢
迎
加
入
湖
南
大
学
考
6-26.
A
6
Clock
B
Problem Solutions – Chapter 6
CLK
CT R 4
0
REG 4
D(0-3) Q(0-3)
CI
ADD 4
C1
C1
C2
A(0-3) C(0-3)
B(0-3)
CO
Load
Count
R1
D(0-3) Q(0-3)
CO
68
R2
R1
b)
05
a)
39
2
6-27.*
REG 4
D(0-3) L Q(0-3)
CI
:
69
C1
C2
ADD 4
R2
A(0-3) C(0-3)
B(0-3)
CO
REG 4
D(0-3) Q(0-3)
L
料
群
Clock
The register transfer logic is as follows:
试
Operation
资
6-28.
L0
L1
L2
CA: R1 ← R0
0
0
0
1
0
CB: R0 ←R1, R2 ← R0
0
1
1
0
1
CC: R1 ← R2, R0 ← R2
1
0
1
1
0
南
大
学
考
S0
湖
入
Load
S1
R0
0 S1 S0
1
2
3-to-1 Mux
LO
R1
迎
加
Select
欢
L1
R2
L2
Clock
7
Problem Solutions – Chapter 6
6-29.
39
2
a)
68
H = XY + XZ
05
b)
:
69
F = XY + XY
6-30.
群
Replace multiplexer with:
Replace multiplexer with:
K1
R1
4
4
R0
4
6-31.*
b) Source Registers → Destination
R0 → Registers
R4
b) Source
-> Destination
R0
R1->
→R4
R0, R3
R1 -> R0, R3
R2->
→R0,
R0,R4
R4
R2
R3
R3->
→R2
R2
R4 -> R1, R2
考
试
a) Destination ← Source Registers
← R1, R2<- Source Registers
a)R0
Destination
R1, R2
R1R0←<-R4
R1 <- R4
R2R2←<-R3,
R3,R4
R4
R1
R3R3←<-R1
R0, R2
R4R4←<-R0,
R2
资
料
R2
R4 → R1, R2
学
c) T he minimum number of buses needed for operation of the transfers
The minimum
number
of busesthree
needed
for operation
isc)three
since transfer
Cb requires
dif
ferent
sources. of the transfers is
大
three since transfer Cb requires three different sources.
d)
R1
R2
R3
MUX
R4
MUX
MUX
欢
迎
6-32.
加
入
湖
南
R0
a) Using two clock cycles, the minimum # of buses is 2 .
a) Using two clock cycles, the minimum # of buses is 2 .
b)
R0
R1
R2
MUX
R3
R4
R5
R6
MUX
8
R7
R8
R9
R10
R11
Problem Solutions – Chapter 6
Two clock cy cles minimum
R1
R2
R3
R4
R5
R6
R7
R8
R9
68
R0
39
2
6-33.
MUX
05
MUX
:
69
6-34.*
0101, 1010, 0101, 1010, 1101, 0110, 0011, 0001, 1000
6-35.*
1
2
3
0111
0011
0001
1000
B
0101
0010
0001
0000
C
0
1
1
4
群
0
A
1100
0000
料
Shifts:
0
资
1
6-36.*
考
试
Default: Z1 = 0, Z2 = 0
Def ault: Z1 = 0, Z2 = 0
· X2
S1
S2
大
学
S0
南
Reset
State: STA, STA, STB, STC, STA, STB, STC, STA, STB
Z: 0,
0,
1,
1,
0,
0,
1,
0,
-
欢
迎
加
入
湖
6-37.*
9
Problem Solutions – Chapter 6
Output
STA
W
STA
*
STA
W
STB
*
STB
XY
STA
*
STB
X
STC
*
STB
XY
STC
Z
STA
Z
群
STC
*Default: Z = 0
68
Next State
05
Input
:
69
State
料
6-39.
试
B
考
A
资
DefDefault:
ault: Z Z==00
学
6-40.*
Default: Z = 0
STA
STB
STD
STC
STE
欢
迎
加
入
湖
南
大
Def ault: Z = 0
10
39
2
6-38.
Problem Solutions – Chapter 6
IDLE
Full
RINSE1
Start
Full
Zero
RINSE2
05
WASH1
Full
68
a) Default: HOT = 0,
DEC = 0, TURN = 0,
DRAIN = 0, COLD = 0, Start
Load = 0.
39
2
6-41.+
WASH2
Empty
SPIN3
Empty
SPIN1
Zero
SPIN4
Zero
SPIN2
料
b) Add a flip-flop called ACTION controlled by Pause and Start.
The flip-flop is set by START and reset by Pause.
OR ACTION with each input condition on the “loop”
for each state. AND ACTION with1) each input condition on the
the transition to the following state from each state and 2) all
the output signals.
Stop causes a transition from each state to a new state END
资
...
群
Zero
Stop
考
试
END
Empty
:
69
Full
学
To IDLE
of the states. The partial diagram for state END appears
at the left.
大
6-42.
S1
S0
欢
迎
加
入
湖
南
Def ault: GN = 0, RE = 0,
Y N = 0, RN = 0, GE = 0,
YE = 0
11
S2
S3
Problem Solutions – Chapter 6
Input
A
B
C
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
Next state
DA  AW  BXY  C
Output
A
B
C
W
W
1
0
0
1
0
0
XY
X
XY
1
0
0
0
0
0
0
1
1
Z
1
0
0
Z
DB  AW
DC  B(X  Y)
Z  BXY  C
STC
05
STB
The implementation consists of the logic represented by the
above equations and three D flip-flops with Reset connected
to S on the first flip-flop and to R on the other two flip-flops.
:
69
STA
68
Present state
39
2
6-43.*
群
6-44.
STA1
000
STB1
001
STC1
011
STC2
100
STB2
110
STA2
111
湖
南
大
Def ault:Z Z
Default:
= 0= 0
学
考
试
资
料
This state
has
closed
loop of
three
transitions
(STA
to In
STB
to STC
This state diagram
has a diagram
closed loop
of athree
transitions
(STA
to STB
to STC to
STA).
a Gray
code,to STA).
a Gray
only
one
may
change Any
in going
f rom one
state. with
to
Any
another
only one bit In
may
changecode,
in going
from
onebitstate
to another.
state machine
diagram
astate
loop of
machine
diagram
with a loop
of an odd
of transitions
is to
impossible
to encode
an odd number
of transitions
is impossible
to encode
withnumber
a Gray code.
For example,
go from STA
to
a Gray
For example,
f rom
to STB
the code
STB supposewith
bit B1
of thecode.
code changes.
Then to to
go go
from
STBSTA
to STC,
somesuppose
other bit, bit
sayB1
B2 of
must
changes.
Thenchanged,
to go f rom
STB to STC,
some
bit, say
change.
change. Since
two bits have
It is impossible
to return
to other
state STA.
Thus,B2
themust
answer
to this Since
twothis
bitsstate
havdiagram
e changed,
impossible with
to return
state STA. Thus, the answer to this problem is that
problem is that
cannotItbeisimplemented
a Graytocode.
this state diagram cannot be implemented with a Gray code.
But suppose that we use two equivaent states to represent each of the original states, STA1, STB1,
But
suppose
that we
two to
equiv
aent states
represent
each such
of the
STC1, STA2,
STB2,
and STC2.
Is ituse
possible
implement
the newtodiagram
generated
theoriginal
it has states, STA1, STB1,
STC1,
STA2,
STB2,
and
STC2.
Is
it
possible
to
implement
the
new
diagram
generated
exactly the same properties as the old diagram. Suppose that the codes are 000, 001, 011, 111, 110,such
100, the
has
the
same
respectively,itfor
theexactly
six states.
The
codedproperties
diagram is:as the old diagram. Suppose that the codes are 000,
001, 01
1, 111, 110, 100, respectiv,ely
f or the six states. The coded diagram is:
欢
迎
加
入
The behav ior of this diagram is the same as that of the original and it has been successf ully Gray coded
assigning
codes
implementation
is asuccessfully
straightforward
problem
withtwo
two unused states.
The behavior ofbythis
diagramtwo
is the
sametoaseach
that state.
of theThe
original
and it has been
Graydesign
coded by
assigning
codes to each state. The implementation is a straightforward design problem with two unused states.
12
Problem Solutions – Chapter 6
1 b)
Count
Load D4 D2 D1
Cnt Parallel Load
R Binary Counter
Q4 Q2 Q1
Count
Reset
Clock
Count
000
D2 D1 D0
Note: Reset to zero is not a problem since the f irst
v alue will nev er be used in the design. Af ter one
count, the v alues will hav e entered the desired range
of 1 through 6.
Count
001
Count
100
Count
Count
010
010
001 011
001
011
011
010 100
010
100
100
011 101
011
101
101
110
110
110
111
ddd
100
101
111
ddd
100
101
DQ4 = Q4 C + Q4 Q2 + Q1 Q2 C
Count
Cnt = 1
DQ4  Q4 C  Q4 Q2  Q1 Q2 C
DQ2 = Q2 C + Q1 Q2 C + Q4 Q2 Q1
群
000
110
001
DQ2  Q2 C  Q1 Q2 C  Q4 Q2 Q1
DQ1 = Q1 C + Q1 C
DQ1  Q1C  Q1 C
010
Cost comparison:
011
Cost comparison:
a) 3(14 + 2 + 8 + 6) + 1 + 2 = 93
100
a) 3 (14 + 2 + 8 + 6) + 1 + 2 = 93
b) 3(14) + 4 + 6 + 11 + 10 = 73
101
b) 3 (14) + 4 + 6 + 11 + 10 = 73
The gate input cost of b) is 78.5 % that of a).
The gate input cost of b) is 78.5 % that of a).
110
料
000 010
Count
Count
资
001
101
011
试
001
Count
110
111
111
ddd
ddd
学
110
考
000
Cnt = 0 Cnt = 1
State
Cnt = 0
000
001
010
Count
Applying K-maps to the table entries:
State
Count
Count
Count
68
0
05
0
:
69
a)
39
2
6-45.
大
6-46.
D2
湖
D1
南
DE1= D4
D4D2
D1 = D4 D2 D1
D1
a)a) DE1
a)D2
DE1
D1
D0
DE1
b) D2
D3
GTE100
GTE100
D5D4
D5
D6
D6
This circuit This
can be
easily
ed by describing
range ofthe
v alues
DE1
circuit
canderiv
be easily
deriv ed by the
describing
range of v alu
greater
or
equal
to
100
in
terms
of
powers
of
2.
Thisthan
circuit
can
be
easily
derived
by
describing
the
greater than
to 100 in terms of powers of 2.
6
5or equal
2
The range
smallest
v alue
is+22 than
+ 2 orand
gest
value
6 the
5tolar
2 in
of The
values
greater
equal
100
terms
of
theislar
gest value is
3 smallest
2
1 v alue is+226 + 25 and
2 be described by say ing
26 + powers
25 + 24 +
2
+
2
+
2
.
This
range
of
D
can
6
5
4
3
2
1
of
2.
The
smallest
value
is2 2. This
+2 +
2 andofthe
2
+
2
+
2
+
2
+
2
+
range
D
can be described by say
5
2 3
6 presentand
3
that largest
26 and 2
must
, any
or range
24ofmust
2 of3 be present
value
is
2and
+ 2255 must
+ 24 +be
2any
+ 22of+ 22,1.2This
that
26 be
presentand
2
,
2
, or 24 must in
beD.
present i
6
5
can beThe
described
by
saying
that
2
and
2
must
be
The D
resulting
equation
is
D6
D5
(D4
+
D3
+
D2).
An
alternativ
e
way
of f indin
resulting
is D6 D5 (D4 + D3 + D2). An alternativ
e wa
2 equation
3
4
and
of contract
2carry
, 2 , orcircuit
2the
must
beDpresent
D.
this present
is to contract
the
f or
+ 2’s in
comp
100100.
of2’s
1 comp
this any
is to
carry
circuit
f or
D+
100100.
of 1
The resulting equation is D6 D5 (D4 + D3 + D2). An
alternative way of finding this is to contract the carry
circuit for D + 2’s comp of 1100100.
欢
迎
加
入
D0
D2
b) D2
D3
D4
13
Problem Solutions – Chapter 6
6-47.
00001
00010
00011
00100
00101
00110
00111
01000
01001
10000
10001
10010
1 0 0 11
10100
10101
10110
68
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
10000
10001
10010
10011
10100
10101
D2  B3 B2  B2 B1
D1  B3 B1  B3 B2 B1
D0  B0
05
C4D3D2D1D0
For C0  1,
C4  B3 B2  B3 B1  B3 B0
D3  B3 B2 B1 B0  B3 B2 B1 B0
D2  B3 B2 B1  B3 B2 B0  B2 B1 B0  B3 B2 B1 B0
D1  B3 B1 B0  B3 B1 B0  B3 B1 B0  B3 B2 B1 B0
D0  B0
Combining,
C4  C0 (B3 B2  B3 B1)  C0 (B3 B2  B3 B1  B3 B0)
D3  C0 (B3 B2 B1)  C0 (B3 B2 B1 B0  B3 B2 B1 B0)
D2  C0 (B3 B2  B2 B1)  C0 (B3 B2 B1  B3 B2 B0  B2 B1 B0  B3 B2 B1 B0)
资
0000
0001
0010
0011
010 0
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
C4D3D2D1D0
D3  B3 B2 B1
:
69
B3B2B1B0
C4  B3 B2  B3 B1
群
BCD (C0 =
1)
BCD (C0 = 0)
料
Binary
39
2
For C0  0,
D1  C0 (B3 B1  B3 B2 B1)  C0 (B3 B1 B0  B3 B1 B0  B3 B1 B0  B3 B2 B1 B0)
试
D0  C0 B0  C0 B0
考
Optimizing,
C4  B3 (B2  B1  C0 B0)
D3  (C0  B0)B3 B2 B1  C0 B3 B2 B1 B0
学
D2  B2 (C0 B1  B3 B1  B1 B0  C0 B3 B0)  C0 B3 B2 B1 B0
D1  (C0  B0) B3 B2 B1  C0 B3 B1  C0 B0 (B3 B1  B3 B1)  B3 B1 B0
6-48.
南
大
D0  C0 B0  C0 B0
a) Transition constraint checking for Figure 6-30.
湖
Constraint 1:
Constraint 2:
INIT: No possible conflicts since a single transition.
Condition implicitly = 1
OK
OK
BEGIN: ROLL  ROLL  1
OK
ROL: ROLL  ROLL  0
OK
ROL: ROLL  ROLL  1
OK
ONE: DIE1  DIE1  0
OK
DIE1  DIE1  1
OK
ROH: ROLL  ROLL  HOLD  0
OK
ROH: ROLL  ROLL  HOLD  ROLL  HOLD  1
OK
ROLL  ROLL  HOLD  0
OK
ROLL  HOLD  ROLL  HOLD  0
OK
迎
加
入
BEGIN: ROLL  ROLL  0
OK
TEST: WN  WN  1
OK
WIN: NEW _ GAME  NEW _ GAME  0
OK
WIN: NEW _ GAME  NEW _ GAME  1
OK
欢
TEST: WN  WN  0
b) Implementation of state machine diagram Figure 6-30 using 1-hot code.
The order from LSB to MSB for the state variables is the same as the order of the states in the diagram from top to bottom. The state
variables have the same respective names as the states, e.g., INIT, BEGIN, ...
14
Problem Solutions – Chapter 6
The flip-flop input equations:
DINIT  INIT(t  1)  WIN  NEW _ GAME
39
2
D BEGIN  BEGIN(t  1)  INIT  ONE  DIE1  TEST  WN  BEGIN  ROLL
D ROL  BEGIN  ROLL  ROH  ROLL  ROL  ROLL
DONE  ROL  ROLL
68
D ROH  ONE  DIE1  ROH  ROLL  HOLD
DTEST  ROH  ROLL  HOLD
05
D WIN  TEST  WN  WIN  NEW _ GAME
The output equations:
:
69
RST1  INIT, RST2  INIT, CPFI  INIT, LDCP  INIT  TEST  WN  ONE  DIE1, RSSU  BEGIN, ENDI  ROL, LDSU
 ONE, LDT1  ROH  CP  ROLL  HOLD, LDT2  ROH  CP  ROLL  HOLD, BP1  WIN  CP, BP2  WIN  CP
群
The circuit consists of gates implementing the above equations with logic shared where possible, and seven D flip-flops. The flipflop for INIT has Reset attached to S and the remaining flip-flops have Reset attached to R.
料
6-49.+
资
Default:P1P1
CP,
P2= CP
CP
Default:
= CP
, P2
大
(DIE1 = 1) + (DIE2 = 1)
南
湖
入
加
if (DIE1 = 1 0) DIE1
001,
if (DIE2 = 1 0) DIE2
001,
else DIE2
DIE2 +1,
else DIE1
DIE1 + 1
T1&2
ROH
SUR
SUR + DIE1 + DIE2
ROLL
CP/TR1
CP/TR2
TR1 + SUR,
TR2 + SUR
ROLL· HOLD
CP
TEST
CP· (TR1  1100100) + CP· (TR2  1100100)
WIN
CP/ P1 = BLINK, CP/P2 = BLINK
NEW_GAME
欢
迎
ROLL
0
(DIE1 = 1)·(DIE2 = 1)
ROLL· HOLD
(CP· (TR1  1100100)
+ CP· (TR2  1100100))/CP
SUR
ROLL
0, ROLL
0,
ROL
学
(DIE1 = 1)·(DIE2 = 1)·CP/TR1
(DIE1 = 1)·(DIE2 = 1)·CP/TR2
CP
CP
BEGIN
考
ROLL
试
INIT
15
Problem Solutions – Chapter 6
IN
LA
L
LB
AR
A(15:0)
Bit 15
L
B(14:0)||0
A(14:0)||0
CLK
S 1 MUX 0
BR
CLK
LC
B(15:0)
L
R
68
CLK
39
2
6-50.*
CR
Zero
:
69
05
R is a synchronous reset that overrides any
simultaneous synchronous transfer
.
A
Def ault: LA = 0,
LB = 0, LC = 0
料
群
B
欢
迎
加
入
湖
南
大
学
考
试
资
C
16
Problem Solutions – Chapter 6
39
2
6-51.
module dff_v(CLK, RESET, D, Q);
input CLK, RESET, D;
output Q;
reg state;
assign
D_in[0] = C[0] ^ Q[0],
D_in[1] = C[1] ^ Q[1],
D_in[2] = C[2] ^ Q[2],
D_in[3] = C[3] ^ Q[3];
:
69
assign Q = state;
always @(posedge CLK or posedge RESET)
begin
if (RESET)
state <= 0;
else
state <= D;
end
endmodule
料
群
dff_v
g1(Clock, Reset, D_in[0], Q[0]),
g2(Clock, Reset, D_in[1], Q[1]),
g3(Clock, Reset, D_in[2], Q[2]),
g4(Clock, Reset, D_in[3], Q[3]);
endmodule
资
module Counter_4bit (Clock, Reset, EN, Q, CO) ;
wire [3:0] C, D_in;
欢
迎
加
入
湖
南
大
学
// (continued in next column)
考
试
input Clock, Reset, EN ;
output [3:0] Q ;
output CO ;
wire[3:0] Q ;
05
C[0] = EN,
C[1] = C[0] & Q[0],
C[2] = C[1] & Q[1],
C[3] = C[2] & Q[2],
CO = C[3] & Q[3];
// Positive Edge-Triggered D Flip-Flop with Reset:
68
// 4-bit Binary Counter
17
Problem Solutions – Chapter 6
39
2
6-52. *
library IEEE;
use IEEE.std_logic_1164.all;
:
69
05
68
entity reg_4_bit is
port (
CLEAR, CLK: in STD_LOGIC;
D: in STD_LOGIC_VECTOR (3 downto 0);
Q: out STD_LOGIC_VECTOR (3 downto 0)
);
end reg_4_bit;
process (CLK, CLEAR)
begin
if CLEAR = ‘0’ then
Q <= “0000”;
elsif (CLK’event and CLK= ‘1’) then
Q <= D;
end if;
end process;
群
architecture reg_4_bit_arch of reg_4_bit is
begin
--asynchronous RESET active Low
资
料
--CLK rising edge
大
学
考
试
end reg_4_bit_arch;
南
6-53.
湖
library IEEE;
use IEEE.std_logic_1164.all;
加
入
entity reg_4_bit is
port (
LOAD, CLK: in STD_LOGIC;
D: in STD_LOGIC_VECTOR (3 downto 0);
Q: out STD_LOGIC_VECTOR (3 downto 0)
);
end reg_4_bit;
architecture reg_4_bit_load_arch of reg_4_bit is
begin
process (CLK)
begin
if (CLK’event and CLK= ‘1’) then --CLK rising edge
if LOAD = ‘1’ then
Q <= D;
end if;
end if;
end process;
endreg_4_bit_load_arch;
欢
迎
-- (continued in next column)
18
Problem Solutions – Chapter 6
39
2
6-54.
architecture counter_4_bit_arch of counter_4_bit is
component dff
port(CLK, RESET, D: in std_logic;
Q: out std_logic
);
end component ;
signal D_in, C, Q_out: std_logic_vector(3 downto 0);
architecture pet_pr of dff is
-- Implements positive edge-triggered bit state storage
-- with asynchronous reset.
signal state: std_logic;
begin
Q <= state;
process (CLK, RESET)
begin
if (RESET = ‘1’) then
state <= ‘0’;
else
if (CLK’event and ClK = ‘1’) then
state <= D;
end if;
end if;
end process;
end;
:
69
料
群
D_in(0) <= C(0) xor Q_out(0);
D_in(1) <= C(1) xor Q_out(1);
D_in(2) <= C(2) xor Q_out(2);
D_in(3) <= C(3) xor Q_out(3);
考
试
资
bit0: dff
port map (Clock, Reset, D_in(0), Q_out(0));
bit1: dff
port map (Clock, Reset, D_in(1), Q_out(1));
bit2: dff
port map (Clock, Reset, D_in(2), Q_out(2));
bit3: dff
port map (Clock, Reset, D_in(3), Q_out(3));
Q <= Q_out;
end counter_4_bit_arch;
欢
迎
加
入
湖
南
大
学
library IEEE;
use IEEE.std_logic_1164.all;
entity counter_4_bit is
port (
Clock, Reset, EN: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR (3 downto 0);
CO: out STD_LOGIC
);
end counter_4_bit;
begin
C(0) <= EN;
C(1) <= C(0) and Q_out(0);
C(2) <= C(1) and Q_out(1);
C(3) <= C(2) and Q_out(2);
CO <= C(3) and Q_out(3);
05
68
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(CLK, RESET, D: in std_logic;
Q : out std_logic);
end dff;
19
Problem Solutions – Chapter 6
39
2
6-55. *
6-56.
大
南
欢
迎
加
入
湖
always @(posedge CLK)
begin
if (LOAD)
Q = D;
end
endmodule
学
考
module register_4_bit_load (D, CLK, LOAD, Q) ;
input [3:0] D ;
input CLK, LOAD ;
output [3:0] Q ;
reg [3:0] Q ;
试
资
料
群
:
69
always @(posedge CLK or negedge CLR)
begin
if (~CLR)
//asynchronous RESET active low
Q = 4’b0000;
else
//use CLK rising edge
Q = D;
end
endmodule
05
input [3:0] D ;
input CLK, CLR ;
output [3:0] Q ;
reg [3:0] Q ;
68
module register_4_bit (D, CLK, CLR, Q) ;
20
Problem Solutions – Chapter 6
if W = ‘1’ then
next_state <= STB;
else
next_state <= STA;
end if;
when STB =>
if X = ‘0’ and Y = ‘1’ then
next_state <= STA;
else
next_state <= STC;
end if;
when STC =>
next_state <= STA;
end case;
end process;
68
library IEEE;
use IEEE.std_logic_1164.all;
entity prob_6_57 is
port (clk, RESET, W, X, Y : in STD_LOGIC;
Z : out STD_LOGIC);
end prob_6_57;
05
architecture process_3 of prob_6_57 is
type state_type is (STA, STB, STC);
signal state, next_state: state_type;
begin
:
69
-- Process 1 - state register
state_register: process (clk, RESET)
begin
if (RESET = ‘1’) then
state <= STA;
else if (CLK’event and CLK=’1’) then
state <= next_state;
end if;
end if;
end process;
群
料
学
6-58. *
-- Process 3 - output function
output_func: process (X, Y, state)
begin
case state is
when STA =>
Z <= ‘0’;
when STB =>
if X = ‘0’ and Y = ‘0’ then
Z <= ‘1’;
else
Z <= ‘0’;
end if;
when STC =>
Z <= ‘1’;
end case;
end process;
end process_3;
资
试
考
-- Process 2 - next state function
next_state_func: process (W, X, Y, state)
begin
case state is
when STA =>
-- Continued in next column
next_state <= STA;
STB: if (X == 0 & Y == 1)
next_state <= STA;
else
next_state <= STC;
STC:
next_state <= STA;
endcase
大
// State Diagram in Figure 6-38 using Verilog
module prob_6_58 (clk, RESET, W, X, Y, Z);
input clk, RESET, W, X, Y;
output Z;
南
reg[1:0] state, next_state;
parameter STA = 2’b00, STB = 2’b01, STC = 2’b10;
reg Z;
湖
end
// State Register
always@(posedge clk or posedge RESET)
begin
if (RESET == 1)
state <= STA;
else
state <= next_state;
end
// Next StateFunction
always@(W or X or Y or state)
begin
case (state)
STA: if (W == 1)
next_state <= STB;
else
// (continued in the next column)
// Output Function
always@(X or Y or state)
begin
Z <= 0;
case (state)
STB: if (X == 0 & Y == 0)
Z <= 1;
else
Z <= 0;
STC:
Z <= 1;
endcase
end
endmodule
入
加
迎
欢
39
2
6-57. *
21
Problem Solutions – Chapter 7
CHAPTER 7
39
2
© 2016 Pearson Education, Inc.
a) A  16, D  8
b) A  19, D  32
c)
A  26, D  64
d) A  31, D  1
(835)10  (11 0100 0011)2 , (15, 103)10  (00111010 1111 1111)2
(513)10 = (10 0000 0001)2, (44,252)10 = (1010 1100 1101 1100)2
:
69
a)
b)
05
7-2.
7-3.*
群
Number of bits in array =  216  24  220  210  210
68
7-1.*
Row Decoder size = 210
料
a) Row Decoder = 10 to 1024, AND gates  210  1024 (assumes 1 level of gates with 10 inputs/gate)
Column Decoder = 6 to 64, AND gates = 26 = 64 (assumes 1 level of gates with 6 inputs/gate)
资
Total AND gates required = 1024 + 64 =1088
试
b) (32000)10  (0111110100 000000)2 , Row  500, Column  0
考
7-4.
a) Number of RAM cell arrays  8 (2G  231 ) / (214  214  228 )  (23  8)
a) Number of RAM cell array s = 8(2G = 231)/(214 x 214 = 228) = (23 = 8)
学
b)
b)
A28 A29 A30
大
S0
S1
S2
0 1 2 3 4 5 6 7
南
Each line is connected to the respective array decoder enable
15 row pins + 14 column pins  229  512 M addresses
入
湖
7-5.
7-6.
迎
加
With 4-bit data, the RAM cell array contains 232/22 = 230 words.
The number of address pins is 30/2 = 15.
欢
7-7.
Interval between refreshes = 64ms/8192 = 7.8125 μs
Using the 60 ns refresh time from the text example, total time for refresh = 8192 × 60 ns = 0.49 ms
Minimum number of pins = 13
1
Problem Solutions – Chapter 7
7-8.*
2 MB/128 K × 16 = 2MB/ 256 KB = 8
b)
With 2 byte/word, 2MB/2 B  220 , Add Bits = 20
128K addresses per chip implies 17 address bits. c) 3 address lines to decoder, decoder is 3-to-8-line
南
大
学
考
试
资
料
群
:
69
05
68
7-9.
39
2
a)
7-10.
A DDR SDRAM uses both the positive and negative edges of the clock to transfer data. This
allows the DRAM to transfer twice as much data while keeping the same clock frequency.
欢
迎
7-11.
加
入
湖
An SDRAM simultaneously reads the desired row and stores all of the information in the I/O
logic. Next the desired column is read from the I/O logic and the data appears on the output.
During burst transfers, the subsequent data words are read from the I/O logic and placed on the
output. This occurs for the predetermined number of words known as the burst length. For burst
transfers, this is faster since the row has already been pre-read.
2
Problem Solutions – Chapter 8
CHAPTER 8
39
2
© 2016 Pearson Education, Inc.
8-1.
05
68
log2 64  6 lines/mux or decoder
8-2.*
:
69
C  C8
V  C8  C7
Z  F7  F6  F5  F4  F3  F2  F1  F0
群
N  F7
XX= 
S0S
A0 A
+ S0AS0 A
A0
D0
A0
D1
考
试
0
D0
A1
D1
Adder
学
C2
D0
D1
D2
0
大
南
湖
入
C1
S1 S0
D3
Ci
S1
S0
Ai
Y = B S1 S0 + B S1
S1 S0
D0
0
D1
Bi
D2
Bi
D3
欢
迎
Bi
1
G0
X
B1
Y  BS1S0  BS1
加
D3
S1 S0
S1
S0
= A S1
A S0
X X AS1
 +AS0
Adder
Y
D2
Y
S
8-4.*
C0
X
D1
S
A1
Cin
D0
资
C B SS B SS BS S C
YY= SS
1 1CininB + S11S00 B + S11S00B + S11S00Cin
B0
料
8-3.*
X
FA
Gi
Y
CI +
1
G1
Problem Solutions – Chapter 8
8-5.
Connect
tofor
Cin
for
first stage.
Connect
Cin
for
first
stage.
Connect
totoCin
first
stage.
GGi i
FA
FA
YY
00
: GGG
 =A=AAB
00:
++(Add)
BB(Add)
00:
(Add)
01:
G
A
1
(Increment)


01:
01:GG==AA++11(Increment)
(Increment)
10
: GG
A=A
A1–(Decrement)
10:
10:
G=
–11(Decrement)
(Decrement)
11:
G

A

B

1
(Subtract)
11:
11:GG==AA++ BB++11(Subtract)
(Subtract)
CCi +1
i +1
SS11SS00
Cascade
Cascadefour
foursuch
suchstages,
stages,connecting
connectingthe
thecarries.
carries.
SS CCinin
68
AAi i
05
00
11
22
33
BBi i
00
11
BBi i
XX
39
2
CCi i
MUX
MUX
8-6.*
a)
XOR  00, NAND  01,
b)
Out  S1AB  S1AB  S1AB  S1S0AB  (one of S 0AB  S1S 0A)
The above is a simplest result.
XNOR  11
料
群
NOR  10
:
69
Cascade four such stages, connecting the carries.
S1
S0
Operation
S2
S1
S0
Operation
0
0
0
A B
1
0
0
sr A
0
0
1
A  B 1
1
0
1
A∨ B
0
1
0
B
1
1
0
0
1
1
B 1
1
1
1
考
试
S2
资
8-7.+
sl A
迎
加
入
湖
南
大
学
A∧ B
欢
8-8.*
(a) 1010
(b) 1110
(c) 0101
2
(d) 1101
Problem Solutions – Chapter 8
BA
MB
FS
MD
RW
---
---
-
----
1
1
(b)
100
000
000
0
1010
0
1
(c)
001
100
---
-
1101
0
1
(d)
011
011
---
-
0001
0
1
(e)
010
010
---
-
1110
0
1
(f)
001
010
100
0
1010
0
(g)
111
001
011
0
0010
0
(h)
100
101
---
0
0101
0
1
1
1
:
69
8-10.*
68
AA
011
05
DA
(a)
39
2
8-9.
R5  R4  R5
R5 = 0000 0100
(d)
R5  R0
R5 = 0000 0000
(b)
(c)
R6  R2  R4  1
R5  R0
R6 = 1111 1110
R5 = 0000 0000
(e)
(f)
R4 ← srConstant
R3 ← Data in
R4 = 0000 0011
R3 = 0001 1011
料
8-11.
资
R3  R3  R1, R3  01100111
试
R4  R4  R1, R4  01110100
R5  R5  R1, R5  01101100
群
(a)
R6  R6  R1  1, R6  01100001
R7  R7  R1  1, R7  01101001
R1  R7, R1  01101001
考
R1  R1, R1  11011111
R1 ... R7 = i, D, g, t, l, a, i Unscrambled is Digital
R1  R1  1, R1  1100000
学
8-12.
b) 32
c) 0 to 65,535
大
a) 64
南
8-13.*
湖
a) Opcode = 8 bits
c) 262,144
–32,768 to +32,767
d) +131,071 and –131,072
Distinct Opcodes = 4 + 16 + 127 = 148
欢
迎
加
入
8-14.
b) 18 bits
d)
3
Problem Solutions – Chapter 8
AA
BA
MB
FS
MD
RW
MW
PL
JB
R[0]  R[7]  R[3]
000
111
011
0
1010
0
1
0
0
x
R[1]  M [ R[4]]
001
100
xxx
x
xxxx
1
1
0
0
x
R[2]  R[5]  2
010
101
xxx
1
0010
0
1
0
0
R[3]  sl R[6]
011
xxx
110
0
1110
0
1
0
0
if R[4]  0 then
PC  PC  se PC
xxx
100
xxx
x
0000
x
0
0
x
1
0
DR
SA
SB or Operand
R[0]  R[7]  R[6]
000 0010
000
111
110
R[1]  R[5]  1
000 0110
001
110
000
R[2]  sl R[4]
000 1110
010
000
R[3]  R[3]
000 1011
011
011
R[4]  R[2]  R[1]
000 1001
100
010
群
Operation Code
100
料
000
001
资
Instruction Register Transfer
x
05
else PC  PC  1
68
DA
:
69
Instruction Register Transfer
39
2
8-15.
MB: B15 - Correct for table specification
RW: B14 - Correct for table specification
考
MD: B13 - Correct for table specification
试
8-16.
学
MW: B15B14 - Correct for table specification
PL: B15 B14 - Correct for table specification
大
JB: B13 - Correct for table specification
BC: B9 - Correct for table specification
湖
南
FS: The logic gives 0000 for FS for PL =1 which selects the value on the A input to the Function Unit to be evaluated for
branches and blocks the value on bit 9 which is otherwise used as BC for branches. For PL = 0, the normal bits for FS are
passed as required from the op code. Correct.
欢
迎
加
入
8-17.
Instruction
Code
ADD R0, R1, R2
000 0101 000 001 010
Registers/Memory changed
SUB R3, R4, R5
000 001 011 100 101
R0 = 3
SUB R6, R7, R0
000 0101 110 111 000
R3 = -1
ADD R0, R0, R3
000 0101 000 000 011
R6 = 4
SUB R0, R0, R6
000 0101 000 000 110
R0 = 2
ST R7, R0
010 0000 000 111 000
R0 = -2
LD R7, R6
011 0000 111 110 000
M[7] = -2
ADI R0, R6, 2
100 0010 000 110 000
R7 = M[4]
ADI R3, R6, 3
100 0010 011 110 011
R0 = 6
R3 = 7
4
Problem Solutions – Chapter 8
8-18.
39
2
R[4]  R[4]  R[4]
V and C are produced by the arithmetic circuit. For the XOR FS code, S1 = 0, S0 = 1. and Cin = 0, giving
arithmetic operation Add. For arbitrary contents in R[4], the values of C and V are a function of the sign and
value of the contents of R4 and are unpredicable.
Next
IL PS DX AX
State
05
68
8-19.
State
Opcode
VCNZ
(a)
EX0
0000101
xxxx
EX1
0
01 0xxx 0xxx 0xxx 0 0101 0
1
0
0
(b)
EX0
0001101
xxxx
INF
0
01 1000 xxxx 1000 0 1101 0
1
0
0
EX0
1100000
xxx0
INF
0
10 xxxx 0xxx xxxx x 0000 0
0
0
0
EX0
1100000
xxx1
INF
0
01 xxxx 0xxx xxxx x 0000 0
0
0
0
EX0
0000000
xxxx
INF
0
01 0xxx 0xxx xxxx x 0000 0
1
0
0
(d)
群
(c)
BX MB FS MD RW MM MW
:
69
Part
Instruction
Z
Next State
EX0
R8 RSA
0
EX1
EX1
R9 zfOP
0101100111000111
x
0
EX2
EX2
R8 srR8
0101100111000111
5
0
EX3
EX3
R9 R9 – 1
0010110011100011
5
0
EX2
EX2
R8 srR8
0010110011100011
4
0
EX3
EX3
R9 R9 – 1
0001011001110001
4
0
EX2
EX2
R8 srR8
0001011001110001
3
0
EX3
EX3
R9 R9 – 1
0000101100111000
3
0
EX2
R8 srR8
0000101100111000
2
0
EX3
R9 R9 – 1
0000010110011100
2
0
EX2
EX2
R8 srR8
0000010110011100
1
0
EX3
EX3
R9 R9 – 1
0000001011001110
1
1
EX4
EX4
RDRR8
0000001011001110
0
0
INF
INF
-
0000001011001110
0
-
-
考
学
大
南
迎
加
入
湖
EX3
试
State
EX2
R8
资
料
8-20.
R9
8-21.+
欢
Removal of the two decisions on zero operations does not affect the number of states in the state machine diagram. The reason for
this is that the same states are required because the datapath of the computer only supports one register transfer per clock cycle.
The transfers required by the instruction execution force the state structure. As a consequence, there can be no reduction of the
number of clock cycles required to execute the instructions. The new state machine diagram is actually a worst case in terms of
execution time for the instruction execution. The two decisions can only improve the execution times. So the analysis suggested is
unnecessary.
5
Problem Solutions – Chapter 8
39
2
8-22.
R8  R  SB 
Next
State
IL
PS
DX
EX0 0010001 xxxx
EX1
0
00
1000 xxxx 0xxx
0
EX1 0010001 xxxx
EX2
0
00
1001 0xxx xxxx
EX2 0010001 xxxx
INF
0
01
0xxx 1000 1001
BX
MB
FS
MD
RW
MM
MW
1100
0
1
0
0
x
xxxx
1
1
0
0
0
0010
1
0
0
0
料
AX
群
State Opcode VCNZ
资
8-23.
:
69
R  DR   R8 + R9 ,PC  PC + 1
05
68
R9  M  R  SA  
Partial state machine diagram: R8  R8
试
R8  R8  R8
R  DR   R  SA  + R  SB 
考
Z   Opcode = 1000110 
V   Opcode = 1000110
V   Opcode = 1000110
学
PC  PC + 1
Z   Opcode = 1000110
大
PC  PC + 1
R8  R8 + 1
加
欢
迎
AOV
BRV
PC  PC + se AD
Opcode
VCNZ
Next
State
IL PS
EX0
1000101
xxxx
EX1
0
00 0xxx 1000 1000
0
1010
0
1
x
0
EX1
1000101
1xxx
EX2
0
00 0xxx 0xxx 0xxx
0
0010
0
1
x
0
EX1
1000101
0xxx
INF
0
01 0xxx 0xxx 0xxx
0
0010
0
1
x
EX2
1000101
xxxx
INF
0
01 1000 1000 xxxx
0
0001
0
1
x
0
EX0
1000110
xxx0
EX3
0
00 1000 1000 xxxx
x
0000
0
1
x
0
EX0
1000110
xxx1
INF
0
01 1000 1000 xxxx
x
0000
0
1
x
0
EX3
1000110
xxxx
INF
0
10 xxxx xxxx xxxx
x
xxxx
0
0
x
0
State
入
Part
湖
南
PC  PC + 1
6
DX
AX
BX
MB
FS MD RW MM MW
Problem Solutions – Chapter 8
Partial state machine diagram:
R8  R8  R8
R 9  R  SA  – R  SB 
05
68
Z   Opcode = 0010001 
39
2
8-24.
R8  R8 + 1
:
69
Z  N   Opcode = 0010001 
PC  PC + 1
R  DR   R8 + 1
Z  N   Opcode = 0010001 
PC  PC + 1
State Opcode VCNZ Next
State
群
PC  PC + 1
IL
PS
DX
AX
BX
MB
FS
MD
RW
MM
MW
EX1
0
00
1000
1000
1000
0
1010
0
1
0
0
EX1 0010001 xxx1
EX3
0
00
1001
0xxx
0xxx
0
0101
0
1
0
0
EX1 0010001 xx00
EX2
0
00
1001
0xxx
0xxx
0
0101
0
1
0
0
EX1 0010001 xx10
INF
0
01
1001
0xxx
0xxx
0
0101
0
1
0
0
EX2 0010001 xxxx
EX3
00
1000
1000
xxxx
x
0001
0
1
0
0
EX3 0010001 xxxx
INF
01
0xxx
1000
xxxx
x
0001
0
1
0
0
资
试
考
学
0
料
EX0 0010001 xxxx
8-25.
大
Partial state machine diagram, assuming the opcode for the new instruction is 0001111:
南
From INF
Opcode  0001111 - R8  R[SB]
EX1
Opcode  0001111 - R[DR]  R[SA]  R8,PC  PC  1
To INF
欢
迎
加
入
湖
EX0
7
Problem Solutions – Chapter 8
39
2
8-26.
68
The operation code used for SMR and these instructions is 0111111 which is easy to generate by complementing all 0’s. The word
to be stored in memory is built in a register by complementing all 0’s and ANDing the result with the value of SB from the
original instruction. The register value generated is incremented, stored in memory and loaded into the IR after the execution of
each transfer from a register to a memory location.
State
Opcode
VCNZ
Next
State
R8  R[SA]
EX0
0111111
xxxx
EX1
0
00 1000 0xxx xxxx
R9  R9  R9 (R9  0)
EX1
0111111
xxxx
EX2
0
0
1001 1001 1001
0
1010
0
R9  R9
EX2
0111111
xxxx
EX3
0
0
1001 1001 xxxx
x
1011
R10  sr R9
EX3
0111111
xxxx
EX4
0
0
1010 1001 xxxx
x
R9  R10  zf SB
EX4
0111111
xxxx
EX5
0
0
1001 1010 xxxx
R11  zf SB
EX5
0111111
xxxx
EX6
0
0
M[R10]  R9
EX6
0111111
xxxx
EX7
IR  M[R10]
EX7
0111111
xxxx
EX8
M[R8]  R[SB]
EX8
0111111
xxxx
R8  R8  1
EX9
0111111
xxxx
R9  R9  1
EX10
0111111
R11  zf SB, Z : EX5
EX11
R11  zf SB, Z : INF, inc PC
EX11
BX
0
0000
1
1
0
0
1
0
0
0
1
0
0
1101
0
0
0
0
1
1000
0
1
0
0
群
料
1011 xxxx xxxx
1
1100
0
1
0
0
xxxx 1010 1001
0
xxxx
x
0
0
1
1
0
xxxx 1010 xxxx
x
xxxx
x
0
0
0
EX9
0
0
xxxx 1000 0xxx
0
xxxx
1
1
0
0
EX10
0
0
1000 1000 xxxx
x
0001
0
1
0
0
xxxx
EX11
0
0
1001 1001 xxxx
x
0001
0
1
0
0
0111111
xxx0
EX5
0
0
xxxx 1011 xxxx
1
0101
x
0
0
0
0111111
xxx1
INF
0
01 xxxx 1011 xxxx
1
0101
x
0
0
0
考
学
大
试
0
南
0
MB FS MD RW MM MW
05
AX
:
69
DX
资
IL PS
欢
迎
加
入
湖
Register Transfer
8
Problem Solutions – Chapter 8
39
2
8-27.
68
Since the condition codes are not fully available to the programmer (only N and Z are used by instructions, not V and C), the approach
of problem 6-1, part c, for a signed comparison using the N and V bits is not possible. Instead the program must make the comparisons
based upon the signs of the current minimum value and the current array element.
料
群
:
69
05
// Assembly for the solution to problem 8-27
// Logic and Computer Design Fundamentals, 5th edition
//
// The problem specifies that the pointer to the array is in memory address 0,
// the length is in address 1, and the result should be stored in address 2.
//
// Register usage
// R0: Pointer to current location in array
// R1: Loop variable for the array length remaining to be checked
// R2: Temporary variable for current array element value
// R3: The current minimum values
// R4: Pointer to where the result will be stored
// R5: Temporary variable for comparisons of the current minimum value and current array
element
//
// Using labels for locations to make the targets of branches and jumps more clear
欢
迎
加
入
湖
南
大
学
考
试
资
LDI R0, 0
// Read in pointer to array and its length
LDI R1, 1
LD R0, R0
LD R1, R1
LDI R4, 2
// Set R4 to point to the location for storing the result
LD R3, R0
// R3 = array[0]
DEC R1, R1
BRZ R1, done
// handling the case where the array is only one element
INC R0, R0
loop: LD R2, R0
// temporary = array[i]
XOR R5, R3, R2 // Compare the signs of current minimum and temporary
BRN R5, different_signs
SUB R5, R3, R2 // If same sign, min = temporary if result of subtraction
//is positive or zero
BRN no_new_min
new_min: MOV R3, R2
no_new_min: DEC R1, R1 // Update loop variable
BRZ R1, done
INC R0, R0
// Point to the next array element
JMP loop
different_signs:
BRN R3, no_new_min // If different signs and current minimum is negative,
// it is still the minimum
JMP new_min
done:
ST R4, R3
// Save the minimum to memory
end: JMP end
// Infinite loop because there's no halt instruction
9
Problem Solutions – Chapter 9
CHAPTER 9
39
2
© 2016 Pearson Education, Inc.
b) MOV
T1, A
R2, B
ADD
T1, B
c) LD
ADD
A
B
LD
R3, C
SUB
T1, C
SUB
C
LD
R4, D
MOV
T2, D
ST
T1
LD
R5, E
SUB
T2, E
LD
D
ADD
R1, R1, R2
R1, R1, R3
T1, T2
X, T1
SUB
SUB
MUL
MOV
SUB
R4, R4, R5
MUL
ST
R1, R1, R4
X, R1
05
R1, A
LD
:
69
a) LD
68
9-1.
E
T1
X
料
群
MUL
ST
a) LD
R1, E
b) MOV
LD
R2, F
ADD
MUL
R1, R1, R2
MUL
LD
R2, D
LD
R2, C
MUL
F
ST
T1
MOV
T2, E
LD
D
MUL
T2, F
SUB
T1
MOV
T3, D
ST
T1
T3, T2
LD
A
T1, T3
Y, T1
ADD
B
MUL
C
DIV
ST
T1
Y
R1, R2, R1
LD
R2, A
DIV
MOV
学
DIV
大
R3, B
R2, R2, R3
MUL
ST
R1, R1, R2
Y, R1
南
ADD
湖
9-3.*
E
T1, C
SUB
LD
c) LD
试
R1, R2, R1
T1, A
T1, B
考
SUB
资
9-2.*
入
a) (A  B)  (A  C)  (B  D)  AB  AC  xBD  x
PUSH A
PUSH B
SUB
PUSH A
PUSH C
A
B
A-B
A
C
A+C
A-B
A
A-B
欢
迎
加
b, c)
A
ADD
A-B
MUL
PUSH B
PUSH D
SUB
MUL
(A-B) × (A+C)
B
D
B-D
(A-B) × (A+C) × (BD)
B
(A-B) × (A+C)
(A-B) × (A+C)
(A-B) × (A+C)
1
POP X
Problem Solutions – Chapter 9
9-4.
PUSH B
MUL
PUSH C
ADD
PUSH D
A
B
A×B
C
(A × B) +C
D
PUSH E
PUSH A
E
((A × B)+C) × D
((A × B)+C) × D
PUSH F
MUL
A
F
A× F
E
A
((A × B)+C) × D
E
E - (A × F)
((A × B)+C) × D
群
POP Y
SUB
E
((A × B)+C) × D
DIV
05
MUL
(A × B)+C
68
A×B
A
:
69
b, c)
PUSH A
9-5.
ZY
b)
c) Z  Y  W  2 d)
Z  M[Y]
ZYX
学
a)
考
试
资
料
(((A × B)+C) × D) ÷ (E - (A × F))
大
9-6.*
a) X = 195 – 208 – 1 = –14
b) X = 1111 1111 1111 0010
南
The number is negative because the branch is backwards. The  1 assumes that the PC has
been incremented to point to the address after that of the address word of the instruction.
湖
9-7.
欢
迎
加
入
a)
X = 1000 – 144 – 1 = 855 b) X = 0000 0011 0101 0111
The number is negative because the branch is backwards. The − 1 assumes that the PC has
been incremented to point to the address after that of the address word of the instruction.
9-8.
a) Read Instruction
Read Address Field
Read Effective Address
Read Operand
Read Address Field
Read Effective Address
Read Operand
Write Result
8 Memory Accesses
b) Read Instruction
Read Address Field
Read Effective Address
Read Operand
Read Address Field
Read Effective Address
Write Result
7 Memory Accesses
2
39
2
a) ((( A  B)  C )  D  ( E  ( A  F ))  AB  C  D  EAF    Y
Problem Solutions – Chapter 9
9-9.
2410
b) Immediate 551
2410 + 2310 = 4720
c) Relative
552 + 2410 = 2962
39
2
a) Direct
d) Indexed
3 Register Fields × 4 bits/Field = 12 bits. 32 bits − 12 bits = 20 bits. 220  1048576
64 < 100 < 128 => 7 bits. 2 Register Fields × 4 bits/Field => 8 bits. 32 bits - 7 bits - 8 bits => 17 Address Bits
05
a)
b)
68
9-10.*
LDI
R6, TOSAD
# Load R6 with address of the Top of Stack
Push and Pop can be implemented in one of two ways.
Method 2
RX, (R6)+
POP RX:
LD
RX,–(R6)
or
ST
RX, –(R6)
LD
RX, (R6)+
料
ST
群
Method 1
PUSH RX:
:
69
9-11.
资
9-12.
PSHR and POPR work as follows:
MSPR0
POPR:
SPSP – 1
南
SPSP – 1
入
湖
9-13.
a) ADD R0, R4
SPSP + 1
R0MSP
LD
R[DR] ADRS
ST
ADRS R[SB]
where ADRS is a memory address.
b) R07B + 4B,
R0 = C6,
C=0
ADC
R1, R5
R124 + ED + 0,
R1 = 11,
C=1
ADC
ADC
R2, R6
R3, R7
R2C6 + 57 + 1,
R31F + 00 + 1
R2 = 1E,
R3 = 20,
C=1
C=0
欢
迎
加
9-14.*
R6MSP
.
.
.
考
大
MSPR7
SPSP + 1
学
MSPR1
SPSP – 1
.
.
.
SPSP + 1
R7MSP
试
PSHR:
3
Problem Solutions – Chapter 9
9-15.
AND:
AND:
0100 1000 OR:
0001 0001 OR:
1110 1111
0111 1001
XOR: 1010 0111
XOR: 0110 1000
b) XOR with (AAAA)16
c) AND with (A A A A)16
05
a) OR with (FF0016
68
9-16.
39
2
a)
b)
:
69
9-17.*
C
0110 1001
1
SHR
0011 0100
1
SHL
0110 1000
0
SHRA
0011 0100
0
SHLA
0110 1000
ROR
0011 0100
ROL
0110 1000
0
RORC
0011 0100
0
ROLC
0110 1000
0
料
Register
0
资
0
考
试
OP
群
Result
学
9-18.
() 0.123450000  105
大
( ) 0.0000000071234 105
南

Smallest Number
Largest Number
0.5
× 2–255
–26
(1 – 2 ) × 2+255
=
=
欢
迎
加
入
湖
9-19.*
() 0.123449993 105 Result  0.123449993 105
4
Problem Solutions – Chapter 9
1111
14
1110
+6
13
1101
+5
12
1100
+4
11
1011
+3
10
1010
+2
9
1001
+1
8
1000
0
7
0111
–1
6
0110
–2
5
0101
–3
4
0100
–4
3
0011
–5
2
0010
–6
1
0001
–7
0
0000
68
15
+7
05
+8
:
69
(e)2
群
e
资
料
E
39
2
9-20.*
9-21.
The largest quantity is 0 1111 11111 = 27 × (0.111111)2 = (1111110)2 = 126. The
smallest quantity is 0 0000 00001 = 2-8 × (0.100001)2 = (0.00000000100001)2 =
0.00201416015625
5.675 = (101.101)2 to six binary digits, which is equal to (0.101101)2 × 23. The 4bit excess 8 exponent would be 1011, and the normalized fraction would be stored
as 01101. So using this floating point format, -5.675 = 1 1011 01101.
试
a)
学
考
b)
a) (  1)sign  2exponent 1023  (1.fraction)
b) –1022
=
(000 0000 0001)2
–1
=
(011 1111 1110)2
0
=
(011 1111 1111)2
+1
=
(100 0000 0000)2
+1023
=
(111 1111 1110)2
c) Largest
=
(2 – 2–52) × 2+1023
Smallest
=
1 × 2–1022
入
湖
南
大
9-22.
欢
迎
加
9-23.
If 2x  10y then:
x log10 2  y log1010
log10 2  0.3, log1010  1
0.3 x = y
Largest is 2127  (2  223 )  2128  2104  100.3128  100.3104  2.5 1038
Smallest is 2126  100.3126  1037.8  1.58 1038
5
Problem Solutions – Chapter 9
9-24.
9-25.*
TEST
BNZ
(0001)16, R
ADRS
(AND Immediate 1 with Register R)
(Branch to ADRS if Z = 0)
:
69
9-26.
Unsigned
A=
1011 0110
182
B=
0011 0111
55
A + B = 1110 1101
C=0, Z=0, N=0, V=0
BNZ, BNC, BNN, BNV
− 74
55
− 19
237
C=0, Z=0, N=1, V=0
BNZ, BNC, BN, BNV
料
b)
c)
d)
Signed
群
a)
资
9-27.*
A=
0101 1101
B=
0101 1100
A–B=
0000 0001
b)
C (borrow) = 0,
Z=0
c)
BA, BAE, BNE
93
−92
1
考
试
a)
A=
1101 1010
–38
B=
0111 0110
–(118)
大
学
9-28.
00010000
100
a)
A–B =
南
b) N = 0, Z = 0, V = 1
c) BL, BLE, BNE
a)
A=
1010 0100
–92
B=
1010 1001
–(-87)
1111 1011
-5
A–B =
b) N = 1, Z = 0, V = 0
c) BL, BLE, BNE
迎
加
入
湖
9-29.
欢
9-30.*
PC
SP
TOS
a) Initially
2000
4000
5000
b) After Call
c) After Return
0502
2002
4001
4000
2002
5000
6
68
39
2
-9.359375 is stored as C115C000 in IEEE single-precision floating point format.
41CBA000 is the IEEE single-precision floating point representation of 25.453125.
05
a)
b)
Problem Solutions – Chapter 9
9-31.
a) R7 ← PC
39
2
PC points to the next instruction in sequence
68
PC ← M [PC – 1]
PC Gets Effective address
b) R7 must be saved to memory.
9-32.
The processor jumps to a new location without the ability to return on its own.
A jump with a way for the processor to return to the instruction after the one that caused
the jump.
A jump initiated by an event, not an instruction. A way to return to the first uncompleted
instruction is provided.
05
Branch Instruction:
Call Instruction:
:
69
Program Interrupt:
Internal Interrupts:
1) Overflow
2) Divide by zero
3) Invalid opcode
4) Memory stack overflow
5) Protection violation
资
料
External Interrupts:
1) Hard Drive
2) Mouse
3) Keyboard
4) Modem
5) Printer
群
9-33.*
考
试
A software interrupt provides a way to call the interrupt routines normally
associated with external or internal interrupts by inserting an instruction into
the code. Privileged system calls for example must be executed through
interrupts in order to switch from user to system mode. Procedure calls do
not allow this change.
学
9-34.
PSR MSP
SP SP + 1
PCMSP
SP SP + 1
Begin fetch of next instruction following
the one for which the interrupt occurred.
入
湖
南
大
a) SP SP – 1
b)
MSPPC
SP SP – 1
MSPPSR
EI 0
PCIVAD
PSR MPC
PCPC + 1
Begin Fetch of Interrupt Service Routine
欢
迎
加
9-35.
a)
LD R0, PARAMETER1
LD R1, PARAMETER2
CALL PART_A_PROCEDURE
b)
PART_B_PROCEDURE:
PUSH R3
PUSH R4
/* … other instructions in the procedure…if a value is returned by the procedure, the value will be
stored in R2 just before the next two instructions… */
POP R4
POP R3
RET
7
Problem Solutions – Chapter 10
CHAPTER 10
39
2
© 2016 Pearson Education, Inc.
10-1.
05
68
a) Maximum frequency = 1/pipe stage delay = 1/0.8 ns = 1.25 GHz.
b) The latency time = 0.8 ns × 3 = 2.4ns.
c) The maximum throughput is 1 instruction per cycle or 1.25 billion instructions per second.
10-2.*
:
69
a) The latency time = 0.5 ns × 8 = 4.0 ns.
b) The maximum throughput is 1 instruction per cycle or 2 billion instructions per second.
c) The time required to execute is 10 instruction + 8 pipe stages -1 = 17 cycles *0.5ns = 8.5ns
IR
Data A
Data B
X
X
X
LDI R1, 1
X
X
N+2
LDI R2, 2
-1
1
N+3
LDI R3, 3
-1
N+4
LDI R4, 4
-1
N+5
LDI R5, 5
-1
N+6
LDI R6, 6
N+7
LDI R7, 7
X
N+10
X
Reg
X
X
X
X
X
X
2
1
X
3
2
R1 = 1
3
R2 = 2
5
4
R3 = 3
-1
6
5
R4 = 4
-1
7
6
R5 = 5
X
X
7
R6 = 6
X
X
X
R7 = 7
试
4
-1
考
X
N+9
学
N+8
Data F
料
N
N+1
资
PC
群
10-3.
大
Data I is not used and thus, not specified.
10-4.
Load, Store, JMR
ADI, SBI, ANI, ORI, XRI, AIU, SIU
BZ, BNZ, JMP, JML
NOP
All instructions not listed above
入
湖
南
Register Indirect:
Register, Immediate:
Relative:
None:
Register:
10-5.
b) Left, SH = 1D = 29 Rt. Rotate = 64  29 = 35 = 32 + 0 + 3
47 lines = 4B4A 0000 0000,
35 lines = 2000 0000,
欢
迎
加
a) Right, SH = 0F = 15 = 0 + 12 + 3
47 lines = 0000 3DF3 CB4A,
35 lines = 0 0003 DF3C,
1
32 lines = 0000 7BE7
32 lines = 4000 0000
Problem Solutions – Chapter 10
10-6.*
39
2
68
Cycle 4:
Cycle 5:
PC = 10F
PC-1 = 110,
IR = 4418 2F0116
PC-2 = 110,
RW = 1, DA = 01, MD = 0, BS = 0, PS = X, MW = 0, FS = 2, SH = 01, MA = 0, MB =1, CS=1
BUS A = 0000 001F, BUS B = 0000 2F01
RW = 1, DA = 01, MD = 0, D0 = 0000 2F20, D1 = XXXX XXXX, D2 = 0000 00000
R1 = 0000 2F20
05
Cycle 1:
Cycle 2:
Cycle 3:
10-7.
IF PC = 10F
DOF PC-1 = 110,IR = 1A61 001D
EX PC-2 = 110,RW = 1, DA = 06, MD = 2, BS = 0, PS = X, MW = 0, FS =D, SH = 1D, MA = 0, MB = 0
Cycle 4:
Cycle 5:
BUS A = 01AB CDEF, BUS B = XXXX XXXX
RW = 1, DA = 06, MD = 0, D0 = 0000 0000, D1 = XXXX XXXX, D2 = 0000 0000
R6 = 0000 0000
群
:
69
Cycle 1:
Cycle 2:
Cycle 3:
料
10-8.
Cycle 1:
PC = 10F
Cycle 2:
PC-1 = 110,
Cycle 3:
PC-2 = 110,
RW = 1, DA = 07, MD = 2, BS = 0, PS = 0, MW = 0, FS = 5, MA = 0, MB = 0, CS = 0
BUS A = 0000 F001, BUS B = 0000 000F
RW = 1, DA = 07 MD = 0, D0 = 0000 EFF2, D1 = XXXX XXXX, D2 = 0000 0000
R7 = 0000 0000
资
试
考
Cycle 4:
Cycle 5:
IR = CA71 9400
学
10-9.
PC = 10F
Cycle 2:
Cycle 3:
PC-1 = 110,
IR = 8A21 635A
PC-2 = 110,
RW = 1, DA = 02, MD = 0, BS = 0, PS = X, MW = 0, FS=5, SH = 1A, MA= 0, MB = 1, CS=0
BUS A = 0A5F BC2B, BUS B = 0000 635A
RW = 1, DA = 02, MD = 0, D0 = 0AF5 58D1, D1 = XXXX XXXX, D2 = 0000 00000
R2 = 0AF5 58D1
南
湖
Cycle 4:
Cycle 5:
大
Cycle 1:
Answer not given; varies depending on synthesis software used.
加
入
10-10.+
10-11.*
欢
迎
MOVA R7, R6
SUB R8, R8, R6
AND R8, R8, R7
MOVA R7, R6
1
IF
SUB R8, R8, R6
AND R8, R8, R7
2
2
DOF
3
EX
4
WB
5
IF
DOF
EX
WB
IF
DOF
EX
6
Data Hazard
WB
Problem Solutions – Chapter 10
1
IF
SUB R7, R7, R2
2
DOF
3
EX
4
WB
5
IF
DOF
EX
WB
BNZ R7, 000F
IF
Data Hazards
AND R8, R7, R4
R4, R8, R2
7
Control Hazards
DOF
EX
WB
IF
DOF
EX
WB
b)
1
SUB R7,R7,R2
1
2
3
SUB R7,R7,R2 IF
NOP IF
SUB R7,R7,R2
DOF EX
NOP
BNZ R7,000F IF
NOP
BNZ R7,000F DOF
NOP
BNZ R7,000F NOP
IF
NOP
NOP
NOP
AND
R8,R7,R4
NOP
AND
R8,R7,R4
NOP
AND R8,R7,R4NOP
OR R4,R8,R2
NOP
OR R4,R8,R2
OR R4,R8,R2
2
3
4
5
DOF EX
WB
IF
DOF
EX
WB
IF
b)
2
IF
DOF
SUB R8,R8,R6
湖
(AND R8,R8,R7)
IF
4
6
WB
7
EX
WB
7
5
EX
WB
DOF EX
WB
IF
DOF
EX
WB
6
7
WB
群
DOF
5
EX
WB
6
7
考
WB
EX
WB
5
学
3
4
5
EX
WB
DOF
EX
WB
IF
DOF
EX
IF
DOF
6
7
EX
迎
加
入
AND R8,R8,R7
IF
EX
IF
南
MOV R7,R6
1
EX
4
6WB
WB
DOF EX
WB
IF
WB
DOF EX
WB
DOF EX
IF
DOF EX
WB
IF
DOF EX
WB
IF
DOF EX
WB
IF
DOF EX
WB
IF
DOF EX
WB
IF
DOF EX
IF
DOF
WB
IF
DOF EX
DOF
大
10-14.
DOF
欢
b)
2
3
4
5
DOF EX
WB
IF
DOF
EX
WB
IF
料
1
1
2
3
a)
MOV R7,R6
IF
MOV
R7,R6
MOV
R7,R6 SUBIF
DOF EX
R8,R8,R6
SUB R8,R8,R6
SUB R8,R8,R6NOP
IF
DOF
NOP
NOP
AND
R8,R8,R7 AND R8,R8,R7 IF
AND R8,R8,R7
资
a)
a)
试
10-13*
:
69
05
OR
6
68
SUB R7, R7, R2
BNZ R7, 000F
AND R8, R7, R4
OR R4, R8, R2
39
2
10-12.
3
WB
1
2
3
4
IF
DOF
EX
WB
IF
DOF
EX
WB
IF
DOF
EX
6
8
WB
Problem Solutions – Chapter 10
10-15.
PC: 0000 0001
PC−1: XXXXXXXX
PC−2: XXXXXXXX
D0: XXXXXXXX
IR: XXXXXXXX
A: XXXXXXXX
D1: XXXXXXXX
B: XXXXXXXX
D2: XXXXXXXX
RW: X DA: XX MD: X
RW: X DA: XX MD: X
39
2
Time Cycle 1
IF
DOF
EX
WB
BS: X PS: X
MW: X FS: X
BS: X PS: X
MW: X FS: X
PC: 0000 0003
PC-1: 0000 0003
PC-2: 0000 0002
D0: XXXXXXXX
IF
DOF
EX
WB
PC: 0000 0003
PC−1: 0000 0003
PC−2: 0000 0002
D0: 0000 0020
B: XXXXXXXX
D2: XXXXXXXX
RW: X DA: XX
RW: X DA: XX
MD: X
MD: X
Time Cycle 3
B: 0000 0010
D2: XXXXXXXX
RW: 1 DA: 07
RW: X DA: XX
Time Cycle 4
B: XXXXXXXX
D2: 0000 0000
RW: 0
RW: 1
DA: 00
DA: 07
PC: 0000 0012
PC-1: 0000 0004
PC-2: 0000 0003
D0: 0000 0020
IF
DOF
EX
WB
PC: 0000 0012
PC-1: 0000 0004
PC-2: 0000 0004
D0: 0000 0020
IF
DOF
EX
WB
PC: 0000 0013
PC-1: 0000 0013
PC-2: 0000 0004
D0: XXXXXXXX
IF
DOF
EX
WB
PC: 0000 0014
PC-1: 0000 0014
PC-2: 0000 0013
D0: 0000 0020
试
IF
DOF
EX
WB
IR: 1083 9000
A: 0000 0020
D1: XXXXXXXX
B: XXXXXXXX
D2: 0000 0000
RW: 0
RW: 0
DA: 00
DA: 00
BS: 0 PS: X
BS: 0 PS:X
MB: X CS: X
MW: 0
FS: 5
MB: 0 CS:X
MW: 0
FS: 0
MB: 1 CS: X
R7: 0000 0020
MD: X
MD: X
BS: 1 PS:1 MW: 0
PC: 0000 0012
FS: 0
MB: 1 CS: X
MD: 0
MD: X
BS: 0 PS:X
MW: 0
FS: 8
MB: 0 CS: X
MD: 0
MD: 0
BS: 0 PS:X
MW: 0
FS: 8
MB: 0 CS: X
考
PC: 0000 0004
PC-1: 0000 0004
PC-2: 0000 0003
D0: 0000 0030
资
Time Cycle 5
IF
DOF
EX
WB
MD: X
MD: X
料
IR: 9003 800F
A: 0000 0030
D1: XXXXXXXX
MD: 0
MD: X
群
IR: 9003800F
A: 0000 0030
D1: XXXXXXXX
05
IF
DOF
EX
WB
IR: 0A73 8800
A: XXXXXXXX
D1: XXXXXXXX
:
69
PC: 0000 0002
PC−1: 0000 0002
PC−2: XXXXXXXX
D0: : XXXXXXXX
68
Time Cycle 2
IF
DOF
EX
WB
MB: X CS: X
大
B: 0000 0020
D2: 0000 0000
IR: XXXXXXXX
A: 0000 0020
D1: XXXXXXXX
RW: 1
RW: 0
DA: 08
DA: 00
Time Cycle 7
B: 0000 0010
D2: 0000 0000
湖
南
IR: 12440800
A: XXXXXXXX
D1: XXXXXXXX
入
加
迎
欢
IR: 12440800
A: 0000 0020
D1:XXXXXXXX
学
Time Cycle 6
RW: 0
RW: 1
DA: 00
DA: 08
Time Cycle 8
R8: 0000 0020
B: 0000 0010
D2: XXXXXXXX
RW: 1
RW: 0
DA: 04
DA: 00
MD: 0
MD: 0
BS: 0 PS: X
MW: 0
FS: 9
MB: 0 CS: X
MD: X
MD: 0
BS: X PS: X
MW: X FS: X
MB: 0 CS: X
Time Cycle 9
IR: XXXXXXXX
A: XXXXXXXX
D1: XXXXXXXX
B: XXXXXXXX
D2: 0000 0000
RW: X
RW: 1
DA: XX
DA: 04
Time Cycle 10
IF
R4: 0000 0020
Fields not specified above have fixed values throughout or are unused: MA = 0, D’, and SH. Based on the register contents, the branch is taken. The data
hazards are avoided, but due to the control hazard, the last two instructions are erroneously executed.
4
Problem Solutions – Chapter 10
10-16.*
PC: 0000 0001
DOF
PC-1:XXXXXXXX IR: XXXXXXXX
EX
PC-2:XXXXXXXX A: XXXXXXXX B: XXXXXXXX RW:X DA:XX MD:X BS:X PS:X MW:X FS:X
WB
D0: XXXXXXXX D1:XXXXXXXX D2:XXXXXXXX RW:X DA:XX MD:X
MB:X MA:X
CS:X
Time Cycle 2
PC: 0000 0002
DOF
PC-1:0000 0002
EX
PC-2:XXXXXXXX A: XXXXXXXX B: XXXXXXXX RW:X DA:XX MD:X BS:X PS:X MW:X FS:X MB:X MA:X CS:X D’:X
WB
D0: XXXXXXXX D1:XXXXXXXX D2:XXXXXXXX RW:X DA:XX MD:X
05
IF
:
69
IR: 0A73 8800
Time Cycle 3
IF
PC: 0000 0003
DOF
PC-1:0000 0003
IR: 9003 800F
EX
PC-2:0000 0002
A: 0000 0030
WB
D0: XXXXXXXX D1:XXXXXXXX D2:XXXXXXXX RW:X DA:XX MD:X
Time Cycle 4
IF
PC: 0000 0004
PC-2:0000 0003 A: 0000 0020
WB
D0: 0000 0020 D1:XXXX XXXX D2:0000 0000
B: XXXXXXXX RW:0 DA:XX MD:X BS:1 PS:1 MW:0 FS:0 MB:1
RW:1 DA:07 MD: 0
试
EX
资
DOF PC-1:0000 0004 IR:1083 9000
群
RW:1 DA:07 MD:0 BS:0 PS:X MW:0 FS:5 MB:0
MA:0
CS:X
D’:X
MA:2
CS:1
D’:1
料
B: 0000 0010
D’:X
68
IF
39
2
Time Cycle 1
PC: 0000 0012
Time Cycle 5
PC: 0000 0013
DOF PC-1: 0000 00013 IR: 1244 0800
EX PC-2: 0000 0004 A: 0000 0020
R7: 0000 0020
考
IF
B: 0000 0020 RW: 1 DA: 08 MD: 0 BS: 0 PS: X MW: 0 FS: 8 MB:0 MA:0 CS:X D’:X
PC: 0000 0014
DOF PC-1: 0000 0014 IR: XXXX XXXX
WB D0: 0000 0010
IF
PC: 0000 0014
B: 0000 0010
南
PC-2: 0000 0013 A: 0000 0020
Time Cycle 6
RW: 1 DA: 04 MD: 0 BS: 0 PS: X MW: 0 FS: 9 MB:0 MA:0 CS:X D’:X
D1: XXXX XXXX D2: 0000 0000 RW: 1 DA: 08 MD: 0
湖
EX
大
IF
学
WB D0: 0000 0020 D1: XXXXXXXX D2: 0000 0000 RW: 0 DA: 00 MD: 0
Time Cycle 7
R7: 0000 0020
DOF PC-1: 0000 0014 IR: XXXX XXXX
PC-2: 0000 0013 A:XXXX XXXX
入
EX
D1: XXXX XXXX
D2: 0000 0000
RW: 1 DA: 04 MD:0
Time Cycle 8
R4: 0000 0010
迎
加
WB D0: 0000 0010
B: XXXX XXXX RW: X DA: XX MD:X BS: X PS:X MW:X FS:X MB:X CS:X D’:X
欢
Fields not specified above have fixed values throughout or are unused: SH. Based on the register contents, the branch is taken. The data
hazards are avoided, but due to the control hazard, the last two instructions are erroneously executed.
5
Problem Solutions – Chapter 10
4
WB
IF
DOF
Branch Detected and IF
Bubbles Launched
5
EX
WB
DOF
EX
IF
6
EX
WB
IF
DOF
EX
IM 7
D0
IM7
D1
IM7
Next Instruction from Target Address
10-18.
D1
IM9
D1
D2
IM 9
D2
IM 14
D2
IM 9
IM 9
0
D3
S1 S0
C14
0
D3
S1 S0
C9
D3
S1 S0
CA7
料
D1
IM14
C31
D0
IM 0
D1
D2
IM 0
D2
D3
S1 S0
CA0
D3
S1 S0
C0
资
CS1
CS0
WB
IM 0
C7
群
D0
D0
D0
0
IM9
0
0
7
68
3
EX
05
2
DOF
:
69
1
IF
39
2
10-17.
AX3:0
D1
DA3:0
FAA3:0
BA 3:0
FAA4
S0
D1
BA 3:0
D0
DA3:0
D1
BX 3:0
D2
DX3:0
D2
BX 3:0
D3
S1 S0
DX3:0
D3
S1 S0
BX 4
DX4
DX0
DX1
DX2
DX3
DX4
欢
迎
加
入
湖
南
FBA3:0
FBA4
大
AX 4
D0
考
D0
学
AA 3:0
试
10-19.*
6
FDA3:0
FDA4
Problem Solutions – Chapter 10
MZ-10
MZ1
MZ0
MI
Z
PS
68
MZ-11
39
2
10-20.
:
69
05
ME1
欢
迎
加
入
湖
南
大
学
考
试
资
料
群
ME0
7
MS
Problem Solutions – Chapter 10
(a) Branch if overflow
R
P M
L
M
MZ
CA
W
DX
D BS S W F S C
MA
B
AX
R31 CC 00001
BOV0
01
01
1
1F
0 00 0
0
8
0
10
1
00
MCMC + 1 (NOP)
BOV1
01
00
0
00
0 00 0
0
0
0
00
0
if (R310)MC BOV5 else
MCMC + 1
BOV2
11
BOV5
0
00
0 00 0
0
0
0
00
MCMC + 1 (NOP)
BOV3
01
00
0
00
0 00 0
0
PCPC–1 + se IM
BOV4
01
00
0
00
0 11 0
0
MCIDLE
BOV5
00
IDLE
0
00
0 00 0
0
(b) Branch if greater than zero
CS
00
11
00
00
1F
00
00
05
00
:
69
0
0
0
00
0
00
00
00
0
0
01
1
00
00
01
0
0
00
0
00
00
00
P M
L
M
MZ
CA
W
DX
D BS S W F S C
MA
B
AX
BX
CS
R31 CC 11000
BLZ0
01
04
1
1F
0 00 0
0
8
0
10
1
00
00
11
MCMC + 1 (NOP)
BLZ1
01
00
0
00
0 00 0
0
0
0
00
0
00
00
00
if (R310)MC BOV5 else
MCMC + 1
BLZ2
11
BLZ5
00
0 00 0
0
0
0
00
0
1F
00
00
MCMC + 1 (NOP)
BLZ3
01
PCPC–1 + se IM
BLZ4
01
MCIDLE
BLZ5
湖
试
考
0
00
0
00
0 00 0
0
0
0
00
0
00
00
00
00
0
00
0 11 0
0
0
0
01
1
00
00
01
IDLE
0
00
0 00 0
0
0
0
00
0
00
00
00
学
南
(c) Compare Less Than
Action
00
资
Address
大
Action
M
料
R
BX
68
Address
群
Action
M
39
2
10-21.
R
Address MZ
CA
M
P M
L
W DX D BS S W F S C
M
MA
B
AX
BX
CS
CGT0
01
00
0
00
0
00
0
0
5
1
00
0
00
00
00
MCMC + 1 (NOP)
CGT1
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
R31 CC 10000
CGT2
01
18
1
1F
0
00
0
0
8
0
10
1
00
00
11
MCMC + 1 (NOP)
CGT3
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
if (R310) MC CGT7
else MCMC + 1
CGT4
11
CGT7 0
00
0
00
1
0
0
0
00
0
1F
00
00
MCMC + 1 (NOP)
CGT5
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
PCPC–1 + se IMS
CGT6
01
00
0
00
0
11
0
0
0
0
01
1
00
00
10
MCIDLE
CGT7
10
IDLE
0
00
0
00
0
0
0
0
00
0
00
00
00
欢
迎
加
入
RSA– RSB
CC L Z N C V
8
Problem Solutions – Chapter 10
10-22.
R
L
W DX D BS S W FS C
M
MA
B
AX
RDRRSA+ 1
PUSH0
01
01
1
01
0
00
0
0
2
0
00
1
00
MCMC + 1 (NOP)
PUSH1
01
00
0
00
0
00
0
0
0
0
00
0
00
MRSARSB
PUSH2
01
00
0
01
0
00
0
1
0
0
00
0
MCIDLE
PUSH3
00 IDLE
0
00
0
00
0
0
0
0
00
0
11
00
00
00
00
00
00
00
00
L
M
CA
W DX D BS S W FS C
MA B
AX
BX
CS
RDRMRSA
POP0
01
00
1 01 1 00
0
0
0
0
00
0
00
00
00
RSBRSA– 1
POP1
01
01
1 00 0 00
0
0
5
0
00
1
00
00
11
MCIDLE
POP2
00
0
0
0
0
00
0
00
00
00
IDLE 0 00 0 00
群
Address MZ
P M
CS
00
料
Action
M
:
69
(b) Pop
R
BX
68
Address MZ CA
P M
05
Action
M
39
2
(a) Push
资
10-23.*
P
M
Address MZ
CA
W
D
BS
S
W
FS
C
MA
B
AX
BX
CS
R31 CC 00010
AWC0 01
试
DX
02
1
1F
0
00
0
0
8
0
10
1
00
00
11
R16 RSA+ RSB
考
(a) Add with carry
R
AWC1 01
00
1
10
0
00
0
0
2
0
00
0
00
00
00
AWC2 11 AWC5
0
00
0
00
0
0
0
0
00
0
1F
00
00
AWC3 01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
AWC4 01
01
1
01
0
00
0
0
2
0
00
1
10
00
11
AWC5 00
IDLE
0
00
0
00
0
0
0
0
00
0
00
00
00
Action
学
if (R310) MC AWC5
else MCMC + 1
大
MCMC + 1 (NOP)
MCIDLE
R
M
P
M
L
M
L
M
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
R31 CC 00010
SWB0
01
02
1
1F
0
00
0
0
8
0
10
1
00
00
11
R16 RSA–RSB
SWB1
01
00
1
10
0
00
0
0
5
0
00
0
00
00
00
if (R310) MC SWB5
else MCMC + 1
SWB2
11 SWB5
0
00
0
00
1
0
0
0
00
0
1F
00
00
MCMC + 1 (NOP)
SWB3
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
RDRR16 – 1
SWB4
01
01
1
01
0
00
0
0
5
0
00
1
10
00
11
MCIDLE
SWB5
00
IDLE
0
00
0
00
0
0
0
0
00
0
00
00
00
欢
迎
加
入
Action
湖
(a) Subtract with borrow
南
RDRR16 + 1
M
9
Problem Solutions – Chapter 10
10-24.
(NOP)
M
M
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
AMI0
01
00
1
10
1
00
0
0
0
0
00
0
00
00
00
AMI1
01
00
0
00
0
00
0
0
0
0
00
AMI2
01
00
1
10
1
00
0
0
0
0
00
AMI3
01
00
0
00
0
00
0
0
0
0
00
AMI4
01
00
1
01
0
00
0
0
2
0
AMI5
00 IDL
E
0
00
0
00
0
0
0
0
(b) Add to memory
M
P
M
群
R
0
00
00
00
0
10
00
00
0
00
00
00
00
0
00
10
00
00
0
00
00
00
L
M
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
R16 MRSA
ATM0
01
00
1
10
1
00
0
0
0
0
00
0
00
00
00
MCMC + 1 (NOP)
ATM1
01
00
0
00
R16 R16 + RSB
ATM2
01
00
1
10
MCMC + 1 (NOP)
ATM3
01
00
0
00
MRDRR16
ATM4
01
00
0
MCIDLE
ATM5
00 IDLE
0
00
0
0
0
0
00
0
00
00
00
0
00
0
0
2
0
00
0
10
00
00
00
0
0
0
0
00
0
00
00
00
0
00
0
1
0
0
00
0
10
00
00
00
0
00
0
0
0
0
00
0
00
00
00
P
M
资
0
01
考
10-25.*
0
料
Address
试
Action
L
05
(NOP)
P
:
69
Action
M
68
R
39
2
(a) Add Memory Indirect
学
Memory Scalar Add (Assume R[SB] > 0 to simplify coding)
M
L
M
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
AX
BX
CS
MSA0
01
00
1
10
0
00
0
0
0
0
00
0
00
00
00
MSA1
01
00
1
12
0
00
0
0
0
0
00
0
00
00
00
MSA2
01
01
1
10
0
00
0
0
5
0
00
1
10
00
11
MSA3
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
MSA4
01
00
1
11
0
00
0
0
2
0
00
0
00
10
00
MSA5
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
if (R160) MC MSA2
else MCMC + 1
MSA6
11 MSA2
0
00
0
00
0
0
0
0
00
0
10
00
00
R18 MR17+ R18
MSA7
01
00
1
12
1
00
0
0
0
0
00
0
11
12
00
RDRR17
MSA8
01
00
1
01
0
00
0
0
0
0
00
0
11
00
00
MCIDLE
MSA9
00
IDLE
0
00
0
00
0
0
0
0
00
0
00
00
00
大
Action
R
R16 RSB
南
R18 R0
MCMC + 1 (NOP)
R17 RSA+ R16
欢
迎
加
入
MCMC + 1 (NOP)
湖
R16 R16 – 1
10
Problem Solutions – Chapter 10
10-26.
P
M
Address
MZ
CA
W
DX
D
BS
S
W
FS
C
MA
B
R16 RSB
MVA0
01
00
1
10
0
00
0
0
0
0
00
0
00
00
00
MCMC + 1 (NOP)
MVA1
01
00
0
00
0
00
0
0
0
0
00
0
00
00
00
R16 R16 – 1
MVA2
01
01
1
10
0
00
0
0
5
0
MCMC + 1 (NOP)
MVA3
01
00
0
00
0
00
0
0
0
0
R17 RSA+ R16
MVA4
01
00
1
11
0
00
0
R18 R16 + RDR
MVA5
01
00
1
12
0
00
0
R19 MR17
MVA6
01
00
1
13
1
00
0
R20 MR18
MVA7
01
00
1
14
1
00
0
MCMC + 1 (NOP)
MVA8
01
00
0
00
0
00
0
R21 R19 + R20
MVA9
01
00
1
15
0
00
if (R160) MC MVA2
else MCMC + 1
MVA10
11 MVA2
0
00
MR18R21
MVA11
01
00
0
01
MCIDLE
MSA12
00
IDLE
0
00
试
M
68
AX BX CS
05
L
00
1
10
00
11
00
0
00
00
00
:
69
M
2
0
00
0
00
10
00
0
2
0
00
0
10
00
00
0
0
0
00
0
11
00
00
0
0
0
00
0
12
00
00
0
0
0
00
0
00
00
00
0
0
2
0
00
0
13
14
00
00
0
0
0
0
00
0
10
00
00
0
00
0
1
0
0
00
0
12
15
00
0
00
0
0
0
0
00
0
00
00
00
料
群
0
0
考
Action
资
R
39
2
Memory Vector Add (Assume R[SB] > 0 to simplify coding)
10-27.
学
(a)
南
大
RDR(RSA31:24+ RSB31:24,
RSA23:16+ RSB23:16,
RSA15:8+ RSB15:8,
RSA7:0+ RSB7:0)
入
10-28.
湖
(b) The function unit requires an additional Add operation in which the carries entering bits 0, 8, 16, and 24 are set to 0. All potential
condition codes produced by the operation, including carries from bits 7, 15, 23 and 31 are ignored.
欢
迎
加
(a) For 16-bit words, the operation can produce a 128-bit result containing 128/16 = 8 minimum words.
(b) For each SPE, there are 128/8 = 16 average bytes produced. Using the eight SPEs, 8 × 16 = 1286 average bytes can be produced.
11
Problem Solutions – Chapter 11
CHAPTER 11
39
2
© 2016 Pearson Education, Inc.
05
Heads × (cylinders/Head) × (sectors/cylinder) × (1 cylinder/track) × (bytes/sector)
=
32,224.5 Kbytes (K = 1024)
a) 1 × 1023 × 63 × 512
b) 4 × 8191 × 63 × 512
=
1,032,066 Kbytes
c) 16 × 16383 × 63 × 512 =
8,257,032 Kbytes
68
11-1*
:
69
11-2.
8.5 msec + 4.17 msec + 0 msec + ((1 sec/(100 Mbytes)) × 1Mbytes)=22.67 ms
料
Subpixels
3,932,160
5,770,000
5,292,000
6,912,000
资
Pixels
a) 1,310,720
b) 1,920,000
c) 1,764,000
d) 2,304,000
群
11-3.
(1100 1010)
RS1 = 1 RS0
2
(CA)
RS1 == 1 0 RS0 = 0
16 = (1100 1010)
2
(1100 1011)2
RS1 = 1 RS0
= 1
(CB)16 = (1100
1011)=2 0 RS0
RS1 == 1 0 RS0 = 1
(1100 1100)
RS1
2
(CC)
1100)=2 0 RS1
RS1 ==0 1 RS0 = 0
(1100 1101)
RS1
2 16 = (1100
(CD)16 = (1100 1101)2
RS1 = 0 RS1 = 1
RS0  A0 , RS1  A1, CS  A7A6A5A 4A3 (A 2A1  A 2A1)
RS0 = A0, RS1 =A 1, CS = A 7A6A 5A 4A3(A 2A 1 + A 2A 1)
RS0
RS1
考
=
=
=
=
学
(CA)16
(CB)16
(CC)16
(CD)16
试
11-4.
A3
大
A2
A1
If each address line is used for a different CS input, there will be no way to address
the four registers so 2 bits are needed to address the registers. Only 14 lines can be used
for CS inputs permitting at most 14 I/O Interface Units to be supported.
Since two bits must be used to address the four registers, there are 14 bits remaining and
214 or 16,384 distinct I/O Interface Units can be supported.
湖
a)
A4
南
11-5.*
A5
A7
A6
欢
迎
11-6.
加
入
b)
#
Port A ADRS
Port B ADRS
Control ADRS
Status ADRS
1
0000 0001
0100 0001
1000 0001
1100 0001
2
0000 0010
0100 0010
1000 0010
1100 0010
3
0000 0100
0100 0100
1000 0100
1100 0100
4
0000 1000
0100 1000
1000 1000
1100 1000
5
0001 0000
0101 0000
1001 0000
1101 0000
6
0010 0000
0110 0000
1010 0000
1110 0000
1
A0
A1
CS
Problem Solutions – Chapter 11
11-7.*
05
68
39
2
A given address can be shared by two registers if one is write only and one is read only. If a register
is both written to and read from the bus, then it needs its own address. An 8-bit address provides
256 addresses. Suppose that the 50 % of registers requiring 1 address is X. Then the remaining 50
% of the registers, also X can share addresses requiring only 0.5 addresses. So 1.5 X = 256 and X =
170.67 registers for a total of 341.33 registers. To meet the original constraints exactly, the total
number of registers must be divisible by 4, so 340 registers can be used, 170 of which are
read/write, 85 of which are read only and 85 of which are write only. There is one more address
available for either one read/write register or up to a pair with a read only register and a write only
register.
CPU
I/O Read
I/O Data
I/O Data Bus
CPU Data Bus
Interface
STB
I/O
Device
STB
IBF
IBF
11-9.*
(a)
RD Strobe
Read Operation
Data bus
I/O
Device
From I/O
Address bus
资
CPU
料
(b)
Data Bus
Address Bus
DATA
群
I/O Read
:
69
11-8.
Strobe
Write
Strobe
试
WR Strobe
Read
考
Data bus
Write Operation
From CPU
Address bus
Strobe
Write
Strobe
学
Read
大
11-10.
南
Read Operation
Data bus
From I/O
Strobe
Write
Strobe
Read
Reply
入
Read
Data Bus
Address Bus
CPU
湖
Address bus
WR Strobe
RD Reply
WR Reply
Write Reply
加
Data bus
Write Operation
From CPU
Address bus
Strobe
迎
Read
Strobe
Read
Reply
欢
Write
RD Strobe
Write Reply
2
I/O
Device
Problem Solutions – Chapter 11
39
2
11-11.*
68
There are 7 edges in the NRZI
waveform
for theinSYNC
patternwav
thatefcan
be fused
forSY
synchronization.
There
are 7 edges
the NRZI
orm
or the
NC pattern that can be used f or sy nchronization.
05
11-12.
01111111001000000001101110000011
(b)
011111101001000000001101110000011
群
:
69
(a)
11-13.*
Dev ice
Address
0100111
Check
4 bits
0110
Endpoint
Address
0010
资
Type
4 bits
1001
CRC
EOP
CRC
EOP
试
SYNC
8 bits
料
(c)
Type
4 bits
1100
Check
4 bits
0011
Data
010000101001111010100110
学
SYNC
8 bits
考
(a) Output packet
SYNC
8 bits
Type
4 bits
0111
Check
4 bits
1000
EOP
(c) Handshake packet (Stall type)
欢
迎
加
入
湖
南
大
(b) Data packet (Data0 type) (bits LSB first)
3
Problem Solutions – Chapter 11
Type
4 bits
1001
SYNC
8 bits
Type
4 bits
1100
Dev ice
Address
0100111
Check
4 bits
0110
Endpoint
Address
0010
CRC
EOP
CRC
EOP
68
SYNC
8 bits
39
2
11-14.
Check
4 bits
0011
Data
111101100011011000010010
05
(a) Output packet
Type
4 bits
0101
SYNC
8 bits
Check
4 bits
1010
:
69
(b) Data packet (Data0 type) (bits LSB first)
EOP
群
(c) Handshake packet (Stall type)
料
11-15.
11-16.*
PI
0
0
After CPU sends acknowledge
1
Device 1
Device 2
RF
VAD
PI
PO
RF
VAD
PI
PO
RF
VAD
0
0
-
0
0
0
-
0
0
1
-
0
1
-
0
0
0
-
0
0
1
-
0
1
0
0
0
0
-
0
0
1
-
南
11-17.
大
Initially
Before CPU acknowledges Device 2
PO
学
Description
考
Device 0
试
资
Interrupt-initiated data transfer permits the action required by an interrupt to occur anywhere within the programs
executing without specifically including code in those programs to sense the need for the action. This makes actions
necessary in response to an interrupt invisible to the typical user program. In contrast, if the interrupt is not used, there
would need to be code within unrelated programs that supports the same necessary actions.
入
Replace the six leading 0’s with 000110.
加
11-18.*
湖
The interrupt service routine polls the devices connected to the common interrupt line. The first device checked has the highest
priority. The priority of the other devices corresponds to when they are checked.
迎
11-19.
欢
Fill in the VAD vector (top to bottom) as A0 , A1, A1, 1, 1, 1, 1, 1, 0.
11-20.*
This is Figure 13-17 with the Interrupt and Mask Registers increased
to 6 bits each, and the 4 × 2 Priority Encoder replaced by a 8 × 3
Priority Encoder. Additionally, VAD must accept a 3rd bit from the
Priority Encoder.
4
Problem Solutions – Chapter 11
1
0
W X
Y
Z
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
1
1
0
1
1
1
1
0
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
0
1
1
0
1
1
1
0
0
1
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
1
1
1
0
1
1
0
1
0
1
0
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
0
1
1
0
1
1
0
0
0
1
0
0
0
0
1
x
x
x
x
x
x
x
x
x
x
x
1
0
1
1
1
1
0
1
0
1
1
0
1
0
0
0
0
0
1
x
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x
11-22.*
考
试
When the CPU communicates with the DMA, the read and write lines are used
as DMA inputs. When the DMA communicates with the Memory, these lines
are used as outputs from the DMA.
11-23.
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b)
CPU initiates DMA by transferring the following:
2048 to the word count register.
4096 to the DMA address register.
1) I/O Device sends the DMA controller a “DMA request.”
2) DMA sends BR (Bus Request) to CPU.
3) CPU responds with BG (Bus Grant).
4) Contents of DMA address register are placed on the address bus:
DMA sends “DMA acknowledge” to I/O device.
Address 4096 + (2048 – WCR) on address bus.
DMA enables the Write control to Memory.
Data word is placed on the data bus by I/O device.
Decrement WCR.
5) If DMA receives a “DMA request” from I/O device, it repeats Step 4, otherwise
it disables the BR line to CPU.
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x
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D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A4 A3 A2 A1 V
39
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11-21.
Problem Solutions – Chapter 12
CHAPTER 12
39
2
© 2016 Pearson Education, Inc.
c
54
0010 1 01 00
M
M
M
58
0010 1 10 00
M
M
M
104 1000 0 01 00
M
M
M
5C
0010 1 11 00
M
M
M
108 1000 0 10 00
M
M
M
60
0011 0 00 00
M
M
M
F0
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M
M
M
64
0011 0 01 00
M
M
M
54
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H
M
58
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10C 1000 0 11 00
M
0010 1 11 00
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M
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H
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M
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H
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M
M
04
0000 0100
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M
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M
60
0110 0000
M
M
M
20
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M
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H
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H
H
28
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M
M
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70
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M
M
M
10
0001 0000
M
H
H
60
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H
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70
0111 0000
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H
M
学
考
60
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12-2.
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H
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试
110 1000 1 00 00
H
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Binary
68
12-1.
Problem Solutions – Chapter 12
12-3*.
68
39
2
Since the lines are 32 bytes, 5 bits are used to address bytes in the lines.
Since there are 1K bytes, there are 1024/32 = 25 cache lines.
a) Index = 5 Bits,
b) Tag = 32 – 5 – 5 = 22 Bits
c) 32 × (32 × 8 + 22 + 1) = 8928 bits
05
12-4.
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:
69
(a) Number of rows = 1M/(4 bytes/line  4 words/line lines/set) = 215 = 32,768
The number of bits for addressing the word and byte within a line is 4 bits.
Index = 15 bits Tag = 32 – 15 – 4 = 13 bits
(b) (Assumes main memory address to bytes, not words)
0C00
4AC8
2CF0
4CF0
2CF0
(c) Yes. Although 7142CF0F and F83ACF04 have the same index, the cache is two-way set associative,
so both of them can fit in the cache simultaneously.
资
12-5.*
试
a) See Instruction and Data Caches section on page 636 of the text.
b) See Write Methods section on page 633 of the text.
12-6.
学
考
Any sequence of instructions and data that share the same indices will cause a unified cache to work poorly and a separate
instruction cache and data cache to work well. Recall that the index for direct mapping are the bits from location 2 through 4.
000001 00 00 (i4)
000001 10 00 (i6)
000010 10 00 (i10)
000000 01 00 (i1)
000011 00 00 (d)
00001 11 00 (i7)
000011 10 00 (d)
000000 10 00 (i2)
000001 01 00 (i5)
000010 00 00 (i8)
000010 11 00 (i11)
000011 01 00 (d)
000010 01 00 (i9)
000011 11 00 (d)
南
000000 00 00 (i0)
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12-7.*
000000 11 00 (i3)
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入
Addresses of instructions (i) and Data (d) in sequence down and then to the right with the instructions in a loop with
instruction i0 following i11. For the split cache, the hit - miss pattern for instructions is (assuming the cache initially empty
and LRU replacement) M, M, M, M, M, M, M, M, M, M, M, M, M, ... since there are only eight locations available for
instructions. For the unified cache, the hit-miss pattern for instructions with the same assumptions is M, M, M, M, M, M, M,
M, M, M, M, M, H, H, H, ... since there are 12 locations indexed appropriately for instructions and four indexed
appropriately for data.
12-8.
The use of write-allocate with a write-through cache defeats the purpose of write-allocate. The idea behind write-allocate is
to load a cache line when a write miss occurs to a word in the line, thus if future writes occur to the same line, no writes to
main memory will be required. If write-through is implemented in the cache, a write to main memory is performed anyway,
thus write-allocate is a waste of design effort in these caches.
2
Problem Solutions – Chapter 12
12-9
68
39
2
a) Number of sets = 1K/(4 
b) Index = 6 bits, Tag = 32 – 6 -2 (word) -2 (byte) = 22 bits
c) Number of sets = 1K/(4 Index = 4 bits, Tag= 32 – 4 -2 (word) -2 (byte) = 24
bits
d) Number of sets = 1K/(2 Index = 7 bits, Tag = 32 – 7 -1 (word) -2 (byte) = 22 bits
a) 264 /23  261
b) Byte = 5,
Tag = 45
:
69
Index = 14,
05
12-10.
12-11.*
Effective Access Time
Effective Access Time
Effective Access Time
=
=
=
0.91 * 4ns + 0.09 * 40 ns = 7.24 ns
0.82 * 4ns + 0.18* 40 ns = 10.48 ns
0.96 * 4ns + 0.04 * 40 ns = 5.44 ns
a)
b)
c)
Effective Access Time
Effective Access Time
Effective Access Time
=
=
=
0.91 * 1ns + 0.09 * 20 ns = 2.71 ns
0.82 * 1ns + 0.18* 20 ns = 4.42 ns
0.96 * 1ns + 0.04 * 20 ns = 1.76 ns
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c)
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12-12.
3
Problem Solutions – Chapter 12
CPU
39
2
12-13.
Main Memory
Address bus
Index
Match
Match
Data
Memory
0
Match
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料
群
Match
Data
Memory
1
Data
Memory
2
05
Ta g
Ta g
Ta g
Ta g
Data
Memory Memory Memory Memory Memory
1
0
3
2
3
:
69
Ta g
68
Ta g
CPU
Data Bus
Main Memory
试
Hit/Miss
考
12-14.+
CPU
16 Ta g
32
2 Word
32
32
32
32
32
32
32
128
32
Match
Valid bits
Valid bits
Dirty bits
Dirty bits
湖
Data
Memory
0
Write M0
128
Match
Write M1
4-to-1 4-to-1
MUX MUX
Hit 0
Read
Mem
Read M1
Hit 1
CPU Data Bus
4
32
4-to-1
MUX
32
32
Read M0
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Data
Memory
1
128
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Ta g
Ta g
Memory Memory
1
0
Main
Memory
Write
Word
1
0
1
0
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Main Memory
Cache Data Bus
大
Index 12
Address bus
学
a)
Problem Solutions – Chapter 12
Write
Cache
Control
Hit 0
Hit 1
Read Main Mem
Read Mem
Read M0
Read M1
Write M0
Write M1
Write Word
Write Main Mem
39
2
Read
群
the cache and the dirty bit is set f or all cases.
:
69
05
68
b) Read Miss:
b)
Read Miss:
at least
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Write
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the cache
All cases are the same as the read misses with the exception that the new v alue is then writen to
12-15.*
资
料
a) Each page table handles 512 pages assuming 64-bit words. There are 4263 pages which
requires 4263/512 8.33 page tables. So 9 page tables are needed.
b) 9 directory entries are needed, requiring 1 directory page.
c) 4263 − 8*512 = 167 entries in the last page table.
考
南
大
d)
e)
With a page size of 4KB, then the page offset is 12 bits
With virtual addresses of 64 bits, then there 264/4K entries in the page table, = 252 entries.
Addressing 1GB of physical memory requires 30 bits for the physical address. So the physical
page frame number requires 30-12 = 18 bits.
The virtual page number requires 64-12 = 52 bits.
With a page size of 16KB instead of 4KB:
The page offset is 14 bits.
There are 264/16K = 250 page table entries.
The physical page frame number requires 30 - 14 = 16 bits.
The virtual page number requires 64 - 14 = 50 bits.
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b)
c)
试
12-16.
12-17.
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Miss - Address not in cache
Miss - Address in cache: E03B32, but Valid = 0
Miss - Address not in cache
Miss - Address in cache: 657777, but Valid = 0
入
(a)
(b)
(c)
(d)
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12-18.
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32-bit word implies 4 bytes/word
(a) 4K byte pages implies 12 bit offset which implies 20 bit tags. With 32 entries, associative memory = 32 × 20 = 320 bits.
(b) 228  384 MB  229 , giving a physical address of 29 bits. With a 12 bit offset, the physical page address is 17 bits. 32 ×
(3 + 17) = 640 bits.
12-19.
Directory pages
Pages Program 1
3224/1024
= 4
= 4
5
Problem Solutions – Chapter 12
Pages Program 2
Pages Program 3
Pages Program 4
5670/1024
1205/1024
2069/1024
= 6
= 2
= 3
39
2
= 19 pages × 4096 = 77,824 bytes = 76 KB
Total
68
12-20.*
:
69
05
In section 12-3, it is mentioned that write-through in caches can slow down processing, but this can be avoided by
using write buffering. When virtual memory does a write to the secondary device, the amount of data being written is
typically very large and the device very slow. These two factors generally make it impossible to do write-through with
virtual memory. Either the slow down is prohibitively large, or the buff-ering cost is just too high.
12-21.
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If locality of reference did not exist, no benefits would be gained by either virtual memories or caches. Without locality
of reference, accesses to both virtual memory and the cache would cause a miss with much greater likelihood. Since any
miss incurs more time than direct accesses to cache or memory, system performance would not be significantly
improved.
6
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