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Simulation and Modeling of Tunnel Field Effect Transistor
Thesis · November 2017
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Indian Institute of Technology Kanpur
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Simulation and Modeling of Tunnel Field Effect
Transistor
A Thesis Submitted
in Partial Fulfillment of the Requirements
for the Degree of
Doctor of Philosophy (Ph.D.)
by
Prateek Jain
(12204070)
to the
Department of Electrical Engineering
Indian Institute of Technology Kanpur
November, 2017
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SYNOPSIS
Name of the Student: Prateek Jain
Roll Number: 12204070
Degree for which Submitted: Ph.D.
Department: Electrical Engineering
Thesis Title: Simulation and Modeling of Tunnel Field Effect Transistor
Names of the Thesis Supervisors: Dr. Yogesh Singh Chauhan and Dr. Amit Agarwal
Month and Year of the Submission: November, 2017
The continuous scaling of transistors and the increase in transistor density, have led to
immense increase in power density on chip. Supply voltage scaling reduces the dynamic power
consumption, which is desirable for power constrained applications, but to achieve the same
ON-current, threshold voltage Vth has to be scaled proportionately. The reduction in Vth causes
exponential increase in OFF-current and static leakage power. This is because of subthreshold
swing limit of 60 mV/decade at room temperature, due to the Boltzmann distribution of carriers. Therefore, it becomes imperative to explore new devices structures, which can operate at
low voltage and consume less power. To overcome these issues, devices such as Tunnel Field
Effect Transistor (TFET) have been explored, and also different architectures (Fully depleted
silicon on insulator and FinFET) and different channel materials (MoS2 , III-V and Graphene)
are attracting attention of the electronics community. In advanced technology nodes, fully and
partially depleted silicon on insulator (FD-SOI and PD-SOI) and FinFET are some of the competitors.
The devices, which are based on some other transport phenomena like interband tunneling
and impact ionization are also being explored. TFET, which is based on interband tunneling
phenomenon has attracted lot of attention of the electronics community, because of its excellent
subthreshold slope and low off current. The main stumbling blocks with TFET are its low ON
current and stringent fabrication steps, which restrict its usefulness for the mainstream device.
Various optimization techniques have been reported to boost the performance of TFETs. In this
work, we have investigated some of the optimization techniques. Further, first principle DFT
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calculations are also performed to study the thickness dependent quantum confinement effects
in Ge source lateral TFETs. We have also presented a surface potential based analytical model
for TFET accounting the mobile charges in the channel.
The thesis is organized as follows:
In Chapter 1, we discuss the challenges involved in CMOS scaling and the available solutions for it. Tunnel field effect transistor is described in detail with the underlying physics
and assumptions involved. The shortcomings of TFETs and the different proposed solutions to
tackle them are also highlighted in this chapter.
In Chapter 2, we have investigated “Dual Metal Gate (DMG)” technique in detail for the
mono and hetero dielectric gate material with Si and relaxed SiGe sources. Dual metal gate
technique allows to individually control the different portions of the transfer characteristics and
this results in improved performance. The hetero dielectric at the gate reduces OFF current
as compared to mono dielectric. Additionally, DMG with SiGe source offers the flexibility to
modulate the band gap of SiGe at the source. Thus SiGe performance is found to be better than
Si DMG-DGTFETs.
In Chapter 3, we have examined the effect of compressive strain at the SiGe source and
tensile strain in Si for Double Gate Tunnel Field Effect Transistor (DGTFET) with strained SiGe
source. Sandwitched SiGe/Si/SiGe source is presented, which results in compressive strain at
the source. The lattice constant of pseudomorphically grown SiGe on Si substrate is higher, as
a result compressive strain is generated at the source. Further, at the vertical interface between
SiGe/Si source, Si channel is tensile strained. The effect of pocket implant on the source for this
structure is also discussed. The source extended structure is also examined to find the optimum
source extension length.
In Chapter 4, extended Ge source lateral TFET is investigated in detail. The direct and
indirect valleys in Germanium (Ge) are separated by a very small offset, which opens up the
prospect of direct tunneling in the Γ valley of extended Ge source TFET. We explore the impact
of thickness scaling of extended Ge source lateral TFET on the band to band tunneling (BTBT)
current. Ge source is extended inside the gate upto 2 nm to confine the tunneling in Ge only.
We observe that as thickness is scaled, the band alignment at Si/Ge hetero junction changes
significantly, and this results in increase of Ge to Si BTBT current. Based on density functional
theory calculations, we first obtain the bandstructure parameters (bandgap, effective masses
vi
etc.) for the Ge and Si slabs of varying thicknesses, and these parameters are used to obtain the
thickness dependent Kane’s BTBT tunneling parameters. Thereafter, Kane’s BTBT parameters
of Si and Ge are used to obtain the scaled BTBT tunneling current.
In Chapter 5, we have presented a comparative study of vertical and lateral tunneling in
Ge source TFET as the source is scaled down from bulk to ultra-thin slabs of 4 nm thickness.
We have theoretically calculated BTBT parameters for ultra-thin slab using band structure results from atomistic simulations, whereas for bulk we have considered bulk parameters. In our
DGTFET structures, we have used an overlapped gate over Ge source to include vertical line
tunneling along with lateral tunneling in the device. First, the impact of the gate overlap length
scaling on DGTFET has been investigated at constant Ge source thickness of 8 nm. We have
then analyzed the impact of scaling the Ge source thickness on DGTFET keeping the gate overlap length fixed. We have observed that Ge source thickness scaling till 8 nm has negligible
effect on the ON current, but as the thickness is further scaled down, line tunneling disappears
in the device. We also examine TFETs with ultra-thin Ge source, but with small gate-source
overlap, to confine the tunneling in Ge only. In this configuration, lateral tunneling drives the
drain current, leading to better sub-threshold slope and ON current. Further, we highlight the
roles of enhanced subsurface BTBT current and gate screening in these ultra-thin lateral TFETs.
In Chapter 6, we have developed a surface potential based analytical model for DGTFET
for the drain current, terminal charges, and terminal capacitances. The model accounts for the
effect of mobile charges in the channel and captures the device physics in depletion as well as in
the strong inversion regime. The narrowing of tunnel barrier, in the presence of mobile charges
in the channel, is incorporated by modeling of the inverse decay length, which is constant
under channel depletion condition and bias dependent under inversion condition. To capture
the ambipolar current behavior in the model, tunneling at the drain junction is also included.
The proposed model is validated against TCAD simulation data and it shows close match with
the simulation data.
In Chapter 7, we summarize the research work presented in this thesis and also suggest the
scope of future work in this area.
Dedicated to
My Grandparents
Acknowledgement
Above all, I thank my parents for their love and moral support. Living away from family is
not easy, but they always make me feel like they are there for me. This would not have been
possible without my parents.
I sincerely thank my supervisor, Dr. Yogesh Singh Chauhan and Dr. Amit Agarwal for giving me the opportunity to work with them. Along with my academic research activities, they
continually encouraged me to explore industrial experiences. All this is possible today, because
they believed in me, more than I believed in myself.
I would also like to thank my previous thesis supervisor Dr. Bahniman Ghosh, Dr. Dipanjan
Basu, and Dr. Shyama Prasad Das for there guidance. I am deeply indebted to my teachers at
IIT Kanpur, especially Prof. Aloke Dutta, Prof. B. Mazhari, Prof. S.S.K. Iyer and Prof. S.
Qureshi for giving me deep insight and proper background during the course work.
I would like to convey my special regards to Dr. Sarvesh Chauhan for sharing his memories of
thesis writing, as it helps me a lot in improving my way of thesis writing. I am very thankful to
my labmates and friends Chandan Yadav, Priyank Rastogi, Chetan Dabhi, Sudip Ghosh, Ravi
Verma and Dinesh for useful discussions. Special thanks to Chetan Dhabi and Ravi Verma as
their jokes were very helpful at the time of work pressure. I would like to thank Mr. Johnson
Whiteford for his timely support in providing accessibility to various TCAD tools.
I forever owe utmost gratitude to almighty GOD, whose blessings provide me faith and strength
to carry on my work.
viii
Contents
List of Figures
xii
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Strain Engineering in SiGe source TFETs
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Device structure, fabrication, and simulation models. . . . . . . . . . . . . . .
3.2.1 Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2
3
Introduction
1.1 CMOS Crisis . . . . . . . . . . . . . . . . . .
1.2 Alternative Solutions to Scale CMOS . . . . .
1.2.1 Alternative Channel Materials . . . . .
1.2.2 Alternative Device Architectures . . . .
1.2.3 Alternative Device Phenomena . . . . .
1.3 Tunnel Field Effect Transistor . . . . . . . . .
1.3.1 MOSFET vs TFET . . . . . . . . . . .
1.4 Operation of Tunnel Field Effect Transistor . .
1.4.1 Shortcomings of the TFETs . . . . . .
1.5 Circuits Performance Using InAs HomoTFETs
1.6 Thesis Goals and Outline . . . . . . . . . . . .
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Dual Metal - Double Gate Tunnel Field Effect Transistor
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 DMG-DGTFET: Schematic, fabrication and simulation. . . . . . .
2.3 DGTFET based on hetero dielectric gate material . . . . . . . . . .
2.4 Workfunction engineered DGTFET with HD gate . . . . . . . . . .
2.4.1 Workfunction engineered - Auxiliary Gate . . . . . . . . . .
2.4.2 Workfunction engineered - Tunnel Gate . . . . . . . . . . .
2.4.3 Output characteristics . . . . . . . . . . . . . . . . . . . . .
2.5 DMG-DGTFET with SiGe Source . . . . . . . . . . . . . . . . . .
2.5.1 Workfunction engineered DMG-DGTFET with SiGe source
2.5.2 Effect of gate dielectrics . . . . . . . . . . . . . . . . . . .
2.5.3 Effect of Ge mole fraction in hetero SiGe source . . . . . .
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
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CONTENTS
3.3
3.4
3.5
3.6
3.7
x
3.2.2 Simulation models . . . . . . . . . . . . . . . . . . . . . . . . . .
Strain Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Compressive Strain in SiGe . . . . . . . . . . . . . . . . . . . . .
3.3.2 Tensile strain in Si . . . . . . . . . . . . . . . . . . . . . . . . . .
BTBT Model Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . .
Field Induced Quantum Confinement (FIQC)- Back Envelope Calculations.
Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 DGTFET with HD gate and c-SiGe source . . . . . . . . . . . . .
3.6.2 DGTFET with Pocket Implant . . . . . . . . . . . . . . . . . . . .
3.6.3 DGTFET with source extended structure . . . . . . . . . . . . . .
3.6.4 Channel length scaling . . . . . . . . . . . . . . . . . . . . . . . .
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4
Band to Band Tunneling in Gamma Valley For Ge Source TFET: Thickness scaling
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Device Structure and Simulation Details . . . . . . . . . . . . . . . . . . . . .
4.2.1 Device Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 Atomistic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3 TCAD Simulation Models . . . . . . . . . . . . . . . . . . . . . . . .
4.3 BTBT Parameter and Current Calculations . . . . . . . . . . . . . . . . . . . .
4.3.1 Effective Masses . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Kane Parameters A and B . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 Effect of DOS in the effective electric field . . . . . . . . . . . . . . .
4.3.4 Effect of band alignment at Si/Ge junction . . . . . . . . . . . . . . . .
4.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1 Ge to Si: Band alignment and BTBT . . . . . . . . . . . . . . . . . . .
4.4.2 Ge to Ge:Band alignment and BTBT . . . . . . . . . . . . . . . . . . .
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5
Vertical and Lateral Tunneling in Ge Source TFET: Thickness Scaling
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Device Structure and Simulation Models . . . . . . . . . . . . . . .
5.3 BTBT Model Parameters Calculations . . . . . . . . . . . . . . . .
5.4 Impact of LOVL and TGe Scaling in TFETs with gate-source overlap
5.4.1 Effect of Overlap Length Scaling on Line Tunneling . . . .
5.4.2 Bulk Ge source Line Tunnel FET (8 nm < TGe ≤ 25 nm) . .
5.4.3 Ultra-Thin Ge Source Line Tunnel FET (TGe ≤ 8 nm) . . .
5.5 Ultra-Thin Ge Source Lateral (P-P) TFET . . . . . . . . . . . . . .
5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Modeling of Current and Capacitances including Mobile Channel Charge and
Ambipolar Behaviour
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6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
CONTENTS
6.2
6.3
6.4
6.5
7
Device Structure and Simulation Models . . . . . . . . . . . . . . . .
Model Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1 Surface potential . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2 Effect of mobile charges on Φs and k2 : dual modulation effect
6.3.3 Electric Field . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.4 BTBT Current . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5 Terminal Charge and Capacitance . . . . . . . . . . . . . . .
Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1 Surface Potential, Electric field, and Current . . . . . . . . . .
6.4.2 Terminal Charges and Capacitances . . . . . . . . . . . . . .
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Conclusions
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7.1 Scope for Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
A List of Publications
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A.1 Journal Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
A.2 Conference Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
List of Figures
1.1
(a) The effect of scaling trend on the supply (VDD ) and threshold voltage (Vth ) with
CMOS technology generation, reproduced from [8]. (b) The scaling effect on the power
density against gate length (LG ). The leakage power density has increased exponentially with LG scaling, reproduced from [9]. . . . . . . . . . . . . . . . . . . . . .
2
1.2
The schematic view of Double Gate Tunnel Field Effect Transistor. . . . . . . . . . .
7
1.3
The schematic cross section view of TFET and MOSFET, reproduced from [46]. The
injection of carrier mechanism from the source to channel is thermionic emission in
MOSFET, while in TFET’s, it is interband tunneling. The range of energy over which
tunneling takes place forms an energy window. The carriers in this energy range tunnel
into the empty states of the channel. . . . . . . . . . . . . . . . . . . . . . . . . .
7
The qualitative comparison and analysis between TFETs, MOSFETs and other semiconductor device. The transfer characteristics is shown for the different device structure, which are engineered to impove the electrostatics of the conventional Si MOSFET
(red), multigate device (MuG, blue), III-V and SiGe high-mobility channel (purple),
and a TFET (green). TFET has a steep OFF to ON transition and lowest OFF state
current. We have shown two point A and B on the transfer characteristics, where the
trend is opposite. At point A, TFETs offers best subthrehold swing and an improved
ION /IOF F as compared to the MOSFET. However at point B, the current is severely
degraded as compared to the other device architecture, reproduced from [35]. . . . . .
9
1.4
1.5
(a) DC Characteristics of an Inverter. (b) Transient analysis of an Inverter.
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11
1.6
Transient Analyis of NAND gate. . . . . . . . . . . . . . . . . . . . . . . . . . .
12
1.7
Transient Analysis of NOR gate.
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1.8
Transient Analysis of XOR gate.
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13
1.9
SR Flip-Flop implementation using TFETs
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1.10 D Flip-Flop implementation using TFETs . . . . . . . . . . . . . . . . . . . . . .
14
2.1
2.2
The schematic cross sectional view of DMG-DGTFET: (a) with hetero dielectric gate material, and (b) with SiGe source and Hf O2 dielectric. . . . . . . . .
26
Method to deposit two contacting gate material using Tilt angle evaporation and
Normal evaporation adapted from Ref. [1] . . . . . . . . . . . . . . . . . . . .
27
xii
LIST OF FIGURES
2.3
2.4
2.5
2.6
xiii
(a) DMG structure reported in Ref. [3] (Laux = 30 nm, Ltun = 20 nm and TSiO2 = 3
nm). (b) Drain to source current in the structure shown in Fig. 2.3a for different
sets of BTBT parameters. The BTBT parameters that are considered in Ref. [3]
severely overestimates the BTBT current with theoretical/experimental BTBT
parameters [14, 15]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
(a) Comparison of SGTFET with DGTFET with SiO2 dielectric (L= 25 nm,
tox = 2 nm and φm = 4.2 eV).(b) DGTFET (L=25 nm and tox = 2 nm) based on
SiO2 +Hf O2 hetero dielectric gate for different value of metal workfunction
(φm ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
Transfer characteristics and energy band diagram for DMG-DGTFET based on
hetero dielectric gate material (φtun = 4.0 eV, Ltun = 7nm and Laux = 18 nm). (a)
Transfer characteristics at VDS = 1.0 V shown on both semi log and linear scale.
Energy band diagram along a horizontal cut line near to the surface is shown in
(b) OFF state (VGS = 0.0 V and VDS = 1 V), and (c) ON-state (VGS =1.5 V and
VDS = 1 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
Transfer characteristics and energy band diagram for DMG-DGTFET based on
hetero dielectric gate material (φaux = 4.4 eV, Ltun = 7 nm and Laux = 18 nm). (a)
Transfer characteristics at VDS = 1.0 V shown on both semi log and linear scale.
Energy band diagram along a horizontal cut line near to the surface is shown in
(b) OFF state (VGS = 0.0 V and VDS = 1 V), and (c) ON-state (VGS =1.5 V and
VDS = 1 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
2.7
(a) Transfer characteristics for mono and hetero dielectric DMG-DGTFET (φaux =
4.4 eV and φtun =4.0 eV) at VDS = 1.0 V. (b) Energy band diagram along a horizontal cut line near to the surface shown at (VGS = -0.5 V and VDS = 1.0 V). . . . 34
2.8
(a)Transfer characteristics with respect to drain voltage for different gate voltages in DMG-DGTFET based on hetero dielectric material gate (φaux = 4.4 eV,
φtun =4.0 eV, Ltun = 7 nm and Laux = 18 nm). (b) Band-to-Band generation rate
at the surface for DMG-DGTFET based on hetero gate dielectric for VGS = 1.0,
0.9, 0.8 and 0.7 V, respectively at VDS =1.0 V. . . . . . . . . . . . . . . . . . .
35
DMG-DGTFET based on SiGe source at 50 % Ge mole fraction in SiGe, and
hafnium oxide gate dielectric (Ltun = 5 nm and Laux = 20 nm). Transfer characteristics at VDS = 1.0 V shown on both semi log and linear scale, (a) for φtun =
4.0 eV and different value of φaux , and (b) for φaux = 4.4 eV and different value
of φtun . (c) Output characteristics at φaux =4.4 eV and φtun =4.0 eV for different
values of gate voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
2.10 DMG-DGTFET based on SiGe source at 50 % Ge mole fraction in SiGe, and
different gate dielectric material (Ltun = 5 nm and Laux = 20 nm). (a) Energy band diagram along a horizontal cut line near to the surface at ON-state
(VGS =1.5 V VDS = 1V). (b) Transfer characteristics at φaux = 4.4 eV and φtun =
4.0 eV for different dielectrics. . . . . . . . . . . . . . . . . . . . . . . . . . .
37
2.9
LIST OF FIGURES
2.11 The effect of different Ge mole fraction on DMG-DGTFET performance with
hafnium oxide gate dielectric and hetero SiGe on the source. (a) Energy band
diagram is shown at ON state (VGS = 1.5 V and VDS = 1.0 V). (b) Transfer characteristics on log and linear scale at φtun =4.0 eV and φaux =4.4 eV, and (c) plot
of average subthreshold slope against Ge mole fraction in SiGe. (d) DIBL effect
evaluated at different Ge mole fraction with φtun =4.0 eV and φaux = 4.4 eV. . .
3.1
3.2
3.3
3.4
3.5
3.6
3.7
xiv
38
Schematic of DGTFET with compressively strained SiGe (c-SiGe) source and
hetero dielectric gate: (a) without pocket implant, and (b) with pocket implant.
(c) Extended SiGe/Si/SiGe source structure with mono dielectric gate. . . . . .
46
Qualitative depiction of the strain effects in Si and SiGe following Ref. [3]. (a)
The effect of compressive strain in SiGe showing the hydrostatic strain shift and
uniaxial component of strain. (b) Valence band splitting of V1 and V2 band for
different mole fraction of Ge in c-SiGe and t-Si. . . . . . . . . . . . . . . . . .
49
DGTFET (L = 25 nm and tox =2 nm) based on the c-SiGe source, 0.5 Ge mole
fraction, and HD gate for different values of φm . (a) Transfer characteristics
at VDS = 1.0 V shown on both semi log and linear scale. Energy band diagram
along a horizontal cut line near to the surface is shown at:(b) ON-state (VGS =1.5
V and VDS = 1V), and (c) OFF-state (VGS = 0.0 V and VDS = 1V). (d) Output
characterisitcs for different gate voltages. . . . . . . . . . . . . . . . . . . . .
54
DGTFET based on c-SiGe source, 0.5 Ge mole fraction and different hetero
gate dielectric. (a) Energy band diagram calculated along a horizontal plane
near to the surface is shown at ON state. (b) Transfer characteristics at φm =4.2
eV at VDS =1.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
The effect of different mole fraction of Ge(x) in DGTFET based on c-SiGe with
HD gate. (a) Energy band diagram along a horizontal cut line near to the surface
is shown at ON-state (VGS =1.5 V and VDS = 1 V). (b) Transfer characteristic at
VDS = 1.0 V at φm =4.2 eV. (c) SSAV G and ION v/s Ge mole fraction (x). . . . .
56
DGTFET (L = 25 nm and tox =2 nm) based on the c-SiGe source, 0.5 Ge mole
fraction, HD gate and pocket implant near the source junction. (a) Energy
band diagram along a horizontal cut line near the surface is shown at ONstate (VGS =1.5 V and VDS = 1 V) for different pocket implant doping (NP OC )
at φm =4.2 eV. (b) Transfer characteristics at VDS = 1.0 V is shown on both semi
log and linear scale for different value of NP OC . (c) SSAV G and ION against
NP OC doping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
Transfer characteristics of DGTFET with extended c-SiGe source and 0.5 Ge
mole fractions for different encroachment length (nm) inside the gate. As the
source is extended inside the gate, tunneling is delayed due to the increase in
tunnel barrier width because of the depletion of the extended part of the source.
(b) Subthreshold slope and ON-current for different extension length inside the
gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
LIST OF FIGURES
3.8
3.9
Energy band diagram along a horizontal cut near to the surface calculated at:
(a) ON state (VGS =1.5 V and VDS =1 V). The tunnel barrier width increases with
the extension length and 2nm extension gives the best BTBT rate.(b) OFF state
(VGS =0 V and VDS =1 V). No tunneling path is formed for any of the structures
in the OFF state as shown by dotted line. . . . . . . . . . . . . . . . . . . . . .
xv
59
(a) Transfer characteristics of DGTFET with extended c-SiGe source, relaxed
SiGe source (r-SiGe) (Ge mole fraction = 0.5) and all Si TFET. (b) The effect of
FIQC in tunneling showing the current components and the shift in the tunneling. 60
3.10 Channel length scaling of DGTFET (a) with gate aligned structure, and (b)
Source extended structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
4.1
Schematic of the double gate TFET with extended Ge source and hetero-dielectricgate (HG). We consider a device of channel length 40 nm, n-type drain doping
of 1018 cm−3 , p-type source doping of 1020 cm−3 , and body is low n-type doped
(1016 cm−3 ), HG gate dielectric with 2 nm thickness. Source is extended inside
the gate by 2 nm. Work function of metal at the gate is Φm = 4.2 eV . . . . . . . 67
4.2
The confined bandstructure for: (a) Ge 4 nm film and (b) Si 6 nm thin film. The
confinement increases the band gap in both cases. Note that Si becomes direct
band gap semiconductor at reduced thickness [23]. . . . . . . . . . . . . . . .
69
(a) Thickness scaling of total BTBT current considering direct and indirect valley of Si (VDS = 0.7 V). Subsurface BTBT improves the current in subthreshold
region with thickness scaling of Ge films due to the improved gate coupling. (b)
Variation of ON current with Ge thickness for a constant gate overdrive voltage
of 0.8 V. Ge film thickness scaling results in decrease of ION (due to increase
in band gap) and improvement in average subthreshold slope (because of the
improved gate coupling). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
Energy band diagram along a horizontal cut line at distance of 1Å from the
surface (at VDS = 0.7 V) for: (a) different values of gate voltage at 4 nm thin
film and (b) at OFF state (VGS = 0V) for different ultra thin thickness. In (a)
as gate voltage increases tunneling shifts from Ge-Si junction to Ge. In (b)
as thickness is scaled, the barrier gets wider due to the confinement effect on
Si and Ge. The voltage range over which tunneling takes place from Ge to Si
increases with thickness scaling, because of the change in band alignment. . . .
75
Transfer characteristics of DGTFET with extended Ge source, where the total
current is broken down into its constituent components of BTBT and SRH current at 4 nm thickness. At OFF state (VGS = 0V), the total current consists of
both SRH and BTBT current. . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
4.3
4.4
4.5
LIST OF FIGURES
4.6
5.1
5.2
5.3
5.4
xvi
BTBT generation rate contour for different VGS at VDS = 0.7 V for different
thickness. At VGS = 0.2 V, the BTBT generation rate is higher for 6 nm thickness, which is due to the simultaneous effect of the improved electrostatics of
the system and better BTBT parameter value. At low VGS , there is tunneling
from Ge to Si. For VGS = 0.6 V, the BTBT generation rate of 8 nm thin film
is higher as compared to the other thickness. This is due to the improved gate
coupling with VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
Schematic of a double gate TFET with gate-source overlap, n-type drain doping
of 1 × 1018 cm−3 , p-type source doping of 1 × 1020 cm−3 , and low n-type body
doping of 1 × 1016 cm−3 . The gate dielectric is HfO2 with 2 nm thickness. The
nominal gate-source overlap length (LOVL ) and the channel length are 8 nm and
40 nm respectively. The metal gate work function is set to 4.2 eV. . . . . . . .
86
Transfer characteristics of DGTFET with different gate-source overlap lengths
(LOVL ). The vertical line tunneling increases with LOVL , because of increased
band bending provided by the overlapped part. Inset shows the ION and SSAVG
variation with LOVL . ION increases linearly with LOVL . SSAVG remains almost
constant with LOVL , but sharply increases at very low LOVL , because of increase
in OFF current. SSAVG is calculated as the inverse of slope between VT (VGS at
which IDS = 1 × 10−7 A/µm) and VOFF . . . . . . . . . . . . . . . . . . . . .
88
(a) Transfer characteristics of DGTFET with gate-source overlap, LOVL = 8 nm.
Lateral P-P tunneling takes place initially at low VGS , and line tunneling sets in
at higher VGS . Both, lateral and vertical tunneling will contribute to the total
current. The inset shows ION and SSAVG for thickness scaling from bulk to
ultra-thin Ge source. The ON current and SSAVG essentially remain constant
as thickness is scaled down from bulk to 8 nm. For Ge thickness less than 8
nm, the ON current and SSAVG degrade, because of the disappearance of line
tunneling (see Fig. 5.3a for more details).(b) Energy band diagrams are shown
for different values of VGS at VDS = 0.7 V for 8 nm thickness along the lateral
direction considered at 1 Å from the interface. Bands are pulled down with
increase in VGS , which improves lateral P-P tunneling.(c) Energy band diagram
along the vertical direction. As VGS increases, bands are pulled down and at
around 0.5 V, vertical tunneling path is formed in the device, and this initiates
line tunneling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
Transfer characteristics for ultra-thin body Ge source having thickness less then
8 nm. The current degrades in the line tunneling configuration as thickness is
scaled to 4 nm. Inset shows the energy band diagram along the vertical direction
for ultra-thin Ge source at VGS = 1 V and VDS = 0.7 V. Gate voltage is not
sufficient to provide enough band bending needed to initiate line tunneling in
the device, and hence the total current is reduced. . . . . . . . . . . . . . . . .
90
LIST OF FIGURES
5.5
6.1
6.2
6.3
6.4
6.5
6.6
Transfer characteristics of DGTFET with lateral P-P Tunneling. There is a cross
over point in the transfer characteristics, which is due to the effect of gate coupling and gate screening. Inset shows the structure of lateral P-P TFETs. Source
is extended inside the gate by 2 nm to limit the tunneling in Ge only. The hetero
dielectric gate is composed of SiO2 (LSiO2 = 35 nm) and HfO2 (LHfO2 = 5 nm).
ION and SSAVG variation with thickness is shown in the inset. ION degrades at
reduced thickness of Ge source because of gate screening. . . . . . . . . . . .
xvii
91
Schematic of the DGTFET used in the study, where R1 is the source depletion
region, R2 is the channel region, and R3 is the drain depletion region. VG ,
VS , and VD are the applied gate, source, and drain voltage, respectively and Φi
represents the potential at the various marked positions. The doping in various
regions and the channel length are mentioned in the figure. The workfunction
of the metal at the gate is Φm = 4.2 eV. . . . . . . . . . . . . . . . . . . . . . . 97
Plot of the channel mid potential as a function of VGS for different values of VDS .
The linear portion corresponds to the depletion in the channel, while the saturated region indicates inversion in the channel. The model results are consistent
with the TCAD simulation data. . . . . . . . . . . . . . . . . . . . . . . . . . 102
Energy band profile in DGTFET showing minimum and maximum tunneling
path at; a) source /body junction and b) drain/ body junction. . . . . . . . . . . 106
Validation of the surface potential and electric field behavior of model against
the TCAD simulation data along the lateral distance in x-axis. In panel(a), the
effect of mobile charge carrier is not included, while it is included in panels (b),
(c) and (d). In panel (a), model without mobile charge effect shows excellent
matching with simulation data at lower VGS but start deviating with increase
in mobile charge carrier at higher gate voltage at VGS =1.2V. The model in depletion condition at VGS =0.2V in panel (b) has excellent match with simulation
data. The deviation in panel (a) at higher VGS highlights the necessity to include the mobile charge carriers in the model, which corrects the deviation at
high VGS values as shown in (c). The panel (c) displays the surface potential
profile along the channel for VGS =1.0V and VDS =0.0V to 1.2V in steps of 0.2V.
The saturation in the mid potential is effectively captured by the model along
with the pinning of the surface potential at the source end. (d) Validation of the
total electric field predicted by the model along the channel with TCAD simulation data in the channel for VDS = 1.0V and different VGS values with smoothing
function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Drain current predicted by the model verified with TCAD simulation data; (a)
transfer characteristics at varying gate voltage for different VDS . (b) Output
current characteristics at different VGS values, perfect saturation in the drain
current is achieved due to the pinning of the surface potential at the source side. 111
Terminal charge (QD , and QG ) predicted by the model against simulation data;
(a) Drain terminal charge for different VDS w.r.t. applied gate to source voltage
and (b) Gate terminal charge for different VDS w.r.t. applied gate to source voltage.111
LIST OF FIGURES
6.7
xviii
Validation of drain capacitance (CDG ) and gate capacitance (CGG ) behavior of
model against the TCAD simulation data. The panel (a) shows the CDG while
panel (b) shows the CGG at different values of VDS w.r.t. applied gate to source
voltage. Note that CGG and CDG looks similar, but their values are different as
QG includes QS in addition to the QD . . . . . . . . . . . . . . . . . . . . . . . 112
Chapter 1
Introduction
The revolution in integrated circuit (IC) technology has led to a new era in the field of electronics
with tremendous computational capabilities and computing power. The research and development carried out by the electronics community over the past four decades has resulted in the
continued miniaturization of the conventional MOSFET dimensions leading to larger circuit
density and higher functionality at reduced cost. Gordon Moore (Intel co-founder) predicted
that “over the history of computing hardware, semiconductor chips would become two times
more powerful every two years at lower cost, and they would ultimately be so small, that they
could be embedded in homes, cars and smartphones” [1]. The predictions of Moore proved to
be accurate for several decades, and guided/motivated the semiconductor industry to use them
as benchmarks to set the goals for research and development. The evolution in IC technology and digital electronics is strongly linked to Moore’s law: quality adjusted microprocessor
prices, memory capacity sensors and even the number and size of pixels in digital cameras.
The miniaturization of the conventional MOSFET according to Moore’s law, cannot be
continued forever. In 2015, Gordon Moore perceived that the pace of progress would eventually
reach saturation, which started appearing at 22 nm node in 2012, and is continuing at 14 nm
[1, 2]. Later Intel made an announcement that “our cadence today is closer to two and a half
years than two”. This is scheduled to hold through the 10 nm width in late 2017 [2, 3]. They
also made an announcement that as we progress from 14 nanometer technology node to 10
nanometer and plan for 7 nanometer and 5 nanometer and even beyond, our plans are proof that
Moores law is still applicable [4–6]. In order to continue with Moore’s law, today’s hardware
1
1.1 CMOS Crisis
2
(a)
(b)
Figure 1.1: (a) The effect of scaling trend on the supply (VDD ) and threshold voltage (Vth ) with CMOS
technology generation, reproduced from [8]. (b) The scaling effect on the power density against gate
length (LG ). The leakage power density has increased exponentially with LG scaling, reproduced from
[9].
needs to utilize many architecture cores, and the programming should be done in a threaded
manner to take the full advantage.
1.1
CMOS Crisis
The scaling of conventional MOSFET has started reaching saturation as already discussed. The
continuous miniaturization of the complementary metal-oxide semiconductor (CMOS) fieldeffect transistors (FETs) has resulted in extraordinary improvements in the switching speed,
transistor density, functionality and reduced cost of microprocessors. But on the flip side,
miniaturization has resulted in increased power density on the chip, which starts affecting the
reliability of chips. Importance of this observation can be realized from the fact that todays
CMOS microprocessor, operates around the power density of a nuclear reactor [7]. The power
crisis in the conventional MOSFET arises due to the fundamental reason that the supply voltage,
applied to operate the transistors has not scaled proportionately with transistor density. Alternatively it can be said that although the transistors dimensions have continued to shrink, but
the supply voltage used to trigger these transistors doesn’t vary with technology generation as
1.1 CMOS Crisis
3
shown in Fig. 1.1a. The supply voltage is nearly flattened at approximately 1 V for 90 nm node
and beyond [8]. The saturation in supply voltage scaling is attributed to the non-scalability of
the conventional MOSFET threshold voltage. The supply voltage scaling reduces the dynamic
power consumption, which is desirable for power constrained applications. But to achieve the
same ON-current, threshold voltage Vth should scale proportionately, as VDD reduces. The reduction in Vth causes an exponential increase in OFF-current and hence the static leakage power.
The exponential increase in OFF-current is due to subthreshold swing limit of 60 mV/decade,
which in turn is due to the Boltzmann distribution of carriers at room temperature. Hence the
transistor dissipates power, even when it is supposed to be off (see Fig. 1.1b) [9].
In order to know the speed of transition from OFF to ON state, subthreshold slope is defined.
The subthreshold slope is used as a performance parameter for the device and it can be defined
as point to point subthreshold slope and average subthreshold slope [10]: Point subthreshold
slope is measured as the amount of voltage that is required to change the current by one order
of magnitude, when the transistor is operated in the subthreshold regime and mathematically
expressed as:
S=
∂ log ID
∂ log VG
−1
∂VG ∂ϕS
∂ϕS ∂ log ID
Cdep
kT
kT
= 1+
ln10 ≥
ln10 .
Cox
q
q
=
(1.1)
In Eq. 1.1, the first term on right hand side is the gate coupling efficiency, and it is a
measure of gate coupling to channel potential, and is greater than 1 for conventional MOSFET.
The second term is due to the thermal Boltzmann distribution of mobile carriers in the channel
and is fundamentally limited to 60 mV/dec at room temperature. Thus from Eq. 1.1, it can be
inferred that even if the gate is coupled perfectly to the surface potential so that 1 + Cdep /Cox
= 1, or Cox >> Cdep , it requires minimum of 60 mV gate voltage to bring one order of change
in the current magnitude. This sets the fundamental limit on the subtheshold slope and shows
why Vth cannot be scaled continuously in a conventional MOSFET. The off current, IOF F ,
increases exponentially with reduction in Vth , hence leakage power dissipation also increases
exponentially [11]. On the other hand, if Vth is set high, then the excessive gate overdrive
1.2 Alternative Solutions to Scale CMOS
4
voltage would not be sufficient to drive the device at high speed [11]. Thus a trade off between
power (energy) dissipation and speed (delay), sets a fundamental energy efficiency limit for
CMOS technology.
Another way to define the steepness is through the average subthreshold slope, SSAV G , and
it is calculated as the slope in the ID − VG between Vth (threshold voltage) and Vof f (gate off
voltage) as:
SSAV G =
Vth − Vof f
,
log IVth − log IVof f
(1.2)
where IVth and IVof f are the drain current at Vth and Vof f .
The electrostatic control of gate on the channel degrades as the channel shrinks, due to the
increase in closeness between source and drain junction [12]. Also the gate coupling to various
sub-surfaces reduces with scaling, resulting in the increased off state leakage current [13]. Additionally, the drain control on channel increases with scaling and hence the leakage current due
to the drain voltage also increases, and this is typically referred as drain induced barrier lowering (DIBL) [14]. In order to deal with these new challenges to scaling, various solutions like
retrograde substrate doping profile, shallow source/drain extensions, halo implants and strained
silicon [15, 16] have been proposed. Adoption of these solutions for the scaling of planar
MOSFETs makes the fabrication process more complex [17]. A promising alternative to scale
CMOS further, is to choose new MOSFET architectures eg. Fully depleted SOI (FD-SOI) [18]
and FinFET [19, 20] and new channel materials eg. MoS2 [21], III-V [22] and Graphene [23].
1.2
Alternative Solutions to Scale CMOS
In order to circumvent the challenges associated with the conventional MOSFET scaling, new
ideas and phenomena are being explored to come up with the new possibilities. The increasing
difficulties in Si CMOS scaling has created the need of investigation of alternative channel
materials, novel device architectures, and new phenomenon are being investigated and these are
presented in the following sections.
1.2 Alternative Solutions to Scale CMOS
1.2.1
5
Alternative Channel Materials
New materials are being explored to replace Si in the conventional MOSFET. Materials like
germanium (Ge) [24] and III-V alloy semiconductors [25] have opened a new portal to a new era
of ultra-low-power and high-speed applications. Further, layered 2-D materials have initiated
another area of immense possibilities. Materials like Graphene, TMD materials (M oS2 etc),
and Phosphorene etc have shown excellent material properties and have supported electric fieldcontrolled bandgap tuning [26]. The problem with the 2-D material is that their interface with
the dielectric is not good. High quality gate dielectric is required to sustain a very high vertical
electric fields in such devices. The fabrication of devices using these materials is a challenge,
as it can be either n type (III-V compound semiconductor) device or p type (Ge) device but
not both, which are required for CMOS circuit designs. The quantum confinement effects,
which are dependent on material thickness scaling can be used as a powerful techniques to
optimize the material properties, because materials having different thicknesses can be viewed
as different materials with entirely different properties. This sets a new platform for electronics
and optoelectronic applications.
1.2.2
Alternative Device Architectures
The new device architectures like fully depleted SOI (FD-SOI, partially depleted PD-SOI)
and FinFET are being used in sub-micron technolody nodes for silicon technology . The device
is structured in such a manner, so that the electrostatics of system is improved. These new
device architectures provide better gate control on the channel, as channel is surrounded by the
gate from multiple sides [27]. Thickness can be scaled in these devices without increasing subsurface leakage paths and, hence, unwanted leakage currents are suppressed [28]. The mobility
is also improved because of undoped body, which eliminates surface roughness scattering [11].
To adjust the threshold voltage, channel doping is not used as a parameter in these structures.
Thus, random dopant fluctuations, a major cause of process variability in bulk MOSFETs, are
eliminated [29–31].
FinFET is another novel device architecture to deal with MOSFET scaling issues. It has
1.3 Tunnel Field Effect Transistor
6
a thin-body non-planar MOSFET constructed on silicon-on-insulator (SOI) or bulk substrate,
using patterning and etching technologies. In FinFET, the SS is improved (i.e., close to 60
mV/decade at room temperature) and SCE are suppressed by optimizing the fin size [14]. The
massive scaling is possible for FinFET and FD-SOI, while maintaining good device performance [32]. These technologies are now being widely used in Integrated Circuits (ICs) due to
lower power consumption.
Gate all around FETs (GAAFETs) are also being widely explored. They provide excellent
electrostatic control. However, the stacked-Nanowire NW-GAA FET technology involves fabrication complexities, like formation of high aspect ratio fin structure etc [33]. Recently, a new
multi-gate transistor architecture having oxide inserted FinFET (iFinFET), has been presented
to overcome the fabrication issues. The iFinFET has better gate control over the channel as the
fringing electric field enhances the coupling between the gate and channel regions [34].
1.2.3
Alternative Device Phenomena
The devices, which are based on some new transport phenomenan are being explored to replace conventional MOSFET. Tunnel field effect transistor (TFET) [35] and impact ionization
MOSFET (IMOS) [36, 37] are some of the devices, which use new phenomena band to band
tunneling and impact ionization respectively, for carrier transport. TFETs have been widely
researched recently for low power VLSI devices, because of their exceptional leakage power
performance and low OFF current. IMOS suffers from the high voltage requirement required
for the impact ionization [37]. The limitations with TFETs are their low ON-current (ION )
compared to ITRS requirements and stringent fabrications steps required for extracting performance [35]. In our work, we have carried out thorough investigation of Tunnel Field Effect
Transistor, as mentioned in the following sections.
1.3
Tunnel Field Effect Transistor
Tunnel field effect transistor (TFET), because of its low subthreshold swing and excellent reduction in leakage current [38–41] is attracting attention of the electronics community. They
1.3 Tunnel Field Effect Transistor
7
Figure 1.2: The schematic view of Double Gate Tunnel Field Effect Transistor.
Figure 1.3: The schematic cross section view of TFET and MOSFET, reproduced from [46]. The injection of carrier mechanism from the source to channel is thermionic emission in MOSFET, while in
TFET’s, it is interband tunneling. The range of energy over which tunneling takes place forms an energy
window. The carriers in this energy range tunnel into the empty states of the channel.
are being investigated for various low power applications [42–44]. TFET is a gated control
PIN diode, in which tunneling takes place from valence band of source to the conduction band
of the channel and this is controlled by the gate voltage (see Fig. 1.2). The gate voltage is
used to modulate the tunneling barrier width at the source/body junction. The tunneling phenomenon was first observed in Tunnel diode by Esaki [45] in 1960. TFET can be operated at
much lower voltage than the conventional MOSFET and, hence it consumes less power than
the conventional MOSFET [42], but operating mechanisms in TFET and MOSFET are quite
different.
1.3.1
MOSFET vs TFET
The structural difference between the conventional MOSFET and TFET is the asymmetric
source and drain junctions as shown in Fig. 1.3. TFET can be viewed as a gated tunnel diode
1.3 Tunnel Field Effect Transistor
8
in series with the conventional MOSFET connected via an internal node. The carrier injection
mechanism from source to channel is different in both the devices as shown in Fig. 1.3. Unlike
the conventional MOSFET, where the injection of carrier takes place over the potential barrier
(i.e.thermionic emission), the carriers in TFETs are injected into the channel through the potential barrier via a process called band-to-band tunneling (BTBT) (see Fig. 1.3) [47, 48]. The
transfer characteristics of TFET are also quite different from conventional MOSFET. TFET has
some offset with respect to the drain voltage in the transfer characteristics [49, 50].
The operation of conventional MOSFET relies on the modulation of channel potential by
the applied gate voltage for the injection of carriers from the source into the channel through a
process called thermionic emission. The carriers are generated thermally and are distributed in
the source region with the Boltzmann distribution, and the resulting current can be expressed
as:
IT hermionic
VGS
∼
.
= exp
nVT
(1.3)
The barrier at the source/channel junction is modulated by the applied gate voltage. In OFF
state, the barrier seen by the carrier from the source region is large, hence resulting current
is leakage current (see Fig. 1.3). The current is not zero because the thermal (exponential)
distribution of carriers still permits a finite number of carriers to be injected over the large
potential barrier.
In the ON state, as the gate voltage increases the barrier at the source/channel junction is
modulated and this results in exponential injection of carriers from the source into the channel (exponential current modulation). The thermal (Boltzmann) distribution of carriers in the
source region ultimately defines, how steeply a MOSFET can switch from on to off-state. The
steepness, defined by the amount of voltage required to modulate the current by one-order of
magnitude, is called the subthreshold swing (S) and is limited to 60 mV/dec at room temperature [10].
In Fig. 1.4, we have shown the qualitative comparison of the transfer characteristics for
TFETs and other device architectures for MOSFETs [35]. TFET shows better subthrshold
swing as compared to the MOSFETs. However, the ON current associated with the TFETs is
1.4 Operation of Tunnel Field Effect Transistor
9
Figure 1.4: The qualitative comparison and analysis between TFETs, MOSFETs and other semiconductor device. The transfer characteristics is shown for the different device structure, which are engineered
to impove the electrostatics of the conventional Si MOSFET (red), multigate device (MuG, blue), III-V
and SiGe high-mobility channel (purple), and a TFET (green). TFET has a steep OFF to ON transition
and lowest OFF state current. We have shown two point A and B on the transfer characteristics, where
the trend is opposite. At point A, TFETs offers best subthrehold swing and an improved ION /IOF F as
compared to the MOSFET. However at point B, the current is severely degraded as compared to the other
device architecture, reproduced from [35].
very less as compared to the ITRS requirements.
1.4
Operation of Tunnel Field Effect Transistor
The operation of TFET relies on the gate modulation of channel potential and the alignment
of band at the source/channel junction. The range of energy over, which bands are aligned at
the source/channel junction, forms an energy window (band pass filter) over which tunneling
takes place as shown in Fig. 1.3. The path connecting two points of the same energy level is
referred as a tunnel path. It may be noted here that the minimum tunneling path dominates the
BTBT current. The alignment of bands at the junction can be staggered band type-I or type-II
or broken band gap alignment.
The BTBT current in a TFET can be toggled ON and OFF by controlling the band bending
through the applied gate voltage. TFET is an ambipolar device that can show p-type behavior
1.4 Operation of Tunnel Field Effect Transistor
10
with dominant hole conduction and n-type behavior with dominant electron conduction. By using an asymmetric doping profile at the source and drain junction or by using a hetero junction,
the tunneling at the drain end can be suppressed and the ambipolar current can be reduced. The
asymmetry in TFET also achieves a low off-state current. In OFF state, the valence band and the
conduction band are not aligned, as a result no tunneling path is formed in the device. Hence
BTBT is suppressed and the OFF state current is limited by the reverse leakage current. As
the gate voltage increases in the negative direction, bands are pulled upward. The conduction
band gets aligned with the valence band and a conducting channel is formed from the source
valence band to the channel conduction band. At low temperature, the energy distribution of
carriers at the source is restricted and the higher energy part of the source fermi level is effectively cut off. This filtering function makes it possible to achieve an subthreshold slope of below
60mV per decade [35, 51]. The key to better voltage scaling of a TFET than a MOSFET is that
subthreshold slope remains below 60mV per decade over several orders of magnitude of drain
current.
1.4.1
Shortcomings of the TFETs
The main stumbling blocks with TFET are its low ON state current (ION ) compared to ITRS
requirements and complicated fabrication steps required for extracting good performance. The
low ON current in TFETs results in increased delay associated with the circuits. The methods
to increase the ON current in TFETs can be categorised as follows:
Structural modifications (hetero junction source [52, 53] etc): The low ON current issue
in TFETs can be tackled by structural modifications. By using a hetero junction, with a smaller
band gap material at the source, the ON current can be boosted. Raised Ge source TFETs [54],
gate source overlapped TFETs (Vertical tunneling TFETs [55]), extended source TFETs [52],
and L-shapted TFETs [56] have been used to increase the ON current. In a conventional lateral
TFET, tunneling takes place in the lateral direction from the source to the channel. This tunneling is referred to as point to point-(P-P) lateral tunneling. However, if sufficient gate to source
1.4 Operation of Tunnel Field Effect Transistor
(a)
11
(b)
Figure 1.5: (a) DC Characteristics of an Inverter. (b) Transient analysis of an Inverter.
overlap is provided, then the BTBT can be initiated in the vertical direction as well from the
bulk to surface. This tunneling is referred to as line tunneling or vertical tunneling [55].
Doping optimization (retrograde doping, pocket implant source [57, 58] etc): The BTBT
takes place within few nm along side the source/body junction. This BTBT is a very strong
function of the steepness in the energy bands, which can be controlled by the doping profile in
the device. Typically n+ pocket implant near the source is utilized to improve the ON current
in TFETs. However, the OFF current also increases by a large amount due to the SRH electric
field enhanced recombination.
Gate metal work function engineering (double gate, dual metal gate [59, 60]): The workfunction of the metal at gate can be engineered to optimize the performance of TFETs. The
steepness of energy bands at source/body junction can be controlled by the metal workfunction.
The techniques like Dual metal gate can be utilized to individually control the different portion
of the transfer characteristics. Different types of contacts can also be used at the source (eg.
wrap around contacts) to play with the metal workfunction.
Improving electrostatics (gate all around structures, nano wires [55]): Improving the electrostatics is another option to increase the ON current in TFETs. In Gate all around (GAA)
TFET and nano wires, the gate electrostatic control on the tunnel junction is improved, which
increases the BTBT current.
Dielectric optimization (with one or multiple dielectrics etc. [61–63]):
High-k dielectric
material at the gate results in better coupling of the gate to the tunnel junction. Mono and hetero
1.5 Circuits Performance Using InAs HomoTFETs
(a)
(b)
12
(c)
Figure 1.6: Transient Analyis of NAND gate.
(a)
(b)
(c)
Figure 1.7: Transient Analysis of NOR gate.
dielectric gate materials can be employed at the gate to boost the ON current in TFETs. In hetero dielectric gate, the OFF current can be reduced further as comprared to the mono dielectric.
Strain Engineering is another way to boost the performance of TFETs. The strain at source
and drain ends can be used to increase the ON current [64–66].
1.5
Circuits Performance Using InAs HomoTFETs
To assess the circuits performance of TFETs with the best state of art ON current, we have
simulated circuits using 20nm InAs homoTFETs. The III-V Tunnel FET Model is a lookup table based model, where the device current and capacitance characteristics are obtained
from experimentally calibrated TCAD Sentaurus simulation [67]. The detailed experimental
calibration and the look up based model of TFET is described in Ref. [67].
The results thus obtained for logic gates are shown in Fig. 1.5 for an inverter, Fig. 1.6 for
1.5 Circuits Performance Using InAs HomoTFETs
(a)
13
(b)
(c)
Figure 1.8: Transient Analysis of XOR gate.
(a)
(b)
(d)
(c)
(e)
Figure 1.9: SR Flip-Flop implementation using TFETs
NAND gate, Fig. 1.7 for NOR Gate, and Fig. 1.8 for XOR gate, respectively. The sequential
circuits are also simulated using look-up-based model. The results for SR and D Flips are shown
in Fig. 1.9 and Fig. 1.10, respectively. From these figures, it is clear that TFET based circuits
can operate at low VDD .
1.6 Thesis Goals and Outline
(a)
14
(b)
(c)
(d)
Figure 1.10: D Flip-Flop implementation using TFETs
1.6
Thesis Goals and Outline
The goal of this thesis is to get insight into the underlying physics of the TFETs. The main
stumbling blocks with TFET are its low ON current and complicated fabrication steps, which
restrict its usefulness for main stream device. The various optimization techniques are adopted
to boost the performance of TFET as already briefly discussed above. In the rest of the chapters, we will discuss some of the optimization technique in details. The first principle density
functional theory (DFT) thickness dependent quantum confinement effects on Ge source extended lateral TFET is also discussed for lateral and vertical tunneling. We have also presented
a surface potential based analytical model for Si-DGTFET accounting the mobile charges in the
channel.
The thesis is organized as follows:
In Chapter 2, we have discussed “Dual Metal Gate” (DMG) technique in detail for the
mono and hetero dielectric gate with Si and relaxed SiGe source. The hetero dielectric at the
gate results in better subthreshold slope as compared to the mono dielectric. DMG with SiGe at
1.6 Thesis Goals and Outline
15
the source allows the tunable band gap and results in improved performance as compared to the
Si TFETs. The effect of varying the mole fraction of Ge in SiGe and the short channel effects
are also discussed for this structure.
In Chapter 3, strain engineering is discussed for the SiGe source. We have incorporated
the effect of the compressive strain at the source in SiGe and tensile strain in Si for DGTFET
with strained SiGe source. Sandwitched SiGe/Si/SiGe source is presented, which results in the
compressive strain at the source. The lattice constant of pseudomorphically grown SiGe on
Si substrate is higher as a result compressive strain is developed at the source. Further, at the
vertical interface between SiGe/Si source, Si channel is tensile strained. The effect of the pocket
implant at the source is also discussed. Additionally source extended structure is discussed to
find the optimized source extension length.
In Chapter 4, the extended Ge source lateral tunnel field effect transistor is scrutinized. The
direct and indirect valley in Germanium (Ge) are separated by a very small offset, which opens
up the prospect of direct tunneling in the Γ valley of extended Ge source TFET. We explore the
impact of thickness scaling of extended Ge source lateral TFET on the band to band tunneling
(BTBT) current. Ge source is extended inside the gate by 2 nm to confine the tunneling in
Ge only. We observe that as thickness is scaled, the band alignment at Si/Ge hetero junction
changes significantly, which results in increase in Ge to Si BTBT current. Based on density
functional calculations we first obtain the bandstructure parameters (bandgap, effective masses
etc.) for the Ge and Si slabs of varying thickness, and these are then used to obtain the thickness
dependent Kane’s BTBT tunneling parameters. The Kane’s BTBT parameters of Si and Ge are
then used to obtain the scaled BTBT tunneling current. The electrostatics improves as thickness
is reduced in the ultra thin Ge flim (≤ 10 nm). The ON current degrades as we scale down in
thickness, however the subthreshold slope (SSAVG ) improves remarkably with thickness scaling
due to subsurface BTBT.
In Chapter 5, we have presented a comparative study of vertical and lateral tunneling in
Ge source TFETs as the source is scaled down from bulk to ultra-thin slabs of 4 nm thickness.
We have theoretically calculated BTBT parameters for ultra-thin thickness using band structure
results from atomistic simulations, while for bulk we have considered bulk parameters. In the
1.6 Thesis Goals and Outline
16
investigated double gate TFET (DGTFET) structures, we have used an overlapped gate over Ge
source to include vertical line tunneling along with lateral tunneling in the device. First, the
impact of the gate overlap length scaling has been investigated at constant Ge source thickness
of 8 nm. We have then analyzed the impact of scaling the Ge source thickness keeping the gate
overlap length fixed. We have observed that Ge source thickness scaling till 8 nm has negligible
effect on the ON current, but as the thickness is further scaled down to ultra-thin Ge films, line
tunneling disappears in the device. We also report TFETs with ultra-thin Ge source, but small
gate-source overlap to confine the tunneling in Ge only. In this configuration, lateral tunneling
drives the drain current, leading to better sub-threshold slope and ON current.
In Chapter 6, we have developed a surface potential based analytical model for double gate
tunnel field effect transistor (DGTFET) for the current, terminal charges, and terminal capacitances. The model accounts for the effect of the mobile charge in the channel and captures the
device physics in depletion as well as in the strong inversion regime. The narrowing of the tunnel barrier in the presence of mobile charges in the channel is incorporated via modeling of the
inverse decay length, which is constant under channel depletion condition and bias dependent
under inversion condition. To capture the ambipolar current behavior in the model, tunneling at
the drain junction is also included. The proposed model is validated against TCAD simulation
data and it shows close match with the simulation data.
Finally in, Chapter 7 summarizes the research work carried out in this thesis and also
suggests the scope of future work in this area.
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Chapter 2
Dual Metal - Double Gate Tunnel Field
Effect Transistor
2.1
Introduction
In the previous chapter, we have discussed the need for a new device, which can circumvent
the issues of the conventional MOSFET. We have proposed that TFET can offer a promising
solution at reduced operating voltage. In this chapter, to tackle the issues of conventional Si
TFETs, Dual Metal-Double Gate Tunnel Field Effect Transistor (DMG-DGTFET) is discussed
for mono and hetero dielectric gate material (HD). The DMG technique offers the flexibility to
have low as well as high work function metals at the gate to control the individual portion of the
transfer characteristics. This results in pragmatic increase in ON current, improved subthreshold slope and reduced threshold voltage. Additionally, the DMG technique is used along with
the mono/hetero dielectric gate material to optimize the performance of Si based TFET. The
hetero dielectric that we have used at the gate is a combination of SiO2 and Hf O2 . The 2-D
device simulations are performed using Sentaurus TCAD and the results thus obtained are discussed using energy band diagram, tunneling barrier width. The comparison has also been made
between mono and hetero dielectric gate. On application of hetero dielectric to the Si DMGDGTFET, the advantages of both the techniques combines, and it results in higher ION /IOF F
(2 × 109 ) compared to the mono dielectric case (2.5 × 108 ). The average subthreshold slope
also improves from 58 mV/decade in mono dielectric to 48 mV/decade in hetero dielectric Si
25
2.1 Introduction
26
(a)
(b)
Figure 2.1: The schematic cross sectional view of DMG-DGTFET: (a) with hetero dielectric gate material, and (b) with SiGe source and Hf O2 dielectric.
DMG-DGTFET.
Further, to address the low ON current issue in Si TFETs, DMG-DGTFET with type-II
staggered band alignment SiGe hetero junction source is presented. The good compatibility of
SiGe with Si leads to better quality hetero junction SiGe source. The hetero SiGe source offers
tunable band gap with variation in Ge mole fraction and results in improved device transfer
characteristics. All the simulations are done in Synopsys TCAD for a channel length of 25nm
using the non-local BTBT tunneling model.
The previous reported work on DMG-DGTFET in Ref. [1–3] have discussed the, Dual Metal
Gate technique for Si, in detail. However, there is no discussion on ambipolarity, gate leakage, and impact of different dielectric materials [2, 3]. The rigorous discussion of different
dielectrics on DGTFET is presented in Ref. [4]. The concept of hetero dielectric is explored
in details in Ref. [5, 6]. To the best of our survey, nobody has reported DMG-DGTFET with
hetero dielectric gate and relaxed SiGe source. DMG-DGTFET with vertical tunneling has also
not been reported.
The rest of the chapter is organized as follows: In section-2.2, we have elaborated the structure of Si DMG-DGTFET [2, 7] with mono and hetero-dielectric gate [5, 8] and DMG-DGTFET
with SiGe source. The fabrication details and the simulation model that are incorporated are
also discussed in this section. In section-2.3, double gate Si structure is discussed for the hetero
dielectric material system. The detailed study of Si based DMG-DGTFETS with hetero /mono
dielectric gate is carried out in section 2.4. This is followed by the discussion of DMG-DGTFET
with SiGe source in section 2.5. In section 2.6, conclusions are drawn.
2.2 DMG-DGTFET: Schematic, fabrication and simulation.
27
Figure 2.2: Method to deposit two contacting gate material using Tilt angle evaporation and Normal
evaporation adapted from Ref. [1]
2.2
DMG-DGTFET: Schematic, fabrication and simulation.
The Si DMG-DGTFET based on hetero dielectric material consists of gate with two different
metals as shown in Fig. 2.1a. The metal gate which is near to the drain is referred as auxiliary gate, and it can be used to control the off state current by tunning its work function. The
metal gate near to the source side is referred as tunnel gate, and it controls the tunneling at
the body/source junction. Hetero dielectric material consists of a combination of different dielectric. The dielectric below the tunnel gate has a high dielectric constant, which assists in
improving the ON current. The schematic of DMG-DGTFET with SiGe source is shown in
Fig. 2.1b, which has SiGe as source and high-k dielectric as gate material.
The fabrication process of TFETs using SiGe source and drain has already been suggested in
Ref. [9]. The process is similar to the conventional CMOS with some additional steps to deposit
the two different work-function metals. Tilt angle evaporation [1, 10] can be used to deposit
gate material-1 with a photoresist layer as the shadow and gate material-2 can be deposited
using normal evaporation techniques as shown in Fig. 2.2 adapted from Ref. [1]. To form
n+ drain region, ion implantation of arsenic (As) is done into Si followed by annealing. The
source is formed by etching of Si underneath the gate followed by regrowth of in-situ doped p+
Si1−x Gex [11–13]. The HD gate can be formed in two steps [6]. First, SiO2 gate dielectric is
selectively etched away at the source side by using buffered hydrogen fluoride (BHF) solution,
2.2 DMG-DGTFET: Schematic, fabrication and simulation.
28
(a)
(b)
Figure 2.3: (a) DMG structure reported in Ref. [3] (Laux = 30 nm, Ltun = 20 nm and TSiO2 = 3 nm).
(b) Drain to source current in the structure shown in Fig. 2.3a for different sets of BTBT parameters.
The BTBT parameters that are considered in Ref. [3] severely overestimates the BTBT current with
theoretical/experimental BTBT parameters [14, 15].
while SiO2 gate dielectric at the drain end is protected by photo resist masks. In the next step
Hf O2 is deposited by atomic layer deposition of high-k material to fill the gap. The inner
high-k spacer is also formed during this step. Then, the outer SiO2 spacer is formed in order to
implement gate underlap structures for performance improvement [5, 8].
All the simulations are done using Synopsys TCAD, using the non-local tunneling model
[16] for the calculation of BTBT tunneling current. The values of the non-local BTBT tunneling
model for Si are calibrated to the experimental results [14] and for SiGe default BTBT parameter values are considered. Phonon assisted tunneling is used in the model. The gate tunneling
current is simulated using Direct tunneling model and the traps are considered as fixed charge
with concentration of 1010 cm−2 . The SRH recombination model along with the Fermi-Dirac
statistics is used throughout the simulation. The doping dependence, high field saturation, and
2.3 DGTFET based on hetero dielectric gate material
29
enormal mobility models are used with their default parameter values [17, 18]. The quantum
effects due to the charge centroid shift is considered using the MLDA model in the simulation.
Traps are likely to exist at the interface of the gate and body, and are modelled by considering
them to be acceptor types, loacted at 0.3 eV from the middle of the band gap [19]. For multiple defects the couple defect level (CDL) recombination is used. A very fine mesh is used
at the surface to simulate the structure. The doping profile is assumed to be constant in the
drain, source and body region [20, 21]. It is to be mentioned over here that in Sentaurus, the
quantum models [3] are not coupled with the non local BTBT tunneling model. Including the
confinement effects in BTBT will lead to a VT shift due to the increase in band gap, because of
quantization of energy states at the surface.
To calibrate our results, we have done the Sentaurus simulation for the structure reported in
Ref. [3]. The results thus obtained are shown in Fig. 2.3. We find that the values of the BTBT
parameters considered in Ref. [3] severely overestimate the BTBT current for Si as reported in
Ref. [14, 15]. Thus, in our work we have considered theoretical/experimental reported values
of BTBT parameters from Ref. [14, 15].
The following parameter value have been used throughout this work, drain doping 1018
cm−3 (Arsenic), source doping 1020 cm−3 (Boron), and body is lightly doped with arsenic concentration of 1016 cm−3 . The thickness of the gate dielectric material is 2 nm. Hetero dielectric that we have used in this study is composed of silicon dioxide (SiO2 ) and hafnium oxide
(Hf O2 ). The gate length that we used throughout this work is 25 nm. The length of auxiliary
gate is Laux = 18 nm and that of tunnel gate is Ltun = 7 nm. The silicon body thickness tSi is 8
nm. The analysis of DMG-DGTFETS has been done for VDD =1.0 V.
2.3
DGTFET based on hetero dielectric gate material
The results obtained from simulations of SGTFET and DGTFET with SiO2 dielectric are shown
in Fig. 2.4a. As expected DGTFET results in better performance as compared to SGTFET due to
better electrostatics of the system. The DGTFET based on hetero dielectric material is simulated
and the results are shown in Fig. 2.4b. The analysis is carried out for DGTFET based on SiO2
2.4 Workfunction engineered DGTFET with HD gate
(a)
30
(b)
Figure 2.4: (a) Comparison of SGTFET with DGTFET with SiO2 dielectric (L= 25 nm, tox = 2 nm and
φm = 4.2 eV).(b) DGTFET (L=25 nm and tox = 2 nm) based on SiO2 +Hf O2 hetero dielectric gate for
different value of metal workfunction (φm ).
and Hf O2 hetero dielectric to find the optimum value of the work function of the metal (φm ).
It can be observed from Fig. 2.4b, that the best possible value of ION /IOFF is achieved at φm =
4.3 eV. The purpose of using hetero dielectric is to optimize the OFF-current as compared to the
case of a mono dielectric device/TFET. The high-k dielectric is manoeuvre at the source side,
since it improves the electrostatics around the tunnel junction. The dielectric on the drain side
affects only the OFF-current. Important thing to note here is that by changing the φm in the
DGTFET based on hetero dielectric gate simply shifts the transfer characteristics parallel to the
X-axis. As a result sub-threhold slope does not change.
2.4
Workfunction engineered DGTFET with HD gate
In this section, DMG-DGTFET based on HD gate material is analyzed. The workfunction of
the metal at the auxiliary and tunnel gate are engineered following the approach of Ref. [22].
The dual metal at the gate in DMG-DGTFET, along with different dielectrics provide additional
flexibility to control different section of the transfer characteristics, thus improving the TFET
performance.
2.4 Workfunction engineered DGTFET with HD gate
(a)
31
(b)
(c)
Figure 2.5: Transfer characteristics and energy band diagram for DMG-DGTFET based on hetero dielectric gate material (φtun = 4.0 eV, Ltun = 7nm and Laux = 18 nm). (a) Transfer characteristics at VDS =
1.0 V shown on both semi log and linear scale. Energy band diagram along a horizontal cut line near to
the surface is shown in (b) OFF state (VGS = 0.0 V and VDS = 1 V), and (c) ON-state (VGS =1.5 V and
VDS = 1 V).
2.4.1
Workfunction engineered - Auxiliary Gate
The workfunction at the auxiliary gate (φaux ) is engineered at constant φtun =4.0 eV. At OFF
state, as φaux increases, the OFF state current first decreases and then increases as shown in
Fig. 2.5a. The OFF state current is composed of reverse leakage current plus the BTBT current.
As φaux increases up to 4.4 eV reverse leakage current will dominate, since there is no tunneling
path formed in the device. But with further increase in φaux , tunneling path is formed at the drain
end as shown in Fig. 2.5b, which increases the OFF state current. At ON state, increase in φaux
does not bring any significant change in the tunnel barrier width as shown in Fig. 2.5c.
2.4 Workfunction engineered DGTFET with HD gate
(a)
32
(b)
(c)
Figure 2.6: Transfer characteristics and energy band diagram for DMG-DGTFET based on hetero dielectric gate material (φaux = 4.4 eV, Ltun = 7 nm and Laux = 18 nm). (a) Transfer characteristics at VDS =
1.0 V shown on both semi log and linear scale. Energy band diagram along a horizontal cut line near to
the surface is shown in (b) OFF state (VGS = 0.0 V and VDS = 1 V), and (c) ON-state (VGS =1.5 V and
VDS = 1 V).
The ambipolar current increases for negative increase in VG values as shown in Fig. 2.5a. As
φaux increases for constant negative VG bands are pulled upwards. As a result tunneling path is
formed at the drain end and barrier width reduces, which increases the current. The gate current
under both the auxiliary and tunnel gate decreases with increase in φaux for constant φtun = 4.0
eV. For φaux = 4.4 eV and φtun = 4.0 eV, the maximum value of gate current under both auxiliary
and tunnel gate is limited to 10−13 A/µm.
2.4 Workfunction engineered DGTFET with HD gate
33
Table 2.1: Comparison of various parameters for DMG (φaux =4.4 eV and φtun =4.0 eV) technique for
mono and hetero dielectric. Mono dielectric (Hf O2 ) and Hetero dielectric (SiO2 + Hf O2 ).
Technique
mono dielectric DMG-DGTFET
hetero dielectric DMG-DGTFET
2.4.2
ION (µA/µm)
24.8
24.8
IOF F (A/µm)
9.8 ×10−14
1.2 ×10−14
ION /IOF F
2.5 ×108
2 ×109
SSAV G (mV/decade)
58
48
Workfunction engineered - Tunnel Gate
The workfunction at the tunnel gate (φtun ) is engineered at constant φaux =4.4 eV, to ensure low
OFF current. As φtun increases the current starts to decrease, as shown in Fig. 2.6a. This is
because of increased tunnel barrier width at the source/body junction as displayed in Fig. 2.6b.
At OFF state tunnel gate work function does not bring any significant change in tunnel barrier
width as shown in Fig. 2.6c.
The ambipolar conduction is not affected by φtun , this is because φtun does not bring significant changes in the energy band at the drain end. Thus current remains unaffected by φtun for
negative VG . The gate current under both the gate decreases with increase in φtun for constant
φaux = 4.4 eV. The maximum gate current under both the gate is limited to 10−13 A/µm for
constant φtun = 4.0 eV and φaux = 4.4 eV. The best possible value for the auxiliary gate work
function φaux is 4.4 eV and for tunnel gate φtun it is 4.0 eV. The metals which can be used at
gates to obtain the desired φaux of 4.4 eV are W, Ta, and Mo etc, and φtun = 4.0 eV are Mo,
Ni-Ti, and Sc etc [23, 24].
The average subthreshold slope, which can be used as a performance parameter in comparison of semiconductor devices is defined as,
SSAV G =
Vt − Vof f
.
log(IVt ) − log(IVof f )
(2.1)
Here, Vt is the threshold voltage, Vof f is the gate voltage from which the drain current starts to
take off [22], IVt is the drain current at Vgs = Vt , and IVof f is the drain current of the device
at Vgs = Vof f . The SSAV G shows a significant improvement from 58 mV/decade in mono
dielectric gate to 48 mV/decade in the hetero dielectric DMG-DGTFET.
The results obtained for DMG-DGTFET based on SiO2 + Hf O2 hetero dielectric and Hf O2
2.4 Workfunction engineered DGTFET with HD gate
(a)
34
(b)
Figure 2.7: (a) Transfer characteristics for mono and hetero dielectric DMG-DGTFET (φaux = 4.4 eV
and φtun =4.0 eV) at VDS = 1.0 V. (b) Energy band diagram along a horizontal cut line near to the surface
shown at (VGS = -0.5 V and VDS = 1.0 V).
mono dielectric gate are compared in Fig. 2.7a. The hetero dielectric at the gate gives better
performance as compared to mono dielectric in Si DMG-DGTFET. The value achieved for
ION /IOF F is 2.5×108 in the mono dielectric, while it is 2×109 for hetero dielectric gate DMGDGTFET. Also the ambipolar conduction in mono dielectric is more as compared to hetero
dielectric. This can be explained as follows: for mono dielectric the voltage drop would be
less in Hf O2 as compared to silicon, as a result the band are pulled upward in mono-dielectric
device as compared to SiO2 +Hf O2 hetero dielectric as shown in Fig. 2.7b. The results are also
summarized in Table. 2.1. We have not compared the SMG with DMG because the bias points
of both the techniques are not same.
2.4.3
Output characteristics
We now focus on the transfer characteristic with respect to drain voltage as shown in Fig. 2.8a.
The saturation voltage (Vdsat ) in the output characteristics are evaluated as the value of drain
voltage for which the drain current reaches 95 % of its final value. For Si-DMG-DGTFET based
on hetero dielectric gate material the value of Vdsat comes out to be 0.85, 0.81, 0.76, and 0.70
for the following gate voltages: 1, 0.9, 0.8, and 0.7 respectively. For mono dielectric, the value
2.5 DMG-DGTFET with SiGe Source
35
(a)
(b)
Figure 2.8: (a)Transfer characteristics with respect to drain voltage for different gate voltages in DMGDGTFET based on hetero dielectric material gate (φaux = 4.4 eV, φtun =4.0 eV, Ltun = 7 nm and Laux = 18
nm). (b) Band-to-Band generation rate at the surface for DMG-DGTFET based on hetero gate dielectric
for VGS = 1.0, 0.9, 0.8 and 0.7 V, respectively at VDS =1.0 V.
of Vdsat is similar to the hetero dielectric case as the value of ION is similar for both the cases.
The band-to-band generation rate is simulated using Kane dispersion relationship and WKB
approximation [25] and is shown in Fig. 2.8b for different value of gate voltages. With Kane
equation, the peak electron generation rate (Gtun.max ), by BTBT is evaluated to be,

3
2
Gtun.max = A
Eg 1
e
2
q 2 wtmin

 −qwtmin 
3
BEg2
,
(2.2)
where wtmin is the minimum tunneling width. As the value of VG increases minimum barrier
width reduces at the junction, which increases the BTBT generation rate as shown in Fig. 2.8b.
2.5
DMG-DGTFET with SiGe Source
In this section, we extend the discussion on DMG-DGTFET to include SiGe source. In particular, we will focus on the impact of Ge mole fraction variation, and different gate materials on
the TFET characteristics. The short channel effect are also discussed in this section.
For SiGe DMG-DGTFET, we have considered the following device dimensions: Laux =20
nm (length of auxiliary gate), Ltun =5 nm (length of tunnel gate), tSi =10 nm (Silicon body
thickness), and tSiGe =10 nm (SiGe layer thickness). The thickness of auxiliary and tunnel
2.5 DMG-DGTFET with SiGe Source
36
(a)
(b)
(c)
Figure 2.9: DMG-DGTFET based on SiGe source at 50 % Ge mole fraction in SiGe, and hafnium oxide
gate dielectric (Ltun = 5 nm and Laux = 20 nm). Transfer characteristics at VDS = 1.0 V shown on both
semi log and linear scale, (a) for φtun = 4.0 eV and different value of φaux , and (b) for φaux = 4.4 eV and
different value of φtun . (c) Output characteristics at φaux =4.4 eV and φtun =4.0 eV for different values
of gate voltage.
gates, tox =2 nm with mono dielectric gate material.
2.5.1
Workfunction engineered DMG-DGTFET with SiGe source
The workfunction at the auxiliary and tunnel gate are engineered in the same manner as it is carried out for Si DMG-DGTFET in section 2.4. The results thus obtained are shown in Fig. 2.9a
for auxiliary gate metal workfunction, and in Fig. 2.9b for tunnel gate metal workfunction, respectively. The best possible value for the auxiliary gate work function φaux comes out to be
4.4 eV and for tunnel gate φtun it is 4.0 eV. For φaux =4.4 eV and φtun =4.0 eV, the maximum
2.5 DMG-DGTFET with SiGe Source
37
Table 2.2: The summarized result in a DG-DMTFET with SiGe source for different gate dielectrics.
Gate Dielectric
SiO2
Si3 N4
Hf O2
ZrO2
Dielectric Constant
3.9
7.5
22
29
(a)
ION (µA/µm)
14
82.3
322
377.4
IOF F (A/µm)
1.2 ×10−15
1.34 ×10−14
8.4 ×10−14
1 ×10−13
SSAV G (mV/decade)
75.6
46.7
22.8
19
(b)
Figure 2.10: DMG-DGTFET based on SiGe source at 50 % Ge mole fraction in SiGe, and different gate
dielectric material (Ltun = 5 nm and Laux = 20 nm). (a) Energy band diagram along a horizontal cut line
near to the surface at ON-state (VGS =1.5 V VDS = 1V). (b) Transfer characteristics at φaux = 4.4 eV and
φtun = 4.0 eV for different dielectrics.
value of gate current under auxiliary gate is limited to 10−13 A/µm, while for tunnel gate it is
limited to 10−12 A/µm.
The ON current for the proposed device comes out to be 300 µA/µm. Besides ON current,
subthreshold slope is very crucial parameter for defining the device performance. The average
subthreshold slope at 50 % Ge mole fraction in SiGe DMG-DGTFET comes out to be 22.8
mV/decade. The drain saturation voltage (Vdsat ) is also computed for Fig. 2.9c. The value of
Vdsat comes out to be 0.87 V, 0.85 V, 0.83 V, and 0.80 V for gate voltage of 1.0 V, 0.9 V, 0.8 V,
and 0.7 V, respectively.
2.5.2
Effect of gate dielectrics
The drain current results obtained for different gate dielectric materials along with the energy
band diagram at ON state are shown in Fig. 2.10a. The gate oxide materials used are silicon
2.5 DMG-DGTFET with SiGe Source
(a)
(c)
38
(b)
(d)
Figure 2.11: The effect of different Ge mole fraction on DMG-DGTFET performance with hafnium
oxide gate dielectric and hetero SiGe on the source. (a) Energy band diagram is shown at ON state
(VGS = 1.5 V and VDS = 1.0 V). (b) Transfer characteristics on log and linear scale at φtun =4.0 eV and
φaux =4.4 eV, and (c) plot of average subthreshold slope against Ge mole fraction in SiGe. (d) DIBL
effect evaluated at different Ge mole fraction with φtun =4.0 eV and φaux = 4.4 eV.
dioxide (SiO2 ), silicon nitride (Si3 N4 ), hafnium oxide (Hf O2 ), and zirconium oxide (ZrO2 )
with dielectric constant of 3.9, 7.5, 22, and 29, respectively.
Higher dielectric constant of the gate dielectric leads to higher ON current, as shown in
Fig. 2.10b. This is a consequence of the reduction in barrier width at the junction, which
increases the BTBT tunnelling probability. As evident from Table-2.2, that with increasing
dielectric constant of gate materials, sub-threshold slope also improves due to better gate control
on the channel with a slight increase in the OFF state current.
2.6 Summary
2.5.3
39
Effect of Ge mole fraction in hetero SiGe source
The effect of varying the Ge mole fraction in hetero SiGe layer on the transfer characteristics
along with the energy band diagram at ON state is shown in Fig. 2.11. As the Ge mole fraction increases energy bandgap decreases at the source as shown in Fig. 2.11a. This results in
increased steepness in the energy band near to the source. The increased steepness in the energy band decreases the tunneling barrier width at the tunneling junction, which increases the
BTBT current (see Fig. 2.11b). The Ge mole fraction variation changes the energy band gap,
which has little impact on intrinsic carrier density and hence on the OFF state current, as shown
in Fig. 2.11b. The average subthreshold slope calculated with variation in Ge mole fraction is
displayed in Fig. 2.11c. The impact of Ge mole fraction variation on the drain induced barrier
lowering (DIBL) is shown in Fig. 2.11d. The DIBL is calculated as the difference in gate voltage for the drain current of 1 nA/µm from the transfer characteristics at drain voltage of 1.0V
and 0.1 V. As the Ge mole fraction increases the barrier width at the junction reduces which
increases the BTBT tunnelling current. Therefore, increasing the Ge mole fraction in SiGe reduces the DIBL effect. The use of high-k dielectric further reduces the DIBL effects due to
better gate coupling with channel.
2.6
Summary
The DMG technique, when applied to Si-DGTFET results in individual control for the different
section of the transfer characteristics by adjusting the work function of the two metal. This
results in the improvement of the ION /IOF F ratio and the average subthreshold slope. We
find that the performance can be improved further by use of a different dielectrics under the
gate (hetero dielectric). However the use of high-k dielectric results in the degradation of the
mobility at the interface due to columbic scattering. This mobility degradation can be improved
by using Retro grade kind of doping profile, where the doping is kept low at the surface and
high in the body. Thus we can conclude that DMG along with hetero dielectric provides a very
powerful technique to boosts the performance of DMG-DGTFET. One limitation of the DMG-
2.6 Summary
40
DGTFET is the increased fabrication complexity particularly for the hetero dielectric devices,
as the device dimensions scale down
The DMG technique along with the SiGe source, further boost the ON current as compared
to Si based DMG-DGTFETs. Increasing the Ge mole fraction in the SiGe source, also leads to
improved subthreshold slope. The device with higher dielectric constant materials show better
ON current and further improvement in short channel effects.
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[19] X. Y. Huang, G. F. Jiao, W. Cao, D. Huang, H. Y. Yu, Z. X. Chen, N. Singh, G. Q. Lo,
D. L. Kwong, and M. F. Li, “Effect of Interface Traps and Oxide Charge on Drain Current
Degradation in Tunneling Field-Effect Transistors,” IEEE Electron Device Letters, vol. 31,
no. 8, pp. 779–781, Aug 2010.
[20] S. Saurabh and M. J. Kumar, “Estimation and Compensation of Process-Induced Variations in Nanoscale Tunnel Field-Effect Transistors for Improved Reliability,” IEEE Transactions on Device and Materials Reliability, vol. 10, no. 3, pp. 390–395, Sept 2010.
[21] M. N. Darwish, J. L. Lentz, M. R. Pinto, P. M. Zeitzoff, T. J. Krutsick, and H. H. Vuong,
“An improved electron and hole mobility model for general purpose device simulation,”
IEEE Transactions on Electron Devices, vol. 44, no. 9, pp. 1529–1538, Sept 1997.
[22] M. Luisier and G. Klimeck, “Performance comparisons of tunneling field-effect transistors made of InSb, Carbon, and GaSb-InAs broken gap heterostructures,” in IEEE International Electron Devices Meeting (IEDM), Dec 2009, pp. 1–4.
BIBLIOGRAPHY
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[23] M. Hasan, H. Park, H. Yang, H. Hwang, H. S. Jung, and J. H. Lee, “Ultralow work function
of scandium metal gate with tantalum nitride interface layer for n-channel metal oxide
semiconductor application,” Applied Physics Letters, vol. 90, no. 10, p. 103510, 2007.
[24] W. Y. Choi and W. Lee, “Hetero-Gate-Dielectric Tunneling Field-Effect Transistors,”
IEEE Transactions on Electron Devices, vol. 57, no. 9, pp. 2317–2319, Sept 2010.
[25] E. O. Kane, “Theory of Tunneling,” Journal of Applied Physics, vol. 32, no. 1, pp. 83–91,
1961.
Chapter 3
Strain Engineering in SiGe source TFETs
3.1
Introduction
The previous chapters motivated the need to boost the ON current in Si TFETs, as it is limited
by the large bandgap in Si. Further, we have seen that the ON current can be boosted by DMG
technique and by using a relaxed SiGe source (low band gap). In this chapter, we study the
effect of compressive strain in SiGe source, and the resulting impact on the BTBT current.
We have proposed different double gate hetero device structure TFETs incorporating the strain
effects at the source and the channel. In the proposed device structure, DGTFET with typeII staggered band alignment, compressively strained SiGe source, and a portion of a tensile
strained Si channel with hetero dielectric gate (HD) material is discussed with the experimental
BTBT parameter values. The effect of pocket implant underneath the gate at the source/body
junction is also discussed for this structure. The use of pocket implant at the source/body
junction increases the ON current, but due to SRH electric field enhanced recombination, the
OFF state current also increases by a large amount.
In the other proposed device structure, DGTFET with type-II staggered band alignment and
SiGe/Si/SiGe extended source is discussed with the experimental BTBT parameter values. The
different encroachment of SiGe under the gates were explored to find that optimum performance occurs for 2 nm extension. The effect of field induced sub-band discretization at the
oxide/semiconductor interface is considered by back envelope calculation method.
In Ref. [1, 2], authors have done experimental and theoretical BTBT parameters calcula45
3.1 Introduction
46
(a)
(b)
(c)
Figure 3.1: Schematic of DGTFET with compressively strained SiGe (c-SiGe) source and hetero dielectric gate: (a) without pocket implant, and (b) with pocket implant. (c) Extended SiGe/Si/SiGe source
structure with mono dielectric gate.
tions. The deviation between experimental and theoretical parameter is accounted by multiplying it with a constant factor. They [1, 2] have not investigated different structures for TFETs,
as we have done in our work. Source extended structure is also not explored incorporating the
compressive strain effects in SiGe. Additionally, we have incorporated the tensile strain effect
in Si on band alignment [3, 4] and the effect of Field Induced Quantum Confinement [5]. Further, we have shown that due to the electric field enhanced SRH recombination, OFF current
increases by large amount in pocket implant TFETs.
The rest of the chapter is organized as follows: In section-3.2, we have elaborated the structure of c-SiGe source DGTFET without and with pocket implant and HD gate, and also the
source extended structure with mono dielectric gate is discussed. The fabrication details and
the simulation model that are incorporated are also discussed in this section. In section-3.3,
the compressive strain effect on SiGe is discussed. The Kane BTBT parameters for c-SiGe is
discussed in section 3.4. This is followed by the discussion of field induced quantum confinement effect in section 3.5. The results that we have obtained from the simulation for different
proposed device structure are discuss in section 3.6. In section 3.7, conclusion are drawn.
3.2 Device structure, fabrication, and simulation models.
3.2
47
Device structure, fabrication, and simulation models.
The proposed device structure are shown in Fig. 3.1a and Fig. 3.1b for hetero dielectric gate
(HD), without and with pocket implant. The sandwiched SiGe/Si/SiGe hetero junction is proposed at the source, that results in a compressive strain at the source and allows to grow higher
Ge mole fraction at the surface of SiGe. Due to the vertical lattice mismatch at SiGe/Si hetero
junction, portion of the Si channel is tensile strained. In the other proposed device structure, we
have extended the compressively strained SiGe source below the gate. The device structure is
shown in Fig. 3.1c, in which SiGe/Si/SiGe source structure is extended into the gate side of the
channel. SiGe is primarily used to exploit the higher tunneling rate from the SiGe region. This
is due to the large built-in electric field at the junction of SiGe with Si, which is caused by the
lower band gap of SiGe.
3.2.1
Fabrication
The method to fabricate TFETs using SiGe source and drain has already been demonstrated in
Ref. [6]. The SiGe source can be formed by etching of Si underneath the gate [6] and regrowth
of in-situ doped p+ Si1−x Gex [7, 8]. The hetero dielectric (HD) gate can be fabricated by the
steps reported in Ref. [9]. We have assumed the doping profile to be constant in the drain,
source and body region [10].
We consider a device of channel length 25 nm, silicon body thickness of 8 nm, n-type drain
doping of 1018 cm−3 , p-type source doping of 1020 cm−3 , and body is low n-type doped of 1016
cm−3 . The length of SiO2 gate is 18 nm and that of Hf O2 is 7 nm. The gate dielectric is 2 nm
in thickness. Further, the thickness of SiGe layer is 2 nm and it is doped p-type with a doping
concentration of 1020 cm−3 . The work function of metal at the gate (φm ) is 4.2 eV.
3.2.2
Simulation models
The simulation are done in Sentaurus from Synopsys TCAD, where all relevant physical effects have been included. The band-to-band-tunneling (BTBT) current was simulated by using
3.3 Strain Analysis
48
non local tunneling model, gate leakage mechanism has been included via the direct tunneling
model. Due to the very high local electric field assumed in the drift diffusion model, unrealistic
impact ionization sets in the device. To avoid this unrealistic impact ionization and to include
non-local electric field effect hydrodynamic transport is considered in the simulation. To account for the very high doping in source, we have included band gap narrowing effects and
Fermi Dirac statistics. The calibrated parameter values were used for non local BTBT model
for compressive strained SiGe following Ref. [1]. The default parameter values of non-local
BTBT model for SiGe in Sentaurus are for relaxed SiGe and is calculated for different mole
fraction of Ge by using interpolation, which over estimates the experimental values [2]. MLDA
model is used to consider the confinement effects due to the charge centroid shift [5].
The compressive strain between SiGe and Si is due to lattice mismatch creates mainly two
effects: (1) it reduces the bandgap of relaxed SiGe [2, 11], and (2) it splits the valence and
conduction band. The default band gap of SiGe is changed with the experimental values following Ref. [3]. The splitting of the valence and conduction band is considered by including
the deformation potential model. The valence band effective mass are considered from the 6band k.p model following Ref. [12]. There are two tunneling path formed in the device due to
the splitting of valence band and it is considered by invoking the second tunneling path in the
BTBT model with the calibrated BTBT parameter values. The sub band discretization due to
the electric field induced quantum confinement is considered by using a correction factor in the
onset voltage. In the next section, we analyze the impact of strain on SiGe and Si.
3.3
Strain Analysis
The lattice constant of pseudomorphically grown SiGe [001] on [001] Si substrate is higher than
Si, as a result biaxial compressive strain develops in SiGe. Due to the vertical lattice mismatch
at source/channel junction (SiGe/Si) a portion of the channel is tensile strained. The strain is
compressive at the SiGe source and tensile in the Si channel and it’s effect is discussed below.
3.3 Strain Analysis
49
(a)
(b)
Figure 3.2: Qualitative depiction of the strain effects in Si and SiGe following Ref. [3]. (a) The effect
of compressive strain in SiGe showing the hydrostatic strain shift and uniaxial component of strain. (b)
Valence band splitting of V1 and V2 band for different mole fraction of Ge in c-SiGe and t-Si.
3.3.1
Compressive Strain in SiGe
The compressive strain in SiGe has a hydrostatic component, which shifts the energy bands and
a uniaxial component along [001] which causes the degeneracy in the band [3]. It splits the ∆6
ellipsoidal non degenerate conduction band into ∆4 and ∆2 band as shown in Fig. 3.2a. ∆4
bands are in lower energy as compared to ∆2 bands. The strain also splits the valence band into
V1 and V2 at the Γ point. The electron effective mass of the c-SiGe ∆4 valley is independent
of strain and Ge content [5]. The hole effective mass is considered by using a 6-band k.p band
model with a set of luttinger parameter [13] values. The energy separation between V1 and V2
is small at low mole fraction of Ge (x) [3] and it increases with x as shown in Fig. 3.2b. The
separation between V1 and V2 bands is only about 80 meV at x=0.5. Thus, we have considered
two BTBT path following Ref. [1, 3].
3.3.2
Tensile strain in Si
At the vertical Si/SiGe interface, due to the difference in lattice constant strain is developed
in Si channel, which is tensile [4]. This tensile strain in Si channel does exactly opposite of
compressive strain i.e it splits the ∆6 band into ∆2 and ∆4 , but the energy of ∆2 band is lower
than ∆4 . We have assumed the tensile region to be of 2 nm. Note that increasing the length
of this region is not going to affect the tunneling, since tunneling is taking place within few
3.4 BTBT Model Parameters
50
nanometer along the side of the c-SiGe/t-Si junction. For t-Si, we have considered the Si BTBT
parameters and band gaps are considered following Ref. [2].
In the following section, we discuss the calibrated values of the BTBT model parameters
that are used throughout the simulation.
3.4
BTBT Model Parameters
The BTBT current is defined as the integral of the generation rate over the entire device region
[14]. Mathematically,
Z Z
Itun = q
GBTBT dydx ,
(3.1)
where GBTBT is the BTBT generation rate per unit volume which depends on the Kane tunneling parameters. In the presence of uniform electric field, GBTBT is defined as [14]
GBTBT
P
E
B
=A
exp −
,
E0
E
(3.2)
where E0 = 1 V/cm, P = 2 and 2.5 for direct and indirect tunneling, respectively, A and B are
the parameters for the Kane model and E is the electric field across the tunneling junction. The
Kane parameters A and B for indirect tunneling are given by:
Aind =
g (mDOSc mDOSv )3/2 (1 + 2NTA ) DT2 A (qE0 )5/2
5/4
221/4 h5/4 mr ρTA (Eg + Mc )7/4
,
(3.3)
1/2
Bind =
27/2 πmr (Eg + Mc )3/2
,
3qh
(3.4)
where the symbols have there conventional meaning as specified in the Ref. [1].
The conduction band density of state effective mass (mDOSC ) of the ∆4 valley is defined
1
as a geometric mean of longitudinal (ml ) and transverse (mt ) effective masses as (ml m2t ) 3 (ml
and mt are nearly independent of Ge Content [13]). Valence band density of states effective
3
3
2
2
mass (mDOSV ) is defined as (mlh
+ mhh
)(2/3) , where, mlh and mhh are the light and heavy hole
effective masses, respectively. The reduced tunneling mass (mr ) is defined as by the curvature
3.4 BTBT Model Parameters
51
Table 3.1: Parameter which are used for the calculation of non-local BTBT model parameters for comre is the relaxed
pressively strained SiGe at various Ge mole fraction taken from the work [1], where EG
band gap. All effective masses are in the units of m0 (free electron mass).
x
0
0.1
0.2
0.3
0.4
0.5
0.6
ρ (kg/m3 )
2329
2673
3008
3332
3646
3951
4245
DT A (eV/m)
1.69 × 1010
1.64 × 1010
1.60 × 1010
1.55 × 1010
1.51 × 1010
1.46 × 1010
1.42 × 1010
T A (meV)
19
18
16.9
15.9
14.8
13.8
12.8
Egre (eV)
1.12
1.08
1.03
0.991
0.959
0.935
0.919
EgV 1 (eV)
1.12
1.08
1.03
0.991
0.959
0.935
0.919
EgV 2 (eV)
1.12
1.06
0.990
0.935
0.882
0.835
0.799
mL
0.92
0.92
0.92
0.92
0.92
0.92
0.92
mT
0.19
0.19
0.19
0.19
0.19
0.19
0.19
mDOSC
0.32
0.32
0.32
0.32
0.32
0.32
0.32
mDOS,V 1
0.52
0.23
0.21
0.20
0.18
0.16
0.15
mDOS,V 2
0.15
0.22
0.21
0.19
0.18
0.16
0.15
Table 3.2: Degeneracy factor g, electron curvature effective mass (me ), hole curvature effective mass
(mV 1 / mV 2 ), and the reduced tunneling mass (mr ) used in the theoretical calculation of Aind and Bind
along [001] tunneling direction in the c-SiGe. All effective mass are in the units of the free electron
mass. Aind and Bind are in units of cm−3 s−1 and M V cm−1 , respectively. Note that g, me and mV 1
(V1 corresponds to HH in relaxed SiGe) are strain independent.
x
0
0.1
0.2
0.3
0.4
0.5
0.6
g
8
8
8
8
8
8
8
me
0.19
0.19
0.19
0.19
0.19
0.19
0.19
mV 1
0.289
0.284
0.277
0.268
0.259
0.250
0.240
mv2
0.201
0.228
0.233
0.288
0.220
0.211
0.20
mVr 1
0.115
0.114
0.113
0.111
0.110
0.108
0.106
mVr 2
0.098
0.104
0.105
0.104
0.102
0.100
0.097
AVind1
7.41 × 1015
2.24 × 1015
2.28 × 1015
2.24 × 1015
2.31 × 1015
2.28 × 1015
2.41 × 1015
V1
Bind
24.9
22.18
19.26
17.01
14.94
13.23
11.61
AVind2
1.47 × 1015
2.40 × 1015
2.31 × 1015
2.158 × 1015
2.158 × 1015
2.08 × 1015
2.02 × 1015
V2
Bind
23
21.6
19.62
17.91
16.29
14.85
13.68
mass of conduction band (me ) and valence bands (mV 1 and mV 2 ) along the [001] tunneling
me mlh
direction mr = me +mlh [15]. NT A = exp(T A1/KT )−1 is the occupation number of the transverse
acoustic phonon, ρ is the mass density, T A is the transverse acoustic phonon energy, and Eg is
the minimum band gap [1].
All the parameters values, which are used to calculate the Kane parameters for c-SiGe are
listed in Table. 3.1. The Kane BTBT tunneling parameters are tabulated in Table. 3.2, along
the [001] tunneling direction. Mass density (ρ) as a function of Ge mole fraction is given
by, ρ = 2.329 + 3.493x − 0.499x2 [16]. The estimated deformation potential of transverse
acoustic phonons (DT A ) for Si is 2.45 ×1010 eV/m, and for Ge is 0.8 ×1010 eV/m [17]. The
transverse acoustic phonon energy T A for Si is 19 meV, and for Ge is 8.6 meV. These values
are extracted from [16], and for SiGe it is determined by linear interpolation [18]. We have only
considered transverse acoustic phonon into account because of its high occupation number and
small phonon energy [19]. Degeneracy factor is expressed as: G= 2gv gc which consists of the
3.5 Field Induced Quantum Confinement (FIQC)- Back Envelope Calculations.
52
electron spin degeneracy factor 2 and the valence and conduction band valley degeneracy.
3.5
Field Induced Quantum Confinement (FIQC)- Back Envelope Calculations.
The effect of sub-band discretization due to the formation of the quantum well at the oxide/semiconductor interface is considered by back envelope calculation method [5]. In the Kane
dispersion relationship, valence and conduction band are considered as continuous in the BTBT
current calculations without sub-band effects. To include the sub-band effect, triangular well
approximation is used and the first sub band energy is evaluated using Airys function approach
as,
α
Esub
= −a0
2
h2 Fox,α
8π 2 m∗α
13
,
(3.5)
where a0 =-2.381 is the first zero of the airy function, and m∗α is electron effective mass in the α
valley. The force acting on the electron at the semiconductor/oxide interface Fox,α at the onset
of tunneling is,
s
Fox,α =
α
2q 2 Ns (EGα + Esub
)
,
s
(3.6)
where s is the semiconductor permitivity, and Egα is the tunneling band gap between the valence
α
band and the α valley of the conduction band. A cubic equation will be formed in Esub
, which
has two imaginary and one real roots [5]. The onset voltage of the tunneling can be written as,
α
α
Vonset
= Egα + Esub
+ Fox,α tox
s
− VF B ,
ox
(3.7)
where VF B is the flat band voltage. The graph is shifted manually by Vonset to include the effect
of FIQC.
3.6 Results and Discussions
3.6
53
Results and Discussions
Having described the strain effects in SiGe and Si. In this section, we discuss in detail the
results that are obtained from the simulation for the different proposed device structure. The
strain effects are incorporated at the source and channel. In section 3.6.1, we discuss heteroDGTFET (H-DGTFET) with HD gate. The effect of pocket implant at the source/channel
junction is discussed in section 3.6.2. This is followed by the discussion of the source extended
structure to find the optimum source extension length in section 3.6.3.
3.6.1
DGTFET with HD gate and c-SiGe source
In this section, the device structure that is shown in Fig. 3.1a is discuss in detail. In particular,
we will focus on the work function engineering, effect of different hetero dielectrics, and impact
of Ge mole fraction variation in c-SiGe.
3.6.1.1
Workfunction Engineering
The work function of the metal at the gate is varied and its impact on the transfer characteristics
is shown in Fig. 3.3a. As the metal gate work function increases, at ON state, the energy bands
are pulled upwards. This results in increased barrier width at the junction as shown in Fig. 3.3b,
which decreases BTBT current as shown in Fig. 3.3a. The use of higher work function metal at
the gate results in threshold voltage shift and the transfer characteristics are shifted parallel to
the X-axis. As a result subthreshold slope is not affected.
The OFF current in TFET is composed of BTBT current plus reverse leakage current, considering the generation and recombination in the depletion region. The OFF current remains
almost constant as the metal work function increases. This is a consequence of the fact that as
work function of metal increases, energy band below the gate are pulled upwards. This prevents the formation of tunneling path in the device as shown in Fig. 3.3c and thus the OFF state
current is composed only of reverse leakage current. At low work function due to the formation of tunneling path in the device BTBT takes place, which increases the OFF current. The
SSAV G for the proposed device structure comes out to be 64.3 mV/decade for 4.2 eV metal
3.6 Results and Discussions
(a)
(c)
54
(b)
(d)
Figure 3.3: DGTFET (L = 25 nm and tox =2 nm) based on the c-SiGe source, 0.5 Ge mole fraction,
and HD gate for different values of φm . (a) Transfer characteristics at VDS = 1.0 V shown on both
semi log and linear scale. Energy band diagram along a horizontal cut line near to the surface is shown
at:(b) ON-state (VGS =1.5 V and VDS = 1V), and (c) OFF-state (VGS = 0.0 V and VDS = 1V). (d) Output
characterisitcs for different gate voltages.
work function and 0.5 Ge mole fraction in c-SiGe.
The output characteristics of the devices for different gate voltage is shown in Fig. 3.3d.
The drain saturation voltage (Vdsat ) is calculated as the value of drain voltage which diminishes
the channel charge at the drain end and is evaluated at 95 % of the steady state value of drain
current. The value of Vdsat comes out to be 0.64 V at VG =1.0 V.
3.6 Results and Discussions
(a)
55
(b)
Figure 3.4: DGTFET based on c-SiGe source, 0.5 Ge mole fraction and different hetero gate dielectric.
(a) Energy band diagram calculated along a horizontal plane near to the surface is shown at ON state. (b)
Transfer characteristics at φm =4.2 eV at VDS =1.0 V.
3.6.1.2
Effect of different hetero dielectrics
The dielectric, which is used at the drain end is fixed with SiO2 and the dielectric at the source
end is replaced with high-k dielectric. The dielectric that we have used are Hf O2 and ZrO2
with a dielectric constant of 22 and 29 respectively. The simulation results obtained using
Hf O2 and ZrO2 are shown in Fig. 3.4 for 4.2 eV as work function of the gate metal.
It is evident from Fig. 3.4a that as the value of dielectric constant increases, barrier width at
the junction reduces as shown in Fig. 3.4a. The reduced barrier width is due to the improved
gate coupling with high-k dielectric. The decrease of the barrier width at the junction results in
increase in the BTBT current as shown in Fig. 3.4b.
3.6.1.3
Effect of Ge mole fraction in c-SiGe
As the mole fraction of Ge increases in c-SiGe, compressive strain increases in the SiGe source,
which reduces the band gap as shown in Fig. 3.5a. This results in reduced barrier width and
the increased BTBT current as shown in Fig. 3.5b. A slight increase in the OFF current is observed due to the change in the intrinsic carrier concentration, because of reduction in bandgap
with increasing Ge mole fraction. The SSAV G and ION is plotted against Ge mole fraction in
Fig. 3.5c. SSAV G and ION improves with Ge mole fraction.
3.6 Results and Discussions
56
(a)
(b)
(c)
Figure 3.5: The effect of different mole fraction of Ge(x) in DGTFET based on c-SiGe with HD gate.
(a) Energy band diagram along a horizontal cut line near to the surface is shown at ON-state (VGS =1.5
V and VDS = 1 V). (b) Transfer characteristic at VDS = 1.0 V at φm =4.2 eV. (c) SSAV G and ION v/s Ge
mole fraction (x).
3.6.2
DGTFET with Pocket Implant
In this section, we explore the impact of pocket implant under the gate at source/body junction
in a DGTFET as shown in Fig. 3.1. The pocket implant is considered to be n-type and 2 nm in
length. As the pocket implant doping increases, BTBT current increases because of the reduced
barrier width at the junction.
The increase in ON current due to pocket implant is due to the band gap narrowing at the
source/body junction. Band gap narrowing results in steeper energy band at the junctions as
shown in Fig. 3.6a, which increase the BTBT current. The increase in BTBT current is more
for pocket implant doping (NP OC ) greater than 1019 cm−3 as shown in Fig. 3.6b. This is because
3.6 Results and Discussions
57
(a)
(b)
(c)
Figure 3.6: DGTFET (L = 25 nm and tox =2 nm) based on the c-SiGe source, 0.5 Ge mole fraction, HD
gate and pocket implant near the source junction. (a) Energy band diagram along a horizontal cut line
near the surface is shown at ON-state (VGS =1.5 V and VDS = 1 V) for different pocket implant doping
(NP OC ) at φm =4.2 eV. (b) Transfer characteristics at VDS = 1.0 V is shown on both semi log and linear
scale for different value of NP OC . (c) SSAV G and ION against NP OC doping.
as the value of NP OC reaches the density of states value, Fermi level moves into the conduction
band. This reduces the effective band gap and results in a discontinuity in the conduction band,
which appeared in the form of kink in Fig. 3.6a.
The OFF state current rises as the value of NP OC increases. The increase in OFF state
current is entirely attributed due to the SRH field enhanced recombination. SRH recombination
lifetime reduces because of high electric field, which causes electron hole pair generation before
BTBT tunneling and increases the OFF state current by a large amount. There are three main
contributor to SRH recombination, which changes the minority carrier life time and hence the
generation and recombination of carriers. The minority carrier lifetime is modeled as product
3.6 Results and Discussions
(a)
58
(b)
Figure 3.7: Transfer characteristics of DGTFET with extended c-SiGe source and 0.5 Ge mole fractions
for different encroachment length (nm) inside the gate. As the source is extended inside the gate, tunneling is delayed due to the increase in tunnel barrier width because of the depletion of the extended part of
the source. (b) Subthreshold slope and ON-current for different extension length inside the gate.
of doping dependence, field dependent and temperature dependent lifetime. The SRH doping
dependence has been taken into account by Scharfater model, which models the carrier lifetime
as a function of doping. The enhanced electric field reduces SRH recombination lifetime in
regions of strong electric field and it is considered by SRH field enhanced model. In Fig. 3.6c,
we have shown the variation of SSAV G and ION with pocket implant doping (NP OC ). The
SSAV G and ON current improves with pocket implant doping.
The effect of FIQC can be considered by manually shifting the curve by Vonset . The calculation of Vonset is discussed in section 3.5. The decrease in band gap due to band gap narrowing
for NP OC =1e+20 cm−3 comes out to be 0.032 eV (extracted from simulations). The value of
onset voltage for NP OC =1e+20 cm−3 at Eg =1.12-0.032 eV comes out to be 0.956 V and the
value of Fox,α comes out to be 3.47 MeV/cm. Without pocket implant the value of onset voltage
comes out to be 0.988 V.
3.6.3
DGTFET with source extended structure
In this section, the source extended structure, which is shown in Fig. 3.1c is discuss. The
transfer characteristics of the device is shown in Fig. 3.7a. It is expected that the extended
p++ doping underneath the gate results in depletion in the extended part of source leading to
3.6 Results and Discussions
(a)
59
(b)
Figure 3.8: Energy band diagram along a horizontal cut near to the surface calculated at: (a) ON state
(VGS =1.5 V and VDS =1 V). The tunnel barrier width increases with the extension length and 2nm extension gives the best BTBT rate.(b) OFF state (VGS =0 V and VDS =1 V). No tunneling path is formed for
any of the structures in the OFF state as shown by dotted line.
a widening source-channel barrier width. This concomitant lower BTBT rate, and increasing
SS with increasing source extension. The extracted subthreshold slope (SS) and ION current
variation for 0, 2, 4 and 6 nm extension comes out to be 67.2, 65.7, 78.3 and 71.6 mV/decades
respectively, as shown in Fig. 3.7b.
It is also observed that the ON-current is maximum for the 2 nm extension as shown in
Fig. 3.7b. The reason for this behavior can be explained as follows: tunneling path is always
shorter for the 0 nm extension as shown in Fig. 3.8a. However, the tunneling, which is from
c-SiGe valence band to t-Si conduction band, mostly occurs in the Si region. On the other hand,
for the 2 nm extension, at larger VG , the whole tunneling path lies completely inside SiGe,
which results in higher BTBT rate due to lower reduced mass.
In the OFF-state, the BTBT current in the TFET is comparable or less than the reverse
leakage diode current, which is dependent on the generation current inside the depletion region.
It has been observed from Fig. 3.8b, in the OFF-state, the source valence band and the channel
conduction band do not overlap and there is no tunneling path at the junctions. Hence OFF
current is limited by the SRH recombination leakage current. This generation rate is higher in
SiGe than in Si due to its lower band gap and higher intrinsic carrier concentration. Extending
the SiGe under the gate also results in depletion in the overlap region, resulting in higher SRH
3.6 Results and Discussions
(a)
60
(b)
Figure 3.9: (a) Transfer characteristics of DGTFET with extended c-SiGe source, relaxed SiGe source
(r-SiGe) (Ge mole fraction = 0.5) and all Si TFET. (b) The effect of FIQC in tunneling showing the
current components and the shift in the tunneling.
leakage currents, which gives the saddle points in the ID -VG at low VG .
3.6.3.1
Si, r-SiGe (relaxed SiGe), and c-SiGe extended source TFET
The comparison between Si-TFET, TFET with r-SiGe (Relaxed SiGe) source and TFET with
c-SiGe source has been made in Fig. 3.10a. It can be concluded that the compressive strain at
the source increases the ON-current, because of reduction in bandgap. The two tunneling path,
which are formed due to the splitting of valence band increase the current by large amount as
compared to relaxed SiGe source. The SSAV G comes out to be 83.7, 79.7 and 65.7 mV/decade
for all Si, r-SiGe and c-SiGe extended source TFET. Significant improvement in both the ONcurrent and the SSAV G can be seen using compressive strain at the source.
The effect of FIQC is considered in the onset voltage. The graph is shifted manually by
Vonset , however the current before the onset of tunneling will consists of reverse saturation
current. We merge these two current at the onset voltage to get the characteristics as shown in
Fig. 3.10b. The decrease in band gap due to band gap narrowing for high doping comes out to be
0.06 eV (extracted from simulations). The value of onset voltage in tunneling at Eg=0.756-0.06
eV comes out to be 0.732 V and the value of Fox comes out to be 3.1 MeV/cm.
3.7 Summary
61
(a)
(b)
Figure 3.10: Channel length scaling of DGTFET (a) with gate aligned structure, and (b) Source extended
structure.
3.6.4
Channel length scaling
We have also performed simulation for different channel lengths for gate aligned and source
extended structure. The channel length scaling should not affect the BTBT current. This is due
to the fact that BTBT takes place only few nm along side source/body junction. As channel
length is scaled, electrostatics of the system is changed slightly, which affects the OFF current.
These results are also verified from the simulations and are shown in Fig. 3.10.
3.7
Summary
This work has emphasized upon the compressive strain effect on SiGe. We have investigated
different device structure and have observed that the compressive strain in SiGe, improves the
SS and ON current as compared to r-SiGe and Si TFETs. As a result of the compressive strain,
splitting of valence and conduction band takes place and the effective band gap reduces. Additionally, from pocket implant study it can be concluded that its not a effective method to
increase the ON current due to very large increase in OFF current. The hetero dielectric gate
results in simultaneous decrease in the OFF current and increase in the ON current, thus good
performance can be achieved. The source extended structure are also scrutinized to improve
3.7 Summary
62
the TFET performance. It is observed that 2 nm source extension inside the gate results in the
best ON current and subthreshold slope. Different extensions length inside the gate degrades
the sub-threshold slope, but the increase in ON state current is large.
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Chapter 4
Band to Band Tunneling in Gamma Valley
For Ge Source TFET: Thickness scaling
4.1
Introduction
The previous chapters presented the Si, r-SiGe and c-SiGe source TFET with the different device architecture to improve the TFET performance. Further, we have discussed the workfunction and strain engineering for DGTFET as well. In this chapter, we have utilized Ge source in
order to boost the current in DGTFET. Germanium (Ge) is a widely used source material because of its low band gap [1–3] and compatibility with Silicon (Si) [4]. The direct and indirect
valley in Germanium (Ge) are separated by a very small offset, which opens up the prospect of
direct tunneling in the Γ valley of Ge tunnel field effect transistor (TFET). We have investigated
a new DGTFET design with Ge source TFET, which is based on point to point lateral tunneling.
Most of the theoretical and simulation studies on Ge TFET include only the indirect tunneling with the default TCAD parameters [5]. However, the direct valley of Ge contributes
significantly to various processes in Ge, including BTBT current. Moreover, Ge can be easily
made to be a direct bandgap semiconductor by high tensile strain (1.8 % ) [6] or by the incorporation of the larger atom Sn in the Ge lattice [7]. At room temperature, the direct valley of
Ge has been been shown (Ge on Si) to give rise to direct band gap electroluminescence [8], and
has also been utilized for photonics application [9, 10]. The dominance of direct tunneling in
Ge based diodes [11–13] has also been reported earlier.
66
4.2 Device Structure and Simulation Details
67
Figure 4.1: Schematic of the double gate TFET with extended Ge source and hetero-dielectric-gate (HG).
We consider a device of channel length 40 nm, n-type drain doping of 1018 cm−3 , p-type source doping
of 1020 cm−3 , and body is low n-type doped (1016 cm−3 ), HG gate dielectric with 2 nm thickness. Source
is extended inside the gate by 2 nm. Work function of metal at the gate is Φm = 4.2 eV
In Si, the difference between direct and indirect valley is 2.3 eV, which prohibits the prospects
of direct tunneling in the Si based TFET’s [14]. The corresponding valley offset in bulk Ge is
0.14 eV [15], which increases the probability of direct tunneling in the Ge based TFETs. It
has already been shown that thickness scaling changes the bandstructure parameters significantly in various devices [16–18]. Therefore, in this chapter, we explore the impact of Ge and
Si thickness scaling on bandstructure parameters (band gap and effective mass), their relative
band alignment, Kane’s BTBT parameters and the BTBT tunneling current in Ge source lateral
TFET.
The chapter is organized as follows: Device structure along with the band structure results,
obtained from DFT calculations, and the simulations models that are used to calculate the BTBT
current are discussed in section 4.2. Section 4.3 explains the theoretical calculation of BTBT
model parameters for ultra thin Ge and Si thickness. This is followed by results and discussion
in section 4.4. Finally we summarize our findings in section 4.5.
4.2
4.2.1
Device Structure and Simulation Details
Device Structure
The device structure under study is shown in Fig. 4.1 with source made of Ge to increase the
BTBT probability. To reduce the ambipolar and OFF currents, we have used hetero-dielectricgate [19]. Since Ge has better BTBT parameters as compared to Si, to enhance the BTBT current, the Ge source is extended inside the gate by 2 nm to confine tunneling inside Ge [20, 21].
The study comprises of ultra thin (≤ 10nm) source lateral TFETs. In BTBT current calcula-
4.2 Device Structure and Simulation Details
68
tions, Kane’s BTBT tunneling parameters for ultra thin Ge and Si slabs is calculated by considering bandstructure parameters, which are obtained through first principle calculations after
incorporating geometrical confinement. This results in the accurate evaluation of the theoretical BTBT parameters. To account the Si thickness scaling effect on BTBT current, we have
considered the confined bandstructure parameter for Si as well.
4.2.2
Atomistic Simulation
The thickness dependent Ge and Si band gap values are obtained from density functional calculations, by simulating the confined Ge and Si super cell using QuantumWise Atomistic Simulation package [22]. Electron-electron interactions and correlation effects have been considered
under meta Generalized Gradient approximation (mGGA) and a vacuum region of 1.5 nm is
added to both sides of Ge and Si super cell to prevent the interactions between the spurious
replica images. The dangling bond on both sides of the Ge and Si layer are passivated by hydrogen atoms, to prevent mid-gap states. Following Ref. [16], we have assumed that the structural properties like inter-layer distance, bond-length etc. remain unaffected due to transverse
confinement and used the bulk lattice constant of Ge and Si. We have calculated the thickness
dependent electronic dispersion at (100) Ge and Si surface orientations [16]. As a first step,
we have calibrated bulk Ge and Si bandstructure with the existing bulk band gap values using
MGGA. Then the same simulation parameters for MGGA are used in all other calculations.
The confined band structure of Ge at 4 nm thickness is shown in Fig. 4.2a. Confinement
increases the band gap of indirect valley from 0.66 eV bulk to 0.82 eV at 4 nm thickness.
Further, we note that the direct valley is not properly captured in ATK simulation (even for
bulk Ge) due to the very small direct valley offset. To overcome this and for consistency with
the reported bulk values, a constant offset at direct valley is added for all thickness [24, 25].
For Si, the confined band structure at 6 nm thickness is shown in Fig. 4.2b. As expected the
confinement increases the band gap in Si from 1.12 eV in bulk to 1.176 eV in indirect valley.
4.2 Device Structure and Simulation Details
(a)
69
(b)
Figure 4.2: The confined bandstructure for: (a) Ge 4 nm film and (b) Si 6 nm thin film. The confinement
increases the band gap in both cases. Note that Si becomes direct band gap semiconductor at reduced
thickness [23].
4.2.3
TCAD Simulation Models
For the calculation of BTBT current, Synopsys Sentaurus TCAD simulator has been used,
where we have included all the relevant physical effects. BTBT current was calculated by
using non-local BTBT tunneling model [26]. Note that the default BTBT model parameter
for Ge in Sentaurus is for indirect tunneling. To overcome this deficiency, we have theoretically calculated the parameters for both direct and indirect tunneling for different Ge thickness
at (100) orientations as tabulated in Table 4.2, and used those parameters to calculate BTBT
current. The thickness dependent Si BTBT parameter are also evaluated from the DFT results
and are tabulated in Table 4.3. To include non-local electric field effects hydrodynamic transport is considered and to account for the very high doping in source, band gap narrowing and
Fermi Dirac statistics are used. Note that the geometrical quantum effects in BTBT tunneling
have been explicitly considered by theoretically calculating BTBT parameters after considering the thickness dependent geometrical confinement effects from atomistic simulations. The
default band-gap is changed with the effective thickness dependent band gap, which we have
obtained from DFT simulations. The charge distribution due to the charge centroid shift at oxide/semiconductor interface is captured using MLDA model. Note that ideally, there will also
be stress at Si/Ge interface. However, we have not included it in our calculations due to the
4.3 BTBT Parameter and Current Calculations
70
huge computational resources required.
4.3
BTBT Parameter and Current Calculations
The BTBT current is defined as the integral of the generation rate over the entire device region
as described in section 3.4 [26].
4.3.1
Effective Masses
The curvature masses and density of state (DOS) effective masses for indirect and direct valley
are needed to evaluate the Kane BTBT parameters in Sentaurus. The effective masses are
extracted from the band structure results that we have obtained from DFT simulations, by using
parabolic fitting. The density of states (DOS) mass in conduction band is defined as mDOSc =
(ml m2t )1/3 where ml (mt ) denotes the longitudinal (transverse) effective mass. Similarly, the
2/3
3/2
3/2
DOS mass in valence band is mDOSv = mlh + mhh
, where mhh (mlh ) is the heavy hole
(light hole) effective mass. The reduced tunneling mass mr is defined by the curvature mass
of conduction band (me ) and valence bands corresponding to the light hole along the tunneling
direction: mr = me mlh /(me + mlh ) [27].
4.3.2
Kane Parameters A and B
The Kane parameters A and B for direct and indirect tunneling are given by:
Adir =
9
π2
1/2
qπmr (qE0 )2
1/2 ,
9h2 EgΓ + Mc
1/2
Bdir =
Aind =
π 2 mr
EgΓ + Mc
qh
3/2
,
g (mDOSc mDOSv )3/2 (1 + 2NTA ) DT2 A (qE0 )5/2
5/4
(4.1)
221/4 h5/4 mr ρTA (Eg + Mc )7/4
(4.2)
,
(4.3)
4.3 BTBT Parameter and Current Calculations
71
Table 4.1: Calculated density of states for indirect and direct valley. Nv , NcL and NcΓ is the DOS at
valence band, conduction band of indirect and direct valley, respectively. χL and χΓ is the electron
affinity at indirect and direct valley. ∆c(L−Γ) and ∆c(Γ−Γ ) are the conduction band offset at Si/Ge hetero
junction considering the indirect and direct valley of Si.
T hickness
Bulk (≥ 10nm)
8nm
6nm
4nm
Nv
5.1e18
5.35e18
5.83e18
7e18
Germanium
NcL
NcΓ
1.02e19 2.9e17
1.03e19 2.9e17
1.09e19 3.27e17
1.23e19 4.02e17
χL
4.1
4.07
4.03
3.94
χΓ
3.96
3.95
3.91
3.81
NcΓ
3e18
3.01e18
3.04e18
3.11e18
Silicon
NcL
χL
4.24e19 4.05
4.33e19 4.04
4.54e19 4.03
4.93e19 3.99
χΓ
4.048
4.037
3.99
3.94
Band Offset at Si/Ge
∆c(L−Γ)
∆c(Γ−Γ )
0.09
0.088
0.09
0.087
0.11
0.08
0.18
0.13
1/2
Bind =
27/2 πmr (Eg + Mc )3/2
,
3qh
(4.4)
where g is the degeneracy factor, DTA , TA and NTA is the deformation potential, energy and
occupation number of the transverse acoustic phonon respectively. Mc is the conduction band
offset at the tunneling junction. At low gate voltage, tunneling is taking place from Ge valence
band to Si conduction band. For this tunneling, Mc is calculated from the difference in electron
affinity of Si and Ge. All other parameters have their conventional meaning. In the calculation
of the Kane’s parameter, DTA = 0.8 × 1010 eV/m and TA is 8.6 meV for Ge [28, 29], while for
Si it is DTA = 2.45 × 1010 eV/m and TA is 19 meV.
4.3.3
Effect of DOS in the effective electric field
The impact of DOS on the BTBT current is two fold: a) as evident from Eqs. 4.1-4.3, the Kane’s
tunneling parameters A and B have DOS dependence in terms of the DOS effective mass, b)
The DOS of the individual valleys has to be included in the carrier distribution as well which is
an input to the 2-D Poisson equation (with quasi static approximation) used to obtain the surface
potential profile in the device. The impact of the direct valley DOS on the internal electric filed
has been neglected in earlier works [30], and is also a shortcoming of Sentaurus in which the
default parameter file for Ge uses the indirect valley DOS for electrostatic calculations.
The effective DOS in the conduction and valence band for the direct and indirect valley can
4.3 BTBT Parameter and Current Calculations
72
Table 4.2: Bandstructure dependent parameters obtained from atomistic simulation for Ge (100) slab.
L and E Γ are the band gap of indirect and direct valleys in eV . Theoretically calculated BTBT
Here, EG
G
model parameters for direct and indirect tunneling for Ge (100) slab at different thickness. A and B are
in units of cm−3 s−1 and M V cm−1 , respectively.
Germanium
Thickness
bulk ≥ 10nm
8nm
6nm
4nm
Band Structure Parameters
ml
mt
EGΓ
mΓ
0.66 1.6
0.08
0.8
0.04
0.69 1.62 0.08 0.81 0.044
0.73 1.61 0.085 0.85 0.047
0.82 1.65 0.096 0.95 0.054
EGL
Direct BTBT
ADir
BDir
20
1.465 × 10
6.03
1.46 × 1020 6.14
1.45 × 1020 6.71
1.42 × 1020 8.19
Indirect BTBT
Aind
Bind
15
2.23 × 10
4.98
2.05 × 1015 5.39
1.89 × 1015
6
1.64 × 1015 7.47
be calculated as:
Nc
Nv
3/2
2πmDOSc kT
= 2M
,
h2
3/2
2πmDOSv kT
= 2
.
h2
2/3
(4.5)
(4.6)
where M is the number of equivalent valleys in the conduction band. The effective mass, and
consequently the DOS for both the valleys also change with thickness scaling. So, we have
theoretically calculated the DOS for direct and indirect valley of Ge and Si and is shown in
Table 4.1.
4.3.4
Effect of band alignment at Si/Ge junction
As we scale down in thickness, the band alignment at the Si/Ge hetero junction changes significantly which affects the BTBT current. Due to the difference in electron affinity and band gap
of Si and Ge, a discontinuity is present at both valence and conduction band at source/channel
junction. Jaro’s theory predict a valence band offset of 4Ev,av = 0.48 eV for a bulk Ge/Si hetero interface [7], which is in reasonable agreement with the experimentally reported value of
0.5 eV [7]. The electron affinity also changes with thickness scaling. It is calculated as per
Ref. [39], and tabulated in Table 4.1. The conduction band offset at Si/Ge interface for various
thickness is evaluated and is tabulated in Table 4.1 for both, direct and indirect valley of Si.
Table 4.2 contains all the bandstructure parameter values obtained from the atomistic sim-
4.4 Results and Discussion
73
L
Table 4.3: Bandstructure parameters obtained from atomistic simulation for Si (100) slab. Here, EG
Γ
and EG are the band gap of indirect and direct valleys in eV . Theoretically calculated BTBT model
parameters for direct and indirect tunneling for Si (100) slab at different thickness. A and B are in units
of cm−3 s−1 and M V cm−1 , respectively.
Silicon
Thickness
bulk ≥ 10nm
8nm
6nm
4nm
Band Structure Parameters
ml
mt
EGΓ
mΓ
1.12
1.4
0.354 1.105 0.206
1.133 1.402 0.361 1.114 0.206
1.176 1.405 0.378 1.138 0.208
1.225 1.416 0.409 1.162 0.211
EGL
Direct BTBT
ADir
BDir
2.44 × 1020 22.3
2.431 × 1020 22.5
2.392 × 1020 23.8
2.31 × 1020 26.6
Indirect BTBT
Aind
Bind
4.68 × 1015 29.85
4.62 × 1015 30.6
4.53 × 1015 32.2
4.18 × 1015 36.5
ulation, that are used to calculate BTBT model parameter for Ge and the other parameters are
taken from Ref. [30]. The Kane’s parameter A and B for Ge are evaluated by considering
all the above mentioned effect and are also tabulated in Table 4.2. As Ge thickness is scaled,
the Kane parameter A decreases while B increases. For BTBT parameters calculated from
DFT after incorporating the above mentioned effects, the value of Bdir for Ge at 8 nm thickness increases from 6.14 MV/cm to 8.19 MV/cm at 4 nm thickness, which should degrade the
current. As a consistency check we note that for Bulk Ge (100), our Bdir = 6.03 MV/cm, is
more or less consistent with earlier reported values of 5.3 MV/cm and 5.7 MV/cm in Refs. [13]
and [12]. Note that the default value of Kane’s parameters used for Ge in Sentaurus TCAD are
A = 9.1 × 1016 cm−3 s−1 and B = 4.9 MV/cm [29, 31], which grossly overestimate the current at reduced thickness. As expected the similar trend is followed for Si thickness dependent
BTBT parameters. The value of A decreases, while B increases. The thickness dependent Si
BTBT parameters are shown in Table 4.3.
4.4
Results and Discussion
Having described the calculations of the BTBT parameters for thickness scaled Ge and Si, in
this section, we discuss the impact of thickness scaling on the BTBT current by using the DFT
calculated BTBT parameters. The band alignment will change significantly with thickness scaling due to the confinement effect in Si and Ge. To investigate the impact of band alignment with
thickness, we have separately discussed the Ge to Si and Ge to Ge tunneling in the following
4.4 Results and Discussion
(a)
74
(b)
Figure 4.3: (a) Thickness scaling of total BTBT current considering direct and indirect valley of Si (VDS
= 0.7 V). Subsurface BTBT improves the current in subthreshold region with thickness scaling of Ge
films due to the improved gate coupling. (b) Variation of ON current with Ge thickness for a constant
gate overdrive voltage of 0.8 V. Ge film thickness scaling results in decrease of ION (due to increase in
band gap) and improvement in average subthreshold slope (because of the improved gate coupling).
subsections.
4.4.1
Ge to Si: Band alignment and BTBT
DFT results of confined Si shows that Si becomes a direct band gap material at scaled thickness
[23], see Fig. 4.2b. Thus, for Si we have considered two tunneling path, both originating from
valence band of Ge to direct and indirect valley of Si, with the direct and indirect tunneling
BTBT parameters, respectively. We find that the direct tunneling in Si dominates over indirect
tunneling, due to the better values of BTBT parameter as shown in Table 4.3.
The drain current calculated for ultra thin Ge devices considering the direct and indirect
valley of Si is shown in Fig. 4.3a. Note that there is a change in the trend of drain current
with thickness, observed at the cross over point which appears at approximately VGS = 0.44
V (marked explicitly in the figure). This can be explained using the electrostatic effects on
tunneling. The electrostatics of the system improves significantly with thickness scaling, due
to the better gate coupling. This results in a substantial contribution to the total current from
the sub-surface BTBT and also results in improved average subthreshold slope (SSAVG ) with
reduced IOFF . The SSAVG is computed as the inverse of slope in the transfer characteristics
4.4 Results and Discussion
(a)
75
(b)
Figure 4.4: Energy band diagram along a horizontal cut line at distance of 1Å from the surface (at VDS
= 0.7 V) for: (a) different values of gate voltage at 4 nm thin film and (b) at OFF state (VGS = 0V) for
different ultra thin thickness. In (a) as gate voltage increases tunneling shifts from Ge-Si junction to
Ge. In (b) as thickness is scaled, the barrier gets wider due to the confinement effect on Si and Ge. The
voltage range over which tunneling takes place from Ge to Si increases with thickness scaling, because
of the change in band alignment.
between VT (VGS at IDS of 1e-7 A/µm) and VOFF . The ON current degrades remarkably with
thickness scaling, as shown in Fig. 4.3b.
Band alignment at the Si/Ge hetero junction will change as a result of the confinement effect
on Si and Ge. Variation of the tunneling path with the applied gate voltage is shown in Fig. 4.4a,
for 4 nm ultra thin film. It can be clearly seen from the figure that as gate voltage increases the
tunneling path shifts from Ge-Si junction towards Ge. Similar trend can be expected for other
thickness as well.
The variation of the tunnel path for different thickness at OFF state is shown in Fig. 4.4b.
The confinement effects results in increase in the band gap of Si and Ge as thickness is scaled.
As a result the bands move up and the tunneling barrier gets wider, which consequently reduced the BTBT current from Ge to Si. Further, as the thickness is scaled the voltage range of
tunneling from Ge-Si junction increases, which is due to the change in the band alignment.
The OFF state current in TFET’s is mainly composed of BTBT current and diode leakage current, considering the generation and recombination of carriers in the depletion region
(Shockley-Read-Hall or SRH currents). There are three main contributors to SRH recombination: (a) doping dependence, (b) field enhancement and (c) temperature dependence, which
4.4 Results and Discussion
76
Figure 4.5: Transfer characteristics of DGTFET with extended Ge source, where the total current is
broken down into its constituent components of BTBT and SRH current at 4 nm thickness. At OFF state
(VGS = 0V), the total current consists of both SRH and BTBT current.
changes the minority carrier life time and hence the generation and recombination of the carriers. Smaller band gap results in increased carrier generation inside the depletion region, because
of SRH electric field enhancement. Thus, SRH current decreases as thickness is reduced because of increased band gap. At OFF state, there is tunneling path from Ge to Si, however, the
tunneling path associated with this process is large, as shown in Fig. 4.4b. Consequently, the
total current at low gate voltage consist of both SRH and BTBT current.
To further investigate the BTBT and SRH component in total current, we have broken down
the total current into BTBT and SRH leakage currents, as shown in Fig. 4.5 for 4 nm thickness.
At OFF state (VGS = 0V), IBTBT and ISRH constitute the total current. The tunneling current
in the device at negative VGS is not affected, as the bands are pulled upward without affecting
the electrostatics at the junction (see Fig. 4.4a). Thus the total current for negative VGS at 4 nm
thickness is predominantly SRH currents while at higher thickness the OFF current comprise of
both SRH and BTBT. The OFF state current decreases as thickness is scaled on account of the
increased band gap with reduced thickness.
4.4.2
Ge to Ge:Band alignment and BTBT
As the gate voltage increases tunneling path shifts from Ge-Si junction to Ge source, due to
the 2 nm Ge source overlap. To analyze the tunneling in Ge, we have shown BTBT carrier
4.4 Results and Discussion
77
Figure 4.6: BTBT generation rate contour for different VGS at VDS = 0.7 V for different thickness. At
VGS = 0.2 V, the BTBT generation rate is higher for 6 nm thickness, which is due to the simultaneous
effect of the improved electrostatics of the system and better BTBT parameter value. At low VGS , there
is tunneling from Ge to Si. For VGS = 0.6 V, the BTBT generation rate of 8 nm thin film is higher as
compared to the other thickness. This is due to the improved gate coupling with VGS .
generation rate contour in the device in Fig. 4.6, for different thickness at different VGS . Two
bias points are considered: one at low gate voltage where mostly the tunneling is taking place
from Ge to Si, and the other at high gate voltage where the tunneling is in Ge only. Now, at low
gate voltage (VGS = 0.2 V), the BTBT generation rate is maximum for 6 nm thickness as shown
in Fig. 4.6. This is due to the combined effect of improved gate coupling, which changes the
electrostatics of the system and better BTBT parameter values than at 4 nm thickness. But, the
total current is higher for 4 nm thickness at VGS = 0.2 V, due to the large effective tunneling area.
As VGS increases, the tunneling gets confined in the Ge only, i.e. now the tunneling is from
valence band of Ge to conduction band of Ge. This tunneling can be both direct and indirect.
However, it has already been shown in various theoretical and experimental work that direct
tunneling dominates in Ge [12, 14, 32]. The improved gate control and increased effective
tunneling area at higher VGS in 8 nm film results in improved carrier generation, as shown in
Fig. 4.6 (for VGS = 0.6 V). This results in higher current for 8 nm thickness.
4.5 Summary
4.5
78
Summary
To summarize, we explore the thickness dependent BTBT current for 2 nm extended Ge source
TFET. We use DFT calculations to calculate the thickness dependent bandstructure parameters
such as the bandgap and effective masses etc. for Ge and Si slabs. These are then used to obtain
accurate Kane’s tunneling parameters to estimate the tunneling current. The band alignment at
Si/Ge junction changes significantly with thickness scaling. It is found that at reduced thickness,
2 nm overlap length is insufficient to confine the tunneling in Ge. In ultra thin devices, the
electrostatic effects also play an important role in BTBT due to enhanced gate coupling, and
this enhances the subsurface BTBT current significantly. The increased contribution of the
subsurface BTBT current to the total drain current in ultra-thin Ge TFET results in significantly
improved subthreshold region characteristics. The calculated ION at over drive voltage of 0.8
V varies from 383 µA/µm to 178 µA/µm, as we move down from 10 nm to 4 nm thickness
respectively, for VDS = 0.7 V. While, the SSAVG improves from 43.5 mV/decade (10 nm) to
33.4 mV/decade (4 nm).
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Chapter 5
Vertical and Lateral Tunneling in Ge
Source TFET: Thickness Scaling
5.1
Introduction
In this chapter, we present a comparative study of vertical and lateral tunneling in Ge source
TFETs, as the source is scaled down from bulk to ultra-thin slabs of 4 nm thickness. It is well
known that quantum confinement changes the band-structure and material parameters significantly. This has been reported in the literature for Ge and other III-V materials [1–3]. In
bulk Ge, the difference between direct and indirect conduction band valleys (valley offset) is
0.14 eV [4], which reduces to 0.1 eV in ultra-thin Ge slabs [1]. The bandgap and effective
masses for each valley are also known to change significantly. Additionally, at this finite thickness there will be a contribution of band-to-band tunneling (BTBT) current from both of the
valleys on account of very low valley offset. Thus, we have theoretically calculated BTBT parameters for ultra-thin thickness using band structure results from atomistic simulations, while
for bulk we have considered bulk parameters. In the investigated double gate TFET (DGTFET)
structures, we have used an overlapped gate over Ge source to include vertical line tunneling
along with lateral tunneling in the device. First, the impact of the gate overlap length scaling has
been investigated at constant Ge source thickness of 8 nm. We have then analyzed the impact
of scaling the Ge source thickness keeping the gate overlap length fixed. We find that Ge source
thickness scaling till 8 nm has negligible effect on the ON current, but as the thickness is further
84
5.2 Device Structure and Simulation Models
85
scaled down to ultra-thin Ge films, line tunneling disappears in the device resulting in reduction
of ION from 380 µA/µm at 25 nm (bulk) to 83.5 µA/µm at 4 nm. We also report TFETs with
ultra-thin Ge source, but small gate-source overlap to confine the tunneling in Ge only. In this
configuration, lateral tunneling drives the drain current, leading to better sub-threshold slope
and ON current. Further, we highlight the roles of enhanced subsurface BTBT current and gate
screening in these ultra-thin lateral TFETs.
In the conventional TFETs, gate is usually aligned with the p+/n- junction. Tunneling
through this junction from source to the channel is referred to as lateral point-to-point (P-P)
tunneling. When there is gate-source overlap, the overlapped part of the source gets depleted.
And, if a strong band bending is provided, then tunneling will take place from the bulk towards
the gate/oxide interface. This vertical tunneling is referred as line tunneling. Line tunneling in
TFETs has recently been explored to improve the ON current [5]. In this chapter we investigate
the impact scaling the Ge source thickness from bulk to ultra-thin films for gate overlapped
structure, accounting for both direct and indirect type of tunneling mechanisms as well as both
line and P-P tunneling.
The rest of the chapter is organized as follows: In section-5.2, we discuss the gate source
overlapped structure along with the simulation models. The scaled Kane BTBT parameters for
Ge source are discussed in section 5.3. This is followed by the discussion of the impact of gate
overlap length (LOVL ) and thickness of Ge (TGe ) scaling in TFETs with gate-source overlap in
section 5.4. The P-P lateral TFETs are discussed in section 5.5. Finally, we summarize our
findings in section 5.6.
5.2
Device Structure and Simulation Models
The TFET device structure under study is shown in Fig. 5.1. It has a gate-source overlap region (of length LOVL ), where vertical tunneling takes place. As the Ge source thickness (TGe )
reduces, the band structure changes due to quantum confinement effects, leading to increase in
the direct and indirect bandgaps and the effective masses, and decrease in the conduction band
valley-offsets. For TGe > 8 nm, the results are close to the bulk values, and hence we have con-
5.3 BTBT Model Parameters Calculations
86
Figure 5.1: Schematic of a double gate TFET with gate-source overlap, n-type drain doping of
1 × 1018 cm−3 , p-type source doping of 1 × 1020 cm−3 , and low n-type body doping of 1 × 1016 cm−3 .
The gate dielectric is HfO2 with 2 nm thickness. The nominal gate-source overlap length (LOVL ) and
the channel length are 8 nm and 40 nm respectively. The metal gate work function is set to 4.2 eV.
sidered the bulk BTBT model parameters for thickness above 8 nm. For ultra-thin Ge source
with TGe ≤ 8 nm, we have calculated the thickness dependent BTBT model parameters using
the thickness dependent bandgap and effective mass data using density functional theory (DFT)
calculations from our previous work [1].
The BTBT current simulations have been performed using the Synopsys Sentaurus TCAD
suite, where we have included all the relevant physical effects. The non-local BTBT tunneling
model [6] is used for the BTBT current, considering both direct and indirect tunneling in the
device. The default values of BTBT model parameters for Ge in Sentaurus are available for
indirect tunneling only, using bulk Ge properties. To overcome this problem at ultra thin Ge
thickness, we have theoretically calculated the BTBT parameters for both direct and indirect
tunneling for different Ge thickness. To include non-local electric field effects, hydrodynamic
transport is considered and to account for the very high doping in source, bandgap narrowing and Fermi Dirac statistics are used. The geometrical quantum confinement effects in the
BTBT are considered by explicitly calculating the BTBT model parameter after considering the
thickness dependent geometrical confinement effects from atomistic simulations. To include
the charge centroid shift due to the quantum effects, the MLDA model has been used.
5.3
BTBT Model Parameters Calculations
According to the Kane dispersion relationship, the BTBT current can be defined as the integral
of the generation rate over the entire device region [6] as already discussed in detail in section
5.4 Impact of LOVL and TGe Scaling in TFETs with gate-source overlap
87
Table 5.1: Theoretically calculated BTBT model parameters for direct and indirect tunneling for Ge (100)
surface orientation with varying thickness. A and B are in units of cm−3 s−1 and MVcm−1 , respectively.
Thickness
Bulk
8 nm
6 nm
4 nm
Direct BTBT
Adir
Bdir
20
1.47 × 10
6.04
1.46 × 1020 6.14
1.43 × 1020 6.6
1.35 × 1020 7.8
Indirect BTBT
Aind
Bind
15
1.67 × 10
6.55
1.509 × 1015 7.00
1.368 × 1015 7.62
1.163 × 1015 9.07
3.4. A and B are the Kane parameters, which for direct and indirect tunneling and are discussed
in section 4.3.2
In Table 5.1, we have listed all the calculated BTBT model parameters for bulk and ultra-thin
Ge. First, as a consistency check we note that for bulk Ge (100) the deviation between our theoretically calculated value for Bdir for direct tunneling (6.04 MV/cm) and the prediction from [8]
(5.3 MV/cm) and the experimental calibration (5.7 MV/cm) [9] is small. It can be seen that in
ultra-thin Ge slabs, the value of the parameter A decreases, while that of parameter B increases
with thickness scaling. For BTBT parameters calculated using DFT bandstructure data, the
value of Bdir at TGe = 8 nm increases from 5.7 MV/cm to 7.44 MV/cm at at TGe = 4 nm, which
should degrade the current, because of the negative exponential dependence on B. The default
values of Kane’s parameters used for Ge in Sentaurus TCAD are A = 9.1 × 1016 cm−3 s−1 and
B = 4.9 MV/cm [10], which grossly overestimate the current at reduced thickness.
5.4
Impact of LOVL and TGe Scaling in TFETs with gate-source
overlap
First, we discuss the effect of the gate-source overlap length (LOVL ) on line tunneling at 8 nm
source thickness. This is followed by a study of the thickness dependence of line tunneling for
a constant LOVL of 8 nm. Then we investigate tunneling mechanisms in ultra-thin Ge source
TFETs including the impact of change in bandstructure.
5.4 Impact of LOVL and TGe Scaling in TFETs with gate-source overlap
88
Figure 5.2: Transfer characteristics of DGTFET with different gate-source overlap lengths (LOVL ).
The vertical line tunneling increases with LOVL , because of increased band bending provided by the
overlapped part. Inset shows the ION and SSAVG variation with LOVL . ION increases linearly with
LOVL . SSAVG remains almost constant with LOVL , but sharply increases at very low LOVL , because
of increase in OFF current. SSAVG is calculated as the inverse of slope between VT (VGS at which
IDS = 1 × 10−7 A/µm) and VOFF .
5.4.1
Effect of Overlap Length Scaling on Line Tunneling
In this section, we have studied the effect of different gate overlap lengths (LOVL ) on line tunneling in TFETs as shown in Fig. 5.2. As LOVL increases, the amount of band bending increases,
and as a result, the vertical tunneling also increases. The onset of vertical tunneling is shifted
towards the left on the VGS axis with increase in LOVL . The ON current variation is almost
linear with LOVL as shown in the inset of Fig. 5.2. The average subthreshold slope, SSAVG
remains unaffected with decreasing LOVL except at 4 nm. This is because line tunneling sets
in the device after the sub-threshold region and before this it’s lateral P-P tunneling which is
playing in sub-threshold region. The adverse effect of increasing the LOVL is on capacitances,
which increases with increasing LOVL . However, the increase in ON current is large as compared to the gate capacitances, thus, the switching speed and RF performance will improve. In
the following sub-sections, we have considered a fixed LOVL of 8 nm in the devices.
5.4 Impact of LOVL and TGe Scaling in TFETs with gate-source overlap
(a)
89
(b)
(c)
Figure 5.3: (a) Transfer characteristics of DGTFET with gate-source overlap, LOVL = 8 nm. Lateral
P-P tunneling takes place initially at low VGS , and line tunneling sets in at higher VGS . Both, lateral
and vertical tunneling will contribute to the total current. The inset shows ION and SSAVG for thickness
scaling from bulk to ultra-thin Ge source. The ON current and SSAVG essentially remain constant as
thickness is scaled down from bulk to 8 nm. For Ge thickness less than 8 nm, the ON current and SSAVG
degrade, because of the disappearance of line tunneling (see Fig. 5.3a for more details).(b) Energy band
diagrams are shown for different values of VGS at VDS = 0.7 V for 8 nm thickness along the lateral direction considered at 1 Å from the interface. Bands are pulled down with increase in VGS , which improves
lateral P-P tunneling.(c) Energy band diagram along the vertical direction. As VGS increases, bands are
pulled down and at around 0.5 V, vertical tunneling path is formed in the device, and this initiates line
tunneling.
5.4.2
Bulk Ge source Line Tunnel FET (8 nm < TGe ≤ 25 nm)
The total current in the structure considered in Fig. 5.1 is shown in Fig. 5.3a with the inset
showing the variation of ION and SSAVG for different TGe values. The spatial view of energy
band diagram along the vertical and horizontal directions for Ge source of thickness 8 nm (bulk)
are shown in Fig. 5.3b and Fig. 5.3c, respectively. As mentioned earlier, the total current is a
5.4 Impact of LOVL and TGe Scaling in TFETs with gate-source overlap
90
Figure 5.4: Transfer characteristics for ultra-thin body Ge source having thickness less then 8 nm. The
current degrades in the line tunneling configuration as thickness is scaled to 4 nm. Inset shows the energy
band diagram along the vertical direction for ultra-thin Ge source at VGS = 1 V and VDS = 0.7 V. Gate
voltage is not sufficient to provide enough band bending needed to initiate line tunneling in the device,
and hence the total current is reduced.
combination of vertical line tunneling and lateral P-P tunneling current, which in turn consist
of both, direct and indirect tunneling. For bulk Ge source, at OFF state (VGS ≤ 0 V), there
is no significant tunneling observed in the device, as the tunneling path associated with the
lateral tunneling is large and also, there is no vertical tunneling path formed in the device, as
depicted in Fig. 5.3b and Fig. 5.3c. Hence, the Shockley-Read-Hall (SRH) and BTBT current
will constitute the OFF state current, and is shown in Fig. 5.3a.
As VGS increases beyond 0 V, band overlapping starts which results in the formation of
lateral tunneling path in the device. This tunneling path reduces with the increase in VGS , see
Fig. 5.3b. Thus, initially it is lateral P-P tunneling, which contributes to the current in the
device. However, as VGS reaches 0.5 V, there is sufficient band bending to initiate tunneling
in the vertical direction, shown in Fig. 5.3c. This addition of line tunneling to the lateral P-P
tunneling boosts the current after VGS = 0.5 V and hence the total current increases. As TGe is
scaled down from 25 nm to 8 nm, the variation in ON current is seen to be very less, except for
a slight decrease in the ON current due to the change in electrostatics in the structure, as shown
in inset of Fig. 5.3a. The average sub-threshold slope SSAVG essentially remains constant with
thickness scaling upto 8 nm.
5.4 Impact of LOVL and TGe Scaling in TFETs with gate-source overlap
91
Figure 5.5: Transfer characteristics of DGTFET with lateral P-P Tunneling. There is a cross over point
in the transfer characteristics, which is due to the effect of gate coupling and gate screening. Inset shows
the structure of lateral P-P TFETs. Source is extended inside the gate by 2 nm to limit the tunneling in
Ge only. The hetero dielectric gate is composed of SiO2 (LSiO2 = 35 nm) and HfO2 (LHfO2 = 5 nm).
ION and SSAVG variation with thickness is shown in the inset. ION degrades at reduced thickness of Ge
source because of gate screening.
5.4.3
Ultra-Thin Ge Source Line Tunnel FET (TGe ≤ 8 nm)
As the thickness is scaled down below 8 nm, the ON current is degraded by an order of magnitude and is shown in Fig. 5.4. This current degradation occurs due to the combined effect of
disappearance of line tunneling and change in the electrostatic in the structure. For TGe ≤ 8 nm,
the material confinement as well as external quantum effects in the device result in a very large
increase in the band-gap for both direct and indirect valleys. The applied voltage at the gate is
not sufficient to cause the voltage drop that is needed to initiate line tunneling in the device, and
thus the current is degraded.
At 4 nm thickness with LOVL = 8 nm, the gate has a better control over the source. But, due
to the overlap of the gate with the heavily doped p-type source, depletion takes place in the overlapped source region, which increases the barrier width and thus causes the lateral P-P current
to degrade, as shown in Fig. 5.4. Even a slight variation in VGS will result in heavy depletion
in the source at 4 nm thickness, because of strong gate coupling and this leads to a degradation
in the current. One way to circumvent this issue is to use low-κ gate dielectric to reduce the
gate coupling, but it will also result in lesser ION . For 6 nm thickness, the positive effect of
increased gate coupling and the adverse effect of increase in band-gap compensate each other.
5.5 Ultra-Thin Ge Source Lateral (P-P) TFET
92
This results in almost the same current for both thickness (6 nm and 8 nm) till 0.4 V. However,
beyond 0.4 V, the current degrades because of gate screening.
5.5
Ultra-Thin Ge Source Lateral (P-P) TFET
To overcome the problem of absence of line tunneling in ultra-thin Ge TFETs, we have studied
a different lateral P-P tunneling structure, as shown in the inset of Fig. 5.5. In this device, we
have used a hetero dielectric gate. Ge source is extended inside the gate by 2 nm to limit the
tunneling to the ultra-thin Ge source only as Ge BTBT parameters are better than Si. We have
considered the same device dimensions as the TFET device in the previous section. We have
find that there is a cross-over behavior in the transfer characteristics with respect to thickness at
VGS = 0.6 V, which is marked in Fig. 5.5. It can be explained as follows: For 0 V < VGS ≤
0.6 V, reduced thickness results in stronger coupling of the gate to the body and sub-surface
tunneling is enhanced. Accordingly, the OFF state current increases with reduced thickness:
IOFF, 4nm > IOFF, 6nm > IOFF, 8nm as shown in Fig. 5.5. This sub-surface BTBT increases the
sub-threshold current and there is substantial contribution to the total current for ultra-thin Ge
source (TGe ≤ 8 nm). As the gate voltage is increased beyond 0.6 V, due to the formation of a
strong tunneling region, the surface charge screens the gate voltage. This strong gate screening
degrades the current for reduced thickness, and a cross-over happens. In the inset of Fig. 5.5,
we have shown the variation of ON current and SS with thickness.
The ON current variation with bulk thickness is only nominal, which is due to the slight
change in the electrostatics of the structure (e.g. ION is found to be 241 µA/µm and 249 µA/µm
in 10 nm and 20 nm devices, respectively). Comparatively, the ON current in TFETs with
gate-source overlap (significant line tunneling) is around 52.2% higher than the ON current in
lateral P-P TFETs at a thickness of 20 nm. However, as we approach ultra thin Ge thickness
(TGe ≤ 8 nm), the reduction of line tunneling current in the gate-source overlap TFET structure
degrades the total current, and ION is in fact only a fraction of the corresponding lateral P-P
TFET current at the same thickness (e.g. the fraction being 54.5% and 56.2% at 4 nm and 6 nm
thickness, respectively).
5.6 Summary
5.6
93
Summary
We have shown that line tunneling disappears in the gate-source overlap TFETs as the Ge source
thickness is scaled down to ultra-thin films (TGe ≤ 8 nm) and the net current is degraded.
Thus, gate overlapped structure with ultra-thin Ge source is not suitable for future low power
applications. We have shown that TFETs with strong lateral P-P tunneling results in better
performance at reduced thickness as compared to the gate-source overlap TFETs that offer
significant line tunneling only in the bulk case. The calculated ION varies from 312 µA/µm to
149.7 µA/µm for lateral P-P TFETs, while for line tunnel FETs with significant gate-source
overlap, the ON current varies from 360 µA/µm to 83.5 µA/µm, as the source is scaled from
8 nm to 4 nm, respectively.
Bibliography
[1] P. Rastogi, T. Dutta, S. Kumar, A. Agarwal, and Y. S. Chauhan, “Quantum Confinement
Effects in Extremely Thin Body Germanium n-MOSFETs,” IEEE Transactions on Electron Devices, vol. 62, no. 11, pp. 3575–3580, 2015.
[2] T. Dutta, S. Kumar, P. Rastogi, A. Agarwal, and Y. S. Chauhan, “Impact of Channel Thickness Variation on Bandstructure and Source-to-Drain Tunneling in Ultra-Thin Body III-V
MOSFETs,” IEEE Journal Electron Device Society, vol. 4, no. 2, pp. 66–71, 2016.
[3] T. Dutta, P. Kumar, P. Rastogi, A. Agarwal, and Y. S. Chauhan, “Atomistic study of band
structure and transport in extremely thin channel InP MOSFETs,” Physics Status Solidi
(A), vol. 213, no. 4, p. 898904, 2016.
[4] “NSM Archive-Physical Properties of Semiconductor.” [Online]. Available:
http:
//www.ioffe.ru/SVA/NSM/Semicond/Ge/bandstr.html
[5] A. M. Walke, A. S. Verhulst, A. Vandooren, D. Verreck, E. Simoen, V. R. Rao, G. Groeseneken, N. Collaert, and A. V. Y. Thean, “Part I: Impact of Field-Induced Quantum Confinement on the Subthreshold Swing Behavior of Line TFETs,” IEEE Transactions on
Electron Devices, vol. 60, no. 12, pp. 4057–4064, Dec 2013.
[6] E. O. Kane, “Theory of Tunneling,” Journal of Applied Physics, vol. 32, no. 1, pp. 83–91,
1961.
94
BIBLIOGRAPHY
95
[7] K. H. Kao, A. S. Verhulst, W. G. Vandenberghe, B. Sore, G. Groeseneken, and K. D.
Meyer, “Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs,” IEEE
Transaction on Electron Devices, vol. 59, no. 2, pp. 292–301, 2012.
[8] D. Kim, T. Krishnamohan, L. Smith, H. S. P. Wong, and K. C. Saraswat, “Double-Gate
Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and
60mV/dec subthreshold slope,” in Device Research Conference, 2007, pp. 57–58.
[9] M. S. Tyagi, “Determination of Effective Mass and the Pair Production Energy for Electrons in Germanium from Zener Diode Characteristics,” Japanese Journal of Applied
Physics, vol. 12, no. 1, pp. 106–108, 1973.
[10] “Sentaurus Device, Synopsys, Version D-2010.03,” 2016. [Online]. Available:
https://www.synopsys.com/silicon/tcad/device-simulation/sentaurus-device.html
Chapter 6
Modeling of Current and Capacitances
including Mobile Channel Charge and
Ambipolar Behaviour
6.1
Introduction
In this chapter, we have presented a surface potential based analytical model of charge, current
and capacitances in DGTFET accounting for the mobile charges in the channel. To facilitate
the use of TFETs in circuit design, an accurate analytical/compact model for TFET is needed,
which is also computationally efficient. While there have been significant efforts to develop
an analytical/compact model for TFETs, there is still considerable scope for improvement. A
good TFET model should capture the device electrostatics accurately, and predict the ambipolar
drain current along with the terminal charges and capacitances accurately in both the depletion
as well as inversion regime, while being computationally efficient for circuit simulations.
Earlier models based on 1-D Poisson equation do not accurately capture the electric field
distribution in short channel devices [1]. Pseudo 2-D method based TFET models capture the
electrostatics correctly, but some of them are valid only for depletion conditions [2–7], while
some do not model the ambipolar current [2–4, 8] and some do not model the terminal charges
and capacitances [4–9]. Additionally, there are some empirical drain current and capacitance
model for TFETs as well [10–12], however these do not account for the mobile charges in the
channel.
96
6.2 Device Structure and Simulation Models
V
V
97
G
V
2
S
o
3
1
2 nm
o
Drain
Source
(10
x
y
cm
-3
R3
R2
R1
R1
p+(Si)
20
D
Intrinsic Si n- (10
)
16
t
n+(Si)
-3
16
-3
cm )
10
cm
( 10
20
cm
Si
-3
)
L = 50 nm
2
x
o
x
R1
x
1
R2
2
x
R3
3
t
Si
= 10 nm
Figure 6.1: Schematic of the DGTFET used in the study, where R1 is the source depletion region, R2 is
the channel region, and R3 is the drain depletion region. VG , VS , and VD are the applied gate, source, and
drain voltage, respectively and Φi represents the potential at the various marked positions. The doping
in various regions and the channel length are mentioned in the figure. The workfunction of the metal at
the gate is Φm = 4.2 eV.
In this chapter, we present a surface potential based model for DG-TEFT, which uses the
pseudo 2-D method to accurately model the surface potential in both the depletion as well as
the inversion regime, which in turn is used to model the drain current along with the terminal
charges and capacitances. Influence of mobile charge carrier on the device electrostatics is
important to account for the precise modeling of the device characteristics. The mobile charges
in the channel bring about i) narrowing in the tunneling barrier width [9] and ii) saturation in
the monotonically increasing mid surface potential. While there are some earlier works which
include one of these effect [8, 9, 13], we show that including both these effects are essential for
modeling the drain current and the terminal charges and capacitances accurately. The chapter
is organized as follows: In Sec. 6.2, we discuss the device structure and simulation details,
followed by a detailed description of the model in Sec. 6.3, which in turn is followed by Sec. 6.4
on model validation and a summary of the work in Sec. 6.5.
6.2 Device Structure and Simulation Models
6.2
98
Device Structure and Simulation Models
The TFET device structure under study is shown in Fig. 6.1. For simplicity, all the junctions
in the device i.e. source/channel and channel/drain are assumed to be abrupt. The device is
simulated using Sentaurus TCAD to obtain the simulation data for model verification [14]. In
order to include the field and doping dependence mobility degradation, high field saturation and
Masetti model is used along with the Lombardi Model. Shockley-Read-Hall (SRH), Boltzmann
statistics, and Quasi static approximation is also activated. To calculate BTBT current, non local
tunnelling path model is included [15].
6.3
Model Description
To calculate the band to band tunneling current in the device, we need to evaluate the electric
field distribution throughout the device. To this end, we first calculate the surface potential in
the device. The surface potential is determined primarily by the electrostatics of the system
which is treated in 6.3.1, along with the impact of mobile charge carriers which is discussed in
6.3.2.
The device is divided into three regions: R1, R2, and R3 as shown in Fig. 6.1. Pseudo 2-D
method is adopted to convert the 2-D Poisson equation into an effective 1-D equation, which is
further used to obtain the surface potential profile along the device.
6.3.1
Surface potential
The 2-D Poisson equation without considering the effect of the mobile charges in the channel
can be written as:
∂ 2 Φ(x, y) ∂ 2 Φ(x, y)
−qNR
+
=
,
2
2
∂x
∂y
Si
(6.1)
where Φ(x, y) is the electrostatic potential, q is the charge, Si is the electrical permittivity of
silicon, and NR represents the doping in different regions of the device. The doping NR = NS ,
Nch , and ND for region R1 , R2 , and R3 , respectively. To proceed further and to convert (6.1) into
6.3 Model Description
99
an effective 1-D equation, we consider a parabolic approximation for the electrostatic potential
along the thickness of the device [2],
Φ(x, y) = a0 (x) + a1 (x)y + a2 (x)y 2 ,
(6.2)
where a0 (x), a1 (x), and a2 (x) are the unknown coefficients which depend on x. The value of
these unknown coefficients can be obtained using the boundary conditions for the electrostatic
potential and electric field in (6.2).
The effective gate voltage (Φg ) is given by
Φg = VG − Φm + χ +
Eg
,
2q
(6.3)
where VG is the applied gate voltage, Φm is the metal gate workfunction, χ is the electron
affinity, and Eg is the energy bandgap. The symmetric double gate structure of the device
implies that the surface potential at the front as well as the back gate are equal, Φ(x, 0) =
Φ(x, tSi ) ≡ Φs (x). Furthermore, electric field at the front surface (E(x, 0)) and back surface
(E(x, tSi )) can be expressed as follows [2]:
Cox [Φg − Φs (x)]
,
Si
Cox [Φs (x) − Φg ]
E(x, tSi ) =
.
Si
E(x, 0) =
(6.4)
In (6.4), Cox is the gate oxide capacitance per unit area and is equal to ox /tox for region R2 and
ox /t for region R1 and R3 with t = πtox /2. Note that t is the effective oxide thickness in the
R3 region, which accounts for the effect of fringing fields of the gate [16].
Now applying the boundary conditions from (6.4) into (6.2), we obtain the unknown coefficients of (6.2) as
a0 (x) = Φs (x),
a2 (x) = −
a1 (x)
= Cox (Φg − Φs (x))/Si tSi .
tsi
(6.5)
Now using a0 (x), a1 (x), and a2 (x) from (6.5) into (6.2) and substituting Φ(x, y) in (6.1), we
6.3 Model Description
100
obtain an effective 1-D Poisson equation,
∂ 2 Φs,i (x)
(0)
− ki2 Φs,i (x) = −ki2 Φd,i ,
∂y 2
(6.6)
where i = 1, 2, and 3 correspond to regions R1, R2, and R3, respectively, and
r
ki =
(0)
qNR tSi
2Cox
(0)
, Φd,i = Φg +
.
Si tsi
2Cox
(6.7)
(0)
Here Φd,i in region R2 i.e. Φd,2 is called the center or the mid potential under depletion condition
and it is a linear function of applied gate voltage and ki is the inverse decay length in the
depletion condition. Note that till now we have not included the effect of mobile charge carriers
(0)
in the channel region and this will lead to the modification of Φd,2 and k2 as discussed later in
Sec. 6.3.2.
The general solution of (6.6) can be expressed as:
Φs,i (x) = bi eki (x−xi−1 ) + ci e−ki (x−xi−1 ) + Φd,i ,
(6.8)
where xi−1 is position x0 , x1 , x2 , and x3 corresponding to i = 0, 1, 2, and 3 as defined in
Fig. 6.1. Defining Φs,i (xi )=Φi , the unknown coefficients bi and ci of (6.8) can be evaluated
using the following boundary conditions,
Φ0 = −Φt ln
NS
ni
= b1 + c1 + Φd,1 ,
Φ1 = b1 ek1 L1 + c1 e−k1 L1 + Φd,1 = b2 + c2 + Φd,2 ,
(6.9)
Φ2 = b2 ek2 L2 + c2 e−k2 L2 + Φd,2 = b3 + c3 + Φd,3 ,
ND
Φ3 = Vd + Φt ln
= b3 ek3 L3 + c3 e−k3 L3 + Φd,3 ,
ni
By solving the linear equations specified in Eq. 6.9. The coefficient b1 , c1 , b2 , c2 , b3 and c3
6.3 Model Description
101
are obtained, and are given by:
b1 =
1
φ1 − φd1 − e−k1 L1 (φ0 − φd1 ) ,
2sinh(k1 L1 )
(6.10)
c1 =
k1 L1
1
e
(φ0 − φd1 ) − φ1 + φd1 ,
2sinh(k1 L1 )
(6.11)
b2 =
k2 L2
1
(φ1 − φd2 ) − φ2 + φd2 ,
e
2sinh(k2 L2 )
(6.12)
c2 =
1
φ2 − φd2 − e−k2 L2 (φ1 − φd2 ) ,
2sinh(k2 L2 )
(6.13)
b3 =
1
φ3 − φd3 − e−k3 L3 (φ2 − φd3 ) ,
2sinh(k3 L3 )
(6.14)
c3 =
k3 L3
1
e
(φ2 − φd3 ) − φ3 + φd3 .
2sinh(k3 L3 )
(6.15)
Here, Φ0 and Φ3 are the surface potential at the source and drain end, respectively, and
Φ1 and Φ2 are the surface potential at the boundary between R1/R2 and R2/R3, respectively
as marked in Fig. 6.1, ni denotes the intrinsic charge carrier concentration, while the thermal
voltage is given by Φt = kT /q. In (6.9), L1 and L3 are the depletion region length in the source
and drain region, respectively, and L2 is the channel length. Within the depletion approximation,
L1 and L3 are given by
s
L1 =
2Si (Φ1 − Φ0 )
, L3 =
qNS
s
2Si (Φ3 − Φ2 )
.
qND
(6.16)
Note unlike some earlier works [2], (6.16) includes the physically relevant potential drop across
the junction in calculation of depletion length. Finally we can evaluate Φ1 and Φ2 at the boundary of R1/R2 and R2/R3 using continuity of the potential following [17] and expressed as:
q
Φ1 = Φd,2 + NS α2 − 1.7NS (Φd,2 − Φ0 )α2 + NS2 α22 ,
(6.17)
q
1.7ND (Φ3 − Φd,2 )α2 + ND2 α22 ,
(6.18)
and
Φ2 = ND α2 − Φd,2 −
6.3 Model Description
102
1.4
V
= 0.8 V
DS
Symbols: Simulation
Line: Model
V
= 0.6 V
DS
(V)
1.2
V
= 0.4 V
DS
d,2
1.0
V
= 0.2 V
DS
0.8
0.6
0.4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
(V)
GS
Figure 6.2: Plot of the channel mid potential as a function of VGS for different values of VDS . The linear
portion corresponds to the depletion in the channel, while the saturated region indicates inversion in the
channel. The model results are consistent with the TCAD simulation data.
where we have defined
α2 =
q
k22 Si
tanh2 (L2 k2 ) .
(6.19)
This gives us a closed form analytical expression for the surface potential and the full spatial
potential profile along the channel of the device can be obtained.
6.3.2
Effect of mobile charges on Φs and k2 : dual modulation effect
In this subsection, we include the effect of mobile charges on the potential profile in the device.
The mobile charges in the channel bring about i) narrowing in the tunneling barrier width and
ii) saturation in the monotonically increasing mid surface potential and this is typically referred
to as the dual modulation effect. The narrowing of the tunnel barrier influences the band to band
tunneling (BTBT) current [8, 13], while the saturation of the mid or center surface potential is
essential for accurate prediction of terminal charges and therefore capacitances [9].
The saturation in the mid surface channel potential is modeled via an empirical equation
and the narrowing of tunneling barrier is included as a correction in the inverse decay length
calculated using a variational approach.
6.3 Model Description
103
Incorporating the saturation effect in the mid-surface potential (Φd,2 ) [9] yields,
Φd,2
q
(0)
(0)
2
2
= 0.5 Φd,2 + Φinv − (Φd,2 − Φinv ) + δ
,
(6.20)
(0)
where Φd,2 is the mid surface potential without the mobile charge carrier effect and
(0)
(0)
Φinv = VD + Ψ + α(Φd,2 − VD − Ψ) + β(Φd,2 − VD − Ψ)2 .
(6.21)
In (6.21), α and β are the fitting parameters and Ψ is given by
Nch Ntran
Ψ = Φt ln
,
n2i
(6.22)
where Ntran is the doping corresponding to the transition from linear variation to saturation in
the mid surface potential and its extracted value is 1014 cm−3 . In Fig. 6.2, we have shown
the modeled Φd,2 in (6.20) against the TCAD simulation data. The linear portion in Fig. 6.2
corresponds to the depletion in the channel, while the saturated region shows the screening
effect of the mobile charge carriers in the channel.
To include the mobile charge effect in the inverse decay length, a variational approach for the
effective action is adopted to solve the 2-D non-linear Poisson equation. Following Ref. [13],
we have
Z Z
S(Φ) =
2
∂Φ
∂Φ 2
dxdy
+
− ρΦ ,
2 ∂x
∂y
(6.23)
where Φ(x, y) is the electrostatic potential and ρ(x, y) is the charge density. On minimizing S(Φ) and neglecting the y dependences, i.e., dS(Φ)/dk2 = 0 we obtain the modified (see
Eq. (6.7)) inverse decay length to be
s
k2 =
2Cox
αNinv
−
,
Si tSi Si tSi (Φ0 − Φd,2 )
(6.24)
where Ninv =2Cox (Φg -Φd,2 ) is the inversion charge in the channel and α is a fitting parameter
whose value lies between 1-2. In (6.24), the second term in r.h.s. accounts for the mobile
6.3 Model Description
104
charge carrier effect and is derived for a long channel length device to decouple the effect of
drain voltage [17]. Including the drain voltage dependence, the expression is further modified
as follows:
s
k2 =
2Cox
αNinv (1 + Vdseff )
−
,
Si tSi
Si tSi (Φ0 − Φd,2 )
(6.25)
where (1 + Vdseff ) is added to include the drain voltage effect. In (6.25), Vdseff implies Vds in
the linear region and Vdsat in the saturation region and in order to ensure smooth transition from
linear to saturation region it is modeled as [18]:
1
Vdseff = Vdsat −
2
q
2
(Vdsat − Vds − Υ) + (Vdsat − Vds − Υ) + 4ΓVdsat
(6.26)
where Υ and Γ are fitting parameters [18].
The calculation of Vdsat is similar to that in conventional MOSFET, and it is given by
Vdsat
q
2
=
Φg + γ 2 /4 − γ/2 − Φ ,
where Φ and γ are
kT
Φ=
log
q
N2 Nm
n2i
√
, γ=
2Si qN2
.
Cox
(6.27)
(6.28)
In (6.28), Nm = 1.8 × 1018 cm−3 .
6.3.3
Electric Field
The electric field in the source and drain depletion region can be approximated by lateral electric
field by ignoring the fringing field effect from the gate. However inside the channel both the
lateral and the vertical component of the field have to be considered. The vertical component of
electric field (Ex ) can be obtained by differentiating (6.2) as
Ex (x, y) = a1 (x) + 2a2 (x)y ,
(6.29)
6.3 Model Description
105
and the lateral component of electric field (Ey ) can be evaluated by differentiating (6.8) and is
given by
Ey (x, y) = ki bi eki (x−xi−1 ) − ki ci e−ki (x−xi−1 ) .
(6.30)
Finally, magnitude of the total electric field (Exy ) is computed as
q
Exy =
Ex2 (x, y) + Ey2 (x, y) .
(6.31)
The electric field predicted by the model in (6.31) deviates from the simulation data [2]. In order
to compensate the mismatch, a smoothing function in the electric field is used as follows [19]:
where
E = Exy (1 − f ) + ζExy f ,
(6.32)
22 
Φg − Φt ln 10
Nch
 .
f = 0.5 1 + tanh 
4Φt
(6.33)


In (6.33), ζ is a fitting parameter and f is a empirical function and its value varies between 0 to
1 [19].
6.3.4
BTBT Current
The BTBT current is defined as the integral of the generation rate over the entire device region. In presence of a uniform electric field, BTBT current from source to channel (Itun,s→c ) in
Ampere/µm can be expressed as follows [15]:
Z
tSi
Z
Wtmin,s
Itun,s→c = q
0
Wtmax,s
P
E
B
A
exp −
dydx ,
E0
E
(6.34)
where E0 = 1 V/cm, P = 2 and 2.5 for the direct and indirect tunneling, respectively, A and B are
the parameters for the Kane model with the unit of cm−3 s−1 and M V cm−1 , respectively and E
is the electric field at a given location across the tunneling junction. The values of A and B that
we have considered in our work are 4 × 1014 cm−3 s−1 and 1.9 × 107 M V cm−1 , respectively.
6.3 Model Description
106
1.5
0.5
(a)
Wtmin,s
Eg
0.0
Wtmax,s
-0.5
-1.0
-1.5
Source
1.0
Energy (eV)
Energy (eV)
1.0
Channel
(b)
0.5
Wtmax,d
0.0
Wtmin,d
-0.5
-1.0
-1.5
-2.0
-2.5
0.00
0.02
0.04
0.04
0.06
Distance ( m)
Drain
Channel
-2.0
0.06
Distance (
0.08
m)
Figure 6.3: Energy band profile in DGTFET showing minimum and maximum tunneling path at; a)
source /body junction and b) drain/ body junction.
In order to simplify the calculation, it is assumed that integration along the vertical direction
is constant and the tunneling is taking place laterally along the surface. This assumption gives
satisfactory result and is widely used in modeling of the current in TFETs [2, 9, 20].
Z
Wtmin,s
Itun,s→c = qAtSi
Wtmax,s
E
E0
P
B
exp −
dx ,
E
(6.35)
The range of energies over which tunneling takes place can be calculated through the evaluation of the minimum and the maximum tunneling path in the source and drain depletion region.
The length over which the channel potential rises by Eg /q w.r.t. the source potential is the minimum tunneling path at source end (Wtmin,s ) (see Fig. 6.3a), while, the maximum tunneling path
at source end (Wtmax,s ) is the width over which the channel potential falls by Eg /q w.r.t. the
mid potential (see Fig. 6.3b). Using the above definition of minimum and maximum tunneling
length, we can evaluate the tunneling lengths at source side to be
1
Eg
Wtmin,s =
ln(c2 ) − ln Φ1 +
− Φd,2
,
2k2
q
1
Eg
Wtmax,s =
ln(c2 ) + ln
.
2k2
q
(6.36)
Since the tunneling probability as specified by WKB (Wentzmer Krammer Brillouin) approximation decays exponentially with increase in tunneling path, it is expected that the generation
6.3 Model Description
107
rate in the Wtmin region is the maximum contribution to the BTBT tunneling current [21].
Following a similar approach, the BTBT tunneling current and tunneling distance at the
drain side can be expressed as,
Z
Wtmin,d
Itun,d→c = qAtSi
Wtmax,d
P
E
B
A
exp −
dx ,
E0
E
1
Eg
Wtmin,d = L2 −
ln(c2 ) − ln Φ2 −
− Φd,2
,
2k2
q
1
Eg
Wtmax,d = L2 −
ln(c2 ) − ln
.
2k2
q
(6.37)
(6.38)
Here, Wtmin,d is the minimum tunneling path along the lateral direction at the drain junction
and it is the distance over which surface potential in channel falls by Eg /q w.r.t. drain potential
(see Fig. 6.3). In (6.38), Wtmax,d is the maximum tunneling length at the drain junction and is
the distance over which surface potential in the channel increases by a amount of Eg /q w.r.t.
channel potential Φd,2 .
The leakage current is included in the total current via an empirical equation as a function
of effective gate voltage [19]:
Ileakage
Φg
= I0 exp −
,
7Φt
(6.39)
where I0 is the pre-factor used to capture the leakage current. Now, using tunneling current
from source to channel and drain to channel, the total current is simply given by
IDS = Itun,s→c + Itun,c→d + Ileakage .
6.3.5
(6.40)
Terminal Charge and Capacitance
To model the capacitance in the device, it is necessary to express the terminal charges variation
w.r.t to terminal voltages. Unlike the conventional MOSFET, in homo-junction TFETs only the
drain is connected to the inversion charge [22]. Therefore, entire channel charge is assumed to
be associated with drain terminal and the charge associated with source terminal mainly con-
6.3 Model Description
108
sists of depletion charge. The charge associated with the device terminals i.e. drain charge (QD )
and source charge (QS ) are modelled using 100/0 charge partitioning scheme. A crude approximation of the uniform charge distribution along the channel is used, which gives satisfactory
result for TFETs [20, 23]. Accounting for the inversion and depletion charge contribution, the
drain terminal charge is expressed as
QD = QDinv + QDdep ,
(6.41)
QDinv = −2Wg Cox (LG − Wtmin )(Φg − Φd,2 ) ,
(6.42)
where
is the inversion charge at the drain end and Wg is the device width and
QDdep = Si (VDS + Vbi − Φd,2 )tSi Wg k2 ,
(6.43)
denotes the depletion charge at the drain end. Since the charge at the source terminal (QS ) is
only due to depletion, therefore, depletion charge calculation approximation is used to evaluate
QS as follows [10]:
QS = −qWg NS L1 tSi .
(6.44)
Now using charge conservation, the total gate charge (QG ) is simply given by
QG = −(QD + QS ) .
(6.45)
The terminal capacitances can now be calculated by differentiating the terminal charges w.r.t.
applied voltages and can be expressed as,
CGG =
∂QG
−∂QD
, CDG =
.
∂VGS
∂VGS
(6.46)
6.4 Model Validation
6.4
109
Model Validation
The proposed model is validated against TCAD simulation data for wide range of applied gate
and source-drain voltages. As we will see below, the model is in reasonable agreement with the
simulation results in most of the operating regimes.
6.4.1
Surface Potential, Electric field, and Current
The surface potential (Φs ) based on the developed model, excluding the mobile charge carrier effect is shown in Fig. 6.4a along with the TCAD simulation data. The surface potential
matches well with the simulation data at lower VGS and at VDS = 1.0 V, corresponding to the
depletion conditions in the channel but it starts showing some deviation close to VGS =1.2 V
due to the presence of mobile charge in channel, where the saturation is not captured by the
model equation for the depletion condition. This deviation at higher VGS values highlights the
necessity for accounting for the effect of mobile charges on the center potential of the channel.
From Fig. 6.4b, it is evident that the surface potential result of the model matches well with the
simulation data for a wide range of the applied drain to source voltage (VDS ), when the device
is in the depletion regime at VGS = 0.2 V.
To overcome the model deficiency in the strong inversion condition, effect of mobile charges
is included in the surface potential and its verification with the simulation data for different
applied bias conditions is shown in Fig. 6.4c. In Fig. 6.4c, the surface potential is shown at
VGS = 1.0 V (corresponding to strong inversion regime in device), for different VDS values.
To obtain close match of model with the simulation data in the entire length of the device,
improvement in the inverse decay length is further required. It is noticeable that pinning of the
surface potential at the tunnel junction i.e. source/channel interface is precisely captured by
the model. The BTBT current is mainly driven by the maximum electric field [21], which is
at the tunnel junction. Deviation of the model in the vicinity of tunnel junction as shown in
Fig. 6.4c affect the BTBT at low VDS , which is a shortcoming of the model. Verification of the
total electric field along the channel with smoothing function is shown in Fig. 6.4d at VDS = 1.0
V, for gate voltages corresponding to depletion to strong inversion in the device.
110
VGS= 1.2
Symbol: Simulation
VDS= 1 V
(a)
V
Line: Model
GS= -1
Surface Potential (V)
Surface Potential (V)
6.4 Model Validation
2.0
Symbol: Simulation
1.5
1.0
0.5
(b)
-0.5
1.0
0.5
(c)
Symbols: Simulation
Line: Model
0.03
0.04
0.05
m
0.06
Lateral distance (
)
0.07
Electric Field (MV/cm)
Surface Potential (V)
VGS= 1.0 V
-0.5
0.02
DS= 0 V
0.03
0.04
0.05
0.06
Lateral distance (
VDS= 0, 0.2, 0.4, 0.6, 0.8, 1 and1.2 V
0.0
V
0.0
m)
2.0
1.5
GS= 0.2 V
V
= 1.2 V
DS
0.02
Lateral distance (
V
Line: Model
0.07
m)
4.5
Symbol: Simulation
Line: Model
3.6
V
= 1 V
DS
2.7
V
= 0,0.4, 0.8, 1.2 V
GS
1.8
(d)
0.9
0.0
0.02
0.03
0.04
0.05
0.06
Lateral distance (
0.07
m)
Figure 6.4: Validation of the surface potential and electric field behavior of model against the TCAD
simulation data along the lateral distance in x-axis. In panel(a), the effect of mobile charge carrier is
not included, while it is included in panels (b), (c) and (d). In panel (a), model without mobile charge
effect shows excellent matching with simulation data at lower VGS but start deviating with increase in
mobile charge carrier at higher gate voltage at VGS =1.2V. The model in depletion condition at VGS =0.2V
in panel (b) has excellent match with simulation data. The deviation in panel (a) at higher VGS highlights
the necessity to include the mobile charge carriers in the model, which corrects the deviation at high
VGS values as shown in (c). The panel (c) displays the surface potential profile along the channel for
VGS =1.0V and VDS =0.0V to 1.2V in steps of 0.2V. The saturation in the mid potential is effectively
captured by the model along with the pinning of the surface potential at the source end. (d) Validation
of the total electric field predicted by the model along the channel with TCAD simulation data in the
channel for VDS = 1.0V and different VGS values with smoothing function.
The surface potential obtained from the model, is further used to model the drain current and
its validation with the simulation data is shown in Fig. 6.5. Transfer characteristics as shown in
Fig. 6.5a highlight the closeness of the proposed drain current model to the TCAD simulation
data in the linear as well as in the saturation regime. The ambipolar current predicted by the
6.4 Model Validation
10
IDS(A/
10
10
10
10
10
10
10
Line: Model
V
= 1.0 V
DS
2.0x10
= 1.4 V
V
GS
-9
-11
V
=0.2 V
DS
-12
-13
m)
m)
10
Symbol: Simulation
1.5x10
IDS(A/
10
-9
-10
111
(a)
-15
Symbol: Simulation
(b)
Line: Model
= 1.3 V
V
GS
1.0x10
-14
-9
-9
= 1.2 V
V
GS
-16
5.0x10
-17
-10
V
= 1.1 V
GS
= 0.2, 0.4, 0.6, 0.8 and 1V
V
DS
-18
0.0
-0.5
0.0
0.5
1.0
0.0
1.5
0.2
0.4
VGS(V)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VDS(V)
Gate Charge (QG){fC}
Drain Charge (QD) {fC}
Figure 6.5: Drain current predicted by the model verified with TCAD simulation data; (a) transfer characteristics at varying gate voltage for different VDS . (b) Output current characteristics at different VGS
values, perfect saturation in the drain current is achieved due to the pinning of the surface potential at the
source side.
0.4
1.6
VDS= 0, 0.2, 0.4, 0.6, 0.8 and 1V
0.0
-0.4
1.2
(a)
0.8
-0.8
VDS= 0, 0.2, 0.4, 0.6, 0.8 and 1 V
Symbols: Simulation
Line: Model
(b)
0.4
Symbol: Simulation
Line: Model
-1.2
0.0
0.0
0.4
0.8
1.2
VGS(V)
1.6
0.0
0.4
0.8
1.2
1.6
VGS(V)
Figure 6.6: Terminal charge (QD , and QG ) predicted by the model against simulation data; (a) Drain
terminal charge for different VDS w.r.t. applied gate to source voltage and (b) Gate terminal charge for
different VDS w.r.t. applied gate to source voltage.
model qualitively follows the TCAD simulation data as shown in Fig. 6.5a. Note that effect of
the phonon scattering on the OFF current [24] is not included in the presented model as well
as in the TCAD simulation. Output characteristics in Fig. 6.5b show that the model reproduces
the simulation data reasonably well.
1.2
112
1.2
VDS= 0, 0.2, 0.4, 0.6, 0.8 and 1 V
0.8
VDS= 0, 0.2, 0.4, 0.6, 0.8 and 1V
0.8
(a)
0.4
0.0
Gate Capacitance (C
) {fF}
GG
Drain Capacitance (C
) {fF}
DG
6.5 Summary
(b)
0.4
0.0
0.4
0.8
VGS(V)
1.2
1.6
Symbols: Simulation
Line: Model
0.0
0.4
0.8
1.2
1.6
VGS(V)
Figure 6.7: Validation of drain capacitance (CDG ) and gate capacitance (CGG ) behavior of model against
the TCAD simulation data. The panel (a) shows the CDG while panel (b) shows the CGG at different
values of VDS w.r.t. applied gate to source voltage. Note that CGG and CDG looks similar, but their
values are different as QG includes QS in addition to the QD .
6.4.2
Terminal Charges and Capacitances
The gate charge (QG ) and the drain charge (QD ) predicted by our model w.r.t. the applied VGS at
different VDS are shown in Fig. 6.6a and Fig. 6.6b, respectively along with the simulation data.
The terminal drain capacitance (CDG ) and gate capacitance (CGG ) w.r.t the applied VGS at VDS
is shown in Fig. 6.7a and Fig. 6.7b and show a reasonable match with the simulation results. In
both the figures, the model shows reasonable consistency with the simulation data. In general
proposed model captures the simulation data trend satisfactorily, albeit with small deviation at
higher VGS values. This small deviation may be due to effects such as fringing field capacitance,
gate overlap capacitance etc. which are not included in our present work. Note that CGG and
CDG looks similar, but their values are different as QG includes QS in addition to the QD .
6.5
Summary
In this chapter, we have developed a surface potential based analytical model of the drain current, terminal charges, and capacitances for a DG-TFET. The surface potential model includes
the effect of mobile charges and is valid over a wide range of applied bias conditions including
6.5 Summary
113
both depletion as well as the saturation regime. The surface potential model is in turn used to
model the ambipolar current in the device. Furthermore, we also calculate the terminal charge
and terminal capacitance. Our model shows a good agreement with the TCAD based simulation
data for the electric field, drain current, terminal charges, and various terminal capacitances in
a DG-TFET over a wide operating range. This highlights the fact that proposed model captures all the relevant aspects of the device physics reasonably well, and it can be very useful
as a compact model for computationally efficient circuit simulations of a DG-TFET. The presented model methodology can also be adopted to model the III-V heterojunction TFETs by
incorporating the effect of the heterojunction.
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Chapter 7
Conclusions
Tunnel field effect transistor (TFET) is one of the promising devices that circumvent the subthreshold swing problem in modern low power transistors. TFETs have been widely researched
recently for low power VLSI devices, because of it’s low OFF current and steeper subthreshold
slope. The limitations of the TFET are its low ON-current as compared to MOSFET/FinFET
requirements and stringent fabrications steps required for good performance. Reported methods to increase ON current in TFETs include structural modifications (hetero junction source),
doping optimization (retrograde doping, pocket implanted source etc), gate metal work function
engineering (double gate, dual metal gate), improving electrostatics (gate all around structures),
and dielectric optimization (with one or multiple dielectrics). Strain at the source and drain end
can also be used to increase the ON current. The lower band gap material at the source side in
tunnel based devices favors better tunneling current.
In order to tackle some of the issues associated with TFETs, we have investigated some
optimization techniques in details. We have first discussed “Dual Metal Gate” technique, in
which two metals are placed at the gate for Si and relaxed SiGe source. Dual metal at the
gate provide additional flexibility to control the different sections of the transfer characteristics.
Further, we have observed that the performance improves by manoeuvring the dielectrics at the
gate (hetero dielectric). Using SiGe at the source gives extra degree of freedom to modulate the
band gap at source. The limitation of the DMG technique is that as the device dimension scales
down, fabrication complexity increases particularly for the hetero dielectric devices.
Next we have worked on strain engineering for SiGe source TFET. We have carried out re117
118
search on different device structures and observed that the compressive strain in SiGe, improves
the subthreshold swing and ON current as compared to relaxed-SiGe and Si TFETs. As a result
of the compressive strain, valence and conduction band split and the effective band gap reduces.
Additionally, from pocket implant study it can be concluded that it’s not an effective method to
increase the ON current, due to very large increase in OFF current because of electric field enhanced SRH recombination. The source extended structures are also scrutinized to improve the
TFET performance. It is observed that 2 nm source extension inside the gate results in the best
ON current and subthreshold slope. Length extension inside the gate degrade the sub-threshold
slope, but increase the ON current significantly.
Additionally, we have used the density functional theory to study thickness dependent study
for extended Ge source lateral TFET. We have extended source by 2 nm inside the gate in order
to confine the tunneling in Ge. We have observed that the band alignment at Si/Ge junction
changes significantly with thickness scaling. It is also found that at reduced thickness, 2 nm
overlap length is insufficient to confine the tunneling in Ge. In ultra thin devices, the electrostatic effects also play an important role in BTBT due to increased gate coupling, and this
enhances the subsurface BTBT current significantly. The increased contribution of the subsurface BTBT current, to the total drain current in ultra-thin Ge TFET, results in significantly
improved subthreshold region characteristics.
Following it, we have presented a comparative study of vertical and lateral tunneling in Ge
source TFETs, as the source is scaled down from bulk to ultra-thin slab of 4 nm thickness. We
have used an overlapped gate over Ge source to include vertical line tunneling along with lateral
tunneling in the device. We have observed that as the Ge source thickness is scaled down to
ultra-thin films (TGe ≤ 8 nm), line tunneling disappears in the gate-source overlapped TFETs
and the net current is degraded. Thus, we find that gate overlapped structure with ultra-thin
Ge source is not suitable for future low power applications. We have shown that TFETs with
strong lateral P-P tunneling result in better performance at reduced thickness, as compared to
the gate-source overlap TFETs, which offer significant line tunneling only in the bulk case.
We have also developed a surface potential based analytical model of the drain current,
terminal charges, and capacitances for a DG-TFET. The surface potential model includes the
7.1 Scope for Future Work
119
effect of mobile charges and is valid over a wide range of applied bias conditions including both
the depletion and the saturation regimes. This model is further used to model the ambipolar
current in the device. Additionally, we calculate terminal charge and terminal capacitance. Our
model is in good agreement with the TCAD based simulation data for the electric field, drain
current, terminal charges, and terminal capacitances in a DG-TFET over a wide operating range.
This highlights the fact that the proposed model captures all the relevant aspects of the device
physics reasonably well, and it can be very useful as a compact model for computationally
efficient simulations for of DG-TFET circuits.
7.1
Scope for Future Work
Further research work in the areas, covered in this thesis can be carried out as follows:
The effect of strain is incorporated on the bulk properties of SiGe. It would be interesting
to include the effect of confinement along with the strain in SiGe and Si as the thickness is
scaled.
The direct valley of Ge can be engineered by using strain, or by incorporating larger
atom like Sn in the lattice structure. Effect of thickness dependent quantum confinement on the
valence band of Ge is another area that can be explored.
Incorporating the effect of strain on the confined Si/Ge interface is another challenging
area for research.
In our work, we have solved the 2-D Poisson equation without the mobile charge carrier
and have considered the mobile charge effect by empirical equation in the center potential and
inverse decay length. It would be interesting to solve the Poisson equation with mobile charge
to make the model simpler.
Modeling the hetero junction TFET’s with III-V alloys is another area to be explored. The
presented model methodology can also be adopted to model the III-V hetero junction TFETs
by incorporating the effect of hetero junction.
Appendix A
List of Publications
A.1
Journal Papers
• P. Jain, V. Prabhat, and B. Ghosh, “Dual metal-double gate tunnel field effect transistor with mono/hetero dielectric gate material”, accepted in Journal of Computational
Electronics, vol. 14, no. 2, pp. 537-542, Jun 2015.
• P. Jain, P. Rastogi, C. Yadav, A. Agarwal and Y. S. Chauhan, “Band-to-band tunneling in
valley for Ge source lateral tunnel field effect transistor: Thickness scaling ”, Journal of
Applied Physics, vol. 122, no. 1, pp.014502, 2017.
• P. Jain, C. Yadav, A. Agarwal and Y. S. Chauhan, “Surface potential based modeling
of charge, current, and capacitances in DGTFET including mobile channel charge and
ambipolar behaviour”, Solid-State Electronics, Vol. 134, no. Supplement C, pp. 74-81,
2017.
• B. Tripathi and P. Jain, “SiGe Source Dual Metal Double Gate Tunnel Field Effect Transistor”, Journal of Low Power Electronics, Vol. 13, no. 1, pp. 76-82, 2017.
A.2
Conference Papers
• P. Jain, P. Rastogi, T. Dutta, A. Agarwal and Y. S. Chauhan, “Impact of Thickness Scaling on Vertical and Lateral Tunneling in Ge Source Tunnel FETs”, IEEE International
120
A.2 Conference Papers
121
Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
• P. Jain and D. Kumar, “Drive Current Boosting Using Pocket Implant Near to the Strained
SiGe/Si Source with Single-Metal/Dual-Metal Double Gate Tunnel Field Effect Transistor”, in Proceedings of International Conference on Intelligent Communication,
Control and Devices:ICICCD 2016, Springer Singapore, Oct. 2016.
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