MOS Inverters:
Switching Characteristics and Interconnect Effects
1
2
CMOS INVERTER CIRCUIT
4
CASCADED CMOS INVERTER STAGES
CASCADED CMOS INVERTER STAGES
Introduction
◆ First-stage CMOS inverter with lumped output load
capacitance.
7
DVLSI
Delay-Time Definitions: Propagation Delays
V50% = VOL +
1
(VOH − VOL )
2
1
= (VOL + VOH )
2
 PHL = t1 − t0
 PLH = t3 − t2
P =
8
DVLSI
 PHL +  PLH
2
Delay-Time Definitions: Rise & Fall Times
V10% = VOL + 0.1 (VOH − VOL )
 fall = t B − t A
V90% = VOL + 0.9  (VOH − VOL )
 rise = tD − tC
9
DVLSI
Calculation of Delay Times (1)
◆ Simplest method : estimating the average capacitance
current
 PHL =
 PLH
Cload  VHL Cload  (VOH − V50% )
=
I avg , HL
I avg , HL
Cload  VLH Cload  (V50% − VOL )
=
=
I avg , LH
I avg , LH
▪ The average current
I avg , HL
I avg , LH
10
1
= iC (Vin = VOH ,Vout = VOH ) + iC (Vin = VOH ,Vout = V50% ) 
2
1
= iC (Vin = VOL ,Vout = V50% ) + iC (Vin = VOL ,Vout = VOL ) 
2
DVLSI
Calculation of Delay Times (2)
◆ More accurate method: solving the state equation of
the output node in time domain
▪ The capacitance current
Cload
dVout
= iC = iD , p − iD ,n
dt
▪ The rising-input case
iD , p  0
Cload
11
dVout
= iC = −iD ,n
dt
DVLSI
Output Load Capacitance
Cload = Cgd ,n (Wn ) + Cgd , p (Wp ) + Cdb ,n (Wn ) + Cdb , p (Wp ) + Cint + Cg
= f (Wn , Wp )
Cdb,n = Wn DdrainC j 0,n K eq ,n + 2(Wn + Ddrain )C jsw,n K eq ,n
Cdb, p = Wp DdrainC j 0, p K eq , p + 2(Wp + Ddrain )C jsw, p K eq , p
Cload =  0 +  nWn +  pW p
where
 0 = 2 Ddrain (C jsw,n K eq ,n + C jsw, p K eq , p ) + Cint + Cg
 n = K eq ,n (C j 0,n Ddrain + 2C jsw,n )
 p = K eq , p (C j 0, p Ddrain + 2C jsw, p )
12
DVLSI
CMOS Ring Oscillator Circuit
T =  PHL1 +  PLH 1 +  PHL 2 +  PLH 2 +  PHL3 +  PLH 3
= 2 P + 2 P + 2 P
= 3  2 P = 6 P
13
DVLSI
Sizing Trends of CMOS Inverter w/ Small
Geometry Devices
0.62
Vth (V)
0.61
0.60
b = 2.58
0.59
0.58
0.57
Noise Margin (V)
Rise & fall time (ps)
Propagation delay (ps)
0.56
28
26
PHL
24
22
20
b = 1.4
18
PLH
16
14
60
55
fall
50
45
b = 2.02
40
35
rise
30
25
0.55
0.54
0.53
0.52
0.51
0.50
0.49
0.48
0.47
0.46
0.45
NMH
b = 2.48
NML
1.0
14
P
b = 2.19
1.5
2.0
2.5
b ratio
3.0
3.5
4.0
DVLSI
Estimation of Interconnect Parasitics
◆ Main components of the
output load
▪
▪
▪
15
Internal parasitic
capacitances of transistors
Interconnect capacitances
Input capacitances of the
fan-out gates
DVLSI
The Transmission-line Models
l
 
 rise ( fall )  2.5   
v
 transmission-line modeling
l
 l  either transmission-line 
2.5      rise ( fall )  5     

v
 v  or lumped modeling 
l
 
 rise ( fall )  5   
v
16
 lumped modeling
DVLSI
Interconnect Delay
100
Gate delay
Relative Delay
Local wire
10
Global wire w/ repeaters
Global wire
1
0.1
250
180
130
90
65
45
32
Process Technology Node (nm)
◆ Dealing with the implications and optimizing a system
for speed
▪ Estimating the interconnect parasitics in a large chip
▪ Simulating the transient effects.
17
DVLSI
Statistical distribution
◆ Statistical distribution of interconnection length on a
typical chip
18
DVLSI
Interconnect Capacitance Estimation (1)
◆ A simplified view of six interconnections on three
different levels
19
DVLSI
Interconnect Capacitance Estimation (2)
◆ The section of a single interconnect
20
DVLSI
Interconnect Capacitance Estimation (3)
◆ The total parasitic capacitance
21
DVLSI
Thickness value of different layers
Field oxide thickness
Gate oxide thickness
Polysilicon thickness
Poly-metal oxide thickness
3μm
2.6nm
1μm (minimum width 0.06μm)
1.1μm
Metal 1 thickness
Metal 2~7 thickness
Metal 8~9 thickness
Via oxide thickness (PO-M1)
1.8μm (minimum width 0.09μm)
2.2μm (minimum width 0.1μm)
9μm (minimum width 0.4μm)
1.75μm
Via oxide thickness (M1-M6)
2.2μm
Via oxide thickness (M6-M9)
9μm
n+ junction depth
p+ junction depth
n-well junction depth
22
23nm
28nm
3μm
DVLSI
Parasitic Parallel-plate capacitance values
FOX
PO
M1
M2
M3
M4
M5
M6
M7
M8
M9
FOX
-
6.37
5.14
2.98
1.99
1.49
1.20
0.99
0.85
3.23
2.45
PO
6.37
-
16.6
5.13
1.99
1.49
1.44
1.16
0.97
3.57
2.64
M1
5.14
16.6
-
15.1
4.28
2.50
1.76
1.36
1.11
3.96
2.85
M2
2.98
5.13
15.1
-
15.1
4.28
2.50
1.76
1.36
4.61
3.17
M3
1.99
1.99
4.28
15.1
-
15.1
4.28
2.50
1.76
5.51
3.57
M4
1.49
1.49
2.50
4.28
15.1
-
15.1
4.28
2.50
6.85
4.09
M5
1.20
1.44
1.76
2.50
4.28
15.1
-
15.1
4.28
9.05
4.79
M6
0.99
1.16
1.36
1.76
2.50
4.28
15.1
-
15.1
13.3
5.77
M7
0.85
0.97
1.11
1.36
1.76
2.50
4.28
15.1
-
25.3
7.26
M8
3.23
3.57
3.96
4.61
5.51
6.85
9.05
13.3
25.3
-
25.3
M9
2.45
2.64
2.85
3.17
3.57
4.09
4.79
5.77
7.26
25.3
-
23
DVLSI
Parasitic Fringing-plate capacitance values
FOX
PO
M1
M2
M3
M4
M5
M6
M7
M8
M9
FOX
-
23.4
15.1
13.2
11.5
10.7
10.2
10.4
10.5
12.3
11.2
PO
23.4
-
27.6
15.6
12.6
11.4
10.4
10.4
10.9
12.7
11.2
M1
15.1
27.6
-
26.4
14.5
12.3
11.3
10.8
11.3
13.2
11.8
M2
13.2
15.6
26.4
-
26.4
14.6
12.4
11.6
11.9
13.9
12.3
M3
11.5
12.6
14.5
26.4
-
26.4
14.7
12.7
12.7
14.9
12.8
M4
10.7
11.4
12.3
14.6
26.4
-
26.4
14.9
13.9
16.4
13.5
M5
10.2
10.4
11.3
12.4
14.7
26.4
-
26.8
16.4
18.6
14.3
M6
10.4
10.4
10.8
11.6
12.7
14.9
26.8
-
28.6
22.6
15.3
M7
10.5
10.9
11.3
11.9
12.7
13.9
16.4
28.6
-
33.0
16.7
M8
12.3
12.7
13.2
13.9
14.9
16.4
18.6
22.6
33.0
-
32.4
M9
11.2
11.2
11.8
12.3
12.8
13.5
14.3
15.3
16.7
32.4
-
24
DVLSI
Interconnect Resistance Estimation
◆ Total resistance in indicated current direction
Rwire
l
l 
= 
= Rsheet  
wt
 w
◆ The sheet resistivity of the line
Rsheet
25

= 
t 
DVLSI
RC Delay Models
◆ Simple lumped RC model & T-model

 t 
Vout ( t ) = VDD 1 − exp  −

 RC  


 
V50% = VDD 1 − exp  − PLH
 RC




 PLH  0.69RC
◆ Distributed RC ladder network model
26
DVLSI
Various RC Models
Vin
R
R/2
Vin
Vout
R/2
C
C
(a) lumped RC model
Vin
R/4
R/4
R/2
C/2
(b) T-model
R
Vin
V out
R/2
C/4
R/2
C/2
C/2
(d) π-model
Vout
C/4
(e) π2-model
27
Vout
C/2
C/2
(c) T2-model
Vin
Vout
Vin
R/3
C/6
R/3
C/3
R/3
C/3
(f) π3-model
DVLSI
Vout
C/6
The Elmore Delay (1)
N
 Di =  C j
j =1

Rk
for all
kPij
◆ The general topology of the RC tree network
▪ Let Pi denote the unique path from the input node to node i,
i = 1, 2, 3, ..., N.
▪ Let Pij = Pi « Pj denote the portion of the path between the
input and the node i, which is common to the path between
the input and node j.
28
DVLSI
The Elmore Delay (2)
 D 7 = R1C1 + R1C2 + R1C3 + R1C4 + R1C5 + ( R1 + R6 ) C6
+ ( R1 + R6 + R7 ) C7 + ( R1 + R6 + R7 ) C8
 D 5 = R1C1 + ( R1 + R2 ) C2 + ( R1 + R2 ) C3 + ( R1 + R2 + R4 ) C4
+ ( R1 + R2 + R4 + R5 ) C5 + R1C6 + R1C7 + R1C8
N
j
 DN =  C j  Rk  DN =   C   R 
N
N
j =1
k =1
j
N
j =1

 k =1 

 C  R   N ( N + 1) 
 N +1
=    
=
RC



2
 N  N  
 2N 

29
DVLSI
 DN =
RC
2
for N → 
Example 6.5 (1)
◆ 1) Examine the propagation delay across a long
polysilicon interconnect line (length=1000μm, width=1μm)
▪ Rsheet= 15 Ω/square
◆ 1) Sol.
R lumped = R sheet  (# of squares)
 1000m 
 = 15k
= 15(/square)  
 1m 
C parallel − plate = (unit area capacitance)  (area)
= 0.106fF / m 2  (1000m 1m) = 106fF
C fringe = (unit length capacitance)  (perimeter)
= 0.043fF / m  (1000m + 1000m + 1m + 1m) = 86fF
Clumped −total = C parallel − plate + C fringe = 192fF
30
DVLSI
Example 6.5 (2)
▪ The simulated output voltage waveforms
1.2
Voltage (V)
1.0
Input
Lumped RC model
Distributed RC model
0.8
0.6
0.4
0.2
0.0
-8
3.5x10
-8
4.0x10
-8
4.5x10
-8
5.0x10
-8
5.5x10
Time (s)
31
DVLSI
-8
6.0x10
-8
6.5x10
-8
7.0x10
-8
7.5x10
Example 6.5 (3)
▪ The simulated output voltage waveforms with an
overestimation of the propagation delay time
1.2
Input
Lumped
RC model
Distributed
RC model
2p - model
T - model
Voltage (V)
1.0
0.8
0.6
2.04ns
0.4
1.22ns
0.2
0.0
-8
3.8x10
-8
4.0x10
-8
-8
4.2x10
4.4x10
Time (s)
32
DVLSI
-8
4.6x10
-8
4.8x10
Example 6.5 (4)
◆ 2) Consider a polysilicon line consisting of two
segments (W=1.5 μm & W=0.5 μm, each 500 μm)
◆ 2) Sol.
 500 m 
 500 m 
R lumped −1 = 15(/square)  
=
15k

,
R
=
15(

/square)



 = 5k
lumped − 2
 0.5 m 
 1.5 m 
R lumped −total = R lumped −1 + R lumped − 2 = 20k
C parallel − plate−1 = 0.106fF / m 2  (500m  0.5m) = 26.5fF
C parallel − plate− 2 = 0.106fF / m 2  (500m 1.5m) = 79.5fF
C fringe−1  C fringe− 2 = 46fF
Clumped −total = C parallel − plate−1 + C parallel − plate− 2 + C fringe−1 + C fringe− 2 = 192fF
33
DVLSI
Example 6.5 (5)
▪ The simulated output voltage waveforms
1.2
Input
Lumped RC model
Distributed RC model
(propagation A → B)
Distributed RC model
(propagation B → A)
Voltage (V)
1.0
0.8
0.6
0.4
0.2
0.0
-8
3.5x10
-8
4.0x10
-8
4.5x10
-8
5.0x10
-8
5.5x10
Time (s)
34
DVLSI
-8
6.0x10
-8
6.5x10
-8
7.0x10
-8
7.5x10
-8
8.0x10
Example 6.5 (6)
▪ The simulated output voltage waveforms with an
overestimation of the propagation delay time
Input
Lumped
RC model
Distributed
RC model
2p - model
T - model
1.2
1.0
Voltage (V)
0.8
0.6
2.68ns
0.4
1.08ns
0.2
0.0
-8
4.0x10
-8
4.2x10
-8
-8
4.4x10
4.6x10
Time (s)
35
DVLSI
-8
4.8x10
-8
5.0x10
Switching Power Dissipation
36
DVLSI
The Average Power Dissipation
Pavg =
1 T
v ( t )  i ( t ) dt

0
T
◆ The average power dissipation of CMOS inverters
Pavg
dV
1 T2

=   Vout  −Cload out
T 0
dt

Pavg

Vout2
1 
=
 −Cload
T 
2

Pavg =
37
T
dVout


dt
+
V
−
V
C
(
)

T 2 DD out  load dt

 
 dt 
 
T 

1

2 
 +  VDD Vout  Cload − CloadVout  
2

T 2
0

T 2
1
2
CloadVDD
or
T
2
Pavg = Cload  VDD
f
DVLSI
The Switching Power Expression
◆ The average switching power
expression will hold for any
CMOS logic circuit.
38
DVLSI
Power Meter Simulation (1)
39
DVLSI
Power Meter Simulation (2)
◆ The current equation for the common node
Cy
dVy
dt
= b is −
Vy
Ry
◆ The initial condition of Vy
 t −
Vy ( t ) =
exp  −
 RC
C y 0
y y

b
t

iDD ( ) d

◆ Assuming RyCy ≫ T,
Vy ( T ) 
b
Cy

T
0
iDD ( )d
b = VDD
1 T
Vy (T ) = VDD   iDD ( )d
T 0
40
DVLSI
Cy
T
Example 6.6 (1)
◆ Simulate the Circuit in Fig. 6.27 w/ power meter
▪ VDD=1.2V, Pavg=0.25mW
1.4
Vin
1.2
Vout
Voltage (V)
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
0
50
100
150
Time (ps)
41
DVLSI
200
250
300
Example 6.6 (2)
◆ Simulation results
18
250
16
14
12
150
Power (uW)
Power Supply Current (uA)
200
100
50
10
8
Pavg (t=T) = 3.33uW
6
4
0
2
-50
0
-100
0
50
100
150
200
250
300
Time (ps)
42
-2
0
50
100
150
Time (ps)
DVLSI
200
250
300
Power-Delay Product
◆ The average dynamic power dissipation
2
PDP = CloadVDD
◆ The power-delay product

PDP = 2 Pavg
P
2
PDP = 2 ( CloadVDD
f max ) P

1
2 
= 2 CloadVDD 
  PHL +  PLH

2
= CloadVDD
43
DVLSI
    PHL +  PLH 
 

2

 
Energy-Delay Product
◆ A fair metric for comparison
Add_a
Delay
(ps)
180
Power consumption
(mW)
40
PDP
(pJ)
7.2
EDP
(10 -21J∙s)
1.296
Add_b
240
30
7.2
1.728
◆ EDP
EDP = PDP  p
2
= CloadVDD
p
*
= 2 Pavg
 P2
44
DVLSI