AN5355
Application note
Mitigation technique of the SiC MOSFET gate voltage glitches with Miller clamp
Introduction
The gate drive requirements of Silicon-Carbide (SiC) MOSFETs are similar to Silicon MOSFETs and IGBTs; however the
superior switching capability combined with the specific electrical characteristics of these power devices and parasitic elements
requires special attention on the gate drive circuit and layout design to avoid the ringing and overshoot phenomena from
becoming an issue. In particular, induced Miller turn-on effects and amplitude voltage glitches across the gate-source terminals
may be slightly exacerbated due to the higher target commutation speed and because the negative gate voltage amplitude
maximum rating (AMR) is different from the positive one contrary to what is typically expected in silicon devices. It is therefore
very important to establish proper driving conditions by preventing these anomalies with appropriate mitigation methods, without
overly compromising the device’s switching performance. The use of a Miller clamp instead of standard gate driver
configurations allows optimal clamping and the best possible gate control under high-speed switching events, to completely
eliminate unwanted Miller induced turn-on effects. In order to demonstrate this concept, the 2nd generation 650 V SiC MOSFETs
from the STPOWER family in an HiP247 package are employed to investigate these anomalies arising at the gate-source
terminals during the switching transients.
AN5355 - Rev 1 - July 2019 - By Anselmo Liberti, Giuseppe Catalisano, Luigi Abbatelli
For further information contact your local STMicroelectronics sales office.
www.st.com
AN5355
Miller turn-on and glitch phenomena
1
Miller turn-on and glitch phenomena
1.1
Glitch phenomena generation
In bridge topologies, during the high negative slew rate of VDS voltage of one switch, a current is injected towards
the gate by the Miller capacitance of the complementary switch (CGD). A voltage spike appears on the switch gate
due to the drop caused by the Miller current across the overall gate path impedance. If the positive VGS spike
exceeds the switch VGS(th) during the rapid rise of the VDS transient, a shoot through may occur across the half
bridge. Power devices with low threshold voltage such as SiC MOSFETs are more likely to suffer from induced
turn-on, which is why certain precautions are required. The negative temperature coefficient of the threshold
voltage can also foster this phenomenon and potential risks of capacitive parasitic turn-on can be obviated by
reducing the RGoff value.
Figure 1. Miller turn-on phenomenon due to fast rising VDS transient in half bridge topology
HV_BUS
DRIVER
VH_HS
RDRI
CGD
RG-ON
This switch is
turning ON
generating the half
bridge’s dv/dt
CDS
V
RG_IN CGS
RG-OFF
PHASE
GND_HS
VH_LS
RDRI
Load current direction
RG_ON
CGD
(High side hard-switching turn-on)
CDS
V
Vgs_spike
RG_OFF
RG_IN CGS
GND_LS
GND_ POWER
This switch is OFF
In general, the duality of glitch phenomena is generated due to the applied positive or negative dv/dt on the
switching node resulting in an instantaneous current IGD flow through the charge of the MOSFET Miller
capacitance CGD. Some current through CGD flows out of the gate terminal and back through the drive sink
resistance, which produces a spurious voltage spike at the MOSFET. During the negative dv/dt, occurring at turnoff of the complementary switch in half bridge topology, the negative VGS peak has to be kept within the AMR to
avoid any possible gate oxide damage.
AN5355 - Rev 1
page 2/19
AN5355
Glitch phenomena generation
Figure 2. Miller current generation with positive
dv/dt
Figure 3. Miller current generation with negative
dv/dt
Figure 4. Duality of glitch phenomena
Negative dv/dt for LS
Positive dv/dt for LS
VGS_LS
HS
Low side
Risk of parasitic turn-on
VGS_pk+
VGS_pk−
Risk of generating
peak below AMR
VDS_HS
LS
ID_HS
High side
TDT = Dead Time
Inductive parasitic turn-on can be also generated during turning off of the load current when a voltage is induced
across the emitter stray inductance. In this condition, the decay of the current induces a voltage on source stray
inductance that shifts the source potential to the negative level. The inductive parasitic turn-on, however, can be
limited by increasing the RGoff value. Useful approaches that help control glitch phenomena include limiting dV/dt
rating, minimizing the parasitic gate loop inductance, selecting a driver with low pull down output impedance or
implementing negative gate bias. False turn-on phenomenon due to a fast positive dv/dt rating can be also limited
by using a separate turn-off gate driving network path or putting a small capacitor between the gate to source at
the expense of reducing the efficiency improvement with higher switching losses. More advanced techniques,
such as "Active Miller Clamp", can be used to provide a low impedance path without compromising the turn-off
slew rate control.
AN5355 - Rev 1
page 3/19
AN5355
Mitigation techniques for induced G-S glitches
1.2
Mitigation techniques for induced G-S glitches
Driving the switch gate to a negative voltage increases the safety margin between the spike level and the VGS(th)
threshold. However, a negative voltage that is too low increases the risk of exceeding the lower AMR limit of VGS
due to the negative spikes caused by CGD discharge in the opposite dv/dt transient; the best trade-off is usually a
negative voltage between -2 V and -5 V in according to the maximum rating of the involved device. The use of an
active Miller clamp to mitigate induced G-S glitches allows to establish a low impedance path without
compromising the turn-off slew rate control when the external switch is already off, which helps avoid the induced
turn-on phenomenon. Moreover, it also enables the turn-off gate resistor on the basis of turn-off speed
requirements only (EOFF), and helps reduce the negative gate spike caused by CGD discharge during the opposite
dv/dt transients.
Figure 6. Active Miller CLAMP
Figure 5. Negative gate driving
DRIVER
PHASE
VH_LS
RDRIV
CGD
RG_ON
V+
CDS
RG_IN
RG_OFF
V-
CGS
Vgs_spike
I
VL_LS
+
VL
GND_ POWER
1.3
How active Miller clamp works
The additional switch between the gate and source controls the Miller current during a high dV/dt situation and
keeps the SiC MOSFET totally off by shorting the gate-to-source path after a voltage level is reached. During
turn-off switching, the gate voltage is detected and the clamp is activated when the gate voltage drops below a
threshold voltage value relative to VEE (see Figure 6. Active Miller CLAMP). The currents across the Miller
capacitance are shunted by the transistor instead of flowing through the output driver VOUT. The Miller clamp
function is only effective during SiC MOSFET turn-off and does not affect SiC turn-on. It provides cost saving
solution by eliminating the need for a negative supply voltage and additional capacitors that reduce driver
efficiency.
AN5355 - Rev 1
page 4/19
AN5355
Voltage coupling through (Miller) capacitance
Figure 7. Active Miller clamp technology
+12V
V+
V-
G-ON
C
R
+12V
C
V+
V-
+12V
VL_LS
EE
1.4
Voltage coupling through (Miller) capacitance
Another important parameter to be taken in account beside the Miller transfer capacitance in order to minimize the
sensitivity to the ringing phenomena is the Crss Ciss ratio in terms of maximum amplitude at VDS = 0 V and how its
trend decreases over the VDS variation. When a voltage appears across the drain and source of the MOSFET, it
couples to the gate and causes the internal gate source capacitor to charge. If the voltage on the gate increases
beyond the MOSFETs threshold voltage, it starts to turn back on which can cause cross conduction. The ratio of
the capacitances Crss and Ciss determines the severity of this effect.
Gen2 SiC MOSFETs also improves on the 1st generation (Gen1) with better CGD/CGS ratio, which determines
voltage coupling, and a smaller CGD with bigger CGS minimizes the residual VGS when device is off (capacitive
divider).
Figure 8. SiC MOSFET intrinsic capacitances
AN5355 - Rev 1
page 5/19
AN5355
Voltage coupling through (Miller) capacitance
Figure 9. Capacitive ratio CGD/CGS Gen1 vs. Gen2 SiC MOSFETs
As visible from the capacitive ratio between Gen1 SiC MOSFET SCT20N120 and Gen2 SiC MOSFET
SCTH90N65G2V-7 of the above attached datasheet capacitance variation curves, the reverse transfer
capacitance Crss is 11 (Gen1) vs 20 (Gen2) times smaller than the input capacitance Ciss at 10 V and 28 (Gen1)
vs 55 (Gen2) at 100 V.
AN5355 - Rev 1
page 6/19
AN5355
Voltage glitch suppression with active Miller clamp
2
Voltage glitch suppression with active Miller clamp
The Miller clamp function implemented on the new ST gapLITE driver has been tested for the reduction of both
positive and negative glitches: positive glitches could cause thermal stresses on the device due to spurious turnon effects, while negative glitches could jeopardize the reliability of the gate oxide. The Miller effect has been
deeply investigated using two SiC MOSFETs connected in a DC/AC half-bridge configuration at Tamb ≈ 25 °C and
driven by gapLITE. The SCTW35N65G2V 2nd generation 650 V / 45 A planar SiC MOSFET by ST in an HiP247
package has been used as the test vehicle. The tested device features extremely low gate charge and input
capacitances, very fast and robust intrinsic body diode capacitance, very high operating temperature capability
(TJ = 200 °C), and very small RDS(on) variation over temperature.
2.1
Half bridge inverter and setup
The tests and measurements were performed on a half-bridge inverter topology board implemented on a PCB, as
shown below.
Figure 10. Half bridge inverter topology
Half Bridge Inverter
STGAP2S
S-PWM
FILTER
VIN = 400VDC
STGAP2S
S-PWM
Vout=110VAC
Figure 11. Half bridge inverter prototype
FILTER
Upper
device
Lower
device
DUT
(SCTW35N65G2V)
Isolated supply
for -5V/+18V
650V Gen2
SiC MOSFETs
Details of the driver:
closed to the DUT
Gate Driver Board
AN5355 - Rev 1
page 7/19
AN5355
Half bridge inverter and setup
Figure 12. Half bridge inverter wiring diagram
STGAP2S/D allows negative gate driving
V_Bus
VCC_+5V
VSS1_H
C1
U1
1
INA
R1
2
220
3
C2
100p
R3
2.2k
4
VDD
GNDISO
IN+ GOFF-CLAMP
IN-
GON-VOUT
GND
VH
8
Q1
R2
7
6
C3
STGAP2S
R9
2.2k
220
3
C6
100p
4
VDD
GNDISO
IN+ GOFF-CLAMP
IN-
GON-VOUT
GND
VH
D1
18V
D2
LED
2
VIN
Q2
R7
6
18
17
16
1
GND NC
R8
C7
4
0
PES1-S5-S24-M
5
STGAP2S
5
+VO
C3
8
7
C1
Q1
GND1_H
C2
8
2
12
11
10
13
14
15
U2
1
7
8
9
+5V
GND1_H
VSS1_L
C5
10u
R6
6
5
4
2.2u
2.2u
INB
1
2
3
C4
VDD1_H
VCC_+5V
VDD1_H
J1
R4
5
R3
2.2k
R4
2.2k
R2
1k
C4
C8
VDD1_L
VSS1_H
V_Bus
GND1_L
C10
2.2uF/ 630V
GND1_H
VDD1_H
VSS1_H
VCC_+5V
1
J2
J3
BNC
INB
1
J5
BNC
2
3
INA
2
3
C11
2.2uF/ 630V
1
2
C9
GND1_L
VDD1_L
VSS1_L
1
2
3
12
11
10
J4
6
5
4
7
8
9
GND1_H
VDD1_H
VSS1_H
GND1_L
VDD1_L
VSS1_L
DC/DC converter for
VGS supply (+18V/-5V)
CON2
Half Bridge inverter
Gate drivers gapLITE single STGAP2S were implemented on the motherboard by allowing negative gate voltage
to drive the two SiC MOSFETs. Short paths between gate pin and driver have been enabled and optimized in
order to guarantee less impedance to the Miller Clamp. Features and electrical characteristics of the used
gapLITE single drive are:
•
3 V 3/5 V logic inputs (1/2, 2/3 of VDD threshold)
•
•
•
•
•
•
•
•
•
•
•
•
•
up to 26 V supply voltage
4 A sink/source current capability
short propagation delay: 80 ns
UVLO function (for each supply)
temperature shut-down protection
stand by function
100 V/ns CMTI
high voltage rail up to 1700 V
active high and active low input pins (for HW interlocking)
STGAP2C: separated output option for easy gate driving tuning
STGAP2SC: Miller clamp pin option to avoid induced turn-on
negative gate drive ability
SO-8 package
Measurements on lower device were taken with the PP023 passive probe with short loop for GND and 500 MHz
of BW. For the upper device, the HVD3106 with twisted terminal and 120 MHz BW. The oscilloscope bandwidth
was 500 MHz.
Figure 13. STGAP2C: separated output
AN5355 - Rev 1
page 8/19
AN5355
2nd Gen 650 V SiC MOSFET
Figure 14. STGAP2SC: Miller CLAMP pin option to avoid induced turn-on
2.2
2nd Gen 650 V SiC MOSFET
ST’s 2nd generation (Gen2) SiC improves on the 1st generation (Gen1) with better RDS(on), smaller chip size,
lower Qg and optimized JFET geometry. In particular, the new Gen2 features a planar structure with a further
elementary pitch reduction that decreases the specific on-resistance RDS(on),SP at 25 ºC (with RDS(on),SP the
RDS(on) x active area) by 40% compared with Gen1 MOSFETs. Gen2 SiC MOSFET driving requirements need a
gate bias voltage of +18 V to obtain the proper RDS(on) with lower drive loss. It is also possible to reduce this to
+15 V, but this increases the RDS(on) by about 80% at 20 A and 25 °C.
Other features are:
•
extremely low gate charge and input capacitances
•
very fast and robust intrinsic body diode capacitance
•
very high operating temperature capability (Tj = 200 °C)
•
very small RDS(on) variation overtemperature
Table 1. Absolute maximum ratings and on/off states
Parameter
SCTW35N65G2V
Drain current (continuous) at Tc = 25 °C
Drain current (continuous) at Tc = 100 °C
Drain current (pulsed)
Gate-source voltage
Gate-source voltage (recommended operating range)
Value
2nd generation 45 A / 650 V planar SiC MOSFET
technology
ID
IDM
VGS
45 A
35 A
90 A
-10 to 22 V
-5 to 20 V
TJ
-55 to 200 °C
Gate threshold voltage
VGS(th)
3.2 V
Static drain-source on-resistance @ VGS = 18 V, TJ = 25 °C
RDS(on)
55 mΩ
Operating junction temperature range
AN5355 - Rev 1
Symbol
page 9/19
AN5355
Gate driver configurations
Table 2. Dynamic, switching energy and times
Parameter
2.3
Symbol
Value
Input capacitance
Cies
1370 pF
Output capacitance
Coes
125 pF
Reverse transfer capacitance
Cres
30 pF
Total gate charge
Qg
73 nC
Turn-on switching energy @ TJ = 25 °C
Eon
100 µJ
Turn-off switching energy @ TJ = 25 °C
Eoff
35 µJ
Fall time @ TJ = 25 °C
tf
14 ns
Rise time @ TJ = 25 °C
tr
9 ns
Gate driver configurations
Two different configurations available for the gate driving networks were implemented: the “Separated Output”
option (indicated as SEP OUT) having a different path for the driving networks' turn-on/off, and the “Active Miller
clamp” function (indicated as AMC) to mitigate both positive and negative voltage glitches.
Figure 15. Separate output configuration
Figure 16. Single output with AMC configuration
AN5355 - Rev 1
page 10/19
1.1
2.4
AMC
AMC MINMIN-
EP OUT
SEP
OUT MINMIN-
-3.5
-3.0
-5.5
AN5355
-7.5
-8.5
−10V
−10V
10
10
-11.6
15
15
20
20
RRG-ON
and R G-OFF(Ω)
(Ω)
G-ON and RG-OFF
3
Test conditions and results
22Ω
22Ω
25
25
Test conditions and results
The tests and measurements with SiC MOSFETs and gapLITE were performed on the half-bridge inverter board
at the following conditions:
•
input voltage VIN = 400 V
•
output voltage VOUT = 110 Vac
•
output power POUT = 1600 W
•
switching frequency FSW = 50 kHz
•
RG_ON = RG_OFF decreased up to 2.2 Ω
•
•
RMS output current IRMS ≈ 14.5 A
gate-source driving voltage VGS_ON = +18 V and VGS_OFF = -5 V
•
death time = 200 ns
The main objectives were:
•
To check whether oscillations during commutation are within the reference limits set as VGS(th)_TYP = 3.2 V
at 25 ºC and VGS,MIN = -10 V (AMR).
•
Compare the two different gate driver configurations in terms of generation and clamping of the gate voltage
glitches, by varying the driving settings and slew rate conditions.
The images below show the low side device measurements in the two different driving configurations comparing
SEP OUT vs AMC. From the values achieved by the positive and negative voltage glitches on VGS signal vs dv/dt
variation, the positive glitches are below the Vth value with both tested AMC and SEP OUT driving configurations,
both positive and negative dv/dt, and in all the three setting conditions for the gate driving resistances of 22 Ω, 10
Ω and 4.7 Ω, respectively. However, the negative glitches exceed the AMR for both configurations and in all the
gate resistance conditions, with the exception of AMC at 22 Ω.
In particular, the positive and negative voltage glitch levels reached by the low side device during the tests were:
+2.4 V and -5.5 V with SEP OUT compared to -3.5 V and -7.5 V with AMC @ RG_ON = RG_OFF = 22 Ω and
positive dv/dt up to 40 V/ns;
-3.0 V and -11.6 V with SEP OUT compared to +1.1 V and -8.5 V with AMC @ RG_ON = RG_OFF = 22 Ω and
negative dv/dt up to 20 V/ns;
+0.3 V and -6.8 V with SEP OUT compared to -2.3 V and -10.2 V with AMC @ RG_ON = RG_OFF = 10 Ω and
positive dv/dt up to 60 V/ns;
-1.5 V and -11.5 V with SEP OUT compared to +2.0 V and -8.9 V with AMC @ RG_ON = RG_OFF = 10 Ω and
negative dv/dt up to 30 V/ns;
-1.3 V and -7.5 V with SEP OUT compared to -0.5 V and -11.5 V with AMC @ RG_ON = RG_OFF = 4.7 Ω and
positive dv/dt up to 80 V/ns;
-0.2 V and -12.0 V with SEP OUT compared to +2.5 V and -10.6 V with AMC @ RG_ON = RG_OFF = 4.7 Ω and
negative dv/dt up to 40 V/ns.
Figure 17. Positive and negative voltage ringing with +dv/dt and -dv/dt @ Rg = 22 Ω
Voltage
(V)
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
Voltage
(V)
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
+3.2V
+3.2V
AMC MAX+
AMC MIN-
SEP OUT MAX+
SEP OUT MIN-
2.4
-3.5
-5.5
-7.5
−10V
−10V
0
AN5355 - Rev 1
Positive and negative ringing with +dV/dt vs RG
5
10
15
RG-ON and RG-OFF (Ω)
20
22Ω
25
Positive and negative
negative ringing
ringing with
with +dV/dt
-dV/dt vs RG
+3.2V
+3.2V
AMC MAX+
AMC
AMC MINMIN-
SEP OUT MAX+
SEP
SEP OUT
OUT MINMIN-
1.1
2.4
-3.5
-3.0
-5.5
-7.5
-8.5
−10V
−10V
00
55
10
10
15
15
RRG-ON
and R G-OFF(Ω)
(Ω)
G-ON and RG-OFF
-11.6
20
20
22Ω
22Ω
25
25
page 11/19
+3.2V
+3.2V
AN5355
Test conditions and results
−10V
−10V
Voltage
(V)
Positive and negative ringing with +dV/dt vs RG
Positive and negative
Voltage
(V)
6 10 Ω
Figure 18.
6 Positive and negative voltage ringing with +dv/dt and -dv/dt @ Rg =
+3.2V
4
Voltage
(V)
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
Positive and negative
ringing with +dV/dt vs RG
2
+3.2V
−10V
0
0
-2
-4
0.3 -6
-8
-2.3 -10
-6.8 -12
-14
5
2 -dV/dt
Positiveand
andnegative
negativeringing
ringingwith
with
-dV/dtvsvsRGRG
Positive
AMC MIN-
2.5
0
66
+3.2V
+3.2V
-2
SEP OUT
SEP OUT MIN4 4 MAX+
-4
2
2
AMC
MAX+
2.02.0
AMC-1.3
MAX+
AMC MINAMC
MAX+
-6
00
SEP
OUT
MAX+
-1.5
SEP OUT MAX+
SEP OUT MINSEP
OUT
MAX+
-2-2
-8
-1.5
-7.5
-4-4
-10
-6
-12
−10V -6
-8-8
-11.5
-8.9
-8.9
-14
-10
-10
−10V
0
-11.5 25
5
10
15
−10V20
-12-12
-11.5
RG-ON and RG-OFF
-14-14(Ω)
15
20
25
00
55
1010
1515
-0.2
-0.5
0
-10.2
AMC
MINAMC
MINSEP
OUT
MINSEP
OUT
MIN-
4.7Ω
10
+3
4
Voltage
Voltage
AMC MAX+
(V)(V)
RG-ONand
and
RG-OFF
(Ω)
RG-ON
RG-OFF
(Ω)
RG-ON and RG-OFF (Ω)
5
2020
10
RG-ON
4.7Ω
2525
Figure 19. Positive and negative voltage ringing with +dv/dt and -dv/dt @ Rg = 4.7 Ω
Voltage
(V)
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
Positive and negative ringing with +dV/dt vs RG
Voltage
(V)
+3.2V
-0.5
AMC MAX+
AMC MIN-
SEP OUT MAX+
SEP OUT MIN-
-1.3
-7.5
−10V
-11.5
0
5
4.7Ω
10
15
RG-ON and RG-OFF (Ω)
20
25
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
Positive and negative ringing with -dV/dt vs RG
+3.2V
2.5
AMC MAX+
AMC MIN-
-0.2
SEP OUT MAX+
SEP OUT MIN-
0
−10V
-10.6
-12.0
5
4.7Ω
10
15
RG-ON and RG-OFF (Ω)
20
25
Figure 20. AMC vs SEP OUT with positive and negative dv/dt and Rg = 22 Ω
Positive dv/dt = 30÷40 V/ns
with RG-ON = RG-OFF = 22 Ω
SEP OUTPUT – ACTIVE MILLER CLAMP
-3.5V
-7.5V
AN5355 - Rev 1
Negative dv/dt = 15÷20 V/ns
with RG-ON = RG-OFF = 22 Ω
SEP OUTPUT – ACTIVE MILLER CLAMP
+3.2V
+2.4V
+1.1V
+3.2V
-3.0V
-5.5V
−10V
-8.5V
-11.6V
−1
-10.6
-12.0
−10V
page 12/19
AN5355
Test conditions and results
Figure 21. AMC vs SEP OUT with positive and negative dv/dt and Rg = 10 Ω
Positive dv/dt = 60 V/ns
with RG-ON = RG-OFF = 10 Ω
SEP OUTPUT – ACTIVE MILLER CLAMP
Negative dv/dt = 30 V/ns
with RG-ON = RG-OFF = 10 Ω
SEP OUTPUT – ACTIVE MILLER CLAMP
+3.2V
+0.3V
-1.5V
-2.3V
-6.8V
-10.2V
+3.2V
+2.0V
-8.9V
−10V
−10V
-11.5V
Figure 22. AMC vs SEP OUT with positive and negative dv/dt and Rg = 4.7 Ω
Positive dv/dt = 80 V/ns
with RG-ON = RG-OFF = 4.7 Ω
SEP OUTPUT – ACTIVE MILLER CLAMP
Negative dv/dt = 40 V/ns
with RG-ON = RG-OFF = 4.7 Ω
SEP OUTPUT – ACTIVE MILLER CLAMP
+3.2V
-1.3V
-0.5V
-7.5V
-11.5V
−10V
+3.2V
2.5V
-0.2V
-10.6V
−10V
-12.0V
The figure below mentions the waveforms acquired in the AMC case with Rg = 10 Ω during positive and negative
dv/dt for both low side and high side devices. The color codes used to differentiate the electrical signals are:
Low side device: drain current in yellow (CH1@10 A/div), drain-source voltage in pink (CH2@100 V/div),
•
gate-source voltage in blue (CH3@5 V/div)
•
High side device: drain current in red (CH7@10 A/div), drain-source voltage in orange (CH8@100 V/div),
gate-source voltage in green (CH4@5 V/div)
Figure 23. AMC with positive and negative dv/dt @ Rg = 10 Ω
AMC
Ringing
-2.3V
+3.2V
+3.2V
-10V
Negative glitch: -10.2V
dv/dt=60V/ns
AN5355 - Rev 1
AMC
Ringing
+2.0V
-10V
Glitch
-10.2V
Negative glitch: -8.9V
dv/dt=30V/ns
Glitch
-8.9V
page 13/19
AN5355
Zener protection among G-S pins with AMC driver configuration
3.1
Zener protection among G-S pins with AMC driver configuration
Further evaluation tests were performed with the AMC driver by inserting zener protection among the G-S pins
using two anti-series diodes to investigate the clamping action towards both positive and negative glitches at
2.2 Ω with the AMC driver:
•
20 V Zener diode to clamp positive glitch
6 V Zener diode to clamp negative glitch
•
Figure 24. AMC configuration with zener protection among G-S pins
Zener protection
V_Bus
VCC_+5V
VSS1_H
C12
U3
1
INA
R10
2
220
3
C13
100p
R13
2.2k
4
VDD
GNDISO
IN+ GOFF-CLAMP
IN-
GON-VOUT
GND
VH
8
Q3
7
6
R12
D4
5
C14
STGAP2S
2.2u
C15
D5
2.2u
VDD1_H
VCC_+5V
VSS1_L
1
10u
INB
R14
R17
2.2k
220
GND1_H
U4
C16
2
3
C17
100p
4
VDD
GNDISO
IN+ GOFF-CLAMP
IN-
GON-VOUT
GND
VH
8
Q4
7
6
R16
D2
5
STGAP2S
C18
C19
D3
VDD1_L
GND1_L
From the following figures with the Zener protection connected among the G-S pins, the negative glitches always
exceed the AMR for configurations with Zener protection and Rg = 2.2 Ω, even if the negative VGS-peak value is
smaller than the value without Zener protection. Moreover, in AMC configuration without Zener diodes, the
positive glitch is above the Vth value, but apparently not long enough to cause parasitic turn-on; while in AMC
configuration with Zener diodes, the positive glitches are always below the Vth value and exhibit an effective
performance improvement.
Figure 25. AMC driver with positive and negative dv/dt @ Rg = 2.2 Ω: comparison with/without Zener
protection
Positive dv/dt = 90 V/ns
with RG-ON = RG-OFF = 2.2 Ω
+5.9V
+3.2V
+2.2V
-12.5V
-15.1V
AN5355 - Rev 1
Negative dv/dt = 45 V/ns
with RG-ON = RG-OFF = 2.2 Ω
+3.9V
+2.3V
−10V
NO Zener – Zener
-13.0V
-11.0V
+3.2V
−10V
NO Zener – Zener
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AN5355
Conclusion
4
Conclusion
Fast switching devices such as Silicon-Carbide (SiC) MOSFETs are affected by a common problem related to the
induced Miller turn-on effect and the generation of glitch phenomena on the gate-source voltage. To better
understand this phenomena, this paper looks at both the negative and positive voltage glitches that occur on the
gate-source terminals of SiC MOSFETs during the transients turn-on and off on a typical half-bridge DC-AC power
converter topology. A suitable gate driver with a Miller clamp function has been used to mitigate false turn-on
behavior under fast switching conditions. The Active Miller Clamp technique shows a significant improvement with
dv/dt ratings lower than around 20 V/ns and this case is of primary importance for applications like motor drive
where slow switching transients are required. Some limitations are visible at higher dv/dt, especially in terms of
negative glitch mitigation, due to the parasitic inductance in the active Miller clamp path that reduces the efficacy
in clamping voltage spikes and is responsible for ringing. The use of Zener protection between gate and source
provides an improvement in terms of spike reduction at high dv/dt, thus representing a further optimization to be
combined with parasitic inductance minimization.
AN5355 - Rev 1
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AN5355
References
5
References
[1]S. Yin et al., “Gate driver optimization to mitigate shoot-through in high-speed switching SiC half bridge
module,”IEEE 11th Int. Conference on Power Ele. and Drive Systems, Sydney, NSW, 2015, pp. 484-491.
[2]H. Chen, D. Divan “High Speed Switching Issues of High Power Rated Silicon-Carbide Devices and the
Mitigation Methods” 2015 ECCE, pp.2254-2260.
[3]F. Gao, Q. Zhou, P. Wang, C. Zhang “A gate driver of SiC MOSFET for Suppressing the negative Voltage
Spikes in a Bridge Circuit,” Power Elect. Trans. on vol. 33, no. 3, pp.2339-2353, April 2017.
[4]T. Funaki, “A study on self-turn-on phenomenon in fast switching operation of high voltage power MOSFET”,
2013 3rd IEEE CPMT Symposium Japan, Kyoto, 2013, pp.1-4
[5]Helong Li and S. Munk-Nielsen,”Detail Study of SiC MOSFET switching Characteristics,” 2014 IEEE 5th
International Symposium on Power Electronics for Distributed Generation Systems (PEDG), 2014.
[6]Y. Mukunoki, T. Horiguchi, Y. Nakayama, and A. Nishizawa, Y. Nakamura, K. Konno, M. Kuzumoto, and H.
Akagi “Modeling of a Silicon-Carbide MOSFET With Focus on Internal Stray Capacitances and Inductances, and
its verification”, APEC 2017, pp. 2671-2677
AN5355 - Rev 1
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AN5355
Revision history
Table 3. Document revision history
AN5355 - Rev 1
Date
Version
15-Jul-2019
1
Changes
First release.
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AN5355
Contents
Contents
1
2
3
Miller turn-on and glitch phenomena . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1
Glitch phenomena generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2
Mitigation techniques for induced G-S glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3
How active Miller clamp works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4
Voltage coupling through (Miller) capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Voltage glitch suppression with active Miller clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Half bridge inverter and setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
2nd Gen 650 V SiC MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Gate driver configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Test conditions and results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1
Zener protection among G-S pins with AMC driver configuration . . . . . . . . . . . . . . . . . . . . . . 14
4
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
5
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
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AN5355
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AN5355 - Rev 1
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