Cairo University
Faculty of Engineering
Credit Hours System
CCE-E
ELCN 301 – Spring 2022
Project #2
Simulation tool to be used is Cadence Virtuoso.
• You work in groups of 2 students (or less).
• You are required to deliver a hard copy report that contains:
➢ Schematic diagrams (snapshots from Cadence showing transistor
dimensions and/or component values: DC Operating Point, Region of
Operation)
➢ Design procedure (hand calculations)
➢ Simulation results (snapshots from Cadence)
➢ Discussion of your results and conclusions.
Any missing item from the 4 items above will be penalized in the report
grading.
Please be aware that ‘bad’ presentation (report document, figures, comments etc.)
of your work is going to affect your grade.
The total grade of the project is 10 points.
The deadline to submit the project report is Thursday May 27th, 2022.
Any copied reports will be given Zero.
V in
+
V out
_
10 pF
Part I:
You are required to design a unity gain buffer (shown in top left figure) based on a
basic CMOS operational amplifier (shown top right figure).
Requirements for the Op-amp:
• Supply VDD = 3V (Use 3V transistors N_HG_33_L130E or
P_HG_33_L130E)
• Input DC level = Output DC level = 2V
• DC gain ≥ 40dB
• GBW ≥ 10MHz
• Phase Margin (PM) ≥ 600
• Output swing ≤ 1.5Vpp (closed loop)
• ISS in implemented as a simple current mirror with IREF =100μA
Documentation:
1. Design procedure (equation-based calculations to show how the transistor
sizes where chosen).
2. Schematic diagrams with dimensions of all transistors and bias currents.
3. Simulation results with the following results/plots:
• DC operating point of all transistors showing region of operation.
• AC response (gain, phase, BW, PM) of the open loop
Hint: Use Stability analysis in Cadence
•
•
•
AC response (gain, BW) of the closed loop.
Transient response for a step input of 10mV (from 2V to 2.01mV).
Transient response for a sine input of 2V+A.sin(2πft), where
A=100mV and f=1MHz. Plot the discrete Fourier transform (DFT) and
find the total harmonic distortion (THD).
•
Plot the gain while sweeping A of the sine input from 100mV to
800mV in steps of 100mV. What is the 1-dB compression point?
• Plot the output noise and input-refereed noise of your design. What is
the integrated noise (from 1kHz to BW)? What are the main noise
contributors? Hint: Use Noise analysis in Cadence.
4. Repeat (3) after adding a capacitor from node VX to VDD of value 10pF (AC
open loop, AC closed loop, and step response only)
5. Calculate the area and total power consumption of your design including
IREF .
6. Discussion of your results and Conclusions.
Part II:
Design a CMOS ring oscillator as shown in Fig below with VDD=1.2V. The unit
cell (stage) consists of a CMOS inverter (M2 & M3), an NMOS current source
(M1), and a PMOS current source (M4). This is called a “Voltage Controlled
Oscillator (VCO)”.
Requirements:
1. Explain why this is a “Voltage Controlled Oscillator (VCO)”.
2. Determine the dimensions of all the transistors (Use 1.2V devices
N_12_HSL130E or P_12_HSL130E) to generate an output frequency of
V
20MHz using 7-stages with Vcont = DD .
2
Documentation:
1. Schematic diagrams showing dimensions of all transistors and bias current
(IB ).
2. Simulate the schematic of the ring oscillator and plot the transient waveforms
at all outputs showing the output frequency (you might need to add an initial
condition to start the oscillations).
3. Vary Vcont from 0 to VDD and record the output frequency versus Vcont in
steps of 0.1V. Plot 𝐕𝐨𝐮𝐭 for 3 different steps.
4. Repeat (2) after doubling the size (2W/2L) of all inverters (M2 & M3).
5. Repeat (2) for 5-satges and 9-stages.
6. Discussion of your results and Conclusions.