ISSN 1828-6003
Vol. 6 N. 4
July 2011
International Review on
Computers and Software
(IRECOS)
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Contents:
455
Ontology Instance Matching Using Distributional Similarity Measure
by Farinaz Alamiyan, Kamran Zamanifar
462
Collusion-Resistant Fingerprinting for Multimedia Using Tardos Code
by Xiliang Zeng, Yan Feng, Jian Ren
473
New Multi-Agent's Control Architecture for the Autonomous Mobile Robots
by S. Benaissa, F. Moutaouakkil, H. Medromi
477
A Novel Evolutionary Neural Network Based Temperature Forecaster Using Ant Colony
Optimization Metaheuristic
by Akshay Gupta
481
Simple Island Parallel Genetic Algorithm Based on MapReduce Using Cloud Computing
by Jianfeng Zhao, Wenghua Zeng, Min Liu, Guangming Li
486
Communicating Positional Accuracy within a Standard-Based Geospatial Service Chain
by Morteza Karimzadeh, Ali A. Alesheikh, Pouria Amirian
494
Effects of Software Manager Profile on Maturity Level of Software Development Process
by Meric Merih Aykol, Zuhal Tanrikulu
505
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Automatic Determination of Information System Subsystems Execution and Development Order
by Robert Kudelić, Alen Lovrenčić
Soft Computing-Based Software Test Cases Optimization: a Survey
by Manoj Kumar, Arun Sharma, Rajesh Kumar
512
A Service-Oriented Architecture for Distributed Geoprocessing: a Case Study of Landslide
Susceptibility Mapping
by Mahsa Amini Tareh, Ali Asghar Alesheikh, Mohammad Ebrahim Poorazizi
527
Anti-Collusion Digital Fingerprinting Scheme Using Hybrid Coding
by Youwu Xu
534
A 4.1-bit, 20 GS/s Comparator for High Speed Flash ADC in 45 nm CMOS Technology
by M. J. Taghizadeh Marvast, H. Sanusi, M. A. Mohd. Ali
538
(continued on outside back cover)
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International Review on Computers and Software
(IRECOS)
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Santolo Meo
Department of Electrical Engineering
FEDERICO II University
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(U.S.A.)
Luis Javier García Villalba
(Spain)
Ismail Khalil
(Austria)
Catalina M. Lladó
(Spain)
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Marios Angelides
(Romania)
Brijesh Verma
(Australia)
Lipo Wang
(Singapore)
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International Review on Computers and Software (I.RE.CO.S.), Vol. 6, N. 4
July 2011
A 4.1-bit, 20 GS/s Comparator for High Speed Flash ADC
in 45 nm CMOS Technology
M. J. Taghizadeh Marvast, H. Sanusi, M. A. Mohd. Ali
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Abstract – A 4.1-bit, high speed comparator for high-speed flash analog-to-digital converter
and K-band applications that can work at a sampling rate of 20GS/s is presented in this paper.
This fully differential comparator consists of three stages using a new structure to improve its
performance. The offset voltage of the designed comparator has been reduced by means of an
active positive feedback. The CMOS positive feedback and a new structure as output circuit are
used to improve sampling rate and performance of comparator. The analyses and simulation
results were obtained by using CMOS parameters. The comparator can operate with a 1 V peak to
peak input range consuming 0.561 mW. The predicted performance is verified by analyses and
simulations using HSPICE tool. Copyright © 2011 Praise Worthy Prize S.r.l. - All rights
reserved.
I.
Introduction
circuits.
The comparator structure is fully differential and
consists of three stages. The first stage is a low gain
differential amplifier with resistive loads (RD), which is
high range band with.
The comparator with resistive loads shows better
linearity offset and gain response in comparison with
comparators with active or diode loads. The first stage of
comparator is used to reduce the input offset of
comparator.
The second stage is a CMOS track and hold with
positive feedback and used of inductor and current
source to reduce regenerative time. The domino output
circuit that is new our suggestion circuit as shown in
right block of Fig. 1 is used instead of SR Latch to
support the comparator in high sampling rate.
In practical implementation, any random or systematic
imbalance of the circuit creates an offset in the
comparator.
Offsets are classified as static or dynamic according to
their origins.
The fully differential comparator has many
advantages to prevent supply and kickback noise and
therefore, achieves a big dynamic range. The differential
amplifier has better linearity.
It has to be clear, which aspect of comparators
performance is important? In addition to power
dissipation there are several items which may be
important, such as supply voltage, gain, swing voltage,
band width, distortion input offset, linearity and over
drive recovery.
In practice, most of these parameter trade with each
other, making the design a multi-dimensional
optimization problem.
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Flash analog-to-digital converters (ADC) with X-band
and K-band frequency sampling rates are critical
components for applications such as radar, signal
capture, satellite, digital oscilloscopes and waveform
recorders [1]. Today researchers and the industry have
extended the requirement for higher frequency and
higher sample rate. Flash can generally achieve the
higher sampling rates, with the comparator limiting the
maximum achievable sampling speed. In addition, this
comparator can be used for UWB, X-band and K-band
technology that offer a lot of capability for the design of
communications
devices
requiring
very
high
performance and low power consumption [2]. The
comparators published in years [3]-[5] still have
relatively high power consumption and operate with
sampling rate lower than the expected future
requirement. In this paper a new CMOS positive
feedback is proposed to increase the speed of track and
hold (T/H) of the comparator. A new structure is also
proposed to achieve the overall high speed for the
comparator. The comparator design incorporates various
techniques to lower its power consumption and improve
its overall performance. The comparator architecture is
described in Sect. 2. The preamplifier design, T/H and
output domino logic are presented in Sect. 3. Section 4
shows the simulation results, and finally Sect. 5 is the
conclusion.
IN
Keywords: Analog -to- Digital Converter, Comparator, Preamplifier
II.
Architecture
Fig. 1 illustrates the comparator architecture that
consists of preamplifier, track&hold (T/H) and output
Manuscript received and revised June 2011, accepted July 2011
Copyright © 2011 Praise Worthy Prize S.r.l. - All rights reserved
538
M. J. Taghizadeh Marvast, H. Sanusi, M. A. Mohd. Ali
Fig. 1. Schematic of comparator
There is a relation between offset and W/L of the
preamplifier that is equal to:
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where Vt is threshold voltage and gm is transconductance
W and L are width and length respectively [6], [7].
Equation (1) indicates that with increase of transistor size
(W) offset will be reduced, but this increase depends on
the design. In addition, swing, bandwidth, output
capacitance and linearity are important factors to choose
the load of preamplifier. The linearity and frequency
response of the preamplifier with passive load is better
than preamplifier with active load. It is important to note
that, with increasing LNA gain, the bandwidth is also
decreased.
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Fig. 2. Relationship between comparator design parameters
(1)
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Voffset
⎛ ∆w1 ∆L1 ∆w2
⎞
+
+
+
⎟
1 ⎜ w1
L1
w2
⎜
⎟
= ∆Vt +
∆wn ∆Ln ⎟
gm ⎜ ∆L 2
+ ... +
+
⎜+
⎟
wn
Ln ⎠
⎝ L2
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Illustrated in Fig. 2 such trade-off present many
challenges in the design of high quality comparator for
flash ADC, requiring intuition and experience to arrive at
an acceptable compromise.
III. Comparator Design
III.2. Comparator Core (T/H) and Output Circuit
III.1. Preamplifier
The comparator core is shown in Fig. 4. The load is
formed by the series combination of a resistor and an
inductor. Vp and Vm are the differential analog inputs
signal from the preamplifier. It has input differential
pairs (MI and M2) that turn on when the clock is low and
track the input from the previous stage. When the clock
is high, the comparator goes into hold mode. In this
paper CMOS positive feedback is applied to improve
speed of comparator and decrease the regenerative time
in latching mode. The passive inductor peaking
technique is also employed in the T/H circuit to enhance
the bandwidth [8]-[10]. The comparator core is designed
using new structure. This type of design is the most
efficient in terms of speed and very low swing signal
operation. Therefore, it's reduced output swing and hence
low-power dissipation. In other words, the domino
output circuit as shown in Fig. 1 is used instead of SR
Latch to support the comparator in high sampling rate
operation. The combination of T/H and output circuit
creates a fast structure for the comparator. Domino logic
as output circuit operates in two phases, the precharge
phase and the evaluation phase. In the precharge phase,
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The low noise amplifier (LNA) is shown in Fig. 3.
The main role of LNA is to reduce the input referred
offset of the comparator. The preamplifier acts as an
isolator between voltage reference and T/H to improve
bandwidth and decrease input offset. The preamplifier
has two inputs for differential analog signal and two
inputs for voltage reference.
Fig. 3. Preamplifier
Copyright © 2011 Praise Worthy Prize S.r.l. - All rights reserved
International Review on Computers and Software, Vol. 6, N. 4
539
M. J. Taghizadeh Marvast, H. Sanusi, M. A. Mohd. Ali
output is precharged from low to high, while in the
evaluation phase, output will either be discharged from
high to low or remain high.
V.
Conclusion
In this paper, a 45nm CMOS K-band comparator for
high speed low power flash ADC is proposed. CMOS
positive feedback and a new structure as output circuit
are used to improve sampling rate and performance of
comparator. We have used new core structure and
domino logic circuit to speed up, reduce crosstalk and
save power consumption of comparator. This structure
will be able to improve performance of all type ADCs.
As shown in Table I, this work demonstrates at least two
times or up to 40 times higher speed as compared to
previous work with better ENOB. The measured ENOB
is 4.1 bits at 20 GS/s with a 6.5 GHz sine input signal.
Simulation Results
Fig. 5. FFT at input frequency of 6.5 GHz
and sampling rate of 20Gsample/s
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The proposed comparator structure is designed using
45 nm CMOS technology. Simulation result was
obtained by using HSPICE tool Table I shows the
summary of comparator performance, in comparison
with the designs in [3] and [4].
The new comparator dissipates only 0.561mW at
20GS/s. Fig. 6 shows the output wave of comparator
with1GHz analog input signal and clock frequency of
20Gs/s. The FFT of the signal at input frequency of 6.5
GHz and sampling rate of 20Gsample/s is shown in Fig.
5.
IN
IV.
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Fig. 4. Comparator core (Track/Hold)
Fig. 6. Output wave of comparator at Fin=1GHz, Fclk=20Gs/s
Author
Supply
voltage
Sampling
frequency (fs)
[4]
1v
4 (GS/s)
[5]
[3]
This work
1.2v
2.2v
1.8v
0.5 (GS/s)
11 (GS/s)
20 (GS/s)
TABLE I
P E R F O R M A N C E COMPARISON
Process
ENOB Effective
number of bits
(ENOB)
4
90nm CMOS
CMOS
3.5
130 nm CMOS
3
120nmBiCMOS
4.1
45 nm CMOS
Copyright © 2011 Praise Worthy Prize S.r.l. - All rights reserved
Power dissipation (P)
years
3.6 mW
2007
0.148mW
0.561mW
2007
2008
2010
International Review on Computers and Software, Vol. 6, N. 4
540
M. J. Taghizadeh Marvast, H. Sanusi, M. A. Mohd. Ali
Reference
Authors’ information
[1]
Mohammad Jafar Taghizadeh Marvast was
born in 1979 in Yazd, Iran. He received the B.Sc.
and M.Sc in electronic engineering from Islamic
Azad University south branch of Tehran in 2002
and 2007. Now he is doing PhD at University
Kebangsaan Malaysia. His main research interest
is VLSI and microelectronic & digital
communication.
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Mohd Alauddin Mohd Ali (M’94) was born in
1955. He received the B.Eng. degree in electrical
engineering, the B.Sc. degree in mathematics,
and the M.Eng.Sc. degree in electrical
engineering from the University of Tasmania,
Australia, in 1978, 1979, and 1984, respectively,
and the Ph.D. degree from the University of
Nottingham, U.K., in 1994. He worked in the
area of microelectronics for his M.S. degree and medical electronics for
his Ph.D. degree. He is currently a Professor with the Department of
Electrical, Electronic and Systems Engineering, Faculty of Engineering
and Built Environment, Universiti Kebangsaan Malaysia (UKM),
Bangi, Malaysia. He was also the Head of the department and the
Deputy Dean of the faculty for the periods 1995–1997 and 1997–2002,
respectively. He is also currently the Deputy Director of the Institute of
Space Science (ANGKASA) and Associate Principal Research Fellow
at the Institute of Microengineering and Nanoelectronics (IMEN),
UKM. His area of expertise and research interest include biomedical
signal processing, instrumentation, intelligent traffic control, integrated
circuit design and testability, and ionospheric studies.
Hilmi Sanusi. BSEE (Hartford), MSEE
(Connecticut). He is the Coordinator for the
Department Laboratories . He is Associate
Fellow of
Institute of Space Science,
ANGKASA. He is executive Center for
educational extension. His Research Interest are
Stochastic Control and Estimation Process, Orbit
Control
and
Determination,
Altitude
Determination of Satellite and Control Systems (ADSC).
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Federal Communications Commission. (2002). First Report and
Order Revision of Part 15 of the commission’s rules regarding
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355.
Copyright © 2011 Praise Worthy Prize S.r.l. - All rights reserved
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