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Summary:
Floorplan
Place
Make
 Source globals.tcl
 Create Shape/Size
 Port placement
 Place Mem/Macro/IP
 Create PG mesh
 Add Physical cell
 Create Placement Blk,
Routing Blk, Region
 Create NDR for design
check
 Check log file with no error and
warning can waive
 Netlist is unique and no issue, has
load file netlist successful
 Shape math with spec
 Pin place position easier connect with
net
 Each mem has at least 2 VDD/VSS
(provide power mem), channel mem
has at least 1 VDD/VSS (provide
power std cell)
 Balance mesh routing and signal
routing
 Endcap insertion check: add
boundary, mem, hard place blk
 Welltap insertion check
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check log file
runtime reasonable
timing check
congestion – routing overflow
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check log file
runtime reasonable
timing check (path same with place,
check skew, lantency)
congestion check
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CTS
Route
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Load Database of Floorplan
Insert I/O buffers
Source
common.dont_touch.tcl
Source
common.dont_use.tcl
place_design
saveDesign, report
source prects.uncertainty.tcl
place_opt_design
saveDesign, report
load database place
set max_fanout
set target_skew
set target_max_trans
add INV balance
set NDR and shield for clock
create file clock_tree_spec
source file clock_tree_spec
source prects.uncertainty.tcl
ccopt_design
saveDesign, report
Load database cts
routeDesign
saveDesign, report
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check log file
runtime reasonable
timing check
routing violation number (short,
open)
Route_opt
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load database route
source
postcts.uncertainty.tcl
optDesign
saveDesign, report
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Check log file
Runtime reasonable
Timing check
Routing violation
+ In floorplan step,
 Creating floorplan shape with the utilization ~= 60%.
 Placing Pin with the preference direction of layer.
 Placing Macro/IO and others ( placement blockages, Routing blockages,..).
 Adding welltap and Endcap for making sure DRC.
 Creating power mesh, which is strong enough for supplying power.
Goal of floorplan:
 Correct with customer specification.
 Making Routable.
 Good for timing optimization.
 Power mesh is strong enough.
Check after running floorplan:
 Check errors and warnings in log file.
 After running floorplan step, Do check uitilization for making sure area for placement.
 Check run time.
+ In place step,
 Placing standard cells into floorplan.
 Adding I/O buffers.
 Adding Tie cells.
 Deciding about using which layers for signal routing.
 Do trial route ( Ideal clock so latency of clock = 0 => skew = 0 ).
Goal of placement:
 Minimum congestion.
 Minimize cell density and pin density.
 Timing, power and area optimizations.
Check after running placement:
 Check errors and warnings in log file.
 Check congestion map – where have routing overflow.
 Check timing reports.
 Check run time.
+ In cts step,
 Set non default rules (NDR).
 Build clock tree ( file clock_tree_spec ).
 Setting about max fan out , max transition and max capacitance.
 Setting about ccopt mode.
 Check run time.
Goal of CTS:
 Minimize latency and minimize skew.
Check after running CTS:
 Check errors and warnings in log file.
 Check timing reports ( skew, latency , …).
 Check congestion.
 Check run time.
+ In route step,
 Routing design with real clock net so timing is worse than place step.
 Global routing -> track assignment -> detail routing -> search and repair.
Goal of route step:
 Minimize the total of wire length.
 Meet DRC (spacing, width,..).
 Complete all required connections without increasing the area of floorplan.
Check after route step:
 Check timing reports.
 Check routing violation ( short,open,…).
 Check errors and warnings in log file.
 Check run time.
+ In route_opt step,
 Optimize routing and meet timing closure.
Goal of route step:
 Minimize the total of wire length.
 Meet DRC (spacing, width,..).
 Complete all required connections without increasing the area of floorplan.
 Optimize timing and decreasing the WNS.
Check after route step:
 Check timing reports.
 Check routing violation ( short,open,…).
 Check errors and warnings in log file.
 Check run time.