DESim Installation Guide
For Quartus® Prime 21.1
1
Introduction
This tutorial shows you how to download and install the DESim application on a computer that is running a Microsoft
Windows or Ubuntu operating systems. To perform the steps given below you will need to have access to the Internet,
and have the required permissions to install application software.
We do not give detailed instructions in this document for using the DESim application, but only show how to install it.
Separate instructions for using the DESim application are provided in the tutorial called Using the DESim Software
with Verilog/VHDL Code. Before using the DESim application it is necessary to install either the ModelSim or
Questa simulation software. This version of the DESim application was built for:
• ModelSim-Intel FPGA edition software v10.5b which comes with the Quartus Prime software v19.1.
• Questa-Intel FPGA edition software v2021.2 which comes with the Quartus Prime software v21.1.
Instructions for installing the ModelSim and Questa applications are provided in the tutorials Using the ModelSimIntel FPGA Simulator with Verilog/VHDL Testbenches and Using the Questa-Intel FPGA Simulator with Verilog/VHDL Testbenches, respectively, available on FPGAcademy.org.
2
Getting Started
The discussion below assumes that you are using the Google Chrome Internet Browser to navigate on the Internet.
If you are using a different browser application, then you may notice some minor discrepancies from some of the
material presented below.
You can download the DESim software installer from its repository on GitHub. Open your Internet browser and
navigate to https://github.com/fpgacademy/DESim/releases. This action opens the repository’s
Releases page, part of which is shown in Figure 1
The DESim repository includes the source-code for the application. You can browse through this code if interested,
but it is not necessary to do so.
If using the Microsoft Windows operating system, read section 2.1. If using the Ubuntu operating system, jump to
section 2.2. After read either of those sections, continue reading at section 2.3
2.1
Windows Installation
Click on the filename desim_setup.exe, as illustrated in Figure 1, which downloads this file to your computer. You
may be presented with a warning message in your browser, because the file that you are downloading is an executable
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program. Make the appropriate selections in your browser to keep the downloaded file so that it is saved onto your
computer.
Figure 1. The Releases page for the DESim repository.
The desim_setup.exe file is the installer program for the DESim application. Open this file (execute the program) to
reach the Welcome screen shown in Figure 2. Click Next to see the License Agreement for the DESim application,
and then click I Agree if you accept the terms of the license. If you do not accept the terms of the agreement, then
the installer will exit. Click Next to reach the screen displayed in Figure 3.
Figure 2. The first screen of the DESim installer.
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As shown in Figure 3, you can specify an installation folder. In the discussion below, we assume that you have
accepted the default location (C:\DESim), but you can change this selection. Click the Install button. During
the installation process you have the option of placing an icon onto your Desktop for this application. This icon
provides an easy way to run the DESim application, and so is recommended.
Figure 3. Installing the DESim application.
The C:\DESim folder created in the installation process contains the DESim software and some example projects
(called demos). Start the DESim application by double-clicking its icon on your Desktop, or by selecting DESim
from the Windows Start menu. Alternatively, you can use File Explorer to run the DESim application by
navigating to the C:\DESim folder, right-clicking on the batch file DESim_run.bat, as illustrated in Figure 4,
and then selecting Open (or, you can double-click on the batch file to open it).
Figure 4. Starting the DESim application under Windows.
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2.2
For Quartus® Prime 21.1
Linux Installation
Click on the filename desim.tar.gz, shown in Figure 1, which downloads this file to your computer. Extract the
contents of the tarball to a folder, such has ∼/DESim, by using the command ‘tar -zxf desim.tar.gz’.
This newly created directory contains the DESim software and some example projects (called demos). Start the
DESim application by running the ./DESim.sh script. As shown in Figure 5, this can be done by:
1. Opening a terminal window using keys Ctrl + Alt + T
2. Navigating to the newly create directory: ‘cd ∼/DESim’
3. Executing the shell script: ‘./DESim.sh’
Figure 5. Starting the DESim application under Linux.
2.3
Enviroment configuration
The DESim software requires that the simulation software’s executables are in your PATH environment variable. Additionally, some versions of the simulation software require a license file. If the installed simulation software on your
computer does require a license file, the path to license file must be properly specified by an LM_LICENSE_FILE
environment variable. If these environment variables are not set correctly on your computer, appropriate values can
be supplied as command-line arguments to the DESim software. To add these command-line arguments, modify the
DESim.bat (Windows) or DESim.sh (Linux) as described in those files.
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For Quartus® Prime 21.1
Running DESim
You should now see the DESim graphical user interface (GUI), illustrated in Figure 6. It should show the message
“The server is running...” near the top of the message pane in the GUI.
Figure 6. The DESim window.
To ensure that the DESim application can communicate with the ModelSim simulator, you may wish to try out one
(or more) of the demo projects that come with DESim. As an example, click the Open Project button in the
DESim GUI and then navigate into the demos folder. Next, click to select the appropriate folder, either modelsim
or questa, depending on which simulation software is installed. Then, click to select either the verilog or vhdl
folder for examples written in your preferred hardware description language (HDL). In Windows, click to select the
folder named LED_HEX and then click the Select Folder button, as illustrated in Figure 7. In Linux, navigate
to the folder named LED_HEX and then click the Open button, as illustrated in Figure 8. In the example, we have
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chosen the Questa simulator and the Verilog HDL. The navigation bar in the dialog will look different, if you chosen
other options.
Figure 7. Opening a sample project in the demos folder under Windows.
Click the Compile Testbench button in DESim. As shown in Figure 9, the Questa simulation software is
executed to compile the Verilog code for the sample project, and the compilation messages that are produced by
Questa are displayed in the DESim message pane.
In the DESim window, click the Start Simulation button, which starts the Questa simulation software. As
illustrated in Figure 10, any messages produced by Questa are displayed in the message pane of the DESim window.
To make your display look like the one in the figure, in the DESim GUI click on the Switch with index number
6, which causes the corresponding LED to turn red. To activate the Seven-segment Display output you have
to reset the LED_HEX circuit. To do this, click on Push Button 0 to press it, and then click again to release
this button. To learn about the features of the LED_HEX project, you can follow the instructions in its Readme.txt
file, shown in Figure 11, and/or read through the HDL file. The Verilog source-code file LED_HEX.v is displayed
in Figure 12. The VHDL source-code file LED_HEX.vhd is displayed in Figure 13. Each example included with
DESim has its own Readme.txt file and HDL files, which can be read to learn more about them.
You can stop the simulation by clicking the Stop Simulation button in the DESim GUI. To close the DESim
program click the × in the upper-right corner of the window.
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Figure 8. Opening a sample project in the demos folder under Linux.
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Figure 9. Compiling the sample project.
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Figure 10. Simulating the sample project.
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The KEYs and SW are used to change the HEX displays.
In this demo:
-- SW are displayed on LEDR
-- KEY[0] is the synchronous reset. It sets the HEX-display selector to 0.
-- KEY[1] provides the active-low enable for the HEX-display selector
To use:
1. First press/release KEY[0] to reset the circuit; HEX0 is selected
-- HEX0 can be changed using SW[6:0]
2. Set SW[9:7] to select a different HEX display (from 0 to 5)
-- press/release KEY[1] to store the selected HEX address
-- the selected HEX display can now be changed using SW[6:0]
3. Set SW[9:7] to select another display, etc.
Figure 11. The Readme.txt file for the LED_HEX project.
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module LED_HEX (CLOCK, KEY, SW, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
LEDR);
input wire
CLOCK;
input wire [ 1: 0] KEY;
input wire [ 9: 0] SW;
output reg [ 6: 0] HEX0;
output reg [ 6: 0] HEX1;
output reg [ 6: 0] HEX2;
output reg [ 6: 0] HEX3;
output reg [ 6: 0] HEX4;
output reg [ 6: 0] HEX5;
output wire [ 9: 0] LEDR;
reg
[ 2: 0] addr;
// used to select a HEX display
assign LEDR = SW;
always @ (posedge CLOCK)
if (KEY[0] == 0)
addr <= 3’b0;
else if (KEY[1] == 0)
addr <= SW[9:7];
always @ (posedge CLOCK)
case (addr)
3’b000: HEX0 <=
3’b001: HEX1 <=
3’b010: HEX2 <=
3’b011: HEX3 <=
3’b100: HEX4 <=
3’b101: HEX5 <=
default: ;
endcase
// sync reset
// select a HEX display
SW[6:0];
SW[6:0];
SW[6:0];
SW[6:0];
SW[6:0];
SW[6:0];
endmodule
Figure 12. The Verilog source-code file LED_HEX.v.
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ENTITY LED_HEX
PORT (
CLOCK
KEY
SW
HEX0
HEX1
HEX2
HEX3
HEX4
HEX5
LEDR
);
END LED_HEX;
For Quartus® Prime 21.1
IS
:
:
:
:
:
:
:
:
:
:
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
STD_LOGIC;
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
STD_LOGIC_VECTOR(
1
9
6
6
6
6
6
6
9
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
0);
0);
0);
0);
0);
0);
0);
0);
0)
ARCHITECTURE Behavior OF LED_HEX IS
SIGNAL addr : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
LEDR <= SW;
PROCESS (CLOCK)
BEGIN
IF (CLOCK’EVENT AND CLOCK = ’1’) THEN
IF (KEY(0) = ’0’) THEN
addr <= (OTHERS => ’0’);
ELSIF (KEY(1) = ’0’) THEN
addr <= SW(9 DOWNTO 7);
END IF;
END IF;
END PROCESS;
PROCESS (CLOCK)
BEGIN
IF (CLOCK’EVENT AND
CASE addr IS
WHEN "000"
WHEN "001"
WHEN "010"
WHEN "011"
WHEN "100"
WHEN "101"
WHEN OTHERS
END CASE;
END IF;
END PROCESS;
CLOCK = ’1’) THEN
=>
=>
=>
=>
=>
=>
=>
HEX0 <=
HEX1 <=
HEX2 <=
HEX3 <=
HEX4 <=
HEX5 <=
NULL;
SW(6
SW(6
SW(6
SW(6
SW(6
SW(6
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO
0);
0);
0);
0);
0);
0);
END Behavior;
Figure 13. The VHDL source-code file LED_HEX.vhd.
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