EEE 303 – Digital Electronics
EEE
ALU Design
303
Lecture 05.1
Dr. Sajid Muhaimin Choudhury, Assistant Professor
Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
EEE 303 – Digital Electronics
Adder Design
Dr. Sajid Muhaimin Choudhury, Assistant Professor
Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
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Addition of Unsigned Numbers
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 3
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Half Adder
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Dr. Sajid Muhaimin Choudhury 4
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Half Adder Circuit Symbol
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 5
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EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 6
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Full Adder
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 7
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EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 8
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Adder
2
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Full Adder with 2 cascaded half adders
Half
Cascading 2 Half -Adders
Full Adder
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 9
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EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 10
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Full Adder – Logic Diagram
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 11
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EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 12
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N-bit Ripple Carry Adder
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 13
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N-bit Ripple Carry Adder
• Chain 1-bit adders together
• Carry ripples through entire chain
• Disadvantage: slow
tripple = NtFA
where tFA is the delay of a 1-bit full adder
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 14
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Each
0 carry calculation needs 2 cascaded gates.
2 delay for each gate Δt
Gate
3
Performance Issue
•
•
• Final result of the addition will be valid after a delay of nΔt,
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 15
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Carry Mechanism
Carry Generate:
Only if A and B both are 1
G = A.B
Carry Propagate
Either A or B is 1
P = A+B
The technique can be exploited to predict carry a priori
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 16
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Each
0 carry calculation needs 2 cascaded gates.
2 delay for each gate Δt
Gate
3
Performance Issue
•
•
• Final result of the addition will be valid after a delay of nΔt,
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 17
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Mitigation: Carry Lookahead Adder
Compute Cout for k-bit blocks using generate and
propagate signals
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 18
Carry-Lookahead Adder
Compute Cout for k-bit blocks using generate and propagate signals
Some definitions:
– Column i produces a carry out by either generating a carry out or propagating a carry
in to the carry out
– Generate (Gi) and propagate (Pi) signals for each column:
• Generate: Column i will generate a carry out if Ai and Bi are both 1.
G i = Ai Bi
• Propagate: Column i will propagate a carry in to the carry out if Ai or Bi is 1.
Pi = Ai + Bi
• Carry out: The carry out of column i (Ci) is:
Ci = Ai Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 19
Propagate and Generate Signals
Examples: Column propagate and generate signals:
Column propagate:
Column generate:
Pi = Ai + Bi
Gi = Ai Bi
Ci = Gi + Pi Ci-1
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 20
Block
Propagate
and
Generate
Block Propagate and Generate
Now use column Propagate and Generate
signals to compute Block Propagate and
Block Generate signals for k-bit blocks, i.e.:
• Compute if a k-bit group will propagate a carry in (of the
block) to the carry out (of the block)
• Compute if a k-bit group will generate a carry out (of the
block)
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 21
Block Propagate and Generate Signals
• Example: 4-bit blocks
• Block propagate signal: P3:0 (single-bit signal)
• A carry-in would propagate through all 4 bits of the block:
P3:0 = P3P2 P1P0
• Examples:
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 22
Block Propagate and Generate Signals
• Example: 4-bit blocks
• Block propagate signal: P3:0 (single-bit signal)
• A carry-in would propagate through all 4 bits of the block:
P3:0 = P3P2 P1P0
• Block generate signal: G3:0 (single-bit signal)
• A carry is generated:
• in column 3, or
• in column 2 and propagated through column 3, or
• in column 1 and propagated through columns 2 and 3, or
• in column 0 and propagated through columns 1-3
G3:0 = G3 + G2P3 + G1P2P3 + G0P1P2P3
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 23
Block Propagate and Generate Signals
• Example: 4-bit blocks
• Block propagate signal: P3:0 (single-bit signal)
• A carry-in would propagate through all 4 bits of the block:
P3:0 = P3P2 P1P0
• Block generate signal: G3:0 (single-bit signal)
• A carry is generated:
• in column 3, or
• in column 2 and propagated through column 3, or ...
G3:0 = G3 + G2P3 + G1P2P3 + G0P1P2P3
G3:0 = G3 + P3 [G2 + P2 (G1 + P1G0 )]
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 24
Block
Generate
Signal
Examples
Block Generate Signal Examples
• Example: 4-bit blocks
• Block generate signal: G3:0 (single-bit signal)
• A carry is: generated in column 3, or generated in column 2 and
propagated through column 3, or ...
G3:0 = G3 + G2P3 + G1P2P3 + G0P1P2P3
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 25
Block Propagate and Generate Signals
• Example: 4-bit blocks
• Block propagate signal: P3:0 (single-bit signal)
• A carry-in would propagate through all 4 bits of the block:
P3:0 = P3P2 P1P0
• Block generate signal: G3:0 (single-bit signal)
• A carry is generated:
• in column 3, or
• in column 2 and propagated through column 3, or …
G3:0 = G3 + G2P3 + G1P2P3 + G0P1P2P3
G3:0 = G3 + P3 [G2 + P2 (G1 + P1G0 )]
C3 = G3:0 + P3:0 C-1
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 26
Block Propagate and Generate Signals
• Example: Block propagate and generate
signals for 4-bit blocks (P3:0 and G3:0):
P3:0 = P3P2 P1P0
G3:0 = G3 + P3 (G2 + P2 (G1 + P1G0 )
C3 = G3:0 + P3:0 C-1
• Generally,
Pi:j = PiPi-1 Pi-2Pj
Gi:j = Gi + Pi (Gi-1 + Pi-1 (Gi-2 + Pi-2Gj )
Ci = Gi:j + Pi:j Cj-1
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 27
32-bit CLA with 4-bit Blocks
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 28
Carry-Lookahead Addition
• Step 1: Compute Gi and Pi for all columns
• Step 2: Compute G and P for k-bit blocks
• Step 3: Cin propagates through each k-bit
propagate/generate logic (meanwhile computing sums)
• Step 4: Compute sum for most significant k-bit block
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 29
Carry-Lookahead Addition
• Step 1: Compute Gi and Pi for all columns
G i = Ai Bi
Pi = Ai + Bi
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 30
Carry-Lookahead Addition
• Step 1: Compute Gi and Pi for all columns
• Step 2: Compute G and P for k-bit blocks
P3:0 = P3P2 P1P0
G3:0 = G3 + P3 (G2 + P2 (G1 + P1G0 )
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 31
Carry-Lookahead Addition
• Step 1: Compute Gi and Pi for all columns
• Step 2: Compute G and P for k-bit blocks
• Step 3: Cin propagates through each k-bit
propagate/generate logic (meanwhile computing sums
B31:28 A31:28
Cout
EEE 303 – Digital Electronics
Department of EEE, BUET
B7:4 A7:4
4-bit CLA C27 4-bit CLA C23
Block
Block
S31:28
Cout
B27:24 A27:24
B3 A3 B2 A2 B1 A1 B0 A0
C
C
C
+ 2 + 1 + 0 + Cin
S3
S2
S1
S0
G3:0
G3
P3
G2
P2
G1
P1
G0
P3
P3:0
P2
P1
Cin
P0
C7 4-bit CLA C3 4-bit CLA
Block
Block
S27:24
Cout
B3:0 A3:0
S7:4
B3 A3 B2 A2 B1 A1 B0 A0
C
C
C
+ 2 + 1 + 0 + Cin
S3
S2
S1
S0
G3:0
G3
P3
G2
P
G21
P1
G0
P3
P3:0
P2
P1
Cin
P0
Cout
B3 A3 B2 A2 B1 A1 B0 A0
C
C
C
+ 2 + 1 + 0 + Cin
S3
S2
S1
S0
G3:0
G3
P3
G2
P2
G1
P1
G0
P3
P3:0
P2
P1
Cin
P0
Cin
S3:0
Cout
B3 A3 B2 A2 B1 A1 B0 A0
C
C
C
+ 2 + 1 + 0 + Cin
S3
S2
S1
S0
G3:0
G3
P3
G2
P2
G1
P1
G0
P3
P3:0
P2
P
Cin
P1
0
Dr. Sajid Muhaimin Choudhury 32
Carry-Lookahead Addition
• Step 1: Compute Gi and Pi for all columns
• Step 2: Compute G and P for k-bit blocks
• Step 3: Cin propagates through each k-bit
propagate/generate logic (meanwhile computing sums)
• Step 4: Compute sum for most significant k-bit block
Cout
EEE 303 – Digital Electronics
Department of EEE, BUET
B3 A3 B2 A2 B1 A1 B0 A0
C
C
C
+ 2 + 1 + 0 + Cin
S3
S2
S1
S0
G3:0
G3
P3
G2
P2
G1
P1
G0
P3
P3:0
P2
P1
Cin
P0
Cout
B3 A3 B2 A2 B1 A1 B0 A0
C
C
C
+ 2 + 1 + 0 + Cin
S3
S2
S1
S0
G3:0
G3
P3
G2
P
G2
1
P1
G0
P
3
P3:0
P2
P1
Cin
P0
Cout
B3 A3 B2 A2 B1 A1 B0 A0
C
C
C
+ 2 + 1 + 0 + Cin
S3
S2
S1
S0
G3:0
G3
P3
G2
P2
G1
P1
G0
P3
P3:0
P2
P1
Cin
P0
Cout
B3 A3 B2 A2 B1 A1 B0 A0
C
C
C
+ 2 + 1 + 0 + Cin
S3
S2
S1
S0
G3:0
G3
P3
G2
P2
G1
P1
G0
P3
P3:0
P2
P
Cin
P1
0
Dr. Sajid Muhaimin Choudhury 33
Carry-Lookahead Addition
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 34
Carry-Lookahead Adder Delay
For N-bit CLA with k-bit blocks:
tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA
– tpg :
delay to generate all Pi, Gi
– tpg_block : delay to generate all Pi:j, Gi:j
– tAND_OR : delay from Cin to Cout of final AND/OR gate in k-bit CLA
block
An N-bit carry-lookahead adder is generally much faster than
a ripple-carry adder for N > 16
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 35
Adder Delay
Comparisons
Adder
Delay Comparisons
Compare delay of: 32-bit ripple-carry, CLA,
• CLA has 4-bit blocks
• 2-input gate delay = 100 ps; full adder delay = 300 ps
tripple = NtFA = 32(300 ps)
= 9.6 ns
tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA
= [100 + 600 + (7)200 + 4(300)] ps
= 3.3 ns
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 36
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Budget: Performance vs Cost
• Ripple Carry adder:
Simpler, Lower Number of transistors, Slow Speed
• Fast Adder:
Complex, Higher Number of Transistors, Fast
• As a designer, you need to choose the appropriate
solution! Performance vs Budget
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 37
EEE 303 – Digital Electronics
Arithmetic Overflow
Dr. Sajid Muhaimin Choudhury, Assistant Professor
Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
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Recall: Signed numbers
EEE 303 – Digital Electronics
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Dr. Sajid Muhaimin Choudhury 39
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Arithmetic Overflow
• If n bits are used to represent signed numbers, then the
result must be in the range −2n−1 to 2n−1 − 1.
• If the result does not fit in this range, then we say that
arithmetic overflow has occurred.
• To ensure the correct operation of an arithmetic circuit, it
is important to be able to detect the occurrence of
overflow.
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 40
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Example of Overflow – 4 bit addition
EEE 303 – Digital Electronics
Department of EEE, BUET
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EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 42
EEE 303 – Digital Electronics
EEE
303
ALU Design: Verilog
Implementations for
Adders, Subtractor
Lecture 05.2
Dr. Sajid Muhaimin Choudhury, Assistant Professor
Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
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4 Bit Adder – with 7483 / 74283 Integrated Circuit
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 44
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8 Bit Adder – with 7483 / 74283 Integrated Circuit
A7A6 A5A4A3A2 A1A0
B7B6 B5B4B3B2 B1B0
S8S7S6 S5S4S3S2 S1S0
A0
A1
A2
A3
B0
B1
B2
B3
S0
S1
S2
S3
A4
A5
A6
A7
B4
B5
B6
B7
S4
S5
S6
S7
S8
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 45
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Verilog Implementation of Full Adder
EEE 303 – Digital Electronics
Department of EEE, BUET
module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;
xor (s, x, y, Cin); xor e 3 ta input
and (z1, x, y);
and (z2, x, Cin);
and (z3, y, Cin);
or (Cout, z1, z2, z3);
endmodule
Dr. Sajid Muhaimin Choudhury 46
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Verilog Implementation of Full Adder
EEE 303 – Digital Electronics
Department of EEE, BUET
module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;
assign s = x^y^Cin;
assign Cout=(x&y)|(x&Cin)|(y&Cin);
endmodule
Dr. Sajid Muhaimin Choudhury 47
Simplified Implementation of Full Adder with
Arithmetic Assignment
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 48
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4-Bit Adder with Cascading Full Adders
module adder4 (carryin, x3, x2, x1, x0, y3, y2, y1, y0, s3, s2, s1, s0,
carryout);
input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
output s3, s2, s1, s0, carryout;
fulladd stage0 (carryin, x0, y0, s0, c1);
fulladd stage1 (c1, x1, y1, s1, c2);
fulladd stage2 (c2, x2, y2, s2, c3);
fulladd stage3 (c3, x3, y3, s3, carryout);
endmodule
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 49
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module
adder4 (carryin,
2
input0 carryin;
input23 [3:0] X, Y;
Verilog Implementation of Full Adder with Vectors
X, Y, S, carryout);
output [3:0] S;
output carryout;
wire [3:1] C;
fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]);
fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]);
fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]);
fulladd stage3 (C[3], X[3], Y[3], S[3], carryout);
endmodule
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 50
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/
module
addern (carryin,
2
parameter
n = 32;
0
input2 carryin;
3
N-bit Ripple Carry Adder
X, Y, S, carryout);
input [n– 1:0] X, Y;
output reg [n –1:0] S;
output reg carryout;
reg [n:0] C;
integer k;
always @(X, Y, carryin) begin
C[0] = carryin;
for(k=0;k< n;k=k+1) begin
S[k] = X[k] Y[k] C[k];
C[k+1] = (X[k] & Y[k]) (X[k] & C[k]) (Y[k] & C[k]);
end
carryout = C[n];
EEE 303 – Digital Electronics
end
endmodule
Department
of EEE, BUET
Dr. Sajid Muhaimin Choudhury 51
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2
module
addern (carryin,
0
2
parameter
n = 32;
3
N-bit adder with arithmetic assignment
X, Y, S);
input carryin;
input [n –1:0] X, Y;
output reg [n –1:0] S;
always @(X, Y, carryin)
S = X + Y + carryin;
endmodule
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 52
The generate Keyword in Verilog
❖ Generates sub-circuits using a loop
❖If a for loop is included in the generate block, the loop index
variable has to be declared of type genvar.
❖ A genvar variable is similar to an integer variable, but
i. it
can have only positive values
ii. it
can be used only inside generate blocks
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 53
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1
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8
/ addern (carryin, X, Y, S, carryout);
module
2
parameter n = 32;
0
input 2carryin;
input 3[n –1:0] X, Y;
N-bit Ripple Carry Adder with generate
eki sathe always ar assign use kora jai kintu always er vitore assign
likha jai na
output [n –1:0] S;
output carryout;
wire [n:0] C;
genvar i;
assign C[0] = carryin;
assign carryout = C[n];
generate
i++ kintu nai
for (i = 0; i < = n –1; i = i+1)
stage
begin:addbit
module ke loop e call korte generate lage
fulladd stage (C[i], X[i], Y[i], S[i], C[i+1]);
end
always er vitore for loop use korle genvar lage na
endgenerate
stage gullar nam== addbit[i].stage
endmodule
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 54
55
Recall: Overflow Checking
EEE 303 – Digital Electronics
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Dr. Sajid Muhaimin Choudhury 55
N-bit adder with overflow check
S omits the MSB
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 56
N-bit adder with overflow check – Extra Memory
Sum requires extra
memory to implement
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 57
Simplified n-bit Adder with Overflow Check
EEE 303 – Digital Electronics
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Dr. Sajid Muhaimin Choudhury 58
EEE 303 – Digital Electronics
Subtraction
Dr. Sajid Muhaimin Choudhury, Assistant Professor
Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
“Taking
the
Two’s
Recall: 2’s Complement
Complement”
• Flips the
sign of a two’s complement number.
•
Method:
1. Invert the bits
2. Add 1
•
(1’s Complement)
(2’s Complement)
Example: Flip the sign of 310 = 00112
1.
2.
1100
+ 1
1101 = -310
Add 6 + (-6) using two’s complement numbers
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 60
“Taking
the
Two’s
Recall: 2’s Complement
Complement”
• Flips the
sign of a two’s complement number.
•
Method:
1. Invert the bits -> Subtract each digit from 1
2. Add 1
•
(1’s Complement)
(2’s Complement)
Example: Flip the sign of 310 = 00112
1.
2.
1100
+ 1
1101 = -310
Add 6 + (-6) using two’s complement numbers
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 61
“Taking
the
Two’s
Radix Complement
Complement”
• Flips the
sign of a N’s complement number in Base-N
•
Method:
1. Subtract Each Digit from (N-1)
2. Add 1
EEE 303 – Digital Electronics
Department of EEE, BUET
(N-1)’s complement
N’s complement
Dr. Sajid Muhaimin Choudhury 62
“Taking
the
Two’s
10’s Complement
Complement”
• Flips the
sign of a 10’s complement number in Base-10.
•
Method:
1. Subtract Each Digit from 9
2. Add 1
•
9’s complement
10’s complement
Example: Flip the sign of 8210 in 10’s Complement
1.
2.
(9-8) (9-2) = (99-82) = 17
+ 1
18
EEE 303 – Digital Electronics
Department of EEE, BUET
9’s complement
10’s complement
Dr. Sajid Muhaimin Choudhury 63
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2
3
2’s complement
• For an n-digit decimal number,
• 2’s
complement:
• 1’s
complement:
• A-B:
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 64
65
1
/
8
/
2
0
2
3
10’s complement
• For an n-digit decimal number,
• 10’s
• 9’s
complement:
complement:
• A-B:
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 65
66
1
/
8
/
2
0
2
3
Understanding 10’s Complement
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 66
67
1
/
8
/
2
0
2
3
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 67
68
1
/
8
/
2
0
2
3
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 68
69
1
/
8
/
2
0
2
A3
Cascading
• If ≥ B, then the operation A + (10n − B) produces a carry-out of 1. This
carry is equivalent to 10n; hence it can be simply ignored.
• If A < B, then the operation
A + (10n − B) produces a carry-out of 0. Let the result obtained be M , so
that A − B = M − 10n
• Or 10n −(B−A)=M, so M is a 10’s complement of (B-A)
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 69
70
1
/
8
/
2
0
2
3
N-bit Subtractor with Adder
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 70
Subtracter
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 71
Comparator: Equality
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 72
Comparator: Less Than
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 73
73
74
1
/
8
/
2
0
2
3
Comparator
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 74
7
5
EEE 303 – Digital Electronics
EEE
303
ALU Design:
ALU, Multiplication,
Division, BCD
Lecture 05.3
Dr. Sajid Muhaimin Choudhury, Assistant Professor
Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
ALU: Arithmetic Logic Unit
ALU should perform:
• Addition
• Subtraction
• AND
• OR
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 76
ALU: Arithmetic Logic Unit
ALUControl1:0 Function
00
Add
01
Subtract
10
AND
11
OR
Example: Perform A + B
ALUControl = 00
Result = A + B
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 77
ALU: Arithmetic Logic Unit
ALUControl1:0 Function
00
Add
01
Subtract
10
AND
11
OR
Example: Perform A OR B
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 78
ALU: Arithmetic Logic Unit
ALUControl1:0 Function
00
Add
01
Subtract
10
AND
11
OR
Example: Perform A OR B
ALUControl1:0 = 11
Mux selects output of OR gate as Result, so
Result = A OR B
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 79
ALU: Arithmetic Logic Unit
ALUControl1:0 Function
00
Add
01
Subtract
10
AND
11
OR
Example: Perform A + B
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 80
ALU: Arithmetic Logic Unit
ALUControl1:0 Function
00
Add
01
Subtract
10
AND
11
OR
Example: Perform A + B
ALUControl1:0 = 00
ALUControl0 = 0, so:
Cin to adder = 0
2nd input to adder is B
Mux selects Sum as Result, so
Result = A + B
EEE 303 – Digital Electronics
Department of EEE, BUET
MSB 0 hole arithmatic
1 hole logic operation
eivabe dorse
Carry in 0 deya lagbe jog
er jonno
biog er jonno
1's complement er sathe 1
jog hiobe
Dr. Sajid Muhaimin Choudhury 81
ALU with Status Flags
Flag Description
N
Result is Negative
Z
Result is Zero
C
Adder produces Carry
out
V
Adder oVerflowed
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 82
ALU with Status Flags
ALU control[1] = 0 hole to jog biog
tai invert kore nise
overflow , carryout ei kotha gulan to sudu jog biog er jonno valid
bakita calculation
result negative naki zero? N Z flag
jeita Cout oitai toh carry
jog er khetre overflow::::: not(0 xor A xor B)
*
(AxorS)
biog er khetre over flow:::: not(1xorA xor B) * Axor S
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 83
ALU with Status Flags: Negative
N = 1 if:
Result is negative
So, N is connected to
most significant bit of
Result
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 84
ALU with Status Flags: Zero
Z = 1 if:
all of the bits of
Result are 0
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 85
ALU with Status Flags: Carry
C = 1 if:
Cout of Adder is 1
AND
ALU is adding or
subtracting
(ALUControl is 00 or
01)
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 86
ALU with Status Flags: oVerflow
V = 1 if:
The addition of 2
same-signed
numbers produces a
result with the
opposite sign
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 87
ALU with Status Flags: oVerflow
V = 1 if:
ALU is performing addition or subtraction
(ALUControl1 = 0)
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 88
ALU with Status Flags: oVerflow
V = 1 if:
ALU is performing addition or subtraction
(ALUControl1 = 0)
AND
A and Sum have opposite signs
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 89
ALU with Status Flags: oVerflow
V = 1 if:
ALU is performing addition or subtraction
(ALUControl1 = 0)
AND
A and Sum have opposite signs
AND
A and B have same signs upon addition
OR
A and B have different signs upon
subtraction
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 90
ALU with Status Flags: oVerflow
V = 1 if:
ALU is performing addition or subtraction
(ALUControl1 = 0)
AND
A and Sum have opposite signs
AND
A and B have same signs upon addition
(ALUControl0 = 0)
OR
A and B have different signs upon
subtraction
(ALUControl0 = 1)
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 91
ALU with Status Flags
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 92
Shifters
Logical shifter: shifts value to left or right and fills empty spaces with 0’s
•
•
Ex: 11001 >> 2 =
Ex: 11001 << 2 =
Arithmetic shifter: same as logical shifter, but on right shift, fills empty spaces with the old
most significant bit (msb)
•
•
Ex: 11001 >>> 2 =
Ex: 11001 <<< 2 =
Rotator: rotates bits in a circle, such that bits shifted off one end are shifted into the other end
•
•
Ex: 11001 ROR 2 =
Ex: 11001 ROL 2 =
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 93
93
Shifters
Logical shifter:
•
•
Ex: 11001 >> 2 = 00110
Ex: 11001 << 2 = 00100
register e jemon shift hoi
Arithmetic shifter:
•
•
Ex: 11001 >>> 2 = 11110
Ex: 11001 <<< 2 = 00100
right shift korle bame 1 add hote thakbe
leftshift normal
Rotator:
•
•
Ex: 11001 ROR 2 = 01110
Ex: 11001 ROL 2 = 00111
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 94
Shifter Design
simple logical right shift
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 95
Multiplication by 2n
• 11011 x 100 = 1101100
• Multiplying with 4 will just increase the number of zeros in
the LSB. This can be implemented with right shifting the
number 2 bits.
• Multiplying with any 2n number will just shift the number n
bits to left.
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 96
Shifters as Multipliers, Dividers
• A << N = A × 2N
• Example:
• Example:
00001 << 2 = 00100 (1 × 22 = 4)
11101 << 2 = 10100 (-3 × 22 = -12)
• A >>> N = A ÷ 2N
• Example:
• Example:
01000 >>> 2 = 00010 (8 ÷ 22 = 2)
10000 >>> 2 = 11100 (-16 ÷ 22 = -4)
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 97
Multipliers
• Partial products formed by multiplying a single digit of the
multiplier with multiplicand
• Shifted partial products summed to form result
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 98
4 x 4 Multiplier
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 99
Dividers
A/B = Q + R/B
Decimal Example: 2584/15 = 172 R4
Long-Hand Revisited:
Long-Hand:
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 100
Dividers
A/B = Q + R/B
Binary: 1101/0010 = 0110 R1
Decimal: 2584/15 = 172 R4
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 101
Divider Algorithm
A/B = Q + R/B
Binary: 1101/10 = 0110 R1
R’ = 0
for i = N-1 to 0
R = {R’ << 1, Ai}
D=R-B
if D < 0, Qi= 0; R’= R
else
Qi= 1; R’= D
R=R’
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 102
4 x 4 Divider
Each row computes one iteration of the division algorithm.
EEE 303 – Digital Electronics
Department of EEE, BUET
Division: A/B = Q + R/B
R’ = 0
for i = N-1 to 0
R = {R’ << 1, Ai}
D=R-B
if D < 0, Qi=0, R’=R
else
Qi=1, R’=D
R=R’
Dr. Sajid Muhaimin Choudhury 103
4 x 4 Divider
Each row computes one iteration of the division algorithm.
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 104
1
/0
5
8
/
2
0
2
3
Design a circuit to multiply a number by 3
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 105
1
/0
6
8
/
2
0
2
3
Design a circuit to multiply a number by 3
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 106
EEE 303 – Digital Electronics
Binary Coded
Decimal computation
107
Dr. Sajid Muhaimin Choudhury, Assistant Professor
Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
BCD Number conversion
• Convert a Binary Number to BCD:
• Rigorous Method:
– Find Truth Table
– Simplify Logic
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 108
BCD Conversion: Truth Table & SOP
Binary Code
Decimal
Number
ABCD
BCD Code
B4 :B3 B2 B1 B0
0000
0
0:0000
0001
1
0:0001
0010
2
0:0010
0011
3
0:0011
0100
4
0:0100
0101
5
0:0101
0110
6
0:0110
0111
7
0:0111
1000
8
0:1000
1001
9
0:1001
1010
10
1:0000
1011
11
1:0001
1100
12
1:0010
1101
13
1:0011
1110
14
1:0100
1111
15
1:0101
EEE 303 – Digital Electronics
Department of EEE, BUET
https://www.javatpoint.com/binary-to-bcd-conversion-in-digital-electronics
Dr. Sajid Muhaimin Choudhury 109
BCD Conversion: Truth Table & SOP
EEE 303 – Digital Electronics
Dr. Sajid Muhaimin Choudhury 110
Department of EEE, BUET
https://www.javatpoint.com/binary-to-bcd-conversion-in-digital-electronics
BCD Number conversion
• Convert a Binary Number to BCD:
• Rigorous Method:
– Find Truth Table
– Simplify Logic
•
Observation:
Add 6 to a 4 bit binary
number to get its BCD
EEE 303 – Digital Electronics
Department of EEE, BUET
Binary Code
Decimal
Number
ABCD
BCD Code
B4 :B3 B2 B1 B0
0000
0
0:0000
0001
1
0:0001
0010
2
0:0010
0011
3
0:0011
0100
4
0:0100
0101
5
0:0101
0110
6
0:0110
0111
7
0:0111
1000
8
0:1000
1001
9
0:1001
1010
10
1:0000
1011
11
1:0001
1100
12
1:0010
1101
13
1:0011
1110
14
1:0100
1111
15
1:0101
1010+011
0
1011+011
0
Dr. Sajid Muhaimin Choudhury 111
Addition
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 112
Schematic
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 113
Verilog code for BCD addition
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 114
BCD Conversion Compact Circuit
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 115
Verilog code for BCD Addition
EEE 303 – Digital Electronics
Department of EEE, BUET
Dr. Sajid Muhaimin Choudhury 116