Basic Layout Techniques
Rahul Shukla
Advisor: Jaime Ramirez-Angulo
Spring 2005
Mixed Signal VLSI Lab
Klipsch School of Electrical and Computer Engineering
New Mexico State University
Outline
• Transistor layout
• Resistor Layout
• Capacitor Layout
• Common Centroid and Inter-digitization Techniques
• Example layouts
• Pad Frame
Transistor layout
• NMOS
D
G
B
1.5um/0.6um
S
NMOS Bulk terminal in AMI 0.5µm process is
always tied to p substrate which is tied to Vss.
S/D
G
D/S
S
• PMOS
G
B
D
1.5um/0.6um
PMOS Bulk terminal in AMI 0.5µm process is free
(N Well process) and can be connected to any voltage
but usually connected to Vdd or the source ‘S’ terminal.
B
S/D
G
D/S
Transistor layout
• A single large transistor layout is not a good idea !!!
• To make a large transistor we split the large transistors and
connect them in parallel.
G
G
S
D
B
120um/1.8um
S
G
D
B
30um/1.8um
Generally
PMOS width (W) < 50µm/1.8µm
NMOS width (W) < 30µm/1.8µm
G
S
G
D
B
B
30um/1.8um 30um/1.8um
S
B
30um/1.8um
Transistor layout
G
G
D
B
120um/1.8um
S
S/D
D/S
Transistor layout
S
G
G
B
D
150µm/1.05µm
D
S
PMOS Bulk terminal connected to the source ‘S’ terminal
reduce body effect. Four transistor of 37.5µm/1.05µm
connected in parallel
B
Resistor layout
• Resistor value is calculated using R=Rs (L/W) where Rs is sheet
resistance of ELEC layer and its value in AMI 0.5µm process is
1024Ω/‫ ٱ‬L and W are length and width of resistor.
• Resistor is implemented using a POLY2 layer or ELEC as it is
called in Cadence.
• A High-Res layer is also used as a layer ID.
• Use minimum W of ELEC to calculate length of ELEC layer
• Value of W and L calculated using formula is an approximate
value. To get a value close enough to desired value, layout the
resistor, extract the layout using the extractor tool in Cadence and
and see the value in extracted view of your cell and change the size
of the resistor in layout view to get to a desired value. This, as we
can see is an iterative process.
Resistor layout
• Example 5kΩ resistor layout.
L
W
ELEC
M1_ELEC
Contact
• Extracted view of the resistor
Highres
Resistor layout
• For laying out a big resistor it is recommended to split it into
series connection of small resistors.
E.g.: 25kΩ using five 5kΩ resistor layout. (note the 25kΩ is not
a large value resistor)
Capacitor layout
• Capacitor value is calculated using R=Cox W.L where Cox is
capacitance of oxide layer per unit area. Its value in AMI 0.5µm
process is 2.4fF/µm2, L and W are length and width of capacitor.
• A parallel plate Capacitor is implemented using a POLY2 layer or
ELEC as it is called in Cadence and POLY layer. The two layer act
act as the parallel plate.
• A cap-id layer can also be used as a layer ID.
• Use minimum W=L so that a square capacitor implementation is
possible.
• Value of W and L calculated using formula is an approximate value.
To get a value close enough to desired value, layout the capacitor,
extract the layout using the extractor tool in Cadence and see the
value in extracted view of your cell and accordingly change the size
of the capacitor in layout to get to a desired value. This, as we can
see is an iterative process.
Capacitor layout
• Example 1pF capacitor layout.
M1_ELEC
contact
ELEC
POLY
M1_POLY
contact
Cross section
Oxide layer
Common Centroid and Interdigitization Techniques
• Process variations during fabrication may limit accuracy and
desired performance of analog circuits.
• Matching between components in layout of analog circuits is an
important issue in many designs. For e.g. current mirrors,
differential pairs.
• Inter-digitization and common centroid are the most basic
techniques to match components in layouts. [1]
[1] “CMOS Circuit design, layout and simulation,” R. Jacob Baker,
Harry W. Li and David E. Boyce, chapter 20 and 24, IEEE press. 1998
Common Centroid and Interdigitization Techniques
• A simple example of how process variation affects circuit performance
Iin
Iout
Assuming that we split M2 in 4 equal sized transistor and
do the layout in following fashion. If process was ideal
(W/L)M2= 4(W/L)M1
G
G
S
W/L M1
M2 4W/L
D
Practically Iout= 4.1Iin
(neglecting 2 order effects)
D
G
S
G
D
S
S
B
W/L M1
Ideally Iout= 4Iin
(neglecting 2 order effects)
G
W/L M21
W/L M22
W/L M23
W/L M24
Since the process is non-ideal we assume a linear variation
along horizontal axis for example a 1% increase in W/L
ratio of each transistor as we go along left to right.
G
G
S
D
B
W/L M1
G
D
G
S
S
1.01W/L M21 1.02W/L M22 1.03W/L M23
G
D
S
1.04W/L M24
Common Centroid and Interdigitization Techniques
• Process variations do not only affect
W/L ratio (aspect ratio) but also
other variation like Vt i.e. threshold
voltage etc.
• Mismatch in a simple differential
amplifier will lead to undesirable
effects like offset, poor CMRR etc.
Vdd
Vbias
Vin+
VinM3
M1
Differential pair
•
Mirror
M4
Vout
Matching important between
•
M5
M2
Differential Amplifier
Common Centroid and Interdigitization Techniques
We have to match two components A and B ( A and B can be
anything like capacitor, resistor or transistor). Lets split A and B
into 4 small components i.e. A1-A4 and B1-B4.
•Inter-digitization Technique: Placing alternate components
A1
B1
A2
A3
B2
B3
A4
B4
• Common centroid Technique: Placing components such that both
components have same centroid.
A1
B1
B2
Both A and B have common
center
A2
.
A3
B3
B4
A4
Example of common centroid technique (Matching between M3 and
M4 of differential amplifier). (W/L)M3= (W/L)M4
M3
M4
M4
M3
M3
M4
M4
M3
Another example of common centroid technique (W/L)M1= 2(W/L)M2
M1
M2
M1 M1
M2
M1
An alternative approach of M1 M1 M2 M2 M1 M1 can also be used !!!
Another example of common centroid technique for matching in
capacitor array at the input stage of a DAC.
C
2C
4C
8C
16C
Poly serves as the
common bottom plate
Dummy capacitors
Done by Milind Sawant for input stage of a DAC
Example layouts
Use NTAP contact around transistors and try to use M2 for horizontal connections and M3
for vertical connections or vice versa.
Example layouts
Pad Frame
• 40 PINS
• P pins are protected
pins
• + is VDD pin
• - is VSS pin
• Pins with no names
are bare pins.
• It has a global
guard rings.
Guard rings
Pin # 1
Pin # 40