Index Number:
RAJARATA UNIVERSITY OF SRI LANKA
FACULTY OF TECHNOLOGY
Bachelor of Information Communication Technology
Third Year - Semester II Examination – July 2020
ICT 3209 – COMPUTER ORGANIZATION AND ARCHITECTURE
Time: Two (02) hours
Answer all Questions in Part A in the paper itself.
Answer only three (03) questions from Part B in the answer booklet.
Part A
Underline the most suitable answer for questions 1 to 15
1. The register which holds the address of the location to or from which data be transferred
is called
a)
b)
c)
d)
Index register
Instruction register
Memory address register
Memory data register
2. The register which contains the data to be written into or read out of the addressed
location is called
a)
b)
c)
d)
Memory address register
Memory data register
Program counter
Index register
3. Which of the following is used as storage locations both in the ALU and the control
unit of a computer?
a) Accumulator
Page 1 of 8
b) Register
c) Adder
d) Decoder
4. Which of the following register is used in the control unit of the CPU to indicate the
next instruction which is to be executed?
a)
b)
c)
d)
Accumulator
Index register
Instruction decoder
Program counter
5. The instructions like MOV or ADD are called as ________
a)
b)
c)
d)
OP-Code
Operators
Commands
None of the mentioned
6. The DMA differs from the interrupt mode by __________
a)
b)
c)
d)
The involvement of the processor for the operation
The method of accessing the I/O devices
The amount of data transfer possible
The active intervention of the processor
7. The reason for the implementation of the cache memory is ________
a)
b)
c)
d)
To increase the internal memory of the system
The difference in speeds of operation of the processor and memory
To reduce the memory access and cycle time
All of the mentioned
8. The algorithm to remove and place new contents into the cache is called _______
a)
b)
c)
d)
Replacement algorithm
Renewal algorithm
Updating
None of the mentioned
9. The algorithm which replaces the cache block which has not been referenced for a
while is called _____
a) LRU
b) ORF
Page 2 of 8
c) Direct
d) Both LRU and ORF
10. Which of the following is not an External Interconnection Standard?
a)
b)
c)
d)
USB
Fireware
Thunderbolt
Ethernet
11. Which of the following is not a CPU register?
a)
b)
c)
d)
Stack Pointer
Program Counter
Accumulator
Math Coprocessor
12. In a computer, set of electrical wires that is used to transfer data is called _____
a)
b)
c)
d)
Bus
Interface
Connectors
Ports
13. Which of the following is not a standard RAID level?
a)
b)
c)
d)
RAID 0
RAID 1
RAID 8
RAID 10
14. Which of the following optical disks is capable of rewriting data?
a)
b)
c)
d)
CD
DVD – R
CD – RW
Blue Ray
15. Which of the following technologies uses red laser beams to read and write data?
a) CD
b) DVD
c) Blue Ray
Page 3 of 8
2.
In the class of ________ the relationship between the organization and architecture is so close.
2 points
Mark only one oval.
IAS Computer
Microcomputers
Super Computers
ENIAC
3.
A computer's _________ defines the attributes that have a direct impact on the logical execution of a
program.
Mark only one oval.
design
organization
architecture
processor
2 points
4.
This image shows,
2 points
Mark only one oval.
The Von Neuman Architecture
Micro Architecture
The Harward Architecture
ISA Architecture
5.
The Architectural attributes of a computer include/s,
Check all that apply.
Control signals
Instruction set
the number of bits used to represent various data types
I/O mechanisms
4 points
6.
Choose the correct statement
2 points
Mark only one oval.
PCBs are also known as the motherboards.
Integrated circuits are carriers that are soldered to the PCB.
ICs are more reliable when compared with PCBs.
A PCB is made by integrating the chips.
7.
Referring to a memory location which is out of user's memory space will throw a,
Mark only one oval.
Hardware Failure Interrupt
Program Interrupt
I/O Interrupt
command to restart the machine
2 points
8.
When an interrupt occurs during the instruction cycle,
2 points
Mark only one oval.
the processor will ignore the interrupt and continue the current program.
the execution of the current program is suspended, and its context is saved.
the interrupt will be disabled
9.
When handling multiple interrupts, the most efficient way is to,
Mark only one oval.
process each intterupt on the First Come Fiet Served basis
let the lower-priority interrupt handler to be interrupted by the high priority interrupts.
handle two or more interrupts simultaneously.
none of the above
2 points
10.
This figure shows a situation of,
Mark only one oval.
Multiple Interrupt occurance
Processing multiple interrupts sequencially
Processing multiple interrupts based on priority
A disabling of multiple interrupts
2 points
11.
In the shared bus architecture _____ perform/s bus cycle to fetch the required data or instructions from the
memory.
2 points
Mark only one oval.
1 processor
2 processors
4 processors
more than 4 processors
12.
The register which holds the address of the location to or from which data be transferred is called
Mark only one oval.
Index register
Instruction register
Memory address register
Memory data register
2 points
13.
Which of the following is used as storage locations both in the ALU and the control unit of a computer?
2 points
Mark only one oval.
Register
Adder
Decoder
Accumulator
14.
Which of the following register is used in the control unit of the CPU to indicate the next instruction which
is to be executed?
2 points
Mark only one oval.
Accumulator
Index register
Instruction Decoder
Program Counter
15.
Fill the blanks in the below sentence.
Main memory consists of up to 2^n ____________, with each ______ having a unique ____ -bit address
4 points
16.
The algorithm which replaces the cache block which has not been referenced for a while is called ,
2 points
Mark only one oval.
LRU
LFU
FILO
Random
PART
TWO
17.
You can either write the answers in the provided space OR write the answer in a separate paper/ file and
upload them as the answer to the last question.
The width of the address bus determines the
maximum possible memory capacity of the
system. Explain this claim briefly.
21 points
18.
Briefly explain how the associative mapping works in cache memory.
19.
UPLOAD your file of answers to the PART 2, if you wrote it on a paper or another word/pdf file. Please rename
your file by your registration number.
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