Common Drain Stage
(Source Follower)
Claudio Talarico, Gonzaga University
Common Drain Stage
vgs = vi - vo
vbs = - vo
VDD
RS
vs
VS
VvIN
i
vi
o
vVOUT
IB
RL
CL
G
+
vgs
-
CgdC
+C
gdgb
Cgs
ro
EE 303 – Common Drain Stage
gm vgs
-gmbvo
vo
S
VB
B&D
RL
Csb+CL
2
CD Bias Point
VDD
RS
§ Assume VB=VOUT, so ID=IB
VIN
VOUT = VIN −VGS
VOUT
VS
IB
RL
VB
VGS = VT +
ID
0.5COXW / L
VT = VT 0 + γ
(
PHI +VOUT − PHI
VDS = VDD −VOUT = VDD −VIN +VGS
§ For M1 to be in saturation
VDS > VOV = VGS +VT
!
VDD −VIN +VGS > VGS +VT
!
VIN < VDD +VT
This is almost always the case
in practical realizations
EE 303 – Common Drain Stage
3
)
I/O DC characteristic (1)
Example:
VIN = 2.5V; I1=400µA;
VDD=5V; W/L=100µm/1µm
DC Transfer Function − 1 um Technology
5
4.5
Vout
3.5
Vout [V]
VDD-Vth ≈ 3.43 V
Source: Razavi
M1
triode
Vth
4
3
2.5
2
M operation
1
1.5
6
1
5
0.5
Vds=Vdd−Vout
0
Vov=Vin−Vout−Vth
4
M1 triode
1
0
1
2
3
2
3
4
Vin [V]
5
6
7
Math “artifact” due to ideal current source
(a current source can take any voltage value
across it !!)
2
0
1
AV (@ VIN = 2.5V) ≅ 0.821
M1 sat.
3
0
4
Vin [V]
5
6
7
8
EE 303 – Common Drain Stage
§ Vout(min) ≈ 0
§ Vout(max) ≈ VDD-Vth
4
8
I/O DC characteristic (2)
element 0:m1
0:m2
model
0:simple_n 0:simple_n
region
Saturati
Saturati
id
452.1261u 452.1261u
ibs
-13.0315f
0.
ibd
-50.0000f -13.0315f
vgs
1.1968
900.0000m
vds
3.6968
1.3032
vbs
-1.3032
0.
vth
833.4784m 500.0000m
vdsat
363.3703m 400.0000m
vod
363.3703m 400.0000m
beta
6.8484m
5.6516m
gam eff 600.0000m 600.0000m
gm
2.4885m
2.2606m
gds
33.0095u
40.0000u
gmb
514.7852u 758.2384u
cdtot
72.3963f
93.2122f
cgtot
256.5245f 256.4846f
cstot
246.1466f 286.3341f
cbtot
66.1318f 128.5634f
cgs
203.3341f 203.3341f
cgd
51.1337f
50.3996f
* measurement
av0= 808.9285m
Vout [V]
I1
Example:
VIN = 2.5V;
I1=400µA;
VDD= 5V;
VB = 0.9V;
W/L=100µm/1µm;
DC Transfer Function − 1 um Technology
5
4.5
4
3.5
3
Vout=Vds2
Vov2
2.5
Vds1
Vov1
2
1.5
1
0.5
0
0
M2 off
M1 sat
§
1
2
M2 triode
M1 sat
3
4
Vin [V]
M2 sat
M1 sat
5
6
7
8
M2 sat
M1 triode
Reduced output (and input) swing
- Vout(max) = VDD – VOV1
- Vout(min) = VOV2
EE 303 – Common Drain Stage
5
CD Voltage Transfer
'
1
vo %% sC Ltot + sC gs +
RLtot
&
vi
+
vgs
-
Cgs
gmvgs
Cgd+Cgb
$
"" − vi sC gs − g m (vi − vo ) = 0
#
g m + sC gs
vo
=
vi g + sC + sC + 1
m
gs
Ltot
RLtot
vo
CLtot
C Ltot = C L + Csb
RLtot
RLtot = RL ||
LHP
zero
sCgs
vo
gm
gm
=
=
⋅
1
s
C
+
C
vi g +
( gs Ltot )
m
1+
RLtot
1
gm +
RLtot
s
1−
z
= av0 ⋅
s
1−
p
1+
1
|| ro
g mb
often RLtot≅ 1/gmb
EE 303 – Common Drain Stage
6
Low Frequency Gain
av 0 =
gm
gm +
RLtot = RL ||
1
RLtot
1
|| ro
g mb
§ Interesting cases
– Ideal current source; PMOS with source tied to body; no load resistor;
RL=∞, ro=∞, gmb= 0
VDD
Vo
Vi
av 0 = 1
CL
Yin
– Ideal current source; NMOS; no load resistor;
VDD
RL=∞, ro=∞, gmb≠0
Vi
Vo
IB
RL
CL
av 0 =
gm
g m + g mb
(typically ≅ 0.8)
– Ideal current source, PMOS with source tied to body; load resistor
ro=∞, gmb=0, RL finite
gm
av 0 =
1
gm +
EE 303 – Common Drain Stage
7
RL
Low frequency input and output resistances
RS
vs
Rin
Rout
vout
vin
gmvin
ro
1/gm
1/gmb
RL
av0= gm / (g’m+1/ro+1/RL)
§ Rin = ∞
§ Rout = ro || (1/g’m)
EE 303 – Common Drain Stage
8
High Frequency Gain
av0 =
s
v
z
av (s ) = o = av 0 ⋅
s
vi
1−
p
1−
gm
g'm +1 / ro +1 / RL
1
RLtot
p=−
C gs + C Ltot
gm +
g
z=− m
C gs
§ Three scenarios:
|z|<|p|
|z|>|p|
|a v(s)|
|z|=|p|
|av(s)|
|av(s)|
av0
av0
av0
f
The presence of a
LHP zero leads to
the possibility that
the pole and zero
will provide some
degree of cancellation,
leading to a broadband
response
f
f
(infinite bandwidth ?!?)
EE 303 – Common Drain Stage
9
CD Input Impedance
§ By inspection:
vi
Yin
Hint:
i=Cgs(vi-vo)
+
vgs
-
Cgs
Yin = sCgd + sCgs (1− av (s))
gmvgs
Cgd+Cgb
vo
CLtot
Consistent with insight from
Miller Theorem
RLtot
§
Gain term av(s) is real and close to unity
up to fairly high frequencies
§
Hence, up to moderate frequencies, we
see a capacitor looking into the input
– A fairly small one, Cgd, plus a fraction
of Cgs
EE 303 – Common Drain Stage
10
CD input impedance for PMOS stage (with Body-source tie)
VDD
§ gmb generator inactive
– Low frequency gain very close
gmro >> 1
to unity
IB
vOUT
Vout
Cgs
vVIN
in
CCinin@≈ CCgdgd Cgd
Cbsub
av0 =
CL
gm
1
gm +
ro
≅1
§ Very small input capacitance
Yin = sCgd + sCgs (1− av (s))
Yin ≅ sCgd
for av=1 (Vout=Vin)
no current flows
through Cgs(perfect
bootstrap)
§ The well-body capacitance Cbsub can be large and may significantly affect
the 3-db bandwidth
EE 303 – Common Drain Stage
11
CD Output Impedance (1)
§ Let's first look at an analytically simple case
– Input driven by ideal voltage source
+
vgs
-
Z out =
Cgs
gmvgs
vo
Cgd+Cgb
Csb
AC shorted
1
1
g m + g mb s (C gs + Csb )
1/gmb
Zout
ZL
YL=sCL+1/RL
EE 303 – Common Drain Stage
Low output impedance
• Resistive up to very high
frequencies
12
CD Output Impedance (2)
§ Now include finite source resistance
vg
Ri
Cgs
gm(vg-vo)
Zx
Cgd+Cgb
ix
Zout
Csb
vo
1/gmb
ZL
Neglect Cgd
Neglecting Cgd
" vg %
ix = ( vo − vg ) ( gm + sCgs ) = vo $1− ' ( gm + sCgs )
# vo &
"
%
$
'
vo 1+ sRiCgs 1 $ 1+ sRiCgs '
Zx = ≅
=
sCgs '
ix gm + sCgs gm $
1+
$
'
g
#
&
m
EE 303 – Common Drain Stage
vg
Ri
≅
1
vo
+ Ri
sCgs
13
CD Output Impedance (3)
Zx ≅
1 (1+ sRiCgs )
gm " sCgs %
$1+
'
gm &
#
NOTE:
Typically 1/gm is small,
so this can happen !!
§ Two interesting cases
Ri < 1/gm
Ri > 1/gm
|Zx(s)|
|Zx(s)|
1/gm
1/gm
f
f
Inductive behavior!
EE 303 – Common Drain Stage
14
Equivalent Circuit for Ri > 1/gm
1 (1+ sRiCgs )
Zx ≅
gm " sCgs %
$1+
'
gm &
#
for s = 0 ⇒ Z x = 1 / gm
for s → ∞ ⇒ Z x = Ri
Zx
Zout
R1
for s = 0 ⇒ Z x = R1 || R2
for s → ∞ ⇒ Z x = R2
R2
Csb
1/gmb
1
R1 || R2 =
gm
R2 = Ri
L
L=
L
(R + sL)R2
RR
R1
Zx = 1
= 1 2
R1 + R2 + sL R1 + R2 1+ L
R1 + R2
Ri2C gs
g m Ri − 1
1+
§ This circuit is prone to ringing!
– L forms an LC tank with any capacitance at the output
– If the circuit drives a large capacitance the response to step-like
signals will result in ringing
EE 303 – Common Drain Stage
15
Inclusion of Parasitic Input Capacitance*
What happens to the output impedance if we don’t neglect Ci=Cgd ?
* Hint:
replace Ri with
(
€
)
1 1+ sRi (Cgs + Ci )
Zx =
gm ! sCgs $
#1+
& (1+ sRiCi )
g
"
m %
Ri
Zi =
Ri + sCi Ri
1
Ri (Cgs + Ci )
<
1
gm
1
<
Cgs RiCi
Ri (Cgs + Ci )
|Zx (s)|
|Zx(s)|
1/gm
1/gm
f
EE114
EE 303 – Common Drain Stage
<
1
g
< m
RiCi Cgs
f
16
Applications of the Common Drain Stage
§ Level Shifter
§ Voltage Buffer
§ Load Device
EE 303 – Common Drain Stage
17
Application 1: Level Shifter
Vi=VGS +Vo
VDD
Vo=Vi – VGS= Vi – (Vt+VOV)
Vi
Vo
VGS=Vt +Vov ≅ const.
IB
§ Output quiescent point is roughly Vt+Vov lower than input quiescent point
§ Adjusting the W/L ratio allows to “tune” Vov (= the desired shifting level)
EE 303 – Common Drain Stage
18
Why is lowering the DC level useful ?
§ When building cascades of CS and CG amplifiers, as we move along
the DC level moves up
§ A CD stage is a way to buffer the signal, and moving down the DC level
EE 303 – Common Drain Stage
19
Application 2: Buffer
VDD
VVBB1
IB1
RD
M1
(large)
Rout
vx
Vvinin
vVout
out
MX
M2
IB2
RL
(small)
VB2
§ Low frequency voltage gain of the above circuit is ~gmRbig
– Would be ~gm(Rsmall||Rbig) ~ gmRsmall without CD buffer stage
§ Disadvantage
– Reduced swing
Vout (max) = VDD −VOV1
Vout (min) = VOV 2
EE 303 – Common Drain Stage
20
Buffer Design Considerations
VDD
§ Without the buffer the minimum
allowable value of Vx for Mx to
remain in saturation is:
VX > VGSX – Vthx
VVB
B1
IB1
RD
(large)
M1
Rout
vx
Vx
V
vinin
MX
vVoutout
VB
M
IB2
2
RL
(small)
§ With the buffer for M2 to remain in sat.
it must be:
VX > VGS1+VGS2-Vth2
VB2
§ Assuming the overdrive of Mx and M2 are comparable this means that the
allowable swing at X is reduced by VGS1 which is a significant amount
(VGS1=VOV1 +Vth1)
EE 303 – Common Drain Stage
21
Application 3: Load Device
Looks familiar ?
“CS stage with diode connected load”
VDD
M2
1/(gm2+gmb2 )
Vo
Vi
M1
§ Advantages compared to resistor load
– "Ratiometric"
• Gain depends on ratio of similar
parameters
• Reduced process and temperature
variations
– First order cancellation of nonlinearities
§ Disadvantage
– Reduced swing
Vout (max) = VDD −V th2
av 0 =
g m1
g m 2 + g mb 2
Vout (min) = VIN −V th1= VOV1
EE 303 – Common Drain Stage
22
CD stage Issues
§ Several sources of nonlinearity
– Vt is a function of Vo (NMOS, without S to B connection)
Vt = Vt 0 + γ
(
PHI +Vo − PHI
)
– ID and thus Vov changes with Vo
• Gets worse with small RL
1
W
2
I D = µCOX (VGS −Vt )
2
L
If we worry about distortion we need to keep ΔVin/2VOV small (à we need large VOV,
and this affect adversely signal swing). If RL is small, things are even worse because
to obtain the desired ΔVout we need more ΔVin (and so even more VOV)
ΔVout
gm
≈
ΔVin g'm +1 / RL
Small RL means less gain
§ Reduced input and output voltage swing
– Consider e.g. VDD=1V, Vt=0.3V, VOV=0.2V (VGS=Vt+Vov=0.5V)
• CD buffer stage consumes 50% of supply headroom!
– In low VDD applications that require large output swing, using a CD buffer is often not
possible
– CD buffers are more frequently used when the required swing is small
• E.g. pre-amplifiers or LNAs that turn µV into mV at the output
EE 303 – Common Drain Stage
23
Summary – Elementary Transistor Stages
§ Common source
– VCCS, makes a good voltage amplifier when terminated with a high
impedance
§ Common gate
– Typically low input impedance, high output impedance
– Can be used to improve the intrinsic voltage gain of a common
source stage
• "Cascode" stage
§ Common drain
– Typically high input impedance, low output impedance
– Great for shifting the DC operating point of signals
– Useful as a voltage buffer when swing and nonlinearity are not an
issue
EE 303 – Common Drain Stage
24
CD Voltage Transfer Revisited (1)
§ The driving circuit has a finite resistance Rs
CD Core
Zin
Zout
RS
vs
example: if RS is the output
resistance of a CS stage
it can be relatively large
vin
Cgd
vout
Cgs
gmvin
1/g’m
Csb
RL
CL
ro||1/g’m
Rtot || Ctot
§ This model resembles the model of the CS stage
- The main difference is in the polarity of the controlled source
- This difference has profound impact on the Miller amplification of
the capacitance coupling input and output
EE 303 – Common Drain Stage
25
CD Voltage Transfer Revisited (2)
Cgs
1+ s
vout
gm
= av0 ⋅
vs
1+ b1s + b2 s 2
av0 = gm Rtot
b1 = RsCgs (1− av0 ) + RS Cgd + Rtot Cgs + Rtot Ctot
b2 = RS Rtot (CgsCgd + CgsCtot + Cgd Ctot )
§ The zero in the transfer function is on the LHP and it occurs at
approximately ωT
§ Unfortunately the high frequency analysis can become quite involved. A
dominant real pole does not always exist, in fact poles can be complex.
In the case the poles are complex a designer should be careful that the
circuit does not exhibit too much overshoot and ringing.
EE 303 – Common Drain Stage
26
CD Voltage Transfer Revisited (3)
Cgs
vout
gm
= av0 ⋅
= av0 ⋅
2
vs
1+ b1s + b2 s
1+ s
1+ s
Cgs
gm
s
s2
1+
+ 2
ω 0Q ω 0
§ Interesting cases:
- A dominant pole condition exist
- Poles are complex
ω 3dB ≅
1
b1
( b = ∑τ )
1
j
A dominant pole condition exist for: Q2 << 1/4
b2
<< 1 / 4
b12
EE 303 – Common Drain Stage
27
Poles Location
s
s2
§ Roots of the denominator of the transfer function: 1+
+ 2 =0
ω 0Q ω 0
§ Complex Conjugate poles
(overshooting in step response)
ω0
2
for Q > 0.5 ⇒ s1,2 = −
2Q
(1± j
Poles location with Q> 0.5
jω
4Q −1
)
- For Q = 0.707 (φ=45°), the -3dB frequency is ω0
(Maximally Flat Magnitude or Butterworth Response)
φ=
σ
- For Q > 0.707 the frequency response has peaking
§ Real poles (no overshoot in the step response)
for Q ≤ 0.5 ⇒ s1,2 = −
ω0
1± 1− 4Q 2
2Q
(
)
EE 303 – Common Drain Stage
Source:
Carusone
28
Frequency Response
|H(s)|
10
H (s) =
1
s
s2
1+
+
ω 0Q ω 02
Magnitude [dB]
5
0
−5
−10
−15
−20 −2
10
Q=0.5
Q=1/sqrt(2)
Q=1
Q=2
−1
10
EE 303 – Common Drain Stage
0
/
10
1
10
0
29
Step Response
“Underdamped” Q > 0.5
Source:
Carusone
Q=0.5
“Overdamped” Q > 0.5
time
§ Ringing for Q > 0.5
§ The case Q=0.5 is called maximally damped response (fastest settling
without any overshoot)
EE 303 – Common Drain Stage
30