ECE2003
Prerequisite:
Digital Logic Design
ECE1002/ECE1013
L T P J C
2 0 2 0 3
Syllabus version
1.01
Course Objectives:
1. To represent logical functions in canonical form and standard forms
2. To design and analyse the combinational logic circuits
3. To design and analyse the sequential logic circuits
4. To implement the combinational and sequential logic circuits using Verilog HDL
Course Outcome:
At the end of the course the student should be able to
1. Understand the number systems and IC characteristics
2. Understand the Boolean algebra and its properties
3. Optimize the logic functions using K-map
4. Design and analyse the combinational logic circuits
5.Get grip on Verilog HDL syntax
6. Design and analyse the sequential logic circuits
7. Implement and simulate the combinational logic circuits using Verilog HDL
Student Learning Outcomes (SLO):
2, 5, 17
Module:1 Number systems and Logic Families:
3 hours
Brief review of Number Systems, Digital Logic Gates and its electrical characteristics, Review
of RTL, DTL, TTL, ECL, CMOS families.
Module:2 Boolean algebra:
2 hours
Basic Definitions, Axiomatic Definition of Boolean Algebra, Basic Theorems and Properties of
Boolean Algebra, Boolean Functions, Canonical and Standard Forms.
Module:3 Gate-Level Minimization:
3 hours
The Map Method - K-map, Product of Sums and Sum of Products Simplification, NAND and
NOR Implementation
Module:4 Design of Combinational Logic Circuits:
5 hours
Design Procedure, Binary Adder-Subtractor, Parallel Adder, Binary Multiplier, Magnitude
Comparator-4 bit, Decoders, Encoders, Multiplexers, De-multiplexer, Parity Generator and
Checker. Application of Multiplexers and De-multiplexers.
Module:5 Verilog HDL Coding Style:
4 hours
Lexical Conventions, Ports and Modules, Gate Level Modelling, Operators, Data Flow
Modelling, Behavioral level Modelling, Testbench.
Module:6 Design of Sequential Logic Circuits:
6 hours
Latches, Flip-Flops-SR, D, JK & T, Shift Registers-SISO, SIPO, PISO, PIPO, Design of
Synchronous Sequential Circuits- State Table and State Diagrams, Design of CountersModulo-n, Johnson, Ring, Up/Down, Design of Mealy and Moore FSM -Sequence Detection.
Module:7 Modelling of Logic Circuits:
Modelling of Combinational and Sequential Logic Circuits using Verilog HDL.
5 hours
Module:8 Contemporary Issues
2 hours
Total Lecture Hours:
30 hours
Text Books:
1. M. Morris R. Mano and Michael D. Ciletti, “Digital Design With an Introduction to the
Verilog HDL”, 2014, 6th Edition, Prentice Hall of India, India.
Reference Books:
1. Charles H. Roth, Jr., "Fundamentals of Logic Design", 2014, 7th Edition Reprint,
Brooks/Cole, Pacific Grove, US.
2. Michael D. Ciletti, 2011, “Advanced Digital Design with the Verilog HDL, 2nd Edition”,
Pearson Pvt. Ltd, Noida, India.
3. Stephen Brown and ZvonkoVranesic, 2013, “Fundamentals of Digital Logic with Verilog
Design”, Third Edition, McGraw-Hill Higher Education, New Delhi, India.
Mode of evaluation: Internal Assessment(CAT, Quizzes, Digital Assignments) & Final
Assessment Test (FAT)
Sl.No.
1
2
List of Challenging Experiments (Indicative)
Characteristics of Digital ICs (Hardware)
4 hours
Implementation of Combinational Logic Design using MUX/Decoder
4 hours
ICs (Hardware)
3
Design and Implementation of various data path elements
4 hours
Adders/Multipliers (Hardware)
4
Design and Implementation of various data path elements like
6 hours
Adders/Multipliers and combinational Logic circuits like Multipliers
(Mandatory: Verilog Modeling, Simulation and Synthesis. FPGA
implementation (optional)
5
Design and implementation of simple synchronous sequential circuits
2 hours
like Counters / Shift registers (Hardware)
6
Complex state machine design (Simulation and Synthesis)
4 hours
7
Simple processor design (Simulation and Synthesis)
6 hours
Total laboratory hours: 30 hours
Mode of assessment: Continuous Assessment & Final Assessment Test (FAT)
Recommended by Board of Studies
13-12-2015
Approved by Academic Council
No. 40
Date:
18-03-2016