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Ro @ cycles Eg ① ADD R2 ,R1,R3 ② SBR R2 ,R3 , R2 ③ STR : fetch intuition return B If , / ID , I , R2 , ( b R2 store / IE , / If , / ID , / I Pipelining Time Program Time Cycle ✗ cycle Instruction × Instructions Program f f RISC CISC reduces this 3 there , steps b) in Decode flFD= = CISC mandatory Sayles , STR RISC Execute ③ malt AIB ① store - MUL : Decode Fetch , - RISC Pipelines fetch ① CISC III parallel techniques Instruction w . . is reduces this s÷ # Pipeline hazards f, / IF , / I D , / IE , a re ) is operation Replication - ① Rg÷#- back on e Pipelining - operation Architecture EI Ed CPU one Registers in - Instruction Set Arithmetic for only any an , instruction , Register / memory ( Reduced Rest for AIM Basic - CISC per cycle ) In In atleast execute tries to Cpu ?⃝ ② Replication ( very long instruction ) Replication replicate CPU *" (hardware) of the ways classify to CPUs : Simple arch VLIW arch - - Superscalar - pro ⑨ 5 ② SIMD ③ MISD ① ISD - - Single - Multiple Single Single - o( in Alpha =b**z Store Next one instruction roam at elementof time point ② f- dstore + B ( C ÷:÷÷÷±i÷÷÷÷÷+÷ :÷÷÷::|É - Blot Load BID load BH " store 401 store Alo ) store cat store Acy Ist Next cover Intel ✗ 86 y time SIMD Load Inst Next - a LoadB_ executed It ; :*¥_| Load lo in # L - we'll ① SISD_ 4) Sum - Multiple - time , MIND Data Multiple - - MIMD Instruction y, arch nemoaoeossnamiasen.ir#nNstamom " ① it ) physical realization of :I ÷÷÷÷¥¥t÷÷÷:÷¥÷i☐ I Architecture hardware one ( mist ③ Superscalar ⑧ VLIW word I n st architecture per micrometer ( SESD) time
