UNIVERSITY OF BAHRAIN
College of Engineering
Department of Electrical and Electronic Engineering
EENG 251: Digital Systems I
Laboratory Manual
List of Experiments
1
INDIVIDUAL LOGIC GATES
2
2
SIMULATING LOGIC CIRCUITS WITH LOGICWORKS
5
3
VERIFICATION OF DE MORGAN'S LAWS
8
4
COMBINATIONAL LOGIC CIRCUIT DESIGN
11
5
COMBINATIONAL LOGIC CIRCUIT DESIGN USING MULTIPLEXERS
13
6
BINARY ADDERS AND SUBTRACTORS
15
7
SEQUENTIAL LOGIC CIRCUITS: J-K FLIP FLOPS
17
8
DESIGN OF SYNCHRONOUS COUNTERS
20
EENG 251: Digital Systems I
1
Dr. R. Al-Alawi
UNIVERSITY OF BAHRAIN
C OLLEGE OF E NGINEERING
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
EENG 251: DIGITAL SYSTEMS I LABORATORY
EXPERIMENT NO. 1
INDIVIDUAL LOGIC GATES: NOT, AND, NAND, OR AND NOR GATES.
OBJECTIVE
After Completing this lab, the student should be able to
 Identify the gate symbols for the Boolean operations AND, OR, NOT, NAND, NOR, XOR and XNOR.
 Construct the truth table for each individual gate.
COURSE INTENDED LEARNING OUTCOME
This lab assignment satisfies the Course Intended Learning Outcome #4 :
 Understand the basic operations and laws of Boolean Algebra
THEORY AND BACKGROUND
In this experiment you will be using a typical TTL integrated circuits (IC) to demonstrate the functions
of basic logic gates. These ICs are housed in a dual-in line package (DIP). You will be referring to the data sheet
at the end of this manual to determine the pin assignments for each logical element.
EQUIPMENT AND COMPONENTS


Digital Trainer
7404 x 1, 7408 x 1 ,7432 x 1, 7400 x 1, 7402 x 1, 7486, .
PROCEDURE
A – VERIFICATION OF THE INVERTER FUNCTION
1.
2.
3.
Insert the 7404 IC into the mounting board.
Refer to the pin diagram of the 7404 IC and connect the Vcc pin to +5V and the GND pin to ground.
Wire the inverter as shown in fig. 1a, such that the input of the inverter is connected to any switch
(e.g., SW1) and the output is connected to any LED (e.g., L1) on the trainer.
A
0
1
Fig. 1
4.
5.
6.
L1 = A'
Table 1.
Power On. Set the switch to the ON position and observe the LED (L1) output.
Set the switch to the OFF position and observe the LED output.
Record your results in table1.
EENG 251: Digital Systems I
2
Dr. R. Al-Alawi
B - VERIFICATION OF THE AND, NAND FUNCTIONS
7.
8.
9.
Insert the 7408 IC and the 7400 IC into the mounting board.
Refer to the pin diagram of the 7408 and 7400 ICs and connect the Vcc pin to +5V and the GND pin
to ground.
Connect the circuit as shown in fig. 2.
7408
7400
10.
11.
Fig. 2.
Power On, Change the position of the data switches SW1 and SW2 as shown in the first column of
table 2.
Record L1 and L2 outputs in the second and the third column respectively of table 2.
A
B
0
0
1
1
0
1
0
1
L1 = A . B
L2 = ( A
. B )'
Table 2.
C - VERIFICATION OF THE OR AND NOR FUNCTIONS
12.
13.
14.
Insert the 7432 IC and the 7402 IC into the mounting board.
Refer to the pin diagram of the 7432 and 7402 ICs and connect the Vcc pin to +5V and the GND pin
to ground.
Connect the circuit as shown in fig. 3.
7402
15.
16.
Fig. 3.
Power On. Change the position of the data switches SW1 and SW2 as shown in the first column of
table 3.
Record L1 and L2 outputs in the second and the third column respectively of table 3.
A
B
L1 = A + B
L2 = ( A + B )'
0
0
1
1
0
1
0
1
Table 3
EENG 251: Digital Systems I
3
Dr. R. Al-Alawi
D - VERIFICATION OF THE XOR AND XNOR FUNCTIONS
17.
18.
19.
Insert the 7486 IC and the 7404 IC into the mounting board.
Refer to the pin diagram of the 7486 and 7404 ICs and connect the Vcc pin to +5V and the GND pin
to ground.
Connect the circuit as shown in fig. 4.
Fig. 4
20.
21.
Power On. Change the position of the data switches SW1 and SW2 as shown in the first column of
table 4.
Record L1 and L2 outputs in the second and the third column respectively of table 4.
A
B
L1
L2
0
0
0
1
1
0
1
1
Table 4
LABORATORY REPORT
1.
2.
3.
Follow laboratory report form provided by your instructor.
Draw the circuits diagram that you built including the pin numbers of the gates
Include your truth tables for all logic functions.
DISCUSSION AND CONCLUSION
1.
2.
3.
4.
5.
Discuss any problems you faced with the procedure.
Did the behavior of the gates match the expected truth table?
Using only 2-input AND gates, draw two circuit configurations that will produce the function
Z=A.B.C.D.E, Which circuit is faster, which circuit is smaller.
Assume that you need a 2-input OR gate but you have only a 3-inputs OR gate available. Show two
methods that you would use to make the 3-input OR gate behave as a 2-input OR gate, i.e.; how the
unused input be connected.
Assume that you need a 2-input AND gate but you have only a 3-inputs AND gate available. Show
two methods that you would use to make the 3-input AND gate behave as a 2-input AND gate, i.e.;
how the unused input be connected.
EENG 251: Digital Systems I
4
Dr. R. Al-Alawi
UNIVERSITY OF BAHRAIN
C OLLEGE OF E NGINEERING
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
EENG 251: DIGITAL SYSTEMS I LABORATORY
EXPERIMENT NO. 2
SIMULATING LOGIC CIRCUITS WITH LOGICWORKS
OBJECTIVE
To be familiar with building and simulating logic circuits using CAD tools such as LogicWorks.
COURSE INTENDED LEARNING OUTCOME
This lab assignment satisfies the Course Intended Learning Outcome #13 :
 Be able to use CAD tools to build and simulate small digital system.
DESIGN PROBLEM
Build and simulate the circuit that corresponds to the following function, then test it to verify its truth table.
𝑓(𝑎, 𝑏, 𝑐, 𝑑) = (𝑐  𝑎𝑏̅) + 𝑑̅
SIMULATION PROCEDURE
1.
Open a new circuit
1.
From the Library, search for XOR gate, and select xor_2, then drag the highlighted gate to the
worksheet.
2.
Repeat for AND-2and OR-2
EENG 251: Digital Systems I
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Dr. R. Al-Alawi
3.
Connect the gates as shown by extending the wires from one gate to the other
4.
Select Binary switch and drag four of them to the worksheet.
5.
Select binary probe to view the output.
6.
7.
Name the inputs and outputs as show, using the text tool
Click on each input wire and give it a name.
EENG 251: Digital Systems I
6
Dr. R. Al-Alawi
Note that when you click on an input signal its corresponding wire(s) will be highlighted.
8.
Label the output as f.
9.
Test the functionality of the circuit by trying all possible combinations of the inputs. Then record the
resulted output on a truth table.
10. Verify that the result matches the expected truth table of the function.
a
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
EENG 251: Digital Systems I
Inputs
b c
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
d
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
a.b’
(c  a.b’)
0
0
7
Output f
(c  a.b’) + d’ simulation
1
?
Dr. R. Al-Alawi
UNIVERSITY OF BAHRAIN
C OLLEGE OF E NGINEERING
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
EENG 251: DIGITAL SYSTEMS I LABORATORY
EXPERIMENT NO. 3
VERIFICATION OF DE MORGAN'S LAWS
OBJECTIVE

To verify De Morgan's Laws which state that:
AB  A  B and

A  B  A B
Simulate simple logic circuits to match a logic function and its complement to verify De Morgan's Laws.
COURSE INTENDED LEARNING OUTCOME
This lab assignment satisfies the Course Intended Learning Outcome #6 and 13 :
 Express Boolean functions in the general canonical form and implement logic functions using universal
logic gates.
 Be able to use CAD tools to build and simulate small digital system.
THEORY AND BACKGROUND
In Boolean Algebra, De Morgan's laws are rules relating the logical operators "AND" and "OR" in terms
of each other via negation, namely:
( 𝐴  𝐵 )′ = 𝐴′ + 𝐵′
(𝐴 + 𝐵)′ = 𝐴′  𝐵′
The rules can be generalized as:
f′(a, b, c, d, … … … , +, . , 0, 1) = f(a′, b′, c′, d′, … … … .. , . , + 1′, 0′)
Hence, the inverse of a Boolean function is formed by replacing the OR with AND, the AND with OR, the 1’s with
0’s and the 0’s with 1’s and the variables with their complements.
De Morgan's Laws relates the OR, AND, NOR and NAND gates as follows:
 A NAND gate is equivalent to an OR gate with inverted inputs
 A NOR gate is equivalent to an AND gate with inverted inputs
 Inverting inputs and outputs of an OR gate makes it an AND gate.
 Inverting inputs and outputs of an AND gate makes it an OR gate.
De Morgan’s theorem allows for the simplification of a Boolean expression by the cancellation of some
redundant inversions.
EQUIPMENT AND COMPONENTS


Digital Trainer
7400, 7402, 7404, 7408 and 7432
EENG 251: Digital Systems I
8
Dr. R. Al-Alawi
PROCEDURE
1.
2.
3.
Connect the circuit shown in fig.1 on the breadboard, such that: input "A" is connected to data switch SW1,
input "B" is connected to data switch SW2, output "Y1" points to LED L1 and output "Y2" points to LED L2.
Fig. 1
Change the position of the data switches SW1 and SW2 as shown in table 1 and record the LED outputs in
the same table.
Compare the two outputs and state the corresponding DeMorgan's law.
De Morgan's law: __________________________________
A = SW!
B = SW2
0
0
0
1
1
0
1
1
Y1= L1
Y2 = L2
Table 1
4.
Connect the circuit shown in fig.2 on the breadboard, such that: input "A" is connected to
data switch SW1, input "B" is connected to data switch SW2, output "Y 1" points to LED L1 and
output "Y2" points to LED L2
.
5.
Fig. 2
Change the position of the data switches SW1 and SW2 as shown in table 2 and record the LED outputs in
the same table.
EENG 251: Digital Systems I
9
Dr. R. Al-Alawi
A = SW!
B = SW2
0
0
1
1
0
1
0
1
Y1= L1
Y2 = L2
Table 2
6.
Compare the two outputs and state the corresponding De Morgan's law.
De Morgan's law: __________________________________
BUILDING AND SIMULATING SIMPLE LOGIC CIRCUIT AND ITS COMPLEMENT
7.
8.
9.
Build and simulate the circuit that correspond to the function 𝑓 (𝐴, 𝐵, 𝐶, 𝐷) given by your instructor.
Test the truth table for 𝑓 (𝐴, 𝐵, 𝐶, 𝐷).
Find the complement of 𝑓 (𝐴, 𝐵, 𝐶, 𝐷) using De Morgan's law.
10.
Build and simulate the circuit that correspond to ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑓 (𝐴, 𝐵, 𝐶, 𝐷)
11.
12.
̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴, 𝐵, 𝐶, 𝐷)
Test the truth table of 𝑓
Verify De Morgan's law.
DISCUSSION AND CONCLUSION:
1.
2.
Apply De Morgan's Law to find the complement of the expression given by your instructor (do not
simplify the results):
Show how you can implement the XOR function using NAND gates only.
EENG 251: Digital Systems I
10
Dr. R. Al-Alawi
UNIVERSITY OF BAHRAIN
C OLLEGE OF E NGINEERING
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
EENG 251: DIGITAL SYSTEMS I LABORATORY
EXPERIMENT NO. 4
COMBINATIONAL LOGIC CIRCUIT DESIGN
OBJECTIVE
After completing this experiment, you will be able to:
 Given a problem statement, design and build a logic circuit that solve the logic problem.
 Write a formal laboratory report describing the circuit and results.
COURSE INTENDED LEARNING OUTCOME
This lab assignment satisfies the Course Intended Learning Outcome 5 :
 Manipulate Boolean Algebra and simplify Boolean functions using Karnaugh maps and derive gate-level
implementation of a given Boolean expression and vice versa.
THEORY AND BACKGROUND
In this experiment you will learn how to design a combinational logic network starting with a word
description of the desired network behavior. The first step is usually to translate the word description into a
truth table or into algebraic expression. Given the truth table for a Boolean function, two standard algebraic
forms can be derived, Standard SOP and Standard POS. Simplification of either of these standard forms leads
directly to realization of the network using AND and OR gates. The Karnaugh map method is a useful tool for
simplifying and manipulating logic functions of three or four variables. The K-map method can be extended to
functions of five, six, or more variables, however, it is not very efficient. When the number of variables exceeds
5, or several functions must be simplified, then the use of computer is desirable.
EQUIPMENT AND COMPONENTS




Digital Trainer
7404
7408
7432
DESIGN PROBLEM:
Your Instructor will give you a word description of the desired network behavior.
PROCEDURE
You will perform the following steps to implement the network in the lab.
1. Construct the truth table of the logic problem
2. Plot the K-map from the truth table.
3. Simplify the function in a minimum SOP form and minimum POS.
4. Draw the minimum two-level circuit that will implement the logic function.
6. Draw the PIN diagram of the circuit.
EENG 251: Digital Systems I
11
Dr. R. Al-Alawi
7.
8.
Connect the circuit on the logic trainer's breadboard.
Test your circuit by setting input switches to all possible combinations and record the generated
output.
DISCUSSION AND CONCLUSION:
1.
2.
3.
Using AND, OR, and Inverters, find the minimum network to realize the above network. (It may
be more than two levels)
Realize the above network using 2-inputs NAND gates only.
Realize the above network as a 3-levels NOR gate network.
EENG 251: Digital Systems I
12
Dr. R. Al-Alawi
UNIVERSITY OF BAHRAIN
C OLLEGE OF E NGINEERING
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
EENG 251: DIGITAL SYSTEMS I LABORATORY
EXPERIMENT NO. 5
COMBINATIONAL LOGIC CIRCUIT DESIGN USING MULTIPLEXERS
OBJECTIVE
After completing this experiment, you will be able to design, draw and implement logic functions using
multiplexers.
COURSE INTENDED LEARNING OUTCOME
This lab assignment satisfies the Course Intended Learning Outcome 7 :
 Be able to design combinational circuit using combinational logic modules such as multiplexers.
THEORY AND BACKGROUND
A multiplexer or data selector has a group of data inputs and a group of control inputs. The control
inputs are used to select one of the data inputs and connect it to the output terminal. A multiplexer with N
control inputs has 2N data inputs and one output, it is recalled 2N-to-1 multiplexer.
The primary application of multiplexers is data selection. In addition, multiplexers can be used to realize
combinational logic functions. The general equation of a 2N-to-1 multiplexer is given by:
z
2 N2 1
m
k 0
k
Ik
where mk is a minterm of the N control variables and Ik is the corresponding data. This equation is similar to the
standard Sum of Product (SOP) form of any logic function. Therefore, multiplexers can be used to realize any
combinational logic functions.
EQUIPMENT AND COMPONENTS


Digital Trainer
74151 8-inputs multiplexer.
DESIGN PROBLEM
Your Instructor will give you a description of the desired network behavior for this experiment. Let the variables
of the network logic function be called W, X, Y and Z.
PROCEDURE
You will be doing the following steps in order to implement your circuit in the lab. .
1. Construct the truth table of the logic problem
2. Plot the K-map from the truth table.
3. From the K-map determine the required data inputs of the 8-to-1 multiplexer given that input variables
W, X, Y are selected as the control inputs and are connected as shown in Figure 1.
4. Complete the circuit diagram of Figure 1, to match your design.
5. Connect the circuit of Figure 1, on the logic trainer's breadboard.
EENG 251: Digital Systems I
13
Dr. R. Al-Alawi
6.
7.
Test your circuit behavior by setting input variables W, X, Y and Z, to all possible combinations and
record the multiplexer generated output.
Fig. 1
Change the variables that are connected to the control inputs as shown in Figure 2, and repeat the
above procedure.
Fig. 2
DISCUSSION AND CONCLUSION:
1.
2.
3.
Show how you can realize the same function using a 2-to-1 multiplexer with W, X as control inputs.
Show how you can realize the same function using a 2-to-1 multiplexer with no added gates.
Show how you can generate a 64-to-1 MUX using a 8-to-1 MUX.
EENG 251: Digital Systems I
14
Dr. R. Al-Alawi
UNIVERSITY OF BAHRAIN
C OLLEGE OF E NGINEERING
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
EENG 251: DIGITAL SYSTEMS I LABORATORY
EXPERIMENT NO. 6
BINARY ADDERS AND SUBTRACTORS
OBJECTIVE
After completing this experiment, you will be able to test a circuit that perform both addition and
subtraction using 2’s complement.
COURSE INTENDED LEARNING OUTCOME
This lab assignment satisfies the Course Intended Learning Outcome 7 :
 Be able to design combinational circuit using combinational logic modules such as adders.
THEORY AND BACKGROUND
The 4-bit adder consists of four full-adders cascaded together. The 7483 is a
4-bit adder that accepts two 4-bit numbers (A and B) and a carry input as inputs. It
provide a 4-bit sum output and a carry output. The logic symbol for a 4-bit adder is
shown in figure 1. To add two 4-bit binary number W= W3W2W1W0 and X = X3X2X1X0,
we will simply connect W3W2W1W0 to the A3A2A1A0 inputs of the 7483 and connect
X3X2X1X0 to the B3B2B1B0 inputs of the 7483. The Cin input will be connected to ground.
To subtract two 4-bit binary number W - X, using 2’s complement, we will
need to convert X to its 2’s complement by inverting X and adding 1 to the result. This
can be performed using the 7483 by connecting W3W2W1W0 to the A3A2A1A0 inputs
of the 7483 and connecting X3’X2’X1’X0’ to the B3B2B1B0 inputs of the 7483. The Cin
input will be connected to Vcc to complete the 2’s complement of X.
In order to implement both functions addition and subtraction, using the same 7485
IC, we need a control switch C that will select either addition (C = 0) or subtraction (C
= 1).
Therefore,
when C = 0
A3A2A1A0 = W3W2W1W0 B3B2B1B0 = X3X2X1X0
and Cin = 0
(1)
when C = 1
A3A2A1A0 = W3W2W1W0 B3B2B1B0 = X3’X2’X1’X0’
and Cin = 1
(2)
Figure 1
From equations 1 and 2, we can deduce the following:
AI  WI ,
BI  X I C  X I C  X i  C
and
Cin = C.
Figure 2, shows the 4 bit adder/subtractor circuit using the 7483 IC.
EQUIPMENT AND COMPONENTS


Digital Trainer
7486, 7483, DIP switches..
EENG 251: Digital Systems I
15
Dr. R. Al-Alawi
PROCEDURE
1.
2.
3.
4.
5.
6.
7.
Refer to the data sheets for the 7483 and 7486 data sheets to connect the adder/subtractor circuit
shown in figure 2.
Select the add mode (C = 0).
Demonstrate the 2’s complement addition by adding the following: 3+4, 2+(-4), 5+8 and (–7)+4
Record down your results, showing the sum, carry out and indicating if an overflow occurs.
Select the subtract mode (C = 1).
Demonstrate the 2’s complement addition by adding the following: 7-2, 4 - (-3), -5 –7, (-3) – 5.
Record down your results, showing the difference, carry out and indicating if an overflow occurs.
Figure 2
DISCUSSION AND CONCLUSION:
1.
2.
What range of positive and negative integers can be represented in a 32-bit computer
Design an overflow detection circuit.
EENG 251: Digital Systems I
16
Dr. R. Al-Alawi
UNIVERSITY OF BAHRAIN
C OLLEGE OF E NGINEERING
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
EENG 251: DIGITAL SYSTEMS I LABORATORY
EXPERIMENT NO. 7
SEQUENTIAL LOGIC CIRCUITS: J-K FLIP FLOPS
OBJECTIVE
After completing this experiment you will be able to operate and test J-K flip-flops using the 7476 IC.
COURSE INTENDED LEARNING OUTCOME
This lab assignment satisfies the Course Intended Learning Outcome 8 :
 Be able to design and implement synchronous sequential circuits using different types of Flip-Flops.
THEORY AND BACKGROUND
Flip flops are the basic building block of sequential networks. A flip flop has the ability to memorize 1
bit of information. A flip flop is a memory device that can assume one of two stable output states, which has a
pair of complementary outputs and has one or more inputs that can cause the output state to change.
The J-K flip flop has three inputs J, K and the clock, which is usually labeled CLK. There are two basic
types of triggering configurations employed when implementing a JK flop flop. A positive edge triggered flip flop
will transfer the input data to the output on the rising edge of the clock pulse. The negative edge triggered flip
flop will transfer the input data to the output on the falling edge of the clock pulse.
In this experiment the JK flip flop will be examined.
EQUIPMENT AND COMPONENTS


Digital Trainer
7476 J-K flip-flop IC.
PROCEDURE
1.
2.
3.
Insert the 7476 IC on the breadboard.
Refer to Fig. 1, wire the asynchronous inputs PS and CLR to two switches SW1 and SW2 respectively.
Wire the synchronous inputs J and K to switches to two switches SW3 and SW4 respectively and the
CLK input to single pulse switch.
EENG 251: Digital Systems I
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Dr. R. Al-Alawi
Fig. 1
4.
5.
Change the position of the PS switch (SW1) and the CLR switch (SW2) as shown in table1.
Record your result in table 1.
INPUTS
OUTPUTS
PS
CLR
0
0
0
1
1
0
1
1
Q
Q'
Name of condition
Prohibited
Table 1
6.
7.
8.
Disable the asynchronous inputs by setting them to logic high.
Change the position of the J switch (SW3) and the K switch (SW4) as shown in table 2.
Record the next state output for each combination of J, K and the present state Q.
Clock
CLK
Data
J
0
0
1
1
0
0
1
1
K
0
1
0
1
0
1
0
1
Present State
Q
Q'
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
Next State
Q+
Q+'
Name of
Condition
Table 2
9. Set all inputs (J, K, PR and CLR) to 1 and connect the CLK input of the flip-flop to 1KHz clock signal.
10. What is the condition of the flip-flop?
11. Use the oscilloscope to monitor both the clock input and Q of the flip flop. What is the relation between
the frequencies of both signals.
EENG 251: Digital Systems I
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Dr. R. Al-Alawi
DISCUSSION AND CONCLUSION:
Suppose that you connect the a 1 KHz clock to the clock input of two cascaded J-K flip flops, such that
both inputs of the first flip flop are connected to Vcc and its Q1 is connected to both inputs of the second J-K flip
flop. What will be the frequency output of the second flip flop. Draw the timing diagram showing the input clock
pulse, Q1 and Q0
EENG 251: Digital Systems I
19
Dr. R. Al-Alawi
UNIVERSITY OF BAHRAIN
C OLLEGE OF E NGINEERING
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
EENG 251: DIGITAL SYSTEMS I LABORATORY
EXPERIMENT NO. 8
DESIGN OF SYNCHRONOUS COUNTERS
OBJECTIVE
The objective of this lab experiment is to design, implement and test a synchronous counter with a given
count sequence.
COURSE INTENDED LEARNING OUTCOME
This lab assignment satisfies the Course Intended Learning Outcome 8 :
 Be able to practically design and implement a small digital system using the various components studied
in this course.
THEORY AND BACKGROUND
Counters are one of the simplest types of sequential networks. A counter is usually constructed from
two or more flip flops which change state in a prescribed sequence when input pulses are received. In this
experiment, you will learn a procedure for deriving the JK flip flop input equations for counters.
EQUIPMENT AND COMPONENTS



Digital Trainer
7476 (JK flip-flop)
7400 (NAND gates)
PROCEDURE:
DESIGN PROBLEM:
The instructor will ask you to design a 3-bit synchronous counter with a specific count sequence. You
should design the counter using JK flip-flops and NAND gates.
DESIGN STEPS:
1.
Construct the state table for the synchronous counter.
Present State
A
B
EENG 251: Digital Systems I
C
Next State
A+
B+
20
C+
Dr. R. Al-Alawi
2.
Draw the flip-flops next state maps as shown below.
AB
C
0
1
3.
4.
5.
6.
7.
AB
00
01
11
10
C
0
1
00
01
11
10
AB
C
0
1
00
01
11
Derive the J-K flip-flop’s input equations from the next state maps.
JA = ________________
JB = ________________
JC = ________________
KA = ________________
KB = ________________
KC = ________________
Draw the circuit diagram of the synchronous counter using JK flip-flops and 2-inputs NAND gates only.
Draw the pin diagram for the synchronous counter.
Mount the circuit on the digital trainer’s breadboard.
Test your circuit and verify that the generated counter sequence is identical to the desired sequence.
DISCUSSION AND CONCLUSION:


Redesign your counter using T flip flops.
Show how you can convert a JK flip flop to a T flip flop.
EENG 251: Digital Systems I
21
Dr. R. Al-Alawi
10
DATA SHEET
EENG 251: Digital Systems I
22
Dr. R. Al-Alawi
EENG 251: Digital Systems I
23
Dr. R. Al-Alawi