Microprocessor Evolution
and Architecture
Prof. Fayez F. M. El-Sousy
Department of Electrical Engineering
College of Engineering
Salman bin Abdulaziz University
Al-Kharj, Saudi Arabia
Prof. Fayez F. M. El-Sousy
1
Year
name
1971
1973
1973
1973
4004
8008
8080
Data
size
4
8
8
memory
#instructions
size
4096 4-bit 45 first microprocessor
16K bytes 48 1st 8-bit µP
64K bytes
10 times faster than 8008
1977
MC6800 8
8085
8
1978
1979
8086
8088
1981
1983
IBM decided to use 8088 in its personal computer
8,16
8,16
80286
8,16
1986
80386
8,16,32
1989
80486
8,16,32
1993
Pentium 8,16,32
1995
Pentium Pro 64
1997
Pentium II 64
1999
Pentium III
2000
Pentium 4
Prof.
Fayez F. M. El-Sousy
64K bytes
64K bytes
1st Motorola µP
246 Intel’s most successful 8-bit
general- purpose µP due to its
low cost Zilog’s Z808
most successful microprocessor
1M bytes >20,000 1st 16-bit µP
1M bytes
prefetch instruction using cache
16M
4G
4G
4G
64G
64G
2
Microprocessor-Based Computer System
µP
Address bus
Data bus
MWTC
MRDC
IOWC
IORC
Read-Only
Memory
(ROM)
Prof. Fayez F. M. El-Sousy
Read-Write
Memory
(RAM)
Keyboard
Printer
3
Microprocessors: CPU on a Chip
1968: INTEL (Integrated Electronics)
Founded by Robert Noyce and Gordon
Moore (Fairchild).
Original goals: semiconductor memory
market
1969: customized IC’s for Busicom for
calculator.
Ted Hoff and Stan Mazor: proposed 4-bit
CPU on a single chip, plus ROM, RAM
chips.
Prof. Fayez F. M. El-Sousy
4
Microprocessors: CPU on a Chip
1971: 4000 Family
By Fredrico Faggin
4001: 2K ROM with 4-bit I/O port
4002: 320-bit RAM, 4-bit output port
4003: 10-bit serial-in parallel-out shift
register
4004: 4-bit processor
Processor-on-a-chip: Micro-processor
Prof. Fayez F. M. El-Sousy
5
Microprocessors: CPU on a Chip
1972: 8008, 8-bit
1974: 8080, an improved version
Prof. Fayez F. M. El-Sousy
6
Microprocessors: CPU on a Chip
8-bit CPUs
16-bit address (64K)
MC6800: Motorola
6502: MOS Technology (spin-off from
Motorola)
o Apple-II, Apple DOS
Z-80: Zilog (spin-off from Intel)
o Z-80 cards on Apple-II, CP/M
Prof. Fayez F. M. El-Sousy
7
Microprocessors: CPU on a Chip
16-bit CPUs (Late 1970s)
8086, 80186, 80286: Intel
• PC, PC-DOS, MS-DOS, SCO-Unix
MC68000: Motorola
• 16-bit instructions
o Hardware multiply and divide
o 20-bit address buses (1MB)
o Workstations: Sun3
Prof. Fayez F. M. El-Sousy
8
Microprocessors: CPU on a Chip
32-bit CPUs
80386, 80486: Intel
MC68020, 68030: Motorola
64-bit CPUs
Pentium, Pentium Pro (64-bit external
data bus, 32-bit internal registers, not
recognized as 64-bit CPUs in terms of
internal register word length)
Prof. Fayez F. M. El-Sousy
9
Computers Based on Microprocessors
1975: MITS Altair 8800 (Kit)
$399, i8080, programmed by depositing
1s/0s via front panel switches
Other Computers boom
8080: MITS, …
6800: SWTPC 6800, …
Z-80: TRS-80, …
6502: Apple I, 8K, programmed with
BASIC
Steve Jobs & Steve Wozniak,
millionaires from PC COM’s …
Prof. Fayez F. M. El-Sousy
10
Personal Computers:
1982: IBM PC
A system board (mother board)
Intel 8088 processor
16K memory
5 expansion slots
Third-party vendors to supply various
IO adapter cards
Open architecture
Computer with interchangeable
components
Prof. Fayez F. M. El-Sousy
11
Micro-controllers: Microcomputers
on a Chip
Microcontroller: a computer on a chip
Microprocessor, plus
On-chip memory, plus
Input/output ports
1995: microcontrollers out sold microprocessors 10:1
embedded on various equipments:
Thermostat, machine tools,
communication, automotive, …
Evolution: getting greater IO capabilities
Intel: MCS-51, MCS-96, …
Prof. Fayez F. M. El-Sousy
12
Summary of Processor History
1940s: Vacuum tube, large and consuming
large power
1950s: Transistor (1948-)
1959: First IC (second industrial revolution)
1960s: IC was popular to build CPU’s.
1971: Intel 4004 microprocessor (2300
transistors)
Starts of the microprocessor age
Late 1970’s: 8080/85
Prof. Fayez F. M. El-Sousy
13
Summary of Processor History
1980: RISC (reduced instruction set
computer)
CISC (complicated instruction set computer)
vs. RISC
CISC family: Intel 80x86, Pentium; Motorola
68000 series
All others are RISC series.
Prof. Fayez F. M. El-Sousy
14
Moore’s Law
Prof. Fayez F. M. El-Sousy
15
Program Development
.SDT
Program
Program
(CVTSYM)
Symbol
Symbol
Converter
Converter
ICE
ICE
.SYM
Editor
Editor
.ASM
Assembler
Assembler
(X8051)
.OBJ
Linker
Linker
.HEX
(Link)
Target
Target
Prof. Fayez F. M. El-Sousy
16
The 8086 and 8088
Processor Model
Programming Model
Prof. Fayez F. M. El-Sousy
17
8086/8088 Processor Model:
Became available in 1978
16-bit data bus
20-bit address bus (was 16-bit for 8080)
memory organization: 16 segments of 64KB
(1 MB limit)
Re-organize CPU into BIU (bus interface unit) and
EU (execution unit)
Allow fetch and execution simultaneously
Internal register expanded to 16-bit
Allow access of low/high byte separately
Prof. Fayez F. M. El-Sousy
18
8086/8088 Processor Model :
Became available in 1979, almost identical to 8086
8-bit data bus: for hardware compatibility with 8080
16-bit internal registers and data bus (same as 8086)
20-bit address bus (was 16-bit for 8080)
BIU re-designed
memory organization: 16 segments of 64KB (1 MB limit)
Two memory accesses for 16-bit data (less
efficient)
But less cost
8088: used by IBM PC (1982), 16K-64K, 4.77MHz
Prof. Fayez F. M. El-Sousy
19
8086/8088 Processor Model :
Address Generation
and Bus Control
EU
BP
DI
SI
SP
AL
BL
CL
DL
Σ
CS
ES
SS
DS
IP
Instruction Queue
AH
BH
CH
DH
BIU
ALU
Prof. Fayez F. M. El-Sousy
Flags
20
8086/8088 Processor Model :
Both 8086/8088 employ parallel processing
Both 8086/8088 contain two processing units
BIU: bus interface unit
EU: execution unit
Both units operate at the same time
This parallel processing make the fetch and
execution of instruction independent
operation
Prof. Fayez F. M. El-Sousy
21
8086/8088 Processor Model :
Functions of the BIU
Interface to the external world
Responsible for all external bus operations
such as:
Instruction fetch
Memory Read/Write operations
I/O Read/Write operations
Instruction queuing and address
generation
Prof. Fayez F. M. El-Sousy
22
8086/8088 Processor Model :
Inside the BIU
BIU Contains:
Segment registers (CS,DS,SS,ES )
Instruction pointer (IP)
Address generation adder
Bus control logic
6 bytes Instruction Queue (FIFO)
Prof. Fayez F. M. El-Sousy
23
8086/8088 Processor Model :
Inside the EU
EU Contains:
ALU
Status and control flags
General purpose registers
Temporary operand registers
Prof. Fayez F. M. El-Sousy
24
8086/8088 Processor Model :
Basic Functions of the EU
Responsible for decoding and executing
instructions
Gets instructions from the output end of the
Queue
Accesses Data from general purpose
Registers
Check & update control flags
Generate operand addresses if necessary
Commands BIU for memory & I/O operations
Prof. Fayez F. M. El-Sousy
25
8086/8088 Processor Model: BIU+EU
BIU
Memory & I/O address generation
EU
Receive codes and data from BIU
• Not connected to system buses
Execute instructions
Save results in registers, or pass to BIU,
to memory and I/O
Prof. Fayez F. M. El-Sousy
26
8086/8088 Processor Model: Registers
Category
General
Bits
Register Names
16
AX, BX, CX, DX
8
AH, AL, BH, BL, CH, CL, DH, DL
Pointer
16
SP, BP
Index
16
SI, DI
Segment
16
CS, DS, SS, ES
Instruction
16
IP
Flag
16
Flag
Prof. Fayez F. M. El-Sousy
27
8086/8088 Processor Model: Registers
00000
External Memory
Address Space
IP
Code segment
64 k byte
CS
DS
SS
ES
Data Segment
64 K Byte
AH
BH
CH
DH
AL
BL
CL
DL
Stack segment
64 k Byte
SP
BP
SI
DI
Extra Segment
64 k Byte
Input / output
Address space
FFFF
28
Prof. Fayez F. M. El-Sousy
SR
0000
FFFFF
8086/8088 Processor Model: Segments
A segment is an area of memory that:
includes up to 64k bytes.
starts on an address evenly divided by
16.
each segment must be assigned a
Base Address that identifies its starting
point.
Prof. Fayez F. M. El-Sousy
29
8086/8088 Processor Model: Segments
An assembly program consists of three
segments:
Code Segment: contains the assembly
instructions.
Data Segment: used to store data that
needs to be processed.
Stack Segment: used for temp storage
of data.
Prof. Fayez F. M. El-Sousy
30
8086/8088 Processor Model: Segments
Segment Registers & Memory Segmentation:
Memory is segmented into 64 KB segments.
Only 4 of these segments can be activated at
a time.
The Code Segment
The Stack Segment
The Data Segment
The Extra Segment
Prof. Fayez F. M. El-Sousy
31
8086/8088 Processor Model: Segments
Base Address for a Memory Segment:
The location of each segment is held by a
register in the BIU.
CS register holds Code Segment Address
SS register holds Stack Segment Address
DS register holds Data Segment Address
ES register holds Extra Segment Address
Prof. Fayez F. M. El-Sousy
32
8086/8088 Processor Model: Memory
How much memory can be activated at a time?
Since only 4 segments can be activated at a
time, then the total memory can be activated
each time is:
4x64 = 256 KB
Prof. Fayez F. M. El-Sousy
33
8086/8088 Processor Model: Memory
Logical & Physical Address:
Three types of addresses:
Physical address: 20 bit actually put on
the address lines.
offset address: a location within a 64 KB
segment range.
logical address: consists of a segment
value & an offset.
Prof. Fayez F. M. El-Sousy
34
8086/8088 Processor Model: Memory
Logical & Physical Address:
FFFFF H
• Segment Registers:
– Point to Base Address
Code
Segment
Segment
Registers
CS
• Index Registers:
– Contain Offset Value
Extra
Segment
ES
SS
DS
Stack
Segment
• Notation (Segmented Address):
– CS:IP
– DS:SI
– ES:DI
– SS:BP
– SS:SP
Data
Segment
System
Memory
Prof. Fayez F. M.
El-Sousy
00000 H
35
8086/8088 Processor Model:
Memory Storage Organization
• Organized as SEGMENTS
– Maximum segment size = 64KB
– (Since 16 bit offsets: 216 = 65,535 = 64KB)
• Maximum Memory Size:
– 220 = 1,048,576 = 1MB
• Newer Processors (386+) Can Utilize More Memory
– Wider address registers 32 bits
– 232 = 4,294,967,296 = 4GB
Prof. Fayez F. M. El-Sousy
36
8086/8088 Processor Model: Memory
Logical & Physical Address:
FFFFF H
• Logical, Segmented Address:
0FE6:012Bh
Code
Segment
Segment
Registers
CS
Extra
Segment
• Offset, Index Address:
012Bh
ES
SS
DS
Stack
Segment
• Physical Address:
0FE60h → 65120
+ 012Bh → 299
0FF8Bh → 65149
Data
Segment
System
Memory
Prof. Fayez F. M.
El-Sousy
00000 H
37
8086/8088 Processor Model: Memory
Logical & Physical Address:
• Logical, Segmented Address 1:
DS:SI = 1234:4321
• Physical Address:
12340h → 74560
+ 4321h → 17185
16661h → 91745
Prof. Fayez F. M. El-Sousy
• Logical, Segmented Address 2:
ES:DI = 1665:0011
• Physical Address:
16650h → 91728
+ 0011h → 00017
16661h → 91745
38
8086/8088 Processor Model: Memory
Logical & Physical Address in Code Segment:
In the code segment CS & IP hold the
logical address for the instruction to be
executed.
The format is
IP=95F3
CS=2500
Adder
CS:IP
physical address A0-A19=2E5F3
0
Shift left CS one digit
Prof. Fayez F. M. El-Sousy
39
8086/8088 Processor Model: Memory
Logical & Physical Address in Code Segment:
If CS =2567 and IP=2341
The logical address 2567:2341
The offset address
:2341
The physical address 279B1
Prof. Fayez F. M. El-Sousy
40
8086/8088 Processor Model: Memory
Logical & Physical Address in Stack Segment:
In the stack segment SS & SP hold the logical
address to access the stack.
The format is
SS:SP
SP=95F3
SS=2500
Adder
physical address A0-A19=2E5F3
0
Shift left SS one digit
Prof. Fayez F. M. El-Sousy
41
8086/8088 Programming Model
7
Accumulator
Base
Counter
Data
0
7
AL
BL
CL
DL
AH
BH
CH
DH
15
Code Segment
Data Segment
Stack Segment
Extra Segment
Prof. Fayez F. M. El-Sousy
Destination
Index
AX
BX
CX
DX
0
CS
DS
SS
ES
15
Instruction Pointer
Stack Pointer
Base Pointer
Source Index
0
0
IP
SP
BP
SI
DI
}
}
}
42
8086/8088 Programming Model
General Purpose Registers
7
Accumulator
Base
Counter
Data
Prof. Fayez F. M. El-Sousy
0
AH
BH
CH
DH
7
0
AL
BL
CL
DL
AX
BX
CX
DX
43
8086/8088 Programming Model
Can Be Used Separately as 1-byte Registers
• AX = AH:AL
Temporary Storage to Avoid Memory
Access
Faster Execution
Avoids Memory Access
Some Special uses for Certain Instructions
Prof. Fayez F. M. El-Sousy
44
8086/8088 Programming Model
AX, Accumulator
Main Register for Performing Arithmetic
MUL/DIV must use AH, AL
“accumulator” Means Register with Simple ALU
BX, Base
Point to Translation Table in Memory
Holds Memory Offsets; Function Calls
CX, Counter
Index Counter for Loop Control
DX, Data
After Integer Division Execution - Holds Remainder
Prof. Fayez F. M. El-Sousy
45
8086/8088 Programming Model
CS, DS, ES, SS - Segment Registers
IP, SP, BP, SI, DI - Offset Registers
15
Code Segment
Data Segment
Stack Segment
Extra Segment
0
CS
DS
SS
ES
15
Instruction Pointer
Stack Pointer
Base Pointer
Source Index
Destination Index
Prof. Fayez F. M. El-Sousy
0
IP
SP
BP
SI
DI
}
}
}
46
8086/8088 Programming Model
CS, DS, ES, SS - Segment Registers
Contains “Base Value”
Value for Memory Address
CS, Code Segment
Used to “point” to Instructions
Determines a Memory Address (along with IP)
Segmented Address written as CS:IP
DS, Data Segment
Used to “point” to Data
Determines Memory Address (along with other registers)
ES, Extra Segment allows 2 Data Address Registers
SS, Stack Segment
Used to “point” to Data in Stack Structure (LIFO)
Used with SP or BP
SS:SP or SS:BP are valid Segmented Addresses
Prof. Fayez F. M. El-Sousy
47
8086/8088 Programming Model
IP, SP, BP, SI, DI - Offset Registers
Contains “Index Value”
Value for Memory Address
IP, Instruction Pointer
Used to “point” to Instructions
Determines a Memory Address (along with CS)
Segmented Address written as CS:IP
SI, Source Index;
DI, Destination Index
Used to “point” to Data
Determines Memory Address (along with other registers)
DS, ES commonly used
SP, Stack Pointer; BP, Base Pointer
Used to “point” to Data in Stack Structure (LIFO)
Used with SS
or SS:BP are valid Segmented Addresses
Prof. SS:SP
Fayez F. M. El-Sousy
48
8086/8088 Programming Model
Flags Register
Status and Control Bits Maintained in Flags Register
Generally Set and Tested Individually.
9 1-bit flags in 8086; 7 are unused
15
x
0
x
x
x OF DF IF TF SF ZF x AF x PF x CF
Prof. Fayez F. M. El-Sousy
49
8086/8088 Programming Model
Flags (Status) Register
Nine of its bits are implemented. Six of these
represent status flags: the carry flag (CF), parity
flag (PF), auxiliary flag (AF), zero flag (ZF), sign
flag (SF), and overflow (OF). The logic state of
these flags indicates conditions that are
produced as the result of executing an
instruction.
The summary of operation of these flags is given
below:
Prof. Fayez F. M. El-Sousy
50
8086/8088 Programming Model
Flags (Status) Register
Nine of its bits are implemented. Six of these
represent status flags: the carry flag (CF), parity
flag (PF), auxiliary flag (AF), zero flag (ZF), sign
flag (SF), and overflow (OF). The logic state of
these flags indicates conditions that are
produced as the result of executing an
instruction.
The summary of operation of these flags is given
below:
Prof. Fayez F. M. El-Sousy
51
8086/8088 Programming Model
Flags (Status) Register
Nine of its bits are implemented. Six of these
represent status flags: the carry flag (CF), parity
flag (PF), auxiliary flag (AF), zero flag (ZF), sign
flag (SF), and overflow (OF). The logic state of
these flags indicates conditions that are
produced as the result of executing an
instruction.
The summary of operation of these flags is given
below:
Prof. Fayez F. M. El-Sousy
52
8086/8088 Programming Model
Flags Register
CF
OF
ZF
SF
Carry Flag
Overflow Flag
Zero Flag
Sign Flag
PF
AF
DF
IF
TF
Parity Flag
Auxiliary Carry
Direction Flag
Interrupt Flag
Trap Flag
Prof. Fayez F. M. El-Sousy
Arithmetic Carry/Borrow
Arithmetic Overflow
Zero Result; Equal Compare
Negative Result; Non-Equal
Compare
Even Number of “1” bits
Used with BCD Arithmetic
Auto-Increment/Decrement
Enables Interrupts
Allows Single-Step
53
8086/8088 Programming Model
Flags Register
TF
DF
IF
OF
SF
Control Flags
ZF
AF
PF
CF
Status Flags
Interrupt Enable
Carry
Sign
Direction
Parity
Overflow
Trap
Prof. Fayez F. M. El-Sousy
Zero
Auxiliary Carry
54
8086/8088 Programming Model
Flags Register
TF
DF
IF
OF
SF
ZF
AF
PF
CF
Set whenever there is a carry out
either from D7 or from D15
Prof. Fayez F. M. El-Sousy
55
8086/8088 Programming Model
Flags Register
TF
DF
IF
OF
SF
ZF
AF
PF
CF
For some operations ,set if the loworder byte of the result has an EVEN
NUMBER of ones
Prof. Fayez F. M. El-Sousy
56
8086/8088 Programming Model
Flags Register
TF
DF
IF
OF
SF
ZF
AF
PF
CF
set if there is a carry from D3 to D4
Prof. Fayez F. M. El-Sousy
57
8086/8088 Programming Model
Flags Register
TF
DF
IF
OF
SF
ZF
AF
PF
CF
set if the result of arithmetic or logic
operation is zero
Prof. Fayez F. M. El-Sousy
58
8086/8088 Programming Model
Flags Register
TF
DF
IF
OF
SF
ZF
AF
PF
CF
after arithmetic or logic operations ,the status
of the sign bit is copied in to the SF
Prof. Fayez F. M. El-Sousy
59
8086/8088 Programming Model
Flags Register
TF
DF
IF
OF
SF
ZF
AF
PF
CF
Set when ever the result of a signed number
operation is too large; overflow in to the sign
bit
Prof. Fayez F. M. El-Sousy
60
8086/8088 Programming Model
Flags Register
TF
DF
IF
OF
SF
ZF
AF
PF
CF
When set , it allows the program to single step
TF
DF
IF
OF
SF
ZF
AF
PF
CF
Enable (when set) the external maskable interrupts
Prof. Fayez F. M. El-Sousy
61
8086/8088 Programming Model
Flags Register
TF
DF
IF
OF
SF
ZF
AF
PF
CF
Enable (when set) the external maskable interrupts
Prof. Fayez F. M. El-Sousy
62
8086/8088 Programming Model
Flags Register
TF
DF
IF
OF
SF
ZF
AF
PF
CF
To control the direction of string operations
When set , pointers are decremented automatically
Prof. Fayez F. M. El-Sousy
63