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Zynq Introduction: Part 2
PS/PL AXI Ports
Interfacing the PL to the PS
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Zynq PS/PL AXI Ports - 2-3
Interfacing the PL to the PS
Interconnect in the PS
AXI Master Interfaces
AXI Slave Interfaces
AXI ACP Interface
Summary
© Copyright 2013 Xilinx
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Interfacing to Programmable Logic
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Most of the interfaces between the PS and PL are accomplished
with nine AXI ports
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Two general-purpose master ports
Two general-purpose slave ports
Four high-performance slave ports
One accelerator coherence port (ACP) slave port
An understanding of PS interconnect (switches) operation is
necessary for proper design use of the various ports
Other diagnostic, clock, and interrupt signals complete the PS-PL
interface
Zynq PS/PL AXI Ports - 2-4
© Copyright 2013 Xilinx
PL and PS AXI Port Terminology
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There are two genders of AXI ports
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Master: M_AXI_GP0 – transaction initiator
Slave: S_AXI_GP0 – transaction target
Like ports cannot connect together (master can
not connect to master and slave not to slave)
All PL to PS and PS to PL AXI ports are AXI3
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All five AXI channels are implemented
Address and data buses
Zynq PS/PL AXI Ports - 2-5
© Copyright 2013 Xilinx
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AMBA AXI 3.0
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The PS-PL AXI ports are based on the AMBA® AXI 3.0 version of
the protocol
Xilinx IP is committed to the AMBA AXI 4.0 version of the protocol
The two versions are very close
Xilinx tools automatically build a logic shim interface as needed
to adapt between the two
Differences between AXI3 and AXI4:
AXI3
AXI4
Max burst size 16 beats
Max burst size 256 beats
N/A (Zynq includes QOS on PS HP and
ACP ports)
Support for QOS
N/A
Support for multiple REGIONs
Requires BRESP not to be given until
Requires BRESP not to be given until
one clk after the acceptance of last data one clk after the acceptance of last data
transfer
transfer and not to be given until one
clk after address acceptance
Zynq PS/PL AXI Ports - 2-6
© Copyright 2013 Xilinx
Interconnect in the PS
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Zynq PS/PL AXI Ports - 2-7
Interfacing the PL to the PS
Interconnect in the PS
AXI Master Interfaces
AXI Slave Interfaces
AXI ACP Interface
Summary
© Copyright 2013 Xilinx
A Picture is Worth a Thousand Words
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Understanding the PS interconnect facilitates a high-performance
Zynq architecture design
The PS has six interconnect structures to facilitate data
movement
Sometimes paths may need to make their way through multiple
switches
Trade-offs exist between
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PS peripheral access
Performance
PL AXI port access and loading
(Pictures are on the following slides)
Zynq PS/PL AXI Ports - 2-8
© Copyright 2013 Xilinx
PS Top-Level Interconnect Diagram (1)
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Zynq PS/PL AXI Ports - 2-9
© Copyright 2013 Xilinx
PS Top-Level Interconnect Diagram (2)
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Zynq PS/PL AXI Ports - 2-10
© Copyright 2013 Xilinx
AXI Master Interfaces
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Zynq PS/PL AXI Ports - 2-11
Interfacing the PL to the PS
Interconnect in the PS
AXI Master Interfaces
AXI Slave Interfaces
AXI ACP Interface
Summary
© Copyright 2013 Xilinx
General-Purpose Master AXI Ports
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Two identical AXI master ports
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M_AXI_GP0
M_AXI_GP1
Provides initiator access from the PS-to-PL target in
programmable logic
Attaches to a slave AXI port in programmable logic
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PL AXI interconnect
PL slave
 Your peripheral built in programmable logic
 IP Integrator interface or other third-party-based IP
Why two ports?
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Each port is capable of driving a number of peripherals using an AXI switch
Multiple ports enable the designer to balance bandwidth
Zynq PS/PL AXI Ports - 2-12
© Copyright 2013 Xilinx
General-Purpose Master AXI Port Features
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Two 32-bit AXI master interfaces
Allows PS masters access to PL devices
Each master is allocated a 1GB address space
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Addresses start at 0x40000000 and 0x80000000, respectively
Only low-order 30 bits of AXI address are meaningful
PS masters can be
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Cortex-A9 processors via the L2 cache controller
USB controller (2)
Ethernet controller (2)
SD/SDIO controllers (2)
DMAC
Debug access port
Mostly used for CPU and IOP data movement to programmable
logic
Zynq PS/PL AXI Ports - 2-13
© Copyright 2013 Xilinx
AXI Slave Interfaces
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Zynq PS/PL AXI Ports - 2-14
Interfacing the PL to the PS
Interconnect in the PS
AXI Master Interfaces
AXI Slave Interfaces
AXI ACP Interface
Summary
© Copyright 2013 Xilinx
General-Purpose Slave AXI Ports
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Two identical AXI slave ports
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S_AXI_GP0
S_AXI_GP1
Provides initiator access from PL master to PS target
Attaches to master AXI port in PL
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PL AXI interconnect
PL master
 MicroBlaze processor
 Your master built in programmable logic
 Other third-party-based IP
Zynq PS/PL AXI Ports - 2-15
© Copyright 2013 Xilinx
General-Purpose Slave AXI Port Features
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Two 32-bit AXI slave interfaces
Allows PL masters to access PS slaves
PS slaves can be
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DDRx controller
On-chip memory (OCM)
IOP peripheral
Device configuration controller (DEVC)
Debug access port (DAP)
Mostly used for PL masters to access IOP, OCM RAM, and DDRx
(simple access)
Zynq PS/PL AXI Ports - 2-16
© Copyright 2013 Xilinx
High-Performance Slave AXI Ports and Features
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Four identical AXI slave ports
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S_AXI_HP0
S_AXI_HP1
S_AXI_HP2
S_AXI_HP3
Provides initiator access from PL master to PS memory
Attaches to master AXI port in PL
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PL AXI interconnect
PL master
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DMA controller
MicroBlaze processor
Your master built in programmable logic
Other third-party-based IP
Zynq PS/PL AXI Ports - 2-17
© Copyright 2013 Xilinx
AXI FIFO Interface (AFI) Diagram
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Zynq PS/PL AXI Ports - 2-19
© Copyright 2013 Xilinx
High-Performance PL to DDR Interfacing
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Four AXI FIFO interfaces (AFI) incorporated into the S_AXI_HPx
ports
Connects to PL memory interconnect located in PS
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32-bit or 64-bit datapath from PL
Two crossbar channels directly to the DDRx memory controller (DMC)
 64 bit interface between PL to Memory interconnect and DMC
Zynq PS/PL AXI Ports - 2-20
© Copyright 2013 Xilinx
High-Performance PL to OCM Interfacing
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Access to 256Kb of PS OCM RAM
Access to OCM boot ROM disabled for security
Uses the same PL AFI interface and PS interconnect as the DMC
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One channel from PL memory interconnect to OCM interconnect (both
located in PS)
Two levels of PS interconnect before reaching OCM
providing very low latency and high bandwidth connection
Internal 64-bit datapath for interconnects and OCM
Zynq PS/PL AXI Ports - 2-21
© Copyright 2013 Xilinx
AXI ACP Interface
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Zynq PS/PL AXI Ports - 2-22
Interfacing the PL to the PS
Interconnect in the PS
AXI Master Interfaces
AXI Slave Interfaces
AXI ACP Interface
Summary
© Copyright 2013 Xilinx
Accelerator Coherence Port (ACP) Slave Port
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One accelerator coherence port (ACP)
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S_AXI_ACP
Provides initiator access from PL master to PS target
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Via the Snoop Control Unit (SCU) to L1 and L2 cache
From L2 cache, the ACP can reach anyplace the CPU can
ACP looks like another CPU to the SCU
Attaches to master AXI port in PL
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Typically a PL-based co-processor
Also could be (extreme design scenarios)
 PL AXI interconnect
 PL master
o MicroBlaze processor
o Custom master built in programmable logic
o Other third-party-based IP
Zynq PS/PL AXI Ports - 2-23
© Copyright 2013 Xilinx
Accelerator Coherence Port (ACP) Slave Port
Features
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64-bit AXI slave port from PS
Direct connection to the snoop control unit (SCU)
Cache coherent with L1 and L2 caches
Coordinated PL co-processor design with PL event ports
Facilitates tightly coupled PL co-processor design
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Performance relies on PL co-processor access cache hits
Software and co-processor access both use cached memory accesses
 Software program coordinated with co-processor design
 Preferably L1 cache hit over L2
 Direct access to memory (cache miss) slower than access by HPx slave port
Zynq PS/PL AXI Ports - 2-24
© Copyright 2013 Xilinx
Accelerator Coherence Port (ACP) Slave Port
Coherency Requests
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ACP transactions are normally filtered through
caches
Referred to as a cache coherent request
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L1 and L2
A L1 cache miss tries the L2 cache
 A L2 cache miss goes to DDR access
A L1 cache miss can be forced
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Referred to as a non-coherent request
Performed on a transaction basis by applying either/or of the AXI signals
 ARUSER[0] = 0
 ARCACHE[1] =0
Zynq PS/PL AXI Ports - 2-25
© Copyright 2013 Xilinx
Enhanced Accelerator SoC Integration
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ARM MPCore: accelerator coherence port (ACP)
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Sharing benefits of the ARM MPCore optimized coherency design
Accelerators gain access to CPU cache hierarchy
Compatible with standard un-cached peripherals and accelerators
Zynq PS/PL AXI Ports - 2-26
© Copyright 2013 Xilinx
Summary
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Zynq PS/PL AXI Ports - 2-27
Interfacing the PL to the PS
Interconnect in the PS
AXI Master Interfaces
AXI Slave Interfaces
AXI ACP Interface
Summary
© Copyright 2013 Xilinx
What are the Differences Between Slave HPx,
GPx, and ACP?
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The four S_AXI_HPx ports can only access the PS OCM and DMC
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Purpose is low-latency PL to memory access
FIFOs built into interface allow for streaming
The two S_AXI_GPx ports can access most PS peripherals,
including memory
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Purpose is programmable logic access to PS IOP and other PS slaves
Much slower access to OCM and DDRx memory
Single S_AXI_ACP can access all PS memory and peripherals
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Purpose is programmable logic co-processor memory interface
 Performance advantage through cache hits
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Lower latency then HPx for cache misses
Zynq PS/PL AXI Ports - 2-28
© Copyright 2013 Xilinx
Apply Your Knowledge
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1. List the PS AXI interfaces to the PL
2. Describe the use of the PS master interface to the PL
3. List the PS components that are accessible from the PL via the
AXI slave interface
Zynq PS/PL AXI Ports - 2-29
© Copyright 2013 Xilinx
Summary
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Nine AXI ports are used to move data between the PS and the PL
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Two general-purpose masters (M_AXI_GPx)
Two general-purpose slaves (S_AXI_GPx)
Four high-performance slaves for DDRx access (S_AXI_HPx)
One slave for DDRx access via processor cache (S_AXI_ACP)
Six PS interconnects provide pathways for PS components and
PS/PL AXI ports
Zynq PS/PL AXI Ports - 2-30
© Copyright 2013 Xilinx
Support
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For questions on this training, please contact
your local Zynq Subject Matter Expert (SME).