start_gui
open_project D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.xpr
open_project D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx_2021_1/Vivado/2021.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/calibration.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_ca_cal.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_ca_vref_cal.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_cal.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_read_mgchk.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_write_mgchk.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_dqs_gate.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_rd_cal.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_rd_dbi_cal.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_rd_vref_cal.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_write_complex.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_write_dqs_to_dq.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_write_latency_cal.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_write_prbs.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_wrlvl.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ddr_wrvref.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/function_dec.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/function_def.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/lpddr4_init_seq.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/lrdimm_cal.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/skip_ddr_dqs_gate.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/skip_ddr_rd_cal.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/skip_ddr_rd_dbi_cal.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/test_ddr4.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/test_lpddr4.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/xsdb_functions.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/register_dump.c'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/cal_reg_define.h'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/global_variable_define.h'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/internal_reg_define.h'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/mc_reg_define.h'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/ral_ddrmc_main.h'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/riu_reg_define.h'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/svdpi.h'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/vmm_ral.h'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/xsdb_reg_define.h'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/register_dump.h'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/make_gcc.bat'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'bd_8be5_MC0_ddrc_0_phy' generated file not found 'd:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/temp/make_gcc.sh'. Please regenerate to continue.
open_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 1556.215 ; gain = 0.000
update_compile_order -fileset sources_1
launch_simulation
Command: launch_simulation INFO: [Vivado 12-12493] Simulation top is 'design_1_wrapper_sim_wrapper'
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Runs 36-567] Checking/generating simulation output products for IPs/BDs (if any)...
INFO: [Vivado 12-12507] Checking for NoC blocks in the design (if any)...
INFO: [Vivado 12-12506] Checking for LNoC instances in the design (if any)...
Wrote : <D:\Xilinx_Device\Versal\NOC_DDR_3_01\NOC_DDR_3_01.srcs\sim_1\bd\xlnoc\xlnoc.bd> INFO: [Vivado 12-12510] Generated 'xlnoc.bd' in 'D:\Xilinx_Device\Versal\NOC_DDR_3_01\NOC_DDR_3_01.srcs\sim_1\bd\xlnoc'
INFO: [Vivado 12-12511] Generating simulation output products for 'D:\Xilinx_Device\Versal\NOC_DDR_3_01\NOC_DDR_3_01.srcs\sim_1\bd\xlnoc\xlnoc.bd'
WARNING: [BD 41-2670] Found an incomplete address path from address space '/nps_0_SNPP_N' to slave interface '/nps_0/SNPP_N'. Please either complete or remove this path to resolve.
WARNING: [BD 41-2670] Found an incomplete address path from address space '/nps_1_SNPP_S' to slave interface '/nps_1/SNPP_S'. Please either complete or remove this path to resolve.
Wrote : <D:\Xilinx_Device\Versal\NOC_DDR_3_01\NOC_DDR_3_01.srcs\sim_1\bd\xlnoc\xlnoc.bd> VHDL Output written to : d:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sim_1/bd/xlnoc/synth/xlnoc.v
VHDL Output written to : d:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sim_1/bd/xlnoc/sim/xlnoc.v
VHDL Output written to : d:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sim_1/bd/xlnoc/hdl/xlnoc_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block nps_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nps_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block nps_2 .
Exporting to file d:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sim_1/bd/xlnoc/hw_handoff/xlnoc.hwh
Generated Block Design Tcl file d:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sim_1/bd/xlnoc/hw_handoff/xlnoc_bd.tcl
Generated Hardware Definition File d:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sim_1/bd/xlnoc/synth/xlnoc.hwdef
INFO: [Vivado 12-12512] Generating simulation wrapper for instatiating design hierarchy and 'xlnoc.bd'...
INFO: [Vivado 12-12514] Simulation wrapper generated: 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.srcs/sources_1/common/hdl/design_1_wrapper_sim_wrapper.v'
INFO: [Vivado 12-12505] Adding 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.srcs/sources_1/common/hdl/design_1_wrapper_sim_wrapper.v' wrapper to simulation fileset 'sim_1'...
WARNING: [filemgmt 56-12] File 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.srcs/sources_1/common/hdl/design_1_wrapper_sim_wrapper.v' cannot be added to the project because it already exists in the project, skipping this file
INFO: [Vivado 12-12515] Updating design compile order...
INFO: [Vivado 12-12508] Compile order up-to-date.
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx_2021_1/Vivado/2021.1/tps/boost_1_72_0'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'C:/Xilinx_2021_1/Vivado/2021.1/data/xsim/xsim.ini' copied to run dir:'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.sim/sim_1/behav/xsim'
INFO: [SIM-utils-50] Design contains embedded sources, generating MEM files for simulation...
INFO: [SIM-utils-54] Inspecting design source files for 'design_1_wrapper_sim_wrapper' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.sim/sim_1/behav/xsim/design_1_noc_tg_0_pattern.csv'
INFO: [SIM-utils-43] Exported 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.sim/sim_1/behav/xsim/design_1_noc_tg_0.mem'
INFO: [SIM-utils-43] Exported 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.sim/sim_1/behav/xsim/all_in_one.csv'
INFO: [SIM-utils-43] Exported 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.sim/sim_1/behav/xsim/nocattrs.dat'
INFO: [SIM-utils-43] Exported 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.sim/sim_1/behav/xsim/xlnoc.bd'
INFO: [SIM-utils-43] Exported 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.sim/sim_1/behav/xsim/xlnoc.bda'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.sim/sim_1/behav/xsim'
"xvlog --incr --relax -L uvm -L clk_gen_sim_v1_0_0 -L sim_trig_v1_0_6 -L axi4stream_vip_v1_1_10 -L axi_vip_v1_1_10 -L perf_axi_tg_v1_0_13 -L axi_pmon_v1_0_0 -L noc_nps_v1_0_0 -L noc_na_v1_0_0 -L xilinx_vip -prj design_1_wrapper_sim_wrapper_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/xlnoc/sim/xlnoc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module xlnoc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/xlnoc/ip/xlnoc_nps_0_0/hdl/bfm/xlnoc_nps_0_0_top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module xlnoc_nps_0_0_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/xlnoc/ip/xlnoc_nps_0_0/hdl/bfm/xlnoc_nps_0_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module xlnoc_nps_0_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/xlnoc/ip/xlnoc_nps_1_0/hdl/bfm/xlnoc_nps_1_0_top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module xlnoc_nps_1_0_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/xlnoc/ip/xlnoc_nps_1_0/hdl/bfm/xlnoc_nps_1_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module xlnoc_nps_1_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/xlnoc/ip/xlnoc_nps_2_0/hdl/bfm/xlnoc_nps_2_0_top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module xlnoc_nps_2_0_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/xlnoc/ip/xlnoc_nps_2_0/hdl/bfm/xlnoc_nps_2_0.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module xlnoc_nps_2_0
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module noc_nmu_v1_0_0_npp_monitor
INFO: [VRFC 10-311] analyzing module scoreboard_nmu
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2204]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2223]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2236]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2250]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2259]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2281]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2300]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2313]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2327]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2336]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2347]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2366]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2400]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2410]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2424]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2443]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2477]
WARNING: [VRFC 10-8469] attribute 'SW_TYPE' is already specified, previous one will be overwritten [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:2487]
INFO: [VRFC 10-311] analyzing module nmu
INFO: [VRFC 10-2458] undeclared symbol areset_n, assumed default net type wire [../../../../NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/nmu_axi_monitor.sv:35]
WARNING: [VRFC 10-8447] parameter 'TIMEOUT' declared inside generate block shall be treated as localparam [../../../../NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/nmu_axi_monitor.sv:7]
WARNING: [VRFC 10-3507] macro 'MEM_DEPTH' redefined [../../../../NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/noc_npp_defines_nmu.vh:32]
WARNING: [VRFC 10-3507] macro 'xil_fatal' redefined [../../../../NOC_DDR_3_01.gen/sources_1/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/noc_npp_sb_nmu.sv:47]
INFO: [VRFC 10-311] analyzing module noc_npp_debug_monitor_nmu
INFO: [VRFC 10-311] analyzing module BM_NOC_NMU512
INFO: [VRFC 10-311] analyzing module BM_NOC_NMU256
WARNING: [VRFC 10-159] /* in comment [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:6280]
WARNING: [VRFC 10-159] /* in comment [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:6281]
INFO: [VRFC 10-311] analyzing module BM_NOC_NMU128
WARNING: [VRFC 10-159] /* in comment [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:7149]
WARNING: [VRFC 10-159] /* in comment [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv:7150]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/bd_8be5_S00_AXI_nmu_0_top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module bd_8be5_S00_AXI_nmu_0_top
WARNING: [VRFC 10-965] invalid size of integer constant literal [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/bd_8be5_S00_AXI_nmu_0_top.sv:547]
WARNING: [VRFC 10-965] invalid size of integer constant literal [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/bd_8be5_S00_AXI_nmu_0_top.sv:561]
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_sim_trig_0/design_1_noc_sim_trig_0_sim_netlist.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_noc_sim_trig_0
INFO: [VRFC 10-311] analyzing module design_1_noc_sim_trig_0_sim_trig_synchronizer
INFO: [VRFC 10-311] analyzing module design_1_noc_sim_trig_0_top
INFO: [VRFC 10-311] analyzing module design_1_noc_sim_trig_0_traffic_shapping
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_pmon_0/sim/design_1_noc_tg_pmon_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_noc_tg_pmon_0
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0_clocking_structure.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_clk_wiz_0_clocking_structure
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0_clocking_MBUFGCE_CE_DLY.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_clk_wiz_0_clocking_MBUFGCE_CE_DLY
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0/design_1_clk_wiz_0_clk_wiz_top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_clk_wiz_0_clk_wiz_top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_clk_wiz_0/sim/design_1_clk_wiz_0.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_clk_wiz_0
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_rst_clk_wiz_100M_0/design_1_rst_clk_wiz_100M_0_sim_netlist.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_rst_clk_wiz_100M_0
INFO: [VRFC 10-311] analyzing module design_1_rst_clk_wiz_100M_0_cdc_sync
INFO: [VRFC 10-311] analyzing module design_1_rst_clk_wiz_100M_0_cdc_sync_0
INFO: [VRFC 10-311] analyzing module design_1_rst_clk_wiz_100M_0_lpf
INFO: [VRFC 10-311] analyzing module design_1_rst_clk_wiz_100M_0_proc_sys_reset
INFO: [VRFC 10-311] analyzing module design_1_rst_clk_wiz_100M_0_sequence_psr
INFO: [VRFC 10-311] analyzing module design_1_rst_clk_wiz_100M_0_upcnt_n
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/sim/design_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_wrapper
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.srcs/sources_1/common/hdl/design_1_wrapper_sim_wrapper.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module design_1_wrapper_sim_wrapper
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2172.641 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '5' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.sim/sim_1/behav/xsim'
"xelab -wto ac53d261f4ce4b958ddb54aad2d1ec98 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L noc_nps_v1_0_0 -L xlconstant_v1_1_7 -L noc_na_v1_0_0 -L clk_gen_sim_v1_0_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_24 -L axi_vip_v1_1_10 -L axis_infrastructure_v1_1_0 -L axi4stream_vip_v1_1_10 -L perf_axi_tg_v1_0_13 -L axi_pmon_v1_0_0 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot design_1_wrapper_sim_wrapper_behav xil_defaultlib.design_1_wrapper_sim_wrapper xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator v2021.1
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx_2021_1/Vivado/2021.1/bin/unwrapped/win64.o/xelab.exe -wto ac53d261f4ce4b958ddb54aad2d1ec98 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L noc_nps_v1_0_0 -L xlconstant_v1_1_7 -L noc_na_v1_0_0 -L clk_gen_sim_v1_0_0 -L axi_infrastructure_v1_1_0 -L axi_register_slice_v2_1_24 -L axi_vip_v1_1_10 -L axis_infrastructure_v1_1_0 -L axi4stream_vip_v1_1_10 -L perf_axi_tg_v1_0_13 -L axi_pmon_v1_0_0 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot design_1_wrapper_sim_wrapper_behav xil_defaultlib.design_1_wrapper_sim_wrapper xil_defaultlib.glbl -log elaborate.log Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 7 for port 'rd2wr_ptr' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:15586]
WARNING: [VRFC 10-3091] actual bit length 11 differs from formal bit length 1273 for port 'data_in' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:15624]
WARNING: [VRFC 10-3091] actual bit length 11 differs from formal bit length 1273 for port 'data_out' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:15628]
WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 7 for port 'rd2wr_ptr' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:15631]
WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 1273 for port 'data_in' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:15650]
WARNING: [VRFC 10-3091] actual bit length 5 differs from formal bit length 1273 for port 'data_out' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:15653]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'TIMEOUT' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:10981]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'TIMEOUT' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:11010]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'TIMEOUT' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:11040]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'TIMEOUT' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:11069]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 8 for port 'TIMEOUT' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:11098]
WARNING: [VRFC 10-3091] actual bit length 13 differs from formal bit length 8 for port 'na2dc_txn_timer_0' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:11127]
WARNING: [VRFC 10-3091] actual bit length 13 differs from formal bit length 8 for port 'na2dc_txn_timer_1' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:11142]
WARNING: [VRFC 10-3091] actual bit length 6 differs from formal bit length 5 for port 'read_add_0' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:11375]
WARNING: [VRFC 10-3091] actual bit length 6 differs from formal bit length 5 for port 'read_add_1' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:11376]
WARNING: [VRFC 10-3091] actual bit length 6 differs from formal bit length 5 for port 'read_add_2' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:11377]
WARNING: [VRFC 10-3091] actual bit length 6 differs from formal bit length 5 for port 'read_add_3' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:11378]
WARNING: [VRFC 10-3091] actual bit length 13 differs from formal bit length 8 for port 'na2dc_txn_timer' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_top.sv:3720]
WARNING: [VRFC 10-3091] actual bit length 13 differs from formal bit length 8 for port 'na2dc_txn_timer' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_top.sv:3831]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 16 for port 'IF_NOC_AXI_AWID' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/bd_8be5_S00_AXI_nmu_0_top.sv:530]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 16 for port 'IF_NOC_AXI_BID' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/bd_8be5_S00_AXI_nmu_0_top.sv:535]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 16 for port 'IF_NOC_AXI_RID' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/bd_8be5_S00_AXI_nmu_0_top.sv:541]
WARNING: [VRFC 10-3091] actual bit length 96 differs from formal bit length 64 for port 'IF_NOC_AXI_ARADDR' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/bd_8be5_S00_AXI_nmu_0_top.sv:547]
WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 16 for port 'IF_NOC_AXI_ARID' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/bd_8be5_S00_AXI_nmu_0_top.sv:552]
WARNING: [VRFC 10-3091] actual bit length 96 differs from formal bit length 64 for port 'IF_NOC_AXI_AWADDR' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/bd_8be5_S00_AXI_nmu_0_top.sv:561]
WARNING: [VRFC 10-3091] actual bit length 10 differs from formal bit length 9 for port 'mem_addr' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_tg_top.sv:660]
WARNING: [VRFC 10-3091] actual bit length 10 differs from formal bit length 9 for port 'addra' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/axi_inst_core.sv:402]
WARNING: [VRFC 10-3091] actual bit length 10 differs from formal bit length 9 for port 'addrb' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/axi_inst_core.sv:403]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'ena' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/axi_inst_core.sv:412]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'regceb' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/axi_inst_core.sv:426]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'ena' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/inst_fifo.sv:224]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'regceb' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/inst_fifo.sv:238]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'reg_cfg_addr_mask_en' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_tg_top.sv:790]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'reg_cfg_addr_mask_val' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_tg_top.sv:791]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'reg_cfg_addr_mask_en' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_tg_top.sv:944]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'reg_cfg_addr_mask_val' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_tg_top.sv:945]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'clear' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_reg_space.sv:1157]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'clear' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_reg_space.sv:1177]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'clear' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_reg_space.sv:1242]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'clear' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_reg_space.sv:1271]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'clear' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_reg_space.sv:1296]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'clear' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_reg_space.sv:1312]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'clear' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_reg_space.sv:1326]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'clear' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_reg_space.sv:1347]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'clear' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_reg_space.sv:1365]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'clear' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_reg_space.sv:1381]
WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'clear' [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_reg_space.sv:1396]
WARNING: [VRFC 10-5021] port 'from_noc_0' is not connected on this instance [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/sim/bd_8be5.v:378]
WARNING: [VRFC 10-5021] port 'lpddr4_odt_ca_a' is not connected on this instance [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/bd_8be5_MC0_ddrc_0_phy_ddr_responder.sv:98]
WARNING: [VRFC 10-5021] port 'main_regs_clk' is not connected on this instance [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_top.sv:2486]
WARNING: [VRFC 10-5021] port 'dc2na_rd_wrap_det' is not connected on this instance [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_top.sv:3327]
WARNING: [VRFC 10-5021] port 'fifo_rden_dly' is not connected on this instance [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_top.sv:3652]
WARNING: [VRFC 10-5021] port 'fifo_rden_dly' is not connected on this instance [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_top.sv:3763]
WARNING: [VRFC 10-5021] port 'reg_ddrmc_nsu_r_egr' is not connected on this instance [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:10121]
WARNING: [VRFC 10-5021] port 'reg_ddrmc_nsu_r_egr' is not connected on this instance [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:10226]
WARNING: [VRFC 10-5021] port 'reg_ddrmc_nsu_r_egr' is not connected on this instance [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:10385]
WARNING: [VRFC 10-5021] port 'reg_ddrmc_nsu_r_egr' is not connected on this instance [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:10485]
WARNING: [VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:11637]
WARNING: [VRFC 10-3597] non-void function 'genblk6.rd_en_gen' called as a task without void casting [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:3770]
WARNING: [VRFC 10-3597] non-void function 'genblk7.rd_en_gen' called as a task without void casting [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:4442]
WARNING: [VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:5486]
WARNING: [VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:5493]
WARNING: [VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:5500]
WARNING: [VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:5507]
WARNING: [VRFC 10-696] first argument of $fatal is invalid, expecting 0, 1 or 2 [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:15567]
WARNING: [VRFC 10-3597] non-void function 'txnq_get_next_state' called as a task without void casting [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv:2648]
WARNING: [VRFC 10-5021] port 'IF_NOC_AXI_TDEST' is not connected on this instance [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/bfm/bd_8be5_S00_AXI_nmu_0_top.sv:334]
WARNING: [VRFC 10-5021] port 'tready' is not connected on this instance [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/csv_sptg/rtl/tg_rtl/design_1_noc_tg_0_syn_top.sv:412]
WARNING: [VRFC 10-5021] port 'IF_NOC_NPP_IN0_NOC_CREDIT_RDY' is not connected on this instance [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/xlnoc/sim/xlnoc.v:96]
WARNING: [VRFC 10-5021] port 'IF_NOC_NPP_IN0_NOC_CREDIT_RDY' is not connected on this instance [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/xlnoc/sim/xlnoc.v:113]
WARNING: [VRFC 10-5021] port 'IF_NOC_NPP_IN2_NOC_CREDIT_RDY' is not connected on this instance [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/xlnoc/sim/xlnoc.v:130]
WARNING: [VRFC 10-3705] select index 23 into 'REG_CONFIG0' is out of bounds [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:7855]
WARNING: [VRFC 10-3705] select index 24 into 'REG_CONFIG0' is out of bounds [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:7856]
WARNING: [VRFC 10-3705] select index 25 into 'mcal_CA_A' is out of bounds [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv:4024]
WARNING: [VRFC 10-3705] select index 25 into 'mcal_CA_A' is out of bounds [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv:4034]
WARNING: [VRFC 10-3705] select index 25 into 'mcal_CA_A' is out of bounds [D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv:4046]
Completed static elaboration
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 5486, File /wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 5493, File /wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 5500, File /wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 5507, File /wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 15567, File /wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 11637, File /wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv
INFO: [XSIM 43-4329] Assuming default value 1 for the first arguement of $fatal at Line 4086, File D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_top.sv
Starting simulation data flow analysis
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=1,RST_VAL=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=1,RST_VAL=1'b0) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=18,RST_VAL=18'b0) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=12,RST_VAL=12'b111111111111) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=3,RST_VAL=3'b0) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=1,RST_VAL=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(RST_VAL=32'b010011100010000) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(RST_VAL=32'b011010110110110000) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=1,RST_VAL=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=1,RST_VAL=1'b0) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=18,RST_VAL=18'b0) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=12,RST_VAL=12'b111111111111) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=3,RST_VAL=3'b0) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(DATA_WIDTH=1,RST_VAL=1'b1) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(RST_VAL=32'b010011100010000) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-4099] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/perf_axi_tg_v1_0/hdl/rtl/cfg_reg_rw.sv" Line 1. Module cfg_reg_rw(RST_VAL=32'b011010110110110000) doesn't have a timescale but at least one module in design has a timescale.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/tb/lpddr4_model/lpddr4_model.sv" Line 677 : The SystemVerilog feature ": Sensitivity on Associative Array" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv" Line 4733 : The SystemVerilog feature ": Sensitivity on Class Property, Queue/Associative/Dynamic Array Element, Select expression on a String" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv" Line 4733 : The SystemVerilog feature ": Sensitivity on Class Property, Queue/Associative/Dynamic Array Element, Select expression on a String" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv" Line 4733 : The SystemVerilog feature ": Sensitivity on Class Property, Queue/Associative/Dynamic Array Element, Select expression on a String" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv" Line 4733 : The SystemVerilog feature ": Sensitivity on Class Property, Queue/Associative/Dynamic Array Element, Select expression on a String" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv" Line 4733 : The SystemVerilog feature ": Sensitivity on Class Property, Queue/Associative/Dynamic Array Element, Select expression on a String" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv" Line 4733 : The SystemVerilog feature ": Sensitivity on Class Property, Queue/Associative/Dynamic Array Element, Select expression on a String" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv" Line 4733 : The SystemVerilog feature ": Sensitivity on Class Property, Queue/Associative/Dynamic Array Element, Select expression on a String" is not supported yet for simulation.
WARNING: [XSIM 43-3980] File "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_dc_lp.sv" Line 4733 : The SystemVerilog feature ": Sensitivity on Class Property, Queue/Associative/Dynamic Array Element, Select expression on a String" is not supported yet for simulation.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package xil_defaultlib.$unit_bd_8be5_MC0_ddrc_0_phy_wra...
Compiling package noc_na_v1_0_0.$unit_noc_na_v1_0_vl_rfs_sv
WARNING: [XSIM 43-3373] "/scratch/proj/xbuilds/SWIP/2021.1_0610_2318/infra/XSIM/lin/.cxl.ip/incl/mc_reg_sidefile_loader.sv" Line 67. System function $sscanf is used as system task. This system function should have a LHS e.g. x=$sscanf().
WARNING: [XSIM 43-3373] "/scratch/proj/xbuilds/SWIP/2021.1_0610_2318/infra/XSIM/lin/.cxl.ip/incl/mc_reg_sidefile_loader.sv" Line 70. System function $sscanf is used as system task. This system function should have a LHS e.g. x=$sscanf().
WARNING: [XSIM 43-3373] "/scratch/proj/xbuilds/SWIP/2021.1_0610_2318/infra/XSIM/lin/.cxl.ip/incl/mc_reg_sidefile_loader.sv" Line 83. System function $sscanf is used as system task. This system function should have a LHS e.g. x=$sscanf().
Compiling package xil_defaultlib.$unit_xlnoc_nps_0_0_top_sv
WARNING: [XSIM 43-3373] "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv" Line 2833. System function $sscanf is used as system task. This system function should have a LHS e.g. x=$sscanf().
WARNING: [XSIM 43-3373] "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv" Line 2836. System function $sscanf is used as system task. This system function should have a LHS e.g. x=$sscanf().
WARNING: [XSIM 43-3373] "D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_0/hdl/noc_nmu_v1_0_vl_rfs.sv" Line 2849. System function $sscanf is used as system task. This system function should have a LHS e.g. x=$sscanf().
Compiling package xil_defaultlib.axi_data_integrity_checker_nmu_p...
Compiling package xil_defaultlib.axi_xil_sb_pkg_nmu
Compiling package noc_nps_v1_0_0.$unit_noc_nps_v1_0_vl_rfs_sv
WARNING: [XSIM 43-3373] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_nps_v1_0/hdl/noc_nps_v1_0_vl_rfs.sv" Line 625. System function $sscanf is used as system task. This system function should have a LHS e.g. x=$sscanf().
WARNING: [XSIM 43-3373] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_nps_v1_0/hdl/noc_nps_v1_0_vl_rfs.sv" Line 628. System function $sscanf is used as system task. This system function should have a LHS e.g. x=$sscanf().
WARNING: [XSIM 43-3373] "/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_nps_v1_0/hdl/noc_nps_v1_0_vl_rfs.sv" Line 641. System function $sscanf is used as system task. This system function should have a LHS e.g. x=$sscanf().
Compiling module unisims_ver.IBUFDS
Compiling module xil_defaultlib.bd_8be5_MC0_ddrc_0_phy_ddr_respo...
WARNING: [VRFC 10-3460] index is always out of bounds for array 'REG_CONFIG0' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:7236]
WARNING: [VRFC 10-3456] index 23 is out of range [22:0] for 'REG_CONFIG0' [/wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_na_v1_0/hdl/noc_na_v1_0_vl_rfs.sv:7236]
Compiling module xil_defaultlib.noc_mc_lpddr4_v1_0_ddrmc_wdb(WDB...
Compiling module xil_defaultlib.noc_mc_lpddr4_v1_0_phy_xiphy_beh...
Compiling module xil_defaultlib.noc_mc_lpddr4_v1_0_dc_lp(REG_SAF...
Compiling module xil_defaultlib.noc_mc_lpddr4_v1_0_top(CPLX_CONF...
Compiling module unisims_ver.XPLL(CLKOUTPHY_DIVIDE="DIV1",XPL...
Compiling module unisims_ver.XPLL(CLKOUT1_PHASE_CTRL=2'b11,CL...
Compiling module xil_defaultlib.bd_8be5_MC0_ddrc_0_phy_wrapper(C...
Compiling module xil_defaultlib.bd_8be5_MC0_ddrc_0_phy
Compiling module xil_defaultlib.bd_8be5_MC0_ddrc_0_wrapper(NPI_R...
Compiling module xil_defaultlib.bd_8be5_MC0_ddrc_0
Compiling module unisims_ver.NOC_NMU512(REG_ADR_MAP_CPM=12'b1...
Compiling module xil_defaultlib.bd_8be5_S00_AXI_nmu_0_top(REG_AD...
Compiling module xil_defaultlib.bd_8be5_S00_AXI_nmu_0
Compiling module xlconstant_v1_1_7.xlconstant_v1_1_7_xlconstant
Compiling module xil_defaultlib.bd_8be5_const_0_0
Compiling module xil_defaultlib.bd_8be5
Compiling module xil_defaultlib.design_1_axi_noc_0_0
Compiling module unisims_ver.IBUF
Compiling module unisims_ver.MMCME5(CLKFBOUT_MULT=30,CLKIN1_P...
Compiling module unisims_ver.BUFG
Compiling module xil_defaultlib.design_1_clk_wiz_0_clocking_stru...
Compiling module xil_defaultlib.design_1_clk_wiz_0_clk_wiz_top(C...
Compiling module xil_defaultlib.design_1_clk_wiz_0
Compiling module clk_gen_sim_v1_0_0.clk_gen_sim_v1_0_0(SYS_CLK0_FREQ...
Compiling module xil_defaultlib.design_1_noc_clk_gen_0
Compiling module xil_defaultlib.design_1_noc_const_0
Compiling module unisims_ver.GND
Compiling module unisims_ver.x_lut1_mux2
Compiling module unisims_ver.LUT1
Compiling module unisims_ver.FDCE_default
Compiling module unisims_ver.FDRE_default
Compiling module xil_defaultlib.design_1_noc_sim_trig_0_sim_trig...
Compiling module xil_defaultlib.design_1_noc_sim_trig_0_traffic_...
Compiling module xil_defaultlib.design_1_noc_sim_trig_0_top
Compiling module xil_defaultlib.design_1_noc_sim_trig_0
Compiling module unisims_ver.BUFGCE_DIV(BUFGCE_DIVIDE=4,SIM_D...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=21...
Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
Compiling module xpm.xpm_memory_sdpram(MEMORY_SIZE=14...
Compiling module axi_infrastructure_v1_1_0.axi_infrastructure_v1_1_0_axi2ve...
Compiling module axi_infrastructure_v1_1_0.axi_infrastructure_v1_1_0_vector...
Compiling module axi_register_slice_v2_1_24.axi_register_slice_v2_1_24_axic_...
Compiling module axi_register_slice_v2_1_24.axi_register_slice_v2_1_24_axic_...
Compiling module axi_register_slice_v2_1_24.axi_register_slice_v2_1_24_axic_...
Compiling module axi_register_slice_v2_1_24.axi_register_slice_v2_1_24_axic_...
Compiling module axi_register_slice_v2_1_24.axi_register_slice_v2_1_24_axic_...
Compiling module axi_register_slice_v2_1_24.axi_register_slice_v2_1_24_axi_r...
Compiling module xil_defaultlib.design_1_noc_tg_0_axi_register_s...
Compiling module axi_infrastructure_v1_1_0.axi_infrastructure_v1_1_0_axi2ve...
Compiling module axi_infrastructure_v1_1_0.axi_infrastructure_v1_1_0_vector...
Compiling module axi_register_slice_v2_1_24.axi_register_slice_v2_1_24_axic_...
Compiling module axi_register_slice_v2_1_24.axi_register_slice_v2_1_24_axic_...
Compiling module axi_register_slice_v2_1_24.axi_register_slice_v2_1_24_axi_r...
Compiling module xil_defaultlib.design_1_noc_tg_0_axi4_register_...
Compiling module xil_defaultlib.design_1_noc_tg_0_reg_space(AXI_...
Compiling module xil_defaultlib.design_1_noc_tg_0_tg_top(BRAM_IN...
Compiling module xil_defaultlib.design_1_noc_tg_0_csvsptg_top(BR...
Compiling module xil_defaultlib.design_1_noc_tg_0_syn_top(C_AXI_...
Compiling module xil_defaultlib.design_1_noc_tg_0
Compiling module xil_defaultlib.design_1_noc_tg_pmon_0
Compiling module unisims_ver.LUT5
Compiling module xil_defaultlib.design_1_rst_clk_wiz_100M_0_cdc_...
Compiling module unisims_ver.x_lut2_mux4
Compiling module unisims_ver.LUT2
Compiling module xil_defaultlib.design_1_rst_clk_wiz_100M_0_cdc_...
Compiling module unisims_ver.SRL16E(INIT=16'b1111111111111111...
Compiling module unisims_ver.LUT4
Compiling module xil_defaultlib.design_1_rst_clk_wiz_100M_0_lpf
Compiling module unisims_ver.FDSE_default
Compiling module unisims_ver.x_lut3_mux8
Compiling module unisims_ver.LUT3(INIT=8'b01111000)
Compiling module unisims_ver.LUT6(INIT=64'b011111111111111111...
Compiling module xil_defaultlib.design_1_rst_clk_wiz_100M_0_upcn...
Compiling module xil_defaultlib.design_1_rst_clk_wiz_100M_0_sequ...
Compiling module xil_defaultlib.design_1_rst_clk_wiz_100M_0_proc...
Compiling module xil_defaultlib.design_1_rst_clk_wiz_100M_0
Compiling module xil_defaultlib.design_1
Compiling module xil_defaultlib.design_1_wrapper
Compiling module noc_nps_v1_0_0.cb_m
Compiling module noc_nps_v1_0_0.noc_npp_if_nps
Compiling module noc_nps_v1_0_0.nps_bfm_new(REG_HIGH_ID0_P01=32'...
Compiling module noc_nps_v1_0_0.BM_NOC_NPS5555(REG_HIGH_ID0_P01=...
Compiling module unisims_ver.NOC_NPS5555(REG_HIGH_ID0_P01=32'...
Compiling module xil_defaultlib.xlnoc_nps_0_0_top(REG_HIGH_ID0_P...
Compiling module xil_defaultlib.xlnoc_nps_0_0
Compiling module noc_nps_v1_0_0.nps_bfm_new(REG_HIGH_ID0_P01=32'...
Compiling module noc_nps_v1_0_0.BM_NOC_NPS5555(REG_CLOCK_MUX=32'...
Compiling module unisims_ver.NOC_NPS5555(REG_CLOCK_MUX=32'b01...
Compiling module xil_defaultlib.xlnoc_nps_1_0_top(REG_HIGH_ID0_P...
Compiling module xil_defaultlib.xlnoc_nps_1_0
Compiling module noc_nps_v1_0_0.nps_bfm_new(REG_HIGH_ID0_P01=32'...
Compiling module noc_nps_v1_0_0.BM_NOC_NPS5555(REG_HIGH_ID0_P01=...
Compiling module unisims_ver.NOC_NPS5555(REG_HIGH_ID0_P01=32'...
Compiling module xil_defaultlib.xlnoc_nps_2_0_top(REG_HIGH_ID0_P...
Compiling module xil_defaultlib.xlnoc_nps_2_0
Compiling module xil_defaultlib.xlnoc
Compiling module xil_defaultlib.design_1_wrapper_sim_wrapper
Compiling module xil_defaultlib.glbl
Built simulation snapshot design_1_wrapper_sim_wrapper_behav
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:00:38 . Memory (MB): peak = 2172.641 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '38' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "design_1_wrapper_sim_wrapper_behav -key {Behavioral:sim_1:Functional:design_1_wrapper_sim_wrapper} -tclbatch {design_1_wrapper_sim_wrapper.tcl} -protoinst "protoinst_files/bd_8be5.protoinst" -protoinst "protoinst_files/design_1.protoinst" -protoinst "protoinst_files/xlnoc.protoinst" -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_8be5.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /design_1_wrapper_sim_wrapper/design_1_wrapper_i/design_1_i/axi_noc_0/inst//S00_AXI_nmu/SAXI4
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/design_1.protoinst
INFO: [Wavedata 42-564] Found protocol instance at /design_1_wrapper_sim_wrapper/design_1_wrapper_i/design_1_i//axi_noc_0/S00_AXI
INFO: [Wavedata 42-564] Found protocol instance at /design_1_wrapper_sim_wrapper/design_1_wrapper_i/design_1_i//noc_tg/M_AXI
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/xlnoc.protoinst
Time resolution is 1 ps
source design_1_wrapper_sim_wrapper.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 100us
File : nocattrs.dat Opened Successfully for IP bd_8be5_MC0_ddrc_0
S80 is ACTIVE
Updating bd_8be5_S00_AXI_nmu_0 and nocattrs.dat
Info: design_1_wrapper_sim_wrapper.design_1_wrapper_i.design_1_i.axi_noc_0.inst.MC0_ddrc.inst.noc_ddr4_phy.inst.u_lpddr4mc_top,initDone raised at 175143 Time: 175143 ps Iteration: 1 Process: /design_1_wrapper_sim_wrapper/design_1_wrapper_i/design_1_i/axi_noc_0/inst/MC0_ddrc/inst/noc_ddr4_phy/inst/u_lpddr4mc_top/Initial2315_79 Scope: design_1_wrapper_sim_wrapper.design_1_wrapper_i.design_1_i.axi_noc_0.inst.MC0_ddrc.inst.noc_ddr4_phy.inst.u_lpddr4mc_top File: D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_axi_noc_0_0/bd_0/ip/ip_2/ip_0/hdl/lpddr4/noc_mc_lpddr4_v1_0_top.sv Line: 2317
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 VC = 'h4
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 -- READ REQUEST --
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 flit = 'hac43f000000000000020000000c070000000010000000
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 aaddr = 'h10000000
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 alen = 'h7
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 asize = 'h4
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 aburst = 'h1
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 alock = 'h0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 acache = 'h0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 aprot = 'h0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 aqos = 'h0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 aid = 'h0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 auser = 'h1
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 type = 'h0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 misc_ctrl = 'h0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 tag = 'h0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 src = 'h0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 dst = 'hfc0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 dst_par = 'h0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 pri = 'h0
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 last = 'h1
design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::display_flit_and_vc : @4122263 ecc = 'hac
Error: design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::determine_dest_port_from_routing_table ::: at time 4122263 ::: ERROR ::: Flit cannot be routed to the same inport it came from. Inport='d3 Routed to='d3
nps_high_id='h0,nps_mid_id='h0,flit_dst_id='hfc0,flit_high_id='h3f,flit_mid_id='h0,flit_low_id='h0
Time: 4122263 ps Iteration: 0 Process: /design_1_wrapper_sim_wrapper/xlnoc_i/nps_1/xlnoc_nps_1_0_top_INST/NOC_NPS5555_INST/BM_NOC_NPS5555_INST/generate_behav_model.u0_nps_bfm/Initial1251_3876 Scope: design_1_wrapper_sim_wrapper.xlnoc_i.nps_1.xlnoc_nps_1_0_top_INST.NOC_NPS5555_INST.BM_NOC_NPS5555_INST.\generate_behav_model.u0_nps_bfm .\nps_ivca::determine_dest_port_from_routing_table File: /wrk/ci/prod/2021.1/sw/continuous/3932/packages/customer/vivado/data/ip/xilinx/noc_nps_v1_0/hdl/noc_nps_v1_0_vl_rfs.sv Line: 111
trace_performance.txt has been created for both NA and DC!
trace_performance.txt has been created for both NA and DC!
trace_performance.txt has been created for both NA and DC!
trace_performance.txt has been created for both NA and DC!
ADEC checks are passing!
Error: TEST FAILED:tg_done is not-asserted
Time: 4122263 ps Iteration: 0 Process: /design_1_wrapper_sim_wrapper/design_1_wrapper_i/design_1_i/noc_tg/inst/u_top_axi_mst/u_tg_top/Always1769_3454 Scope: design_1_wrapper_sim_wrapper.design_1_wrapper_i.design_1_i.noc_tg.inst.u_top_axi_mst.u_tg_top File: D:/Xilinx_Device/Versal/NOC_DDR_3_01/NOC_DDR_3_01.ip_user_files/bd/design_1/ip/design_1_noc_tg_0/hdl/rtl/design_1_noc_tg_0_tg_top.sv Line: 1775
=========================================================
>>>>>> SRC_ID 0 :: AXI_PMON :: BW ANALYSIS >>>>>>
=========================================================
AXI Clock Period = 4000 ps
Error: ERROR :: Write Bandwidth/Latency is not calculated since the responses are not completely received for all sent write requests
Time: 4122263 ps Iteration: 0
***************************************************
Error: ERROR :: Read Bandwidth/Latency is not calculated since the responses are not completely received for all sent read requests
Time: 4122263 ps Iteration: 0
$finish called at time : 4122263 ps : File "/scratch/proj/xbuilds/SWIP/2021.1_0610_2318/infra/XSIM/lin/.cxl.ip/incl/nps_ivca.sv" Line 112
WARNING: [Simulator 45-29] Cannot open source file /scratch/proj/xbuilds/SWIP/2021.1_0610_2318/infra/XSIM/lin/.cxl.ip/incl/nps_ivca.sv: file does not exist.
xsim: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2385.305 ; gain = 212.664
INFO: [USF-XSim-96] XSim completed. Design snapshot 'design_1_wrapper_sim_wrapper_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 100us
launch_simulation: Time (s): cpu = 00:00:27 ; elapsed = 00:01:10 . Memory (MB): peak = 2385.305 ; gain = 829.090