Advanced Materials Research Vols. 756-759 (2013) pp 4267-4270
Online available since 2013/Sep/18 at www.scientific.net
© (2013) Trans Tech Publications, Switzerland
doi:10.4028/www.scientific.net/AMR.756-759.4267
Use N+ Buried Layer to Design a Low On-Resistance VDMOS
TANG Zhaohuan1, a, WANG Bin2, b, WANG Jianan2, c and TAN Kaizhou1, d
1
Science and Technology on Analog Integrated Circuit Laboratory, Chongqing 400060, China
2
Sichuan Institute of Solid-State Circuits, Chongqing 400060, China
a
sisc_tang@163.com, bwbwaif@163.com, cwangja1207@163.com, dtkz123@163.com,
Keywords: VDMOS; N+ buried layer; On-resistance; Breakdown voltage.
Abstract. A novel structure of a VDMOS in reducing on-resistance is proposed and experimentally
demonstrated with a 200V N-channel VDMOS. With this structure, the on-resistance value of the
VDMOS is reduced by 19.6% than that of a traditional VDMOS structure as the breakdown voltage
almost maintained the same value, and there is only one additional mask in processing this new
structure VDMOS, which is easily fabricated. By TCAD tool, the specific on-resistance value will
reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies
and four buried layers. The novel structure can be widely used in high-voltage VDMOS and BCD
areas.
Introduction
In recent years, requirements for DC/DC converter, DC/AC converter, relay and relay driver are
becoming more and more stringent, a lot of companies and institutes pay more and more attention to
research and explore in these areas, such as IR, CSMT, ST, Motorola and Vishay. As interrelated
technician known, the characteristic frequency, thermal stability and input impedance of the power
MOSFET are somewhat better than those of bipolar power transistors [1], and VDMOS is also a kind
of device，of which the channel conductance is controlled by gate voltage, its driving current is
lower, the driving circle is much simple than that of a bipolar power transistor[1,3], hence the
high-performance VDMOS is one of the key devices in these systems.Especially, high output power
of the VDMOS is the development trend of miniaturization and lightweight of global-system, and the
relatively large on-resistance (RON) of power MOSFETs has became a considerable problem to
designers [1.2]. From the original field-effect transistor introduced in the 1970s, the VVMOS,
VUMOS and trench-MOSFET were proposed to reduce the RON, these device structures did some
efforts on RON, but they are difficult to fabricate.
In this paper, a novel structure in reducing RON of VDMOS is designed, and its tech-scheme is to
reduce epitaxial layer resistance (REPI) by adding the buried layer (NBL) which is shown in Fig.1.With
the structure, the specific RON value of VDMOS reduces by 22% than that of the traditional VDMOS
structure as the breakdown voltage maintains the same value in theory. On second thoughts, the
specific RON value will reduce by 33%, if the device is processed in three epitaxies and four NBLs, the
novel structure can be widely used for high-voltage VDMOS and DMOS in BCD process.
Structure and Analysis
As known to all, in order to optimize the NBL for high-voltage VDMOS, the most difficulty is to
find out the tradeoff between size/doping of NBL and breakdown voltage (BVDSS) of VDMOS.
Device Design. The novel structure of VDMOS is shown in Fig.1, and the differentia between the
proposed structure and traditional VDMOS structure is the added NBL which is fabricated before
epitaxy, the NBL is bellow neck area.
The designed process for the novel structure of N-channel 200V-VDMOS as follows:
Initial
oxide→NBL
photo/etch→thin
oxide→arsenic
implant→anneal→strip
oxide
all→epitaxy→field oxide→guard ring photo/etch→boron implant→LPCVD SiO2 → anneal →
ACTIVE photo/etch → gate oxide → LPCVD poly-silicon → poly-silicon doping → poly-silicon
All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of TTP,
www.ttp.net. (ID: 130.159.70.209, University of Strathclyde, Glasgow, United Kingdom-23/03/15,12:09:06)
4268
Information Technology Applications in Industry, Computer Engineering and
Materials Science
photo/etch → poly-silicon oxide → PBODY photo → boron implant → PBODY anneal → source
photo/etch→phosphorus implant→photo/etch →boron implant→LPCVD SiO2 →anneal→contact
photo/etch→metallization →passivation→test.
Fig.1 Cross section of the novel VDMOS structure
As the structure and process mentioned, the simulated cross section of the proposed structure is
shown in Fig.2, From Fig.2, there is only one NBL in the structure, and there are four NBLs can be
used to reduce RON of VDMOS, which is shown in Fig.3
Fig.2 Simulated cross section of the proposed
structure (cell:16µm×16µm, BVDSS =248V)
Fig.3 Simulated cross section of the optimized
structure (cell:16µm×16µm, BVDSS =243V)
Fig.4 Simulated specific REPI curve of the novel Fig.5 Simulated specific REPI curve of the novel
structure VDMOS with NBL_size varying
structure VDMOS with NBL_dose varying from
from 2µm to 14µm at 1µm step
2E15/cm2 to 2E16/cm2 at 2E15/cm2 step
In order to find out the tradeoff between size/doping of NBL and BVDSS of VDMOS, with TCAD
tools, the relationship between size of NBL and BVDSS / RON is simulated, which is shown in Fig.4.
From the curve, we can know that the specific RON will decrease by 23.45%, if there is one NBL in
Advanced Materials Research Vols. 756-759
4269
structure, and the value will decrease by 33.49%, if there are four NBLs in structure. And the more
important information we can get is that the specific RON and BVDSS will almost maintain the same
value as the size of NBL changes from 2µm to 12µm at 1µm step. If the NBL is treated as a rectangle,
the NBL resistor can be simply calculated from resistor equation, and the NBL implant dose is
1E16/cm2, the NBL resistor value is 0.0025mΩ when there are four NBLs and the size of NBL is
2µm. And the value is 0.0004 mΩ when the size of NBL is 12µm.Finally, the specific RON will
maintain the same value as the size of NBL changes from 2µm to 12µm.
Fig.5 shows the simulated relationship curve between implant dose of NBL and BVDSS / RON.
From the curve, we can know that the specific RON will decrease by 20.99%, if there is one NBL in
structure, and the value will decrease by 31.41%, if there are four NBLs in structure. And the more
important information we can get is that the specific RON and BVDSS will maintain the same value as
the implant dose of NBL changes from 2E15/cm2 to 2E16/cm2 at 2E15/cm2 step.
On-resistance Analysis.The section headings are in boldface capital and lowercase letters.
Second level headings are typed as part of the succeeding paragraph (like the subsection heading of
this paragraph).
The BVDSS of VDMOS is made up of several components as shown in Fig.1, and there are only
four main resistance signed in the cross section, the contact resistance between the source and drain
metallization and the silicon, metallization and lead-frame are ignored, because these are normally
negligible in high voltage devices[2,3], such as 200V. The BVDSS of VDMOS is given by
RON = RCS + RCH + Rneck + REPI + RSUB + RCD
(1)
Where RCS is the contact resistance between the source metallization and the silicon and source
diffusion resistance, RCH is the channel resistance, Rneck is the component-resistance of the region
between the two body regions, RSUB is the substrate resistance and RCD is the contact resistance
between the drain metallization and the silicon.
In a general way, the epitaxial layer (EPI) is treated as a rectangle in high-voltage VDMOS [1, 8],
so calculating the REPI value is comparatively simple. As known to all, the depth of NBODY junction
(r1) is about 2.5µm, the depth of N+ carrier diffusing in EPI (W1) is about 2.0µm. On the assumption
that the thickness of EPI needs 24µm to fulfill BVDSS=200V, and the wasting thickness of EPI (W4) in
process is about 2.0µm, the specific REPI value will be calculated. The traditional structure specific
REPI is given by
W
W
R EPI = ρ × 2 = qµ n N D × 2
S
S
(2)
where W2=W3-W1-W4-r1=17.5µm,ρ=4.35Ω.cm. at 200V device. From eq.2, specific REPI is about
761250Ω/µm2.
As shown in Fig.6, if there is a NBL in the structure, W2=r2=r3, specific REPI is about
609000Ω/µm2, and the specific REPI reduced by 25%, which match the simulated value very well.
Fig.6 Sketch map of key size for breakdown voltage and on-resistance
4270
Information Technology Applications in Industry, Computer Engineering and
Materials Science
Experiment and Results
As the mentioned structure and process above, a 200V N-channel VDMOS is fabricated. Table1 is the
tested results of the novel structure VDMOS and traditional VDMOS, and the RON of the proposed
VDMOS is 135.2mΩ, the RON of the VDMOS which did not use NBL is 161.7 mΩ,hence the RON
value of VDMOS is reduced by 19.6% than that of a traditional VDMOS.
Photograph for NBL after thick epitaxy is shown in Fig.7, and output characteristic of the proposed
VDMOS is shown in Fig.8.
Table.1 Tested results for the proposed VDMOS and a traditional VDMOS
Sample
With NBL
Without NBL
Parameter
RON
BVDSS
RON
BVDSS
target value
94
243
120
248
Test Value
135.2
235
161.7
245
units
mΩ
V
mΩ
V
IDS=10μ
μA/div(Y axis)
VDS=50V/div(X axis)
Fig. 7 Photograph for NBL after thick epitaxy
Fig. 8 Measured output characteristic of the VDMOS
Summary
A novel structure of VDMOS in reducing RON is developed. The specific RON value will reduce by
22% than that of the traditional structure, if there is a NBL in VDMOS, and the value will reduce by
33%, if three epitaxies and four buried layers are used in processing the new structure VDMOS.
Especially, the proposed structure and its excellence are experimentally demonstrated with a 200V
N-channel VDMOS, the tested RON value of VDMOS is reduced by 19.6% than that of the traditional
VDMOS. The novel structure and its process can be widely used to fabricate high-voltage VDMOS
and develop high-voltage BCD process.
References
[1] SeongDong Kim, Iljung Kim, Minkoo Han, et al: Solid-State Electronic. Forum Vol. 38-2(1995),
p. 345
[2] Vrej Barkhordarian, International Rectifier, El Segundo, Ca.Power MOSFET Basics
[3] Sze S M: Physics of Semiconductor Devices .Second Edition, 1981:222
[4] Jiang Yan, Chen Long, Shen Keqiang: Chinese Journal of Electron Device. Forum Vol. 31-2
(2008), p. 357
[5] Yuan Shoucai, Liu Yamei: Journal of Electron Device. Forum Vol. 31-4 (2008), p. 1219
[6] Taurus MediciTM MediciTM User Guide [M].Version W-2004.09, Sep.2004
[7] Rene P.Zingg: IEEE Transactions on Electron Devices. Forum Vol. 51-3 (2004), p. 492
Information Technology Applications in Industry, Computer Engineering and Materials Science
10.4028/www.scientific.net/AMR.756-759
Use N+ Buried Layer to Design a Low On-Resistance VDMOS
10.4028/www.scientific.net/AMR.756-759.4267
DOI References
[1] SeongDong Kim, Iljung Kim, Minkoo Han, et al: Solid-State Electronic. Forum Vol. 38-2(1995), p.345.
http://dx.doi.org/10.1016/0038-1101(94)00122-V