CS/ECE 3700
Spring 2019
Myers
Lab #1
LAB #1: Design with Verilog and FPGAs
This lab is due in your discussion section during the week of January 28th.
The objective of this lab is to learn top-down design of a logic circuits using Altera Quartus CAD tool
and prototyping using FPGAs. In particular, you will use schematics and Verilog to specify your design,
use simulation to validate the correctness of your design, and then apply synthesis to produce an FPGA
implementation. In particular, you will design, simulate, and synthesize the elementary 2-bit computer
introduced in Problems 5-7 of Homework 1. Your job is to:
• Design the logic using a CAD tool called a “Schematic Editor”;
• Simulate your design using a Verilog testbench;
• Re-design the same circuit using a Verilog description and simulate using the same test bench; and
• Synthesize the netlist and download the design onto the FPGA to demonstrate its correct operation.
On CANVAS, you will find a tutorial that gives step-by-step procedures for using the CAD tools, and this
tutorial will be demoed to you in your discussion section. You should also complete the tutorial yourself.
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The Two-bit Computer
In this lab, you are to design a simple 2-bit “computer”. The circuit takes three (word-level) inputs A[1 : 0],
B[1 : 0] , I[1 : 0]; where A, B, I are each 2-bit vectors. In other words, A[1 : 0] = (a1 , a0 ), are binary
variables. A[1 : 0], B[1 : 0] are the “data” inputs of the design and I[1 : 0] corresponds to the “control” or
the “instruction” input. The output is also a 2-bit vector, F [1 : 0] = (f1 , f0 ).
Circuit functionality: The values of the input control signals (I[1 : 0]) decide the operation of this
circuit. The instructions are:
• When I[1 : 0] = (i1 , i0 ) = (0, 0), the output F [1 : 0] is a bit-wise complement of A[1 : 0] (i.e., f0 = a0
and f1 = a1 ).
• When I[1 : 0] = (i1 , i0 ) = (0, 1), the output F [1 : 0] is a bit-wise AND of the inputs (i.e., f1 = a1 · b1 ;
f0 = a0 · b0).
• When I[1 : 0] = (i1 , i0 ) = (1, 0), the output F [1 : 0] is the sum of A and B.
• When I[1 : 0] = (i1 , i0 ) = (1, 1), the output F [1 : 0] is the difference of A from B.
Note that when the result of the sum or difference requires more than two bits that the error output is
asserted.
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The Assignment
You are asked to design a circuit that implements the above function. You are free to use any technique that
you wish for circuit optimization. Spend a few minutes to think about the design, perhaps you may want to
draw a circuit diagram on paper. Once your design is ready, do the following:
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• Schematic entry: Using the Altera Quartus tool, draw the schematic corresponding to your design,
using AND, OR, NOT, XOR, etc. gates. Do not use pre-designed multiplexors (MUXs). Using a
Verilog testbench, simulate the schematic and verify the correctness of your design. Your testbench
should apply ALL possible inputs to the design.
• Verilog: now use the Verilog description of the circuit prepared as Problem 7 in Homework 1. Using
the same testbench from above, simulate the Verilog code.
• Synthesis: synthesize the circuit, generate the schematics, place and route the hardware and generate
the bit-file to program the FPGA. Following the tutorial, you will download the circuit onto the FPGA
and show its correct operation. You may choose any type of switches/LEDs from your lab kits.
You are expected to document your labs in a professional manner. Show your optimizations (if any),
turn in the schematic of your circuit (CAD tools can print the schematics for you). Take care to draw the
schematics neatly. Organize your layout spacing the wires and components as evenly as possible. Eliminate
jogs in wires, line-up the components, etc. Also, turn in your Verilog code, simulation testbenches, and
simulation results.
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