SEDRA/SMITH
INSTRUCTOR’S SOLUTIONS MANUA
FOR
Microelectronic Circuits
INTERNATIONAL SEVENTH EDITION
Adel S. Sedra
University of Waterloo
New York
Oxford
OXFORD UNIVERSITY PRESS
Oxford University Press is a department of the University of Oxford.
It furthers the University’s objective of excellence in research,
scholarship, and education by publishing worldwide.
Oxford New York
Auckland Cape Town Dar es Salaam Hong Kong Karachi
Kuala Lumpur Madrid Melbourne Mexico City Nairobi
New Delhi Shanghai Taipei Toronto
With offices in
Argentina Austria Brazil Chile Czech Republic France Greece
Guatemala Hungary Italy Japan Poland Portugal Singapore
South Korea Switzerland Thailand Turkey Ukraine Vietnam
Copyright  2017 by Oxford University Press
For titles covered by Section 112 of the US Higher Education
Opportunity Act, please visit www.oup.com/us/he for the
latest information about pricing and alternate formats.
Published by Oxford University Press
198 Madison Avenue, New York, New York 10016
http://www.oup.com
Oxford is a registered trademark of Oxford University Press
All rights reserved. No part of this publication may be reproduced,
stored in a retrieval system, or transmitted, in any form or by any means,
electronic, mechanical, photocopying, recording, or otherwise,
without the prior permission of Oxford University Press.
ISBN: 978-0-19-933916-7
Exercise Solutions (Chapters 1-17)
Problem Solutions (Chapters 1-17)
Preface
This Instructor’s Solution Manual (ISM) contains complete solutions for all exercises and
end-of-chapter problems included in the book Microelectronic Circuits, International
Seventh Edition by Adel S. Sedra and Kenneth C. Smith.
Most of the solutions are new; however, I have used and/or adapted some of the solutions
from the ISM of the International Sixth Edition. Credit for these goes to the problem
solvers listed therein.
This manual has greatly benefited from the careful work of the accuracy checkers listed
below. These colleagues and friends worked diligently to ensure that the 2,030 solutions
are free of error. Despite all of our combined efforts, however, there is little doubt that
some errors remain, and for these I take full responsibility. I will be most grateful to
instructors who discover errors and point them out to me. Please send all corrections and
comments by email to: sedra@uwaterloo.ca.
Adel Sedra
Waterloo, Ontario, Canada
October 2015
Accuracy Checkers
• Professor Tony Chan Carusone, University of Toronto - Assisted by graduate students
Jeffrey Wang and Luke Wang
• Professor Vincent Gaudet, University of Waterloo
• Professors Shahriar Mirabbasi and Mandana Amiri, University of British Columbia
• ProfessorWai Tung Ng, University of Toronto
• Professor Olivier Trescases, University of Toronto
• Professor Amir Yazdani, Ryerson University
Exercise 1–1
Rs
Ex: 1.1 When output terminals are
open-circuited, as in Fig. 1.1a:
For circuit a. v oc = v s (t)
vs (t) For circuit b. v oc = is (t) × Rs
vo
When output terminals are short-circuited, as in
Fig. 1.1b:
For circuit a. isc =
RL
If RL = 100 k:
v s (t)
Rs
v o = 10 mV ×
For circuit b. isc = is (t)
100
= 9.9 mV
100 + 1
If RL = 10 k:
For equivalency
v o = 10 mV ×
Rs is (t) = v s (t)
10
9.1 mV
10 + 1
If RL = 1 k:
Rs
a
v o = 10 mV ×
1
= 5 mV
1+1
If RL = 100 :
vs (t) v o = 10 mV ×
100
0.91 mV
100 + 1 K
For v o = 0.8v s ,
b
RL
= 0.8
RL + Rs
Figure 1.1a
Since Rs = 1 k,
a
is (t)
RL = 4 k
Ex: 1.4 Using current divider:
Rs
io
b
is 10 A
RL
Rs
Figure 1.1b
Ex: 1.2
io = is ×
Rs
voc vs isc = 10 μA
v oc
10 mV
=
= 1 k
isc
10 μA
Ex: 1.3 Using voltage divider:
v o (t) = v s (t) ×
Given is = 10 μA, Rs = 100 k.
For
RL = 1 k, io = 10 μA ×
100
= 9.9 μA
100 + 1
For
RL = 10 k, io = 10 μA ×
v oc = 10 mV
Rs =
isc
Rs
Rs + RL
RL
Rs + RL
Given v s (t) = 10 mV and Rs = 1 k.
100
9.1 μA
100 + 10
For
RL = 100 k, io = 10 μA ×
100
= 5 μA
100 + 100
For RL = 1 M, io = 10 μA ×
0.9 μA
For io = 0.8is ,
100
= 0.8
100 + RL
⇒ RL = 25 k
100 K
100 K + 1 M
Exercise 1–2
Ex: 1.5 f =
1
1
= −3 = 1000 Hz
T
10
ω = 2πf = 2π × 103 rad/s
Ex: 1.6 (a) T =
1
1
=
s = 16.7 ms
f
60
1
1
(b) T = = −3 = 1000 s
f
10
(c) T =
1
1
= 6 s = 1 μs
f
10
Ex: 1.7 If 6 MHz is allocated for each channel,
then 470 MHz to 806 MHz will accommodate
806 − 470
= 56 channels
6
Since the broadcast band starts with channel 14, it
will go from channel 14 to channel 69.
Ex: 1.8 P =
1
T
T
Ex: 1.9 (a) D can represent 15 distinct values
between 0 and +15 V. Thus,
v A = 0 V ⇒ D = 0000
v A = 1 V ⇒ D = 0001
v A = 2 V ⇒ D = 0010
v A = 15 V ⇒ D = 1111
(b) (i) +1 V (ii) +2 V (iii) +4 V (iv) +8 V
(c) The closest discrete value represented by
D is 5 V; thus D = 0101. The error is −0.2 V, or
−0.2/5.2 × 100 = −4%.
Ex: 1.10 Voltage gain = 20 log 100 = 40 dB
Current gain = 20 log 1000 = 60 dB
Power gain = 10 log Ap = 10 log (Av Ai )
v2
dt
R
= 10 log 105 = 50 dB
0
V
V2
1
×
×T =
T
R
R
Alternatively,
=
2
P = P1 + P3 + P5 + · · ·
2
4V 2 1
4V
1
= √
+
√
R
R
2π
3 2π
2
4V
1
+ √
+ ···
R
5 2π
8
1
1
1
V2
× 2 × 1+ +
+
+ ···
=
R
π
9 25 49
Ex: 1.11 Pdc = 15 × 8 = 120 mW
√
(6/ 2)2
PL =
= 18 mW
1
Pdissipated = 120 − 18 = 102 mW
η=
PL
18
× 100 = 15%
× 100 =
Pdc
120
Ex: 1.12 v o = 1 ×
10
10−5 V = 10 μV
10 + 10
6
It can be shown by direct calculation that the
infinite series in the parentheses has a sum that
approaches π 2 /8; thus P becomes V 2/R as found
from direct calculation.
(10 × 10−6 )2
= 10−11 W
10
With the buffer amplifier:
Fraction of energy in fundamental
vo = 1 ×
= 8/π 2 = 0.81
Fraction of energy in first five harmonics
1
1
8
= 0.93
= 2 1+ +
π
9 25
PL = v 2o /RL =
=1×
PL =
Ri
RL
× Av o ×
Ri + Rs
RL + Ro
10
1
×1×
= 0.25 V
1+1
10 + 10
v 2o
0.252
= 6.25 mW
=
RL
10
0.25 V
vo
= 0.25 V/V
=
vs
1V
Fraction of energy in first seven harmonics
1
1
1
8
+
= 0.95
= 2 1+ +
9 25 49
π
Voltage gain =
Fraction of energy in first nine harmonics
1
1
1
1
8
+
+
= 0.96
= 2 1+ +
π
9 25 49 81
Power gain (Ap ) ≡
Note that 90% of the energy of the square wave is
in the first three harmonics, that is, in the
fundamental and the third harmonic.
= −12 dB
PL
Pi
where PL = 6.25 mW and Pi = v i i1 ,
v i = 0.5 V and
ii =
1V
= 0.5 μA
1 M + 1 M
Exercise 1–3
This figure belongs to Exercise 1.15.
Stage 1
Stage 2
100 k
vs vi1
1 M
10vi1
Thus,
Pi = 0.5 × 0.5 = 0.25 μW
and
Ap =
1 k
1 k
6.25 × 10−3
= 25 × 103
0.25 × 10−6
vi2
100vi2
100 k
vL
100 Ex: 1.16 Refer the solution to Example 1.3 in the
text.
v i1
= 0.909 V/V
vs
v i1 = 0.909 v s = 0.909 × 1 = 0.909 mV
10 log Ap = 44 dB
v i2
v i2
v i1
=
×
= 9.9 × 0.909 = 9 V/V
vs
v i1
vs
Ex: 1.13 Open-circuit (no load) output voltage =
Av o v i
v i2 = 9 × v S = 9 × 1 = 9 mV
Output voltage with load connected
= Av o v i
0.8 =
RL
RL + Ro
1
⇒ Ro = 0.25 k = 250 Ro + 1
Ex: 1.14 Av o = 40 dB = 100 V/V
2 v2
RL
PL = o = Av o v i
RL
RL
RL + Ro
2 1
= v 2i × 100 ×
1000 = 2.5 v 2i
1+1
Pi =
v 2i
v 2i
=
Ri
10,000
Ap ≡
PL
2.5v 2
= −4 i 2 = 2.5 × 104 W/W
Pi
10 v i
10 log Ap = 44 dB
v i3
v i3
v i2
v i1
=
×
×
= 90.9 × 9.9 × 0.909
vs
v i2
v i1
vs
= 818 V/V
v i3 = 818 v s = 818 × 1 = 818 mV
vL
vL
v i3
v i2
v i1
=
×
×
×
vs
v i3
v i2
v i1
vs
= 0.909 × 90.9 × 9.9 × 0.909 744 V/V
v L = 744 × 1 mV = 744 mV
Ex: 1.17 Using voltage amplifier model, the
three-stage amplifier can be represented as
Ro
vi
Ex: 1.15 Without stage 3 (see figure above)
vL
=
v s
1 M
100 k
(10)
100 k + 1 M
100 k + 1 k
100
×(100)
100 + 1 k
vL
= (0.909)(10)(0.9901)(100)(0.0909)
vs
= 81.8 V/V
Ri
Avovi
Ri = 1 M
Ro = 10 Av o = Av 1 ×Av 2 ×Av 3 = 9.9×90.9×1 = 900 V/V
The overall voltage gain
Ri
RL
vo
=
× Av o ×
vs
Ri + Rs
RL + Ro
Exercise 1–4
For RL = 10 :
Ex: 1.20 Using the transresistance circuit model,
the circuit will be
Overall voltage gain
=
10
1M
× 900 ×
= 409 V/V
1 M + 100 K
10 + 10
ii
Ro
For RL = 1000 :
Overall voltage gain
=
is
Rs
Ri
1000
1M
× 900 ×
= 810 V/V
1 M + 100 K
1000 + 10
Rmii
RL
∴ Range of voltage gain is from 409 V/V to
810 V/V.
ii
Rs
=
is
Ri + Rs
Ex: 1.18
ii
v o = Rm ii ×
io
RL
RL + Ro
vo
RL
= Rm
ii
RL + Ro
is
Rs
Ri
Ro
RL
Ais ii
ii = is
Rs
Rs + Ri
io = Ais ii
Now
vo
vo
ii
Rs
RL
=
× = Rm
×
ii
is
RL + Ro
Ri + Rs
is
= Rm
RL
Rs
×
Rs + Ri
RL + Ro
Ex: 1.21
Ro
Rs
Ro
= Ais is
Ro + RL
Rs + Ri Ro + RL
Thus,
Rs
Ro
io
= Ais
is
Rs + Ri Ro + RL
Ex: 1.19
Ri
vs vi = vs
vi
Ri
Ri
Ri + Rs
v o = Gm v i (Ro RL )
Ri
(Ro RL )
= Gm v s
Ri + Rs
Thus,
Ri
vo
= Gm
(Ro RL )
vs
Ri + Rs
Ro
Gmvi
RL
vo
v b = ib rπ + (β + 1)ib Re
= ib [rπ + (β + 1)Re ]
But v b = v x and ib = ix , thus
vx
vb
=
= rπ + (β + 1)Re
Rin ≡
ix
ib
Ex: 1.22
f
10 Hz
10 kHz
100 kHz
1 MHz
Gain
60 dB
40 dB
20 dB
0 dB
vo
Exercise 1–5
Gain (dB)
Ex: 1.24 Refer to Fig. E1.24
60
40
V2
=
Vs
20 dB/decade
20
1
10
0
10
10
10
10
10
10
f (Hz)
3 dB
frequency
Ri
Ri
s
=
1
1
Rs + Ri
+ Ri
Rs +
s+
sC
C(Rs + Ri )
which is an HP STC function.
1
≤ 100 Hz
f3dB =
2πC(Rs + Ri )
C≥
1
= 0.16 μF
2π(1 + 9)103 × 100
Ex: 1.23
Rs 1 k
Vi
Ri GmVi
Ro RL
Vo
CL
Vs
Ri 9 k
Vo = Gm Vi [Ro RL CL ]
=
C
Gm Vi
1
1
+
+ sCL
Ro
RL
Vo
Gm
1
Thus,
=
×
1
1
sCL
Vi
+
1+
1
1
Ro
RL
+
Ro
RL
Ex: 1.25 T = 50 K
ni = BT 3/2 e−Eg/(2kT )
−5 ×50)
= 7.3 × 1015 (50)3/2 e−1.12/(2×8.62×10
9.6 × 10−39 /cm3
T = 350 K
ni = BT 3/2 e−Eg/(2kT )
−5 ×350)
= 7.3 × 1015 (350)3/2 e−1.12/(2×8.62×10
= 4.15 × 1011 /cm3
Gm (RL Ro )
Vo
=
Vi
1 + sCL (RL Ro )
Ex: 1.26 ND = 1017 /cm3
which is of the STC LP type.
From Exercise 1.1, ni at
DC gain = Gm (RL Ro ) = 10 × (RL 50)
T = 350 K = 4.15 × 1011 /cm3
nn = ND = 1017 /cm3
To obtain a dc gain of at least 40 dB (i.e., 100),
10(RL 50) ≥ 100
ni2
pn ∼
=
ND
⇒ RL ≥ 12.5 k
=
ω0 =
(4.15 × 1011 )2
1017
= 1.72 × 106 /cm3
1
CL (RL Ro )
1
=
CL (12.5 50) × 103
For ω0 to be a least 2π × 100 × 103 , the highest
value allowed for CL is
CL =
V2
1
= 159.2 pF
2π × 10 × 10 × 103
5
Ex: 1.27 At 300 K, ni = 1.5 × 1010 /cm3
pp = NA
Want electron concentration
= np =
1.5 × 1010
= 1.5 × 104 /cm3
106
∴ NA = pp =
ni2
np
Exercise 1–6
=
(1.5 × 1010 )2
1.5 × 104
= 1.5 × 10 /cm
16
Dn = μn VT = 1350 × 25.9 × 10−3
∼
= 35 cm2 /s
3
Dp = μp VT = 480 × 25.9 × 10−3
∼
= 12.4 cm2 /s
Ex: 1.28 (a) νn−drift = −μn E
Here negative sign indicates that electrons move
in a direction opposite to E.
We use
νn-drift = 1350 ×
1
∵ 1 μm = 10−4 cm
2 × 10−4
= 6.75 × 106 cm/s = 6.75 × 104 m/s
(b) Time taken to cross 2-μm
length =
2 × 10−6
30 ps
6.75 × 104
(c) In n-type silicon, drift current density Jn is
Ex: 1.31 Equation (1.50),
2s 1
1
+
V0
W =
q NA
ND
2s NA + ND
=
V0
q
NA ND
2s NA + ND
W2 =
V0
q
NA ND
1 q
NA ND
V0 =
W2
2 s
NA + ND
Jn = qnμn E
1V
2 × 10−4
= 1.6 × 10−19 × 1016 × 1350 ×
= 1.08 × 104 A/cm2
Ex: 1.32 In a p+ n diode NA ND
2s 1
1
Equation (1.50), W =
+
V0
q NA
ND
(d) Drift current In = AJn
thus
= 27 μA
−8
Note that 0.25 μm = 0.25 × 10
2
Ex: 1.29 Jn = qDn
2
cm .
dn(x)
dx
W
n0 = 10 /cm = 10 /(μm)
5
3
3
Dn = 35 cm2 /s = 35 × (104 )2 (μm)2 /s
dn
105 − 0
=
= 105 μm−4
dx
1
dn(x)
Jn = qDn
dx
= 1.6 × 10
−6
= 56 × 10
× 35 × 10 × 10
NA
NA
=W
ND
NA + ND
8
ND
ND
NA
W
=W
NA
ND
5
For In = 1 mA = Jn × A
1 mA
10 μA
⇒A=
=
18 μm2
Jn
56 μA/(μm)2
3
Ex: 1.30 Using Eq. (1.45),
Equation (1.53), QJ = Aq
Aq
2
Dp
Dn
=
= VT
μn
μp
NA
NA + ND
since NA
A/μm2
= 56 μA/μm
2s
· V0
qND
Equation (1.52), xp = W
= 35 × 108 (μm)2 /s
−19
W Equation (1.51), xn = W
From Fig. E1.5,
17
1
1
as compared to
,
NA
ND
We can neglect the term
= 0.25 × 10−8 × 1.08 × 104
NA ND
W
NA + ND
NA ND
W
NA
= AqND W
NA ND
V0
Equation (1.54), QJ = A 2s q
NA + ND
NA ND
A 2s q
ND
V0 since NA
NA
= A 2s qND V0
Exercise 1–7
Ex: 1.33 In Example 1.10, NA = 1018 /cm3 and
= 6.08 × 10−5 cm = 0.608 μm
ND = 1016 /cm3
Using Eq. (1.53),
NA ND
W
QJ = Aq
NA + ND
18
10 × 1016
= 10−4 × 1.6 × 10−19
× 6.08 ×
1018 + 1016
In the n-region of this pn junction
nn = ND = 1016 /cm3
pn =
n2i
(1.5 × 1010 )2
=
= 2.25 × 104 /cm3
nn
1016
As one can see from above equation, to increase
minority-carrier concentration (pn ) by a factor of
2, one must lower ND (= nn ) by a factor of 2.
10−5 cm
= 9.63 pC
Reverse current I = IS = Aqn2i
Ex: 1.34
Equation (1.65) IS =
Since
Aqn2i
= 10−14 × 1.6 × 10−19 × (1.5 × 1010 )2
10
18
×
+
5 × 10−4 × 1016
10 × 10−4 × 1018
Dp
Dn
+
.
Lp ND
Ln NA
Dp
Dn
and
have approximately
Lp
Ln
similar values, if NA
= 7.3 × 10−15 A
ND , then the term
Dp
can be neglected as compared to
.
Lp ND
Dn
Ln NA
Dp
∴ IS ∼
= Aqn2i
Lp ND
Ex: 1.35 IS = Aqn2i
Dp
Dn
+
Lp ND
Ln NA
= 10−4 × 1.6 × 10−19 × (1.5 × 1010 )2
⎛
⎜
×⎜
⎝
10
5 × 10−4 ×
+
16
10
2
⎞
⎟
18
⎟
−4
18 ⎠
10 × 10 × 10
= 1.46 × 10−14 A
I = IS (eV /V T − 1)
−3 )
IS eV /V T = 1.45 × 10−14 e0.605/(25.9×10
= 0.2 mA
2s
q
Ex: 1.36 W =
=
2 × 1.04 × 10−12
1.6 × 10−19
1
1
+
NA
ND
1
1018
=
= 3.2 pF
Equation (1.71),
Cj0
Cj = VR
1+
V0
3.2 × 10−12
= 2
1+
0.814
+
1
(V0 − VF )
(0.814 − 0.605)
1016
= 1.66 × 10−5 cm = 0.166 μm
Ex: 1.37 W =
Ex: 1.38 Equation (1.72),
q N N 1 s
A D
Cj0 = A
2
NA + ND
V0
1.04 × 10−12 × 1.6 × 10−19
= 10−4
2
1018 × 1016
1
0.814
1018 + 1016
= 1.72 pF
2s
q
2 × 1.04 × 10−12
1.6 × 10−19
1
1
+
NA
ND
1
1018
+
(V0 + VR )
1
1016
Dp
Dn
+
Lp ND
Ln NA
(0.814 + 2)
Ex: 1.39 Cd =
d
dQ
=
(τ T I )
dV
dV
d
[τ T × IS (eV /V T − 1)]
dV
d
(eV /V T − 1)
= τ T IS
dV
1 V /V T
e
= τ T IS
VT
τT
=
× IS eV /V T
VT
τT
∼
I
=
VT
=
Exercise 1–8
Ex: 1.40 Equation (1.75),
τp =
ND = 1016 /cm3
L2p
Dp
Assuming NA
−4 2
(5 × 10 )
10
= 25 ns
=
In Example 1.10, NA = 1018 /cm3 ,
Equation (1.81),
τT
I
Cd =
VT
ND ,
τ T τ p = 25 ns
25 × 10−9
∴ Cd =
0.1 × 10−3
25.9 × 10−3
= 96.5 pF
Chapter 1–1
(e) P = I 2 R ⇒ I = P/R
I = 1000 mW/1 k = 31.6 mA
5V
V
=
= 5 mA
R
1 k
5V
V
=
= 5 k
(b) R =
I
1 mA
(c) V = IR = 0.1 mA × 10 k = 1 V
1.1 (a) I =
V = IR = 31.6 mA × 1 k = 31.6 V
1V
V
=
= 0.01 A = 10 mA
(d) I =
R
100 Note: Volts, milliamps, and kilohms constitute a
consistent set of units.
1.2 (a) P = I 2 R = (20 × 10−3 )2 × 1 × 103
= 0.4 W
−3 2
(b) P = I R = (40 × 10 ) × 1 × 10
1.4 See figure on next page, which shows that
there are 17 possible resistance values: 5.7, 6.7, 8,
8.6, 10, 13.3, 14.3, 17.1, 20, 23.3, 28, 30, 40,
46.7, 50, 60, and 70 k.
1.5 Shunting the 10 k by a resistor of value of R
result in the combination having a resistance Req ,
1
Thus, R should have a -W rating.
2
2
Note: V, mA, k, and mW constitute a consistent
set of units.
3
Req =
10R
R + 10
= 1.6 W
Thus, for a 1% reduction,
Thus, the resistor should have a 2-W rating.
R
= 0.99 ⇒ R = 990 k
R + 10
(c) P = I 2 R = (1 × 10−3 )2 × 100 × 103
= 0.1 W
1
Thus, the resistor should have a -W rating.
8
(d) P = I 2 R = (4 × 10−3 )2 × 10 × 103
= 0.16 W
Thus, the resistor should have a
1
-W rating.
4
(e) P = V 2 /R = 202 /(1 × 103 ) = 0.4 W
Thus, the resistor should have a
1
-W rating.
2
(f) P = V /R = 11 /(1 × 10 ) = 0.121 W
2
2
For a 5% reduction,
R
= 0.95 ⇒ R = 190 k
R + 10
For a 10% reduction,
R
= 0.90 ⇒ R = 90 k
R + 10
For a 50% reduction,
R
= 0.50 ⇒ R = 10 k
R + 10
Shunting the 10 k by
(a) 1 M results in
3
1
Thus, a rating of W should theoretically suffice,
8
1
though W would be prudent to allow for
4
inevitable tolerances and measurement errors.
1.3 (a) V = IR = 5 mA × 1 k = 5 V
P = I 2 R = (5 mA)2 × 1 k = 25 mW
(b) R = V /I = 5 V/1 mA = 5 k
P = VI = 5 V × 1 mA = 5 mW
Req =
10
10 × 1000
=
= 9.9 k
1000 + 10
1.01
a 1% reduction;
(b) 100 k results in
Req =
10 × 100
10
=
= 9.09 k
100 + 10
1.1
a 9.1% reduction;
(c) 10 k results in
Req =
10
= 5 k
10 + 10
a 50% reduction.
(c) I = P/V = 100 mW/10 V = 10 mA
R = V /I = 10 V/10 mA = 1 k
(d) V = P/I = 1 mW/0.1 mA
= 10 V
R = V /I = 10 V/0.1 mA = 100 k
1.6 VO = VDD
R2
R1 + R2
To find RO , we short-circuit VDD and look back
into node X,
RO = R2 R1 =
R1 R2
R1 + R2
Chapter 1–2
This figure belongs to 1.4.
10
10
10
40
46.7
20
20
20
10
40
20
30
40
10
10
40
50
20
6.7
20
40
60
10
10
40
20
70
20
40
40
8.0
10
13.3
20
40
8.6
40
14.3
20
17.1
10
20
20
5.7
10
40
20
40
10
40
23.3
10
10
20
40
1.7 Use voltage divider to find VO
VO = 5
2
=2V
2+3
28
5 V
3 k
Equivalent output resistance RO is
VO
RO = (2 k 3 k) = 1.2 k
The extreme values of VO for ±5% tolerance
resistor are
VOmin = 5
2(1 − 0.05)
2(1 − 0.05) + 3(1 + 0.05)
2 k
RO
= 1.88 V
VOmax = 5
= 2.12 V
2(1 + 0.05)
2(1 + 0.05) + 3(1 − 0.05)
The extreme values of RO for ±5% tolerance
resistors are 1.2 × 1.05 = 1.26 k and
1.2 × 0.95 = 1.14 k.
Chapter 1–3
1.8
9 V
9 V
10 k
6 V
R 20 // 10 k
6.67 k
10 k
10 k
3 V
R 10 // 10 // 10
3.33 k
3 V
R 10 k // 20 k
6.67 k
10 k
10 k
10 k
(c)
(a)
9 V
9 V
10 k
10 k
10 k
6 V
4.5 V
10 k
10 k
R 10 // 10
5 k
R 10 // 10 // 10
3.33 k
(b)
(d)
15 V
Voltage generated:
+3V [two ways: (a) and (c) with (c) having lower
output resistance]
+4.5 V (b)
+6V [two ways: (a) and (d) with (d) having a
lower output resistance]
R
10 k
5.00 V
1.9
15 V
4.7 k
10 k
VO
4.7 k
Thus
1
1
1
+ =
10 R
9.4
⇒ R = 156.7 ≈ 157 k
Now,
VO = 15
4.7
= 4.80 V
10 + 4.7
To increase VO to 10.00 V, we shunt the 10-k
resistor by a resistor R whose value is such that
10 R = 2 × 4.7.
RO = 10 k R 4.7 k
9.4
= 3.133 k
3
To make RO = 3.33, we add a series resistance of
approximately 200 , as shown on the next page.
= 9.4 4.7 =
Chapter 1–4
This figure belongs to 1.9.
that the current through it will be 0.8I ; thus
15 V
157 k
R
4
The input resistance of the divider, Rin , is
0.2IR = 0.8IR1 ⇒ R1 =
10 k
R
1
= R
4
5
Now if R1 is 10% too high, that is, if
Rin = R R1 = R 200 R
4
the problem can be solved in two ways:
R1 = 1.1
VO
4.7 k
RO
(a) Connect a resistor R2 across R1 of value such
that R2 R1 = R/4, thus
R
R2 (1.1R/4)
=
R2 + (1.1R/4)
4
1.10
I1
I
R1
I2
V
R2
1.1R2 = R2 +
11R
= 2.75 R
4
1.1R 11R
Rin = R 4
4
R
R
=R =
4
5
⇒ R2 =
V = I (R1 R2 )
R1 R2
=I
R1 + R2
V
R2
I1 =
=I
R1
R1 + R2
V
R1
I2 =
=I
R2
R1 + R2
0.2I
I
2
I
3
I
3
RL 10 k
R
4
(b) Connect a resistor in series with the load
resistor R so as to raise the resistance of the load
branch by 10%, thereby restoring the current
division ratio to its desired value. The added
series resistance must be 10% of R (i.e., 0.1R).
⇒ R = 5 k
IL R
0.8 I
0.2 I
0.1R
1.1R
4
I
1.12
R
0.2 I
0.8 I
Rin
I
R
11R
4
}
10I /3 = 2IR/3
1.1R
4
R
Rin
1.11 Connect a resistor R in parallel with RL .
To make IL = I /3 (and thus the current through
R, 2I /3), R should be such that
I
1.1R
4
R1
Rin
To make the current through R equal to 0.2I , we
shunt R by a resistance R1 having a value such
Rin = 1.1R 1.1R
4
1.1R
5
that is, 10% higher than in case (a).
=
Chapter 1–5
1.13 For RL = 10 k , when signal source
generates 0−0.5 mA, a voltage of 0−2 V may
appear across the source
(b) Same procedure is used for (b) to obtain
0.5 k
2
0.75 V
3
is
00.5 mA
RL
vs
(c) Between terminals 1 and 3, the open-circuit
voltage is 1.5 V. When we short circuit the voltage
source, we see that the Thévenin resistance will
be zero. The equivalent circuit is then
R
1
To limit v s ≤ 1 V, the net resistance has to be
≤ 2 k. To achieve this we have to shunt RL with
a resistor R so that (R RL ) ≤ 2 k.
1.5 V
R RL ≤ 2 k.
3
RRL
≤ 2 k
R + RL
1.15
For RL = 10 k
R ≤ 2.5 k
The resulting circuit needs only one additional
resistance of 2 k in parallel with RL so that
v s ≤ 1 V. The circuit is a current divider, and the
current through RL is now 0–0.1 mA.
1.14 (a) Between terminals 1 and 2:
1
1 k
1.5 V
VTh
2
1 k
RTh
1 k
RTh
1 k
1
0.5 k
0.75 V
2
(cont’d on the next page)
Chapter 1–6
12.31 k
0.77 V
Now, subtracting Eq. (1) from Eq. (3) yields
I
40I2 = 20
3 k
⇒ I2 = 0.5 mA
Substituting in Eq. (2) gives
2I1 = 5 − 7 × 0.5 mA
Now, when a resistance of 3 k is connected
between node 4 and ground,
I=
⇒ I1 = 0.75 mA
0.77
12.31 + 3
I3 = I1 + I2
= 0.05 mA
= 0.75 + 0.5
= 1.25 mA
1.16 (a) Node equation at the common mode
yields
V = I3 R3
I3 = I1 + I2
Using the fact that the sum of the voltage drops
across R1 and R3 equals 10 V, we write
10 = I1 R1 + I3 R3
= 10I1 + (I1 + I2 ) × 2
= 12I1 + 2I2
R1
10 k
I2 = 0.5 mA
I3 = 1.25 mA
V = 2.5 V
Thus,
10 − V
5−V
V
+
=
10
5
2
I1
V
I1 = 0.75 mA
10 − V
5−V
V
+
=
R1
R2
R3
5 V
I2
To summarize:
(b) A node equation at the common node can be
written in terms of V as
10 V
R2
5 k
= 1.25 × 2 = 2.5 V
I3
⇒ 0.8V = 2
R3
2 k
⇒ V = 2.5 V
Now, I1 , I2 , and I3 can be easily found as
I1 =
That is,
12I1 + 2I2 = 10
(1)
10 − 2.5
10 − V
=
10
10
= 0.75 mA
5 − 2.5
5−V
=
5
5
Similarly, the voltage drops across R2 and R3 add
up to 5 V, thus
I2 =
5 = I2 R2 + I3 R3
= 0.5 mA
= 5I2 + (I1 + I2 ) × 2
I3 =
which yields
2I1 + 7I2 = 5
(2)
Equations (1) and (2) can be solved together by
multiplying Eq. (2) by 6:
12I1 + 42I2 = 30
(3)
V
2.5
= 1.25 mA
=
R3
2
Method (b) is much preferred, being faster, more
insightful, and less prone to errors. In general,
one attempts to identify the lowest possible
number of variables and write the corresponding
minimum number of equations.
Chapter 1–7
1.17 Find the Thévenin equivalent of the circuit
to the left of node 1.
current Vx /2 k and Ix will be the sum of the two
current,
Ix =
2Vx
Vx
=
2 k
1 k
Between node 1 and ground,
RTh = (1 k 1.2 k) = 0.545 k
VTh = 10 ×
1.2
= 5.45 V
1 + 1.2
Find the Thévenin equivalent of the circuit to the
right of node 2.
Thus,
Req ≡
Vx
= 1 k
Ix
Now, if R4 is raised to 1.2 k, the symmetry will
be broken. To find Is we use Thévenin’s theorem
as shown in the figures on the next page. Thus,
I5 =
0.545Vx − 0.5Vx
= 0.022Vx
0.5 + 1 + 0.545
Vx
+ 0.022 Vx × 0.5
2
= 0.5Vx × 1.022 = 0.511Vx
V1 =
Between node 2 and ground,
V2 = V1 + I5 R5 = 0.533Vx
RTh = 9.1 k 11 k = 4.98 k
VTh = 10 ×
Vx − V1
= 0.489Vx
1 k
Vx − V2
I2 =
= 0.467Vx
1 k
Ix = I1 + I2 = 0.956Vx
I1 =
11
= 5.47 V
11 + 9.1
The resulting simplified circuit is
0.545 k 1
I5
2 4.98 k
⇒ Req ≡
R5 2 k
5.45 V
I5 =
V5
5.47 V
5.47 − 5.45
4.98 + 2 + 0.545
= 2.66 μA
V5 = 2.66 μA × 2 k
= 5.32 mV
1.18 From the symmetry of the circuit, there will
be no current in R5 . (Otherwise the symmetry
would be violated.) Thus each branch will carry a
Vx
= 1.05 k
Ix
1.19 Refer to Fig. P1.19. Using the voltage
divider rule at the input side, we obtain
rπ
vπ
=
vs
rπ + Rs
(1)
At the output side, we find v o by multiplying the
current gm v π by the parallel equivalent of ro
and RL ,
v o = −gm v π (ro RL )
(2)
Finally, v o /v s can be obtained by combining Eqs.
(1) and (2) as
rπ
vo
=−
gm (ro RL )
vs
rπ + Rs
Chapter 1–8
This figure belongs to Problem 1.18.
(c) ω = 6.28 × 102 rad/s
ω
= 102 Hz
f =
2π
1
T = = 10−2 s
f
(d) T = 10 s
f =
1
= 10−1 Hz
T
ω = 2πf = 6.28 × 10−1 rad/s
(e) f = 60 Hz
T=
1
= 1.67 × 10−2 s
f
ω = 2πf = 3.77 × 102 rad/s
(f) ω = 1 krad/s = 103 rad/s
ω
= 1.59 × 102 Hz
f =
2π
1
T = = 6.28 × 10−3 s
f
(g) f = 1900 MHz = 1.9 × 109 Hz
T=
1
= 5.26 × 10−10 s
f
ω = 2π f = 1.194 × 1010 rad/s
1.21 (a) Z = 1 k at all frequencies
(b) Z = 1 /jωC = − j
At f = 60 Hz,
1
2πf × 10 × 10−9
Z = − j265 k
At f = 100 kHz, Z = − j159 At f = 1 GHz,
Z = − j0.016 (c) Z = 1 /jωC = − j
At f = 60 Hz,
1
2πf × 10 × 10−12
Z = − j0.265 G
At f = 100 kHz, Z = − j0.16 M
At f = 1 GHz,
Z = − j15.9 (d) Z = jωL = j2πf L = j2πf × 10 × 10−3
1.20 (a) T = 10−4 ms = 10−7 s
At f = 60 Hz,
Z = j3.77 1
= 107 Hz
f =
T
At f = 100 kHz,
Z = j6.28 k
At f = 1 GHz,
Z = j62.8 M
ω = 2πf = 6.28 × 107 rad/s
(b) f = 1 GHz = 109 Hz
T=
1
= 10−9 s
f
ω = 2πf = 6.28 × 10 rad/s
9
(e) Z = jωL = j2πf L = j2πf (1 × 10−6 )
f = 60 Hz,
Z = j0.377 m
f = 100 kHz,
Z = j0.628 f = 1 GHz,
Z = j6.28 k
Chapter 1–9
1.22 (a) Z = R +
1
jωC
(b) v s = v oc = 0.1 V
is = isc = 1 μA
1
= 10 +
j2π × 10 × 103 × 10 × 10−9
3
v oc
0.1 V
= 0.1 M = 100 k
=
isc
1 μA
Rs =
= (1 − j1.59) k
(b) Y =
=
1
+ jωC
R
1.24 The observed output voltage is 1 mV/ ◦ C,
which is one half the voltage specified by the
sensor, presumably under open-circuit conditions:
that is, without a load connected. It follows that
that sensor internal resistance must be equal to
RL , that is, 5 k.
1
+ j2π × 10 × 103 × 0.01 × 10−6
104
= 10−4 (1 + j6.28) Z=
=
104
1
=
Y
1 + j6.28
1.25
Rs
10 (1 − j6.28)
1 + 6.282
4
= (247.3 − j1553) vs
1
(c) Y = + jωC
R
1
+ j2π × 10 × 103 × 100 × 10−12
=
100 × 103
−5
= 10 (1 + j0.628)
Z=
105
1 + j0.628
(d) Z = R + jωL
= 40
1+
1.23
(2)
1 + (Rs /10)
=4
1 + (Rs /100)
Rs
is
Thévenin
equivalent
v oc = v s
Rs
⇒ RS = 50 k
Substituting in Eq. (2) gives
Norton
equivalent
v s = 60 mV
The Norton current is can be found as
is =
isc = is
v s = is Rs
vs
60 mV
= 1.2 μA
=
Rs
50 k
1.26
Rs
Thus,
v oc
isc
(a) v s = v oc = 1 V
vs v oc
1V
=
= 10 k
isc
0.1 mA
io vo
is = isc = 0.1 mA
Rs =
(1)
= 10
Rs
10
Dividing Eq. (1) by Eq. (2) gives
= (100 + j628), Rs =
Rs
100
and
vs
= 100 + j6.28 × 100
vs RL
vo
=
vs
RL + Rs
Rs
vo = vs
1+
RL
1+
= 100 + j2π × 10 × 103 × 10 × 10−3
RL vo
Thus,
vs
= (71.72 − j45.04) k
v o = v s − io Rs
is
io Rs
vo
Chapter 1–10
Highest value = 1 V
1
2π
Period T = =
= 10−3 s
f0
ω0
1
Frequency f = = 1 kHz
I
vo
Open-circuit
(io 0)
vs
voltage
Slope Rs
vs
is
Rs
0
io
Short-circuit (vo 0) current
1.27
Case
ω (rad/s)
f (Hz)
T (s)
a
3.14 × 1010
5 × 109
0.2 × 10−9
b
2 × 10
3.18 × 10
c
6.28 × 10
d
3.77 × 102
60
1.67 × 10−2
e
6.28 × 104
1 × 104
1 × 10−4
f
6.28 × 105
1 × 105
1 × 10−5
9
8
10
−9
3.14 × 10
1 × 10−10
1 × 10
10
1.31 The two harmonics have the ratio
126/98 = 9/7. Thus, these are the 7th and 9th
harmonics. From Eq. (1.2), we note that the
amplitudes of these two harmonics will have the
ratio 7 to 9, which is confirmed by the
measurement reported. Thus the fundamental will
have a frequency of 98/7, or 14 kHz, and peak
amplitude of 63 × 7 = 441 mV.
√ The rms value of
the fundamental will be 441/ 2 = 312 mV. To
find the peak-to-peak amplitude of the square
wave, we note that 4V/π = 441 mV. Thus,
Peak-to-peak amplitude
π
= 2V = 441 × = 693 mV
2
1
1
= 71.4 μs
Period T = =
f
14 × 103
1.32
Decimal Binary
1.28 (a) v = 10 sin(2π × 103 t), V
√
(b) v = 120 2 sin(2π × 60),V
0
0
6
110
11
1011
28
11100
59
111011
(c) v = 0.1 sin(2000t), V
(d) v = 0.1 sin(2π × 103 t), V
√
1.29 (a) Vpeak = 117 × 2 = 165 V
√
(b) Vrms = 33.9/ 2 = 24 V
√
(c) Vpeak = 220 × 2 = 311 V
√
(d) Vpeak = 220 × 2 = 311 kV
1.33
b3
b2
b1
b0
Value Represented
0
0
0
0
+0
0
0
0
1
+1
0
0
1
0
+2
0
0
1
1
+3
0
1
0
0
+4
0
1
0
1
+5
0
1
1
0
+6
0
1
1
1
+7
1
0
0
0
–0
1
0
0
1
–1
1
0
1
0
–2
1
0
1
1
–3
1
1
0
0
–4
Average value = 0.5 V
1
1
0
1
–5
Peak-to-peak value = 1 V
1
1
1
0
–6
1
1
1
1
–7
1.30 Comparing the given waveform to that
described by Eq. (1.2), we observe that the given
waveform has an amplitude of 0.5 V (1 V
peak-to-peak) and its level is shifted up by 0.5 V
(the first term in the equation). Thus the
waveform looks as follows:
v
1V
T
0
Lowest value = 0 V
...
t
Chapter 1–11
Note that there are two possible representations of
zero: 0000 and 1000. For a 0.5-V step size, analog
signals in the range ±3.5 V can be represented.
Input
Steps Code
+2.5 V
+5
b1 is the MSB
(c) iOmax =
10 V
10 k
1
1
1
1
+ 2 + 3 + 4
21
2
2
2
0101
−3.0 V
−6
1110
+2.7
+5
0101
−2.8
−6
1110
1.34 (a) For N bits there will be 2N possible
levels, from 0 to VFS . Thus there will be (2N − 1)
discrete steps from 0 to VFS with the step size
given by
Step size =
(b) bN is the LSB
VFS
2N − 1
This is the analog change corresponding to a
change in the LSB. It is the value of the resolution
of the ADC.
(b) The maximum error in conversion occurs
when the analog signal value is at the middle of a
step. Thus the maximum error is
+
1
1
1
1
+ 6 + 7 + 8
25
2
2
2
= 0.99609375 mA
Corresponding to the LSB changing from 0 to 1
the output changes by (10/10) × 1/28 =
3.91 μA.
1.36 There will be 44,100 samples per second
with each sample represented by 16 bits. Thus the
throughput or speed will be 44, 100 × 16 =
7.056 × 105 bits per second.
1.37 (a) Av =
vO
10 V
= 100 V/V
=
vI
100 mV
or 20 log 100 = 40 dB
Ai =
0.1 A
iO
v O /RL
10 V/100 =
=
=
iI
iI
100 μA
100 μA
= 1000 A/A
or 20 log 1000 = 60 dB
Step
Ap =
v O iO
vO
iO
=
×
= 100 × 1000
v I iI
vI
iI
= 105 W/W
or 10 log 105 = 50 dB
1 VFS
1
× step size =
2
2 2N − 1
This is known as the quantization error.
5V
≤ 2 mV
(c) N
2 −1
(b) Av =
2N − 1 ≥ 2500
For N = 12,
Resolution =
5
= 1.2 mV
212 − 1
Quantization error =
1.2
= 0.6 mV
2
1.35 (a) When bi = 1, the ith switch is in
position 1 and a current (Vref /2i R) flows to the
output. Thus iO will be the sum of all the currents
corresponding to “1” bits, that is,
Vref b1
b2
bN
+
+
·
·
·
+
iO =
R
21
22
2N
vO
1V
= 1 × 105 V/V
=
vI
10 μV
or 20 log 1 × 105 = 100 dB
Ai =
2N ≥ 2501 ⇒ N = 12,
=
iO
v O /RL
1 V/10 k
=
=
iI
iI
100 nA
0.1 × 10−3
0.1 mA
=
= 1000 A/A
100 nA
100 × 10−9
or 20 log Ai = 60 dB
Ap =
v O iO
vO
iO
=
×
v I iI
vI
iI
= 1 × 105 × 1000
= 1 × 108 W/W
or 10 log AP = 80 dB
(c) Av =
vO
5V
= 5 V/V
=
vi
1V
or 20 log 5 = 14 dB
Chapter 1–12
Ai =
iO
v O /RL
5 V/10 =
=
iI
iI
1 mA
or 20 log 11 = 20.8 dB
Ai =
0.5 A
= 500 A/A
=
1 mA
22 mA
= 22 A/A
1 mA
or 20 log Ai = 26.8 dB
√
po
(2.2/ 2)2 /100
Ap =
=
pi
0.2
10−3
√ × √
2
2
=
or 20 log 500 = 54 dB
v O iO
vO
iO
=
×
v I iI
vI
iI
Ap =
io
2.2 V/100 =
ii
1 mA
= 5 × 500 = 2500 W/W
or 10 log Ap = 34 dB
= 242 W/W
1.38 For ±5 V supplies:
The largest undistorted
√ sine-wave output is of 4-V
peak amplitude or 4/ 2 = 2.8 Vrms . Input
needed is 14 mVrms .
For ±10-V supplies, the largest undistorted
sine-wave output is of 9-V peak amplitude or
6.4 Vrms . Input needed is 32 mVrms .
vO
VDD 1.0
200 V/V
or 10 log AP = 23.8 dB
Supply power = 2 × 3 V ×20 mA = 120 mW
√
v2
(2.2/ 2)2
= 24.2 mW
Output power = orms =
RL
100 24.2
= 0.1 mW (negligible)
242
Amplifier dissipation Supply power − Output
power
Input power =
= 120 − 24.2 = 95.8 mW
Amplifier efficiency =
vI
=
VDD 1.0
Output power
× 100
supply power
24.2
× 100 = 20.2%
120
RL
RL + Ro
RL
Ri
= Av o v s
Ri + Rs RL + Ro
1.40 v o = Av o v i
For ±15-V supplies, the largest undistorted
sine-wave output is of 14-V peak amplitude or
9.9 Vrms . The input needed is 9.9 V/200 =
49.5 mVrms .
Rs
1.39
vs +3 V
1 mA
t
Ri
Av ovi RL
vi
20 mA
(average)
vo
vi vi
2.2 V
ii
Ro
0.2 V
20 mA
(average)
3 V
RL
100 Thus,
Ri
RL
vo
= Av o
vs
Ri + Rs RL + Ro
(a) Av o = 100, Ri = 10Rs , RL = 10Ro :
10Rs
10Ro
vo
= 100 ×
×
vs
10Rs + Rs
10Ro + Ro
= 82.6 V/V or 20 log 82.6 = 38.3 dB
vo
2.2
Av =
=
vi
0.2
= 11 V/V
(b) Av o = 100, Ri = Rs , RL = Ro :
vo
1 1
= 100 × × = 25 V/V or 20 log 25 = 28 dB
vs
2 2
Chapter 1–13
vo
RL
=
vs
RL + Rs
(c) Av o = 100 V/V, Ri = Rs /10, RL = Ro /10:
Rs /10
Ro /10
vo
= 100
vs
(Rs /10) + Rs (Ro /10) + Ro
=
= 0.826 V/V or 20 log 0.826 = −1.7 dB
100 100 + 100 k
0.001 V/V
Rs 100 k
1.41
100 vo
100vi 500 vi
1 M
which is clearly a much worse situation. Indeed
inserting the amplifier increases the gain by a
factor 8.3/0.001 = 8300.
20 log Av o = 40 dB ⇒ Av o = 100 V/V
vo
Av =
vi
500
= 100 ×
500 + 100
= 83.3 V/V
1.43
1V
1 M
For a peak output sine-wave current of 20 mA,
the peak output voltage will be 20 mA × 500 = 10 V. Correspondingly v i will be a sine wave
with a peak value of 10 V/A
√ v = 10/83.3, or an
rms value of 10/(83.3 × 2) = 0.085
√ V.
Corresponding output power = (10/ 2)2 /500 = 0.1 W
1.42
Rs
vs
vi
Ri
Av ovi
vo = 1 V ×
RL
×1×
100 1vi
vo
1 M
1 M + 200 k
100 100 + 20 100
1
×
= 0.69 V
1.2 120
vo
= 0.69 V/V or −3.2 dB
Voltage gain =
vs
=
Current gain =
Ro
vi
v 2o /500 = A2v × 104 = 1.39 × 107 W/W
v 2i /1 M
or 10 log (1.39 × 107 ) = 71.4 dB.
20 200 k
or 20 log 83.3 = 38.4 dB
Ap =
vo
RL
100 vs v o /100 = 0.69 × 1.2 × 104
v s /1.2 M
vo
= 8280 A/A
or
Power gain =
v 2o /100 v 2s /1.2 M
78.4 dB
= 5713 W/W
or 10 log 5713 = 37.6 dB
vo
100 10 k
× 1000 ×
=
vs
10 k + 100 k
100 + 1 k
100
10
× 1000 ×
= 8.26 V/V
=
110
1100
The signal loses about 90% of its strength when
connected to the amplifier input (because
Ri = Rs /10). Also, the output signal of the
amplifier loses approximately 90% of its strength
when the load is connected (because RL = Ro /10).
Not a good design! Nevertheless, if the source
were connected directly to the load,
(This takes into account the power dissipated in
the internal resistance of the source.)
1.44 (a) Case S-A-B-L (see figure on next page):
vo
vo
v ib
v ia
=
×
×
=
vs
v ib
v ia
vs
10
100
× 100 ×
×
10 ×
100 +1000
10 + 10
100
100 + 100
Chapter 1–14
This figure belongs to 1.44, part (a).
This figure belongs to 1.44, part (b).
This figure belongs to Problem 1.45.
vo
= 22.7 V/V and gain in dB 20 log 22.7 =
vs
Av 2 =
27.1 dB
= 9.09 V/V
(b) Case S-B-A-L (see figure above):
Av 3 =
v o v ia v ib
vo
=
·
·
vs
v ia v ib v s
100
×
= 100 ×
100 + 10 K
100 K
10 ×
×
100 K + 1 K
10 K
10 K + 100 K
vo
= 0.89 V/V and gain in dB is 20 log 0.89 =
vs
−1 dB. Obviously, case a is preferred because it
provides higher voltage gain.
1.45 In Example 1.3, when the first and the
second stages are interchanged, the circuit looks
like the figure above, and
v i1
100 k
= 0.5 V/V
=
vs
100 k + 100 k
Av 1 =
v i2
1 M
= 100 ×
v i1
1 M + 1 k
= 99.9 V/V
v i3
10 k
= 10 ×
v i2
10 k + 1 k
vL
100 = 0.909 V/V
=1×
v i3
100 + 10 Total gain = Av =
vL
= Av 1 × Av 2 × Av 3
v i1
= 99.9 × 9.09 × 0.909 = 825.5 V/V
The voltage gain from source to load is
vL
vL
v i1
v i1
=
×
= Av ·
vs
v i1
vS
vS
= 825.5 × 0.5
= 412.7 V/V
The overall voltage has reduced appreciably. This
is because the input resistance of the first stage,
Rin , is comparable to the source resistance Rs . In
Example 1.3 the input resistance of the first stage
is much larger than the source resistance.
1.46 Each of stages #1, 2, ..., (n − 1) can be
represented by the equivalent circuit:
vo
v i1
v i2
v i3
v in
vo
=
×
×
× ··· ×
×
vs
vs
v i1
v i2
v i(n−1)
v in
where
Chapter 1–15
This figure belongs to 1.46.
Rs 10 k
vs
5 mV
#1
#2
#n
vi1
vi2
vin
vo
RL
200 Ri1 10 k
Ron 1 k
1 k
#m
vim
vi(m 1)
vim
Ri(m 1) v i1
10 k
= 0.5 V/V
=
vs
10 k + 10 k
10 k
10 k vi(m 1)
10vim
Thus Ri = 40 k.
vo
200 = 1.67 V/V
= 10 ×
v in
1 k + 200 v i2
10 k
v i3
v in
=
= ··· =
= 10×
v i1
v i2
v i(n−1)
10 k + 10 k
= 9.09 V/V
For Ri = 40 k. ii = 0.1 μA peak, and
=
2 mA
= 2 × 104 A/A
0.1 μA
Overall power gain ≡
Thus,
2 V/1 k
v o /RL
=
ii
0.1 μA
Overall current gain =
vo
= 0.5 × (9.09)n−1 × 1.67 = 0.833 × (9.09)n−1
vs
2
√
2
−3 v 2orms /RL
v s(rms) × ii(rms)
2 1000
vo
For v s = 5 mV and v o = 3 V, the gain
must be
vs
≥ 600, thus
=
0.833 × (9.09)n−1 ≥ 600
= 8 × 106 W/W
⇒ n=4
(This takes into account the power dissipated in
the internal resistance of the source.)
Thus four amplifier stages are needed, resulting in
vo
= 0.833 × (9.09)3 = 625.7 V/V
vs
and correspondingly
=
vo
vs
2V
= 400 V/V
0.005 V
(b) The smallest Ri allowed is obtained from
0.1 μA =
×
0.1 × 10−6
√
2
5 mV
⇒ Rs + Ri = 50 k
Rs + Ri
(c) If ( Av o v i ) has its peak value limited to 3 V,
the largest value of RO is found from
Ro
Rs 10 k
v o = 625.7 × 5 mV = 3.13 V
1.47 (a) Required voltage gain ≡
5 × 10
√
2
ii
vs
5-mV
peak
=3×
Ri
vi
vo
Av ovi RL
1 k
RL
1
= 2 ⇒ Ro = RL = 500 RL + Ro
2
(If Ro were greater than this value, the output
voltage across RL would be less than 2 V.)
Chapter 1–16
This figure belongs to 1.48.
0.5 M
30 mV
rms
10 k
vi1
∼
1 M
10vi1
vi2
(d) For Ri = 40 k and Ro = 500 , the
required value Av o can be found from
400 V/V =
10 k
100vi2
10 k
vi3
1vi3
vo
100 v i3
10 k
= 100 ×
= 90.9
v i2
10 k + 1 k
⇒ v i3 = 100 mV × 90.9 = 9.09 V
1
40
× Av o ×
40 + 10
1 + 0.5
100 vo
=1×
= 0.833
v i3
100 + 20 ⇒ Av o = 750 V/V
(e) Ri = 100 k(1 × 105 )
⇒ v o = 9.09 × 0.833 = 7.6 V
Ro = 100 (1 × 10 )
2
400 =
20 1 k
Po =
1000
100
× Av o ×
100 + 10
1000 + 100
v 2orms
7.62
= 0.57 W
=
RL
100
which exceeds the required 0.5 W. Also, the
signal throughout the amplifier chain never drops
below 20 mV (which is greater than the required
minimum of 10 mV).
⇒ Av o = 484 V/V
1.48 Deliver 0.5 W to a 100- load.
Source is 30 mV rms with 0.5-M source
resistance. Choose from these three amplifier
types:
A
Ri 1 M
B
Ri 10 k
C
Ri 10 k
Av 10 V/ V
Av 100 V/ V
Av 1 V/ V
Ro 10 k
Ro 1 k
Ro 20 1.49 From the equivalent circuit of the output
side of a voltage amplifier [Fig. 1.16(b)]:
v o = (Av o v i )
RL
RL + Ro
200 = (Av o v i )
1000
1000 + Ro
(1)
195 = (Av o v i )
780
780 + Ro
(2)
Dividing Eq. (2) by Eq. (1), we have
1000 + Ro
195
= 0.78
200
780 + Ro
Choose order to eliminate loading on input and
output:
⇒ Ro = 100 A, first, to minimize loading on 0.5-M source
(Av o v i ) = 200[(1000 + 100)/1000] = 220 mV
B, second, to boost gain
C, third, to minimize loading at 100- output.
We first attempt a cascade of the three stages in
the order A, B, C (see figure above), and obtain
1.50 The equivalent circuit at the output side of a
current amplifier loaded with a resistance RL is
shown. Since
io
1
1 M
v i1
=
=
1 M + 0.5 M
1.5
vs
1
= 20 mV
1.5
10 k
=5
= 10 ×
10 k + 10 k
⇒ v i1 = 30 ×
v i2
v i1
⇒ v i2 = 20 × 5 = 100 mV
Aisii
Ro
RL
Chapter 1–17
io = (Ais ii )
Ro
Ro + RL
we can write
1 = (Ais ii )
Ro
Ro + 1
(1)
and
0.5 = (Ais ii )
Ro
Ro + 12
(2)
1.53 To obtain the weighted sum of v 1 and v 2
Dividing Eq. (1) by Eq. (2), we have
Ro + 12
⇒ Ro = 10 k
Ro + 1
2=
v o = 10v 1 + 20v 2
we use two transconductance amplifiers and sum
their output currents. Each transconductance
amplifier has the following equivalent circuit:
10 + 1
= 1.1 mA
Ais ii = 1 ×
10
1.51
vi
Rs 1 k
Ri
2 k
vs
vi
Gmvi
Ro
RL
Ro
10 k
Gm 20 mA/V
vo
The parallel connection of the two amplifiers at
the output and the connection of RL means that
the total resistance at the output is
RL = 1 k
10
k. Thus the
3
component of v o due to v 2 will be
Ri
Rs + Ri
10 k 10 k 10 k =
2
2
= vs
1+2
3
v o2 = v 2
v o = Gm v i (RL Ro )
10
10
× Gm2 ×
10 + 10
3
= v 2 × 0.5 × 20 ×
20 × 1
vi
= 60
20 + 1
20 2
= 60 × v s
21 3
Overall voltage gain ≡
vo
= 38.1 V/V
vs
1.52
i2
ix
vx Gmvi
Consider first the path for the signal requiring
higher gain, namely v 2 . See figure at top of next
page.
Ro = 20 k
= vs
Ri
10 k
Gm = 60 mA/V
vi = vs
⎫
ix = i1 + i2 ⎪ ix = v x /Ri + gm v x
⎪
⎪
⎪
⎪
1
⎬
i1 = v i /Ri ⎪
ix = v x
+ gm
Ri
⎪
i2 = gm v i ⎪
⎪
1
v
⎪
x
⎪
⎪
=
⎭
i
1/R
x
i + gm
vi = vx
Ri
=
= Rin
1 + gm Ri
vi
i1
Ri
gmvi
10
= 33.3v 2
3
To reduce the gain seen by v 2 from 33.3 to 20, we
connect a resistance Rp in parallel with RL ,
10
Rp = 2 k
3
⇒ Rp = 5 k
We next consider the path for v 1 . Since v 1 must
see a gain factor of only 10, which is half that
seen by v 2 , we have to reduce the fraction of v 1
that appears at the input of its transconductance
amplifier to half that that appears at the input of
the v 2 transconductance amplifier. We just saw
that 0.5 v 2 appears at the input of the v 2
transconductance amplifier. Thus, for the v 1
transconductance amplifier, we want 0.25v 1 to
appear at the input. This can be achieved by
shunting the input of the v 1 transconductance
Chapter 1–18
This figure belongs to Problem 1.53.
amplifier by a resistance Rp1 as in the following
figure.
1+
Rs1 10 k
v1
Thus,
Rp1
Ri1
vi1
10 k
Rs1
=4
(Rp1 Ri1 )
⇒ Rp1 Ri1 =
Rp1 10 =
10
Rs1
=
3
3
10
3
The value of Rp1 can be found from
⇒ Rp1 = 5 k
(Rp1 Ri1 )
= 0.25
(Rp1 Ri1 ) + Rs1
The final circuit will be as follows:
Chapter 1–19
For Rs varying in the range 1 k to 10 k and
load current variation limited to 10%, select Ri to
be sufficiently low:
1.54 Voltage amplifier:
Rs
1 to 10 k
Ro
vs Ri
vo
Avo vi
vi
io
RL
1 k to
10 k
Ri ≤
Rsmin
10
Ri =
1 k
= 100 = 1 × 102 10
For RL varying in the range 1 k to 10 k and
the load current variation limited to 10%, Ro is
selected sufficiently large:
For Rs varying in the range 1 k to 10 k and
v o limited to 10%, select Ri to be sufficiently
large:
Ro ≥ 10 R Lmax
Ri ≥ 10 Rsmax
Ro = 10 × 10 k
Ri = 10 × 10 k = 100 k = 1 × 105 For RL varying in the range 1 k to 10 k, the
load voltage variation limited to 10%, select Ro
sufficiently low:
= 100 k = 1 × 105 Now we find Ais :
Rsmin
Ro
× Ais ×
Rsmin + Ri
Ro + RLmax
RLmin
10
1 k
= 100 = 1 × 102 Ro =
10
Now find Av o :
Ri
RLmin
v omin = 10 mV ×
× Av o
Ri + Rsmax
Ro + RLmin
iomin = 10 μA ×
100 k
100 k + 10 k
1 k
× Av o ×
100 + 1 k
⇒ Av o = 121 V/V
⇒ Ais = 121 A/A
Ro ≤
1 × 10−3 = 10 × 10−6
× Ais
1 = 10 × 10−3 ×
io
Ri
100 k
100 k + 10 k
Current amplifier equivalent circuit:
ii
Ro
vi
1 k
1 k + 100 Ri
vo
Avovi
Ro
Ais ii
Ri = 1 × 102 , Ais = 121 A/A,
Values for the voltage amplifier equivalent
circuit are
Ro = 1 × 105 Ri = 1 × 10 , Av o = 121 V/V, and
5
Ro = 1 × 102 1.56 Transconductance amplifier:
1.55 Current amplifier:
ii
is
10 A
Rs
1 k to Ri
10 k
io
Ais ii
Ro
RL
1 k to
10 k
Rs
1 to 10 k
io
vs
Ri
10 mV
nominal
vi
Gmvi
Ro
RL
1 to
10 k
Chapter 1–20
For Rs varying in the range 1 to 10 k, and io
limited to 10%, we have to select Ri sufficiently
large;
Ri ≥ 10Rsmax
The overall current gain can be found as
io
v o /RL
5 V/2 k
=
=
is
1 μA
1 μA
=
Ri = 100 k = 1 × 105 For RL varying in the range 1 to 10 k, the
change in io can be kept to 10% if Ro is selected
sufficiently large;
2.5 mA
= 2500 A/A
1 μA
or 68 dB.
Ap =
v 2o /RL
= ii2 Ri
Ro ≥ RLmax
52 /(2 × 103 )
2
200
10−6 ×
5 × 103
200 + 5
= 2.63 × 106 W/W or 64.2 dB
Thus Ro = 100 k = 1 × 105 For v s = 10 mV,
iomin = 10−2
Ri
Ro
Gm
Ri + Rsmax
Ro + RLmax
10−3 = 10−2
100
100
Gm
100 + 10
100 + 10
1.58
Gm = 1.21 × 10−1 A/V
= 121 mA/V
In
100 k
vi
1.57 Ro =
= 2 k
v o = 10 ×
Out
Gmvi
100 k
Gm 121 mA/V
Open-circuit output voltage
10 V
=
Short-circuit output current
5 mA
2
=5V
2+2
The node equation at E yields the current through
RE as (βib + ib ) = (β + 1)ib . The voltage v c can
be found in terms of ib as
v c = −βib RL
(1)
The voltage v b can be related to ib by writing for
the input loop:
v b = ib rπ + (β + 1)ib RE
Thus,
v b = [rπ + (β + 1)RE ]ib
(2)
Dividing Eq. (1) by Eq. (2) yields
βRL
vc
=−
vb
rπ + (β + 1)RE
Av =
vo
10(2/4)
=
vi
1 × 10−6 × (200 5) × 103
Q.E.D
The voltage v e is related to ib by
v e = (β + 1)ib RE
1025 V/V or 60.2 dB
Ai =
=
io
v o /RL
=
ii
v i /Ri
v o Ri
5 k
= 1025 ×
v i RL
2 k
= 2562.5 A/A or 62.8 dB
That is,
v e = [(β + 1)RE ]ib
Dividing Eq. (3) by Eq. (2) yields
ve
(β + 1)RE
=
vb
(β + 1)RE + rπ
(3)
Chapter 1–21
amplifier circuit. In developing the model of
Fig. 1.16(a), we assumed that the amplifier is
unilateral (i.e., has no internal feedback, or that
the input side does not know what happens at the
output side). If we neglect this internal feedback,
that is, assume g12 = 0, we can compare the two
models and thus obtain:
Dividing the numerator and denominator by
(β + 1) gives
ve
RE
=
vb
RE + [rπ /(β + 1)]
Q.E.D
1.59
Ri = 1/g11
gm gmv1
v1
100 mA/V
R 5 k
Ro = g22
vo
R
Av o = g21
1.61 Circuits of Fig. 1.22:
io
R
v2
gmv2
Vi
Vo Vi
C
R
For (a) Vo = Vi
∴ vo = 0 V
v 1 = 1.01 V
v 2 = 0.99 V
∴ v o = 100 × 5 × 0.02 = 10 V
1.60
g22
I1
g12 I2
g21V1
V1 1/g11
I2
V2
Ro
I1
V1
I2
Ri
1/sC
1/sC + R
Vo
1
=
Vi
1 + sCR
v1 = v2 = 1 V
(b)
v o = io RL = gm R(v 1 − v 2 )
Vo
(a)
io = gm v 1 − gm v 2
C
AvoV1
V2
which is of the form shown for the low-pass
function in Table 1.2 with K = 1 and ω0 = 1/RC.
⎛
⎞
⎜
For (b) Vo = Vi ⎝
⎟
1 ⎠
R+
sC
R
Vo
sRC
=
Vi
1 + sCR
Vo
=
Vi
s
s+
1
RC
which is of the form shown in Table 1.2 for the
high-pass function, with K = 1 and ω0 = 1/RC.
1.62
The correspondences between the current and
voltage variables are indicated by comparing the
two equivalent-circuit models above. At the
outset we observe that at the input side of the
g-parameter model, we have the controlled
current source g12 I2 . This has no correspondence
in the equivalent-circuit model of Fig. 1.16(a). It
represents internal feedback, internal to the
Rs
Vs
Ri
Ci
Vi
Chapter 1–22
1
sCi
1
Ri +
Vi
sCi
⎛
=
1
Vs
⎜ Ri sCi
Rs + ⎜
⎝
1
Ri +
sCi
f0 =
Ri
Ri
1 + sCi Ri
⎞ =
Ri
R
+
s
⎟
1 + sCi Ri
⎟
⎠
ω0
1
=
2π
2π × 1 × 10−6 (10 + 40) × 103
= 3.18 Hz
1
K
40
|T (jω0 )| = √ =
√ = 0.57 V/V
10 + 40 2
2
1.64 Using the voltage divider rule,
Ri
=
Rs + sCi Ri Rs + Ri
Ri
Vi
=
=
Vs
(Rs + Ri ) + sC i Ri Rs
Ri
(Rs + Ri )
Ci Ri Rs
1+s
Rs + Ri
which is a low-pass STC function with
Ri
and ω0 = 1/[Ci (Ri Rs )].
K=
Rs + Ri
Vs
Vl
=
Vs
For Rs = 10 k, Ri = 40 k, and Ci = 5 pF,
ω0 =
f0 =
C
Rs
1
= 25 Mrad/s
5 × 10−12 × (40 10) × 103
25
= 4 MHz
2π
=
RL
Vl
RL
RL + Rs +
RL
RL + Rs
1
sC
s
s+
1
C(RL + Rs )
which is of the high-pass STC type (see Table
1.2) with
K=
1.63 Using the voltage-divider rule.
RL
RL + Rs
ω0 =
1
C(RL + Rs )
For f0 ≤ 100 Hz
R1
Vi
1
≤ 100
2πC(RL + Rs )
C
R2
Vo
⇒C≥
1
2π × 100(20 + 5) × 103
Thus, the smallest value of C that will do the job
is C = 0.064 μF or 64 nF.
T (s) =
Vo
=
Vi
T (s) =
R2
R2 + R1 +
R2
R1 + R2
1
sC
⎛
⎞
⎜
⎜
⎝
⎟
⎟
⎠
1
s+
C(R1 + R2 )
s
1.65 The given measured data indicate that this
amplifier has a low-pass STC frequency response
with a low-frequency gain of 40 dB, and a 3-dB
frequency of 104 Hz. From our knowledge of the
Bode plots for low-pass STC networks [Fig.
1.23(a)], we can complete the table entries and
sketch the amplifier frequency response.
which from Table 1.2 is of the high-pass type with
R2
K=
R1 + R2
1
ω0 =
C(R1 + R2 )
As a further verification that this is a high-pass
network and T(s) is a high-pass transfer function,
see that as s ⇒ 0, T (s) ⇒ 0; and as s → ∞,
T (s) = R2 /(R1 + R2 ). Also, from the circuit,
observe as s → ∞, (1/sC) → 0 and
Vo /Vi = R2 /(R1 + R2 ). Now, for R1 = 10 k,
R2 = 40 k and C = 1 μF,
f (Hz) |T |(dB) ∠T (◦ )
0
40
0
100
40
0
1000
40
0
104
37
−45◦
105
20
−90◦
106
0
−90◦
Chapter 1–23
This figure belongs to 1.65.
R
10 k C
T , dB
40
37
30
20 dB/decade
3 dB
20
V
R
100 k
R
1 k
V
R
100V
1 k
V
For f01 ≤ 100 Hz,
10
0
10
102
103
104
105
106 f (Hz)
1
≤ 100
2πC1 (10 + 100) × 103
⇒ C1 ≥
1.66 Since the overall transfer function is that of
three identical STC LP circuits in cascade (but
with no loading effects, since the buffer
amplifiers have infinite input and zero output
resistances) the overall gain will drop by 3 dB
below the value at dc at the frequency for which
the gain of each STC circuit is 1 dB down. This
frequency is found as follows: The transfer
function of each STC circuit is
T (s) =
1
1+
1
= 1.4 × 10−8 F
2π × 110 × 103 × 102
Thus we select C1 = 1 × 10−7 F = 0.1 μF. The
actual corner frequency resulting from C1 will be
f01 =
1
= 14.5 Hz
2π × 10−7 × 110 × 103
For the output circuit,
f02 =
1
2πC2 (Ro + RL )
For f02 ≤ 100 Hz,
s
ω0
where
1
≤ 100
2πC2 (1 + 1) × 103
ω0 = 1/CR
⇒ C2 ≥
Thus,
1
= 0.8 × 10−6
2π × 2 × 103 × 102
Select C2 = 1 × 10−6 = 1 μF.
1
|T (jω)| = 1+
ω
ω0
2
1
= −1
ω1 dB 2
1+
ω0
20 log ⇒1+
ω1 dB
ω0
This will place the corner frequency at
f02 =
1
= 80 Hz
2π × 10−6 × 2 × 103
T (s) = 100 s
1+
2πf01
s
1+
s
2πf02
2
= 100,1
ω1dB = 0.51ω0
ω1dB = 0.51/CR
1.67 For the input circuit, the corner frequency
f01 is found from
f01 =
C
1
2πC1 (Rs + Ri )
1.68 Since when C is connected to node A the
3-dB frequency is reduced by a large factor, the
value of C must be much larger than whatever
parasitic capacitance originally existed at node A
(i.e., between A and ground). Furthermore, it must
be that C is now the dominant determinant of the
amplifier 3-dB frequency (i.e., it is dominating
over whatever may be happening at node B or
anywhere else in the amplifier). Thus, we can
write
200 kHz =
1
2πC(Ro1 Ri2 )
Chapter 1–24
⇒ (Ro1 Ri2 ) =
1
2π × 200 × 103 × 1 × 10−9
= 0.8 k
A
#1
#2
B
#3
Av, dB
1 nF
C
The Bode plot for the overall transfer function
can be obtained by summing the dB values of the
two individual plots and then shifting the
resulting plot vertically by 60 dB (corresponding
to the factor 1000 in the numerator). The result is
as follows:
60
50
40
Ro1
20 dB/decade
20 dB/decade
30
20
vo1 C
10
Ri2
0
1
Now Ri2 = 100 k.
f = 10
Av ~
– 40
10 102 103 104 105 106 107 108
f (Hz)
102 103 104 105 106 107 108 (Hz)
60
60
60
57
60
40
20
0 (dB)
57
0.8 k
Thus Ro1
Similarly, for node B,
20 kHz =
1
2πC(Ro2 Ri3 )
⇒ Ro2 Ri3 =
1
2π × 20 × 103 × 1 × 10−9
= 7.96 k
The designer should connect a capacitor of value
Cp to node B where Cp can be found from
⇒ Cp =
1.70 Ti (s) =
Vi (s)
1/sC 1
1
=
=
Vs (s)
1/sC 1 + R1
sC1 R1 + 1
LP with a 3-dB frequency
Ro2 = 8.65 k
10 kHz =
Bandwidth = 105 − 102 = 99,900 Hz
f0i =
1
1
=
= 159 kHz
2πC1 R1
2π10−11 105
For To (s), the following equivalent circuit can be
used:
1
2πCp (Ro2 Ri3 )
C2
R2
1
2π × 10 × 103 × 7.96 × 103
GmR2Vi
= 2 nF
Vo
R3
Note that if she chooses to use node A, she would
need to connect a capacitor 10 times larger!
Vo
R3
= −Gm R2
Vi
R2 + R3 + 1/sC 2
1.69 The LP factor 1/(1 + jf /105 ) results in a
Bode plot like that in Fig. 1.23(a) with the
3-dB frequency f0 = 105 Hz. The high-pass factor
1/(1 + 102 /jf ) results in a Bode plot like that in
Fig. 1.24(a) with the 3-dB frequency
To (s) =
f0 = 102 Hz.
which is an HP, with
= −Gm (R2 R3 )
s
s+
1
C2 (R2 + R3 )
Chapter 1–25
3-dB frequency =
=
1
2πC 2 (R2 + R3 )
Ri ≥ Rs
f0 =
1
1+
× − 909.1 ×
s
2π × 159 × 103
s
s + (2π × 14.5)
20 dB/decade
159 kHz
Bandwidth = 159 kHz – 14.5 Hz
(1)
1
1
+
RL
R0
1
1
≥ 2πCL f3dB −
Ro
RL
Ro ≤
(a) To satisfy constraint (1), namely,
x Vs
Vi ≥ 1 −
100
1
2πf3dB CL −
(4)
1
RL
(c) To satisfy constraint (c), we first determine
the dc gain as
we substitute in Eq. (1) to obtain
x
Ri
≥1−
Rs + Ri
100
(2)
dc gain =
Ri
Gm (Ro RL )
Rs + Ri
For the dc gain to be greater than a specified
value A0 ,
Thus
1
R s + Ri
≤
x
Ri
1−
100
Ri
Gm (Ro RL ) ≥ A0
Rs + Ri
The first factor on the left-hand side is (from
constraint (2)) greater or equal to (1 − x/100).
Thus
x
1
Rs
100
≤
x −1=
x
Ri
1−
1−
100
100
A0
x (Ro RL )
1−
100
Gm ≥ which can be expressed as
(5)
Substituting Rs = 10 k and x = 10% in (3)
results in
100
Ri ≥ 10
− 1 = 90 k
100
x
1−
Ri
100
≥
x
Rs
100
resulting in
Substituting f3dB = 2 MHz, CL = 20 pF, and
RL = 10 k in Eq. (4) results in
Rs
V
s
1
1
+
≥ 2πCL f3dB
RL
Ro
159 kHz
Ri
1.71 Vi = Vs
Rs + Ri
1
2πCL
To obtain a value for f0 greater than a specified
value f3dB we select Ro so that
1
1
1
+
≥ f3dB
2πCL RL
Ro
59.2 dB
14.5 Hz
1
1
1
ω0 =
2π
2π CL (RL Ro )
Thus,
f0 =
20 dB/decade
(3)
(b) The 3-dB frequency is determined by the
parallel RC circuit at the output
1
= 14.5 Hz
2π100 × 10−9 × 110 × 103
∴ T (s) = Ti (s)To (s)
=
100
−1
x
Vi Ri
Ro
Gm Vi
RL
Vo
CL
Ro ≤
1
2π × 2 × 10 × 20 × 10−12 −
6
= 6.61 k
1
104
Chapter 1–26
Substituting A0 = 100, x = 10%, RL = 10 k, and
Ro = 6.61 k, Eq. (5) results in
100
= 27.9 mA/V
10
(10 6.61) × 103
1−
100
which, using Eq. (1), can be expressed in the
alternate form
1
R2
R1 + R2
Gm ≥ Vo
=
Vi
1.72 Using the voltage divider rule, we obtain
Thus when the attenuator is compensated
(C1 R1 = C2 R2 ), its transmission can be
determined either by its two resistors R1 , R2 or by
its two capacitors. C1 , C2 , and the transmission is
not a function of frequency.
Z2
Vo
=
Vi
Z1 + Z2
where
1
1
and Z2 = R2 Z1 = R1 sC1
sC2
It is obviously more convenient to work in terms
of admittances. Therefore we express Vo /Vi in the
alternate form
Vo
Y1
=
Vi
Y1 + Y2
1
+ sC1
Vo
R1
=
1
1
Vi
+
+ s(C1 + C2 )
R1
R2
1.73 The HP STC circuit whose response
determines the frequency response of the
amplifier in the low-frequency range has a phase
angle of 5.7◦ at f = 100 Hz. Using the equation
for ∠T (jω) from Table 1.2, we obtain
tan−1
f0
= 5.7◦ ⇒ f0 = 10 Hz
100
−tan−1
103
= −5.7◦ ⇒ f0
f0
1
20 log 1+
This transfer function will be independent of
frequency (s) if the second factor reduces to unity.
10
100
2
= −0.04 dB
Similarly, at the drop in gain f = 1 kHz is caused
by the LP STC network. The drop in gain is
This in turn will happen if
1
1
1
1
=
+
C1 R1
C1 + C2 R1
R2
1+
10 kHz
At f = 100 Hz, the drop in gain is due to the HP
STC network, and thus its value is
1
C1 R1
1
1
1
s+
+
(C1 + C2 ) R1
R2
s+
which can be simplified as follows:
C1 + C2
1
1
= R1
+
C1
R1
R2
=
The LP STC circuit whose response determines
the amplifier response at the high-frequency end
has a phase angle of −5.7◦ at f = 1 kHz. Using
the relationship for ∠T (jω) given in Table 1.2, we
obtain for the LP STC circuit.
and substitute Y1 = (1/R1 ) + sC1 and
Y2 = (1/R2 ) + sC2 to obtain
C1
=
C1 + C2
R1
1+
R2
1
20 log 1+
(1)
R1
C2
=1+
C1
R2
1000
10, 000
2
= −0.04 dB
The gain drops by 3 dB at the corner frequencies
of the two STC networks, that is, at f = 10 Hz and
f = 10 kHz.
or
1.74 Use the expression in Eq. (1.2), with
C1 R1 = C2 R2
B = 7.3 × 1015 cm−3 K −3/2 ;
When this condition applies, the attenuator is said
to be compensated, and its transfer function is
given by
k = 8.62 × 10−5 eV/K; and Eg = 1.12 V
Vo
C1
=
Vi
C1 + C2
we have
T = −55◦ C = 218 K:
Chapter 1–27
ni = 2.68 × 106 cm−3 ;
N
= 1.9 × 1016
ni
That is, one out of every 1.9 × 1016 silicon atoms
is ionized at this temperature.
T = 0◦ C = 273 K:
ni = 1.52 × 109 cm−3 ;
N
= 3.3 × 1013
ni
◦
T = 20 C = 293 K:
−5 ×398)
= 7.3 × 1015 × (398)3/2 e−1.12/(2×8.62×10
= 4.72 × 1012 /cm3
pn =
n2i
= 2.23 × 108 /cm3
ND
At 398 K, hole concentration is
pn = 2.23 × 108 /cm3
ni = 8.60 × 109 cm−3 ;
N
= 5.8 × 1012
ni
T = 75◦ C = 348 K:
N
= 1.4 × 1011
ni = 3.70 × 10 cm ;
ni
−3
11
At 398 K, ni = BT 3/2 e−Eg /2kT
T = 125◦ C = 398 K:
1.78 Hole concentration in intrinsic Si = ni
ni = BT 3/2 e−Eg /2kT
−5 ×300)
= 7.3 × 1015 (300)3/2 e−1.12/(2×8.62×10
= 1.5 × 1010 holes/cm3
ni = 4.72 × 1012 cm−3 ;
N
= 1.1 × 1010
ni
1.75 Use Eq. (1.2) to find ni ,
ni = BT 3/2 e−Eg /2kT
In phosphorus-doped Si, hole concentration drops
below the intrinsic level by a factor of 108 .
∴ Hole concentration in P-doped Si is
pn =
1.5 × 1010
= 1.5 × 102 cm−3
108
Substituting the values given in the problem,
3/2 −1.42/(2×8.62×10−5 ×300)
ni = 3.56 × 10 (300)
e
= 2.2 × 10 carriers/cm
3
14
6
1.76 Since NA
ni , we can write
pp ≈ NA = 5 × 1018 cm−3
Now, nn
ND and pn nn = n2i
nn = n2i /pn =
(1.5 × 1010 )
1.5 × 102
2
= 1.5 × 1018 cm−3
ND = nn = 1.5 × 1018 atoms/cm3
Using Eq. (1.3), we have
1.79 (a) The resistivity of silicon is given by
Eq. (1.41):
n2
np = i = 45 cm−3
pp
For intrinsic silicon,
1.77 T = 27◦ C = 273 + 27 = 300 K
At 300 K, ni = 1.5 × 1010 /cm3
p = n = ni = 1.5 × 1010 cm−3
Using μn = 1350 cm2 /V · s and
μp = 480 cm2 /V · s, and q = 1.6 × 10−19 C we
have
Phosphorus-doped Si:
nn
ND = 1017 /cm3
pn =
n2i
(1.5 × 1010 )
=
= 2.25 × 103 /cm3
ND
1017
ρ = 2.28 × 105 -cm.
2
Using R = ρ ·
L
with L = 0.001 cm and
A
Hole concentration = pn = 2.25 × 103 /cm3
A = 3 × 10−8 cm2 , we have
T = 125◦ C = 273 + 125 = 398 K
R = 7.6 × 109 .
Chapter 1–28
(b) nn ≈ ND = 5 × 1016 cm−3 ;
pn =
n2i
= 4.5 × 103 cm−3
nn
10 μm
Using μn = 1200 cm2 /V · s and
3 V
μp = 400 cm2 /V · s, we have
ρ = 0.10 -cm; R = 3.33 k.
νp-drift = μp E = 480 × 3000
−3
(c) nn ≈ ND = 5 × 10 cm ;
18
pn =
= 1.44 × 106 cm/s
n2i
= 45 cm−3
nn
νn-drift = μn E = 1350 × 3000
= 4.05 × 106 cm/s
Using μn = 1200 cm2 /V · s and
μp = 400 cm2 /V · s, we have
−3
ρ = 1.0 × 10
4.05 × 106
νn
=
= 2.8125
νp
1.44 × 106
-cm; R = 33.3 .
νn = 2.8125 νp
As expected, since ND is increased by 100, the
resistivity decreases by the same factor.
(d) pp ≈ NA = 5 × 1016 cm−3 ; np =
or
n2i
nn
Or, alternatively, it can be shown as
νn
μn E
1350
μn
=
=
=
νp
μp E
μp
480
= 2.8125
= 4.5 × 103 cm−3
ρ = 0.31 -cm; R = 10.42 k
(e) Since ρ is given to be 2.8 × 10−6 -cm, we
directly calculate R = 9.33 × 10−2 .
1.80 Cross-sectional area of Si bar
1.82
pn0 =
2
n2i
(1.5 × 1010 )
=
= 2.25 × 104 /cm3
ND
1016
From Fig. P1.82,
= 5 × 4 = 20 μm2
108 pn0 − pn0
dp
=−
dx
W
Since 1 μm = 10−4 cm, we get
since 1 nm = 10−7 cm
= 20 × 10−8 cm2
108 × 2.25 × 104
dp
=−
dx
50 × 10−7
Current I = Aq(pμp + nμn )E
= 20 × 10
−8
× 1.6 × 10
−19
1V
(10 × 500 + 10 × 1200) ×
10 × 10−4
16
1.81 Electric field:
E=
=
Hence
Jp = −qDp
dp
dx
= −1.6 × 10−19 × 12 × (−4.5 × 1017 )
= 0.864 A/cm2
3V
3V
=
10 μm
10 × 10−6 m
3V
10 × 10−4 cm
= 3000 V/cm
108 pn0
50 × 10−7
= −4.5 × 1017
4
= 160 μA
−
1.83 Use Eq. (1.45):
Dp
Dn
=
= VT
μn
μp
Dn = μn VT and Dp = μp VT where
VT = 25.9 mV.
Chapter 1–29
Doping
Concentration
μn
μp
Dn
Dp
(carriers/cm3 ) cm2 /V · s cm2 /V · s cm2 /s cm2 /s
Intrinsic
Depletion width
1350
480
35
12.4
16
1200
400
31
10.4
W =
17
750
260
19.4
6.7
18
380
160
9.8
4.1
10
10
10
2 s
q
W =
1
1
+
V0 ← Eq. (1.50)
NA
ND
2 × 1.04 × 10−12
1
1
+
× 0.754
1.6 × 10−19
1017
1016
1.84 Using Eq. (1.46) and NA = ND
= 0.328 × 10−4 cm = 0.328 μm
= 5 × 1016 cm−3 and ni = 1.5 × 1010 cm−3 ,
Use Eqs. (1.51) and (1.52) to find xn and xp :
we have V0 = 778 mV.
Using Eq. (1.50) and
−14
F/cm, we have
s = 11.7 × 8.854 × 10
−5
W = 2 × 10 cm = 0.2 μm. The extension of
the depletion width into the n and p regions is
given in Eqs. (1.51) and (1.52), respectively:
xn = W
NA
xn = W ·
= 0.1 μm
NA + ND
xp = W
xp = W ·
NA
1017
= 0.328 × 17
NA + ND
10 + 1016
= 0.298 μm
ND
1016
= 0.328 × 17
NA + ND
10 + 1016
= 0.03 μm
ND
= 0.1 μm
NA + ND
Since both regions are doped equally, the
depletion region is symmetric.
Use Eq. (1.53) to calculate charge stored on either
side:
Using Eq. (1.53) and
A = 20 μm2 = 20 × 10−8 cm2 , the charge
magnitude on each side of the junction is
QJ = Aq
QJ = 1.6 × 10−14 C.
= 100 μm2 = 100 × 10−8 cm2
VT at 300 K = 25.9 mV
Hence, QJ = 4.8 × 10−14 C
1.86 Equation (1.50):
= 0.754 V
2 s
q
W =
W
W , where junction area
× 0.328 × 10−4
Using Eq. (1.46), built-in voltage V0 is obtained:
NA ND
= 25.9 × 10−3 ×
V0 = VT ln
n2i
1017 × 1016
ln 2
1.5 × 1010
Holes
QJ = 100 × 10−8 × 1.6 × 10−19
1.85 From Table 1.3,
NA ND
NA + ND
xp
xn
Electrons
Since NA
1
1
+
NA
ND
W
V0 =
ND , we have
2 s 1
V0
q ND
qND 2
·W
2 s
V0 ,
1017 · 1016
1017 + 1016
Chapter 1–30
Here W = 0.2 μm = 0.2 × 10−4 cm
1.90 Equation (1.63):
So V0 =
2
1.6 × 10−19 × 1016 × 0.2 × 10−4
2 × 1.04 × 10
−12
= 0.31 V
NA ND
QJ = Aq
W ∼
= AqND W
NA + ND
ND , we have QJ = 3.2 fC.
since NA
1.87 V0 = VT ln
NA ND
n2i
I=
Aqn2i
Dp
Dn
+
Lp ND
Ln NA
Here Ip = Aqn2i
In = Aqn2i
eV /VT − 1
Dp V /VT
e
−1
Lp ND
Dn V /VT
−1
e
Ln NA
Dp Ln NA
Ip
=
· ·
In
Dn Lp ND
If NA or ND is increased by a factor of 10, then
new value of V0 will be
10 N A ND
V0 = VT ln
n2i
The change in the value of V0 is
VT ln10 = 59.6 mV.
=
10 10 1018
×
× 16
20
5
10
Ip
= 100
In
Now I = Ip + In = 100 I n + In ≡ 1 mA
In =
1.88 Using Eq. (1.46) with NA = 1017 cm−3 ,
ND = 1016 cm−3 , and ni = 1.5 × 1010 , we have
V0 = 754 mV
Using Eq. (1.55) with VR = 5 V, we have
W = 0.907 μm.
Using Eq. (1.56) with A = 1 × 10−6 cm2 , we
have QJ = 13.2 × 10−14 C.
1
mA = 0.0099 mA
101
Ip = 1 − In = 0.9901 mA
1.91 Equation (1.65):
IS = Aqn2i
Dp
Dn
+
Lp ND
Ln NA
A = 100 μm2 = 100 × 10−8 cm2
2
IS = 100 × 10−8 × 1.6 × 10−19 × 1.5 × 1010
1.89 Equation (1.55):
2 s 1
1
W =
+
(V0 + VR )
q NA
ND
=
2 s
q
1
1
+
NA
ND
V0 1 +
VR
V0
VR
1+
V0
5 × 10−4 × 1016
+
18
10 × 10−4 × 1017
= 7.85 × 10−17 A
I∼
= IS eV /VT
∼
= 0.3 mA
Equation (1.56):
NA N D
Qj = A 2 s q
NA + ND
10
= 7.85 × 10−17 × e750/25.9
= W0
= A 2 sq
NA N D
NA + ND
= QJ 0 1 +
· (V0 + VR )
VR
V0 · 1 +
V0
1.92 ni = BT 3/2 e−Eg /2kT
At 300 K,
3/2
ni = 7.3 × 1015 × (300)
×e−1.12/(2×8.62×10
= 1.4939 × 1010 /cm2
VR
V0
n2i (at 300 K) = 2.232 × 1020
)
−5 ×300
Chapter 1–31
Cj0 = 100 × 10−8
At 305 K,
= 2.152 × 1010
1.04 × 10−12 × 1.6 × 10−19
1017 × 1016
1
2
1017 + 1016 0.754
n2i (at 305 K) = 4.631 × 1020
= 31.6 fF
ni = 7.3 × 1015 × (305)
so
3/2
× e−1.12/(2×8.62×10
)
−5 ×305
n2i (at 305 K)
= 2.152
n2i (at 300 K)
Thus IS approximately doubles for every 5◦ C rise
in temperature.
1.93 Equation (1.63):
V /V
Dp
Dn
I = Aqn2i
+
e T −1
Lp ND
Ln NA
So Ip = Aqn2i
In = Aqn2i
I
Ip =
Cj0
VR m
1+
V0
Aqn2i
1+
Aqn2i
1
0.75
1/3
= 0.3 pF
ND , thus Ip
In and
Dp V /VT
e
−1
Lp ND
0.4 pF
For VR = 10 V, Cj = 1+
10
0.75
1/3
= 0.16 pF
For this case using Eq. (1.65):
IS
0.4 pF
For VR = 1 V, Cj = Dn V /VT
e
−1
Ln NA
For p −n junction NA
= 14.16 fF
1.95 Equation (1.73), Cj = Dp V /VT
−1
e
Lp ND
+
Cj0
31.6 fF
= Cj = VR
3
1+
1+
V0
0.754
Dp
= 104 × 10−8 × 1.6 × 10−19
Lp ND
2
× 1.5 × 1010
10
10 × 10−4 × 1017
1.96 Equation (1.67):
α = A 2 sq
= 3.6 × 10−16 A
I = IS eV /VT − 1 = 1.0 × 10−3
NA ND
NA + ND
Equation (1.69):
−3
3.6 × 10−16 eV /(25.9×10 ) − 1 = 1.0 × 10−3
α
Cj = √
2 V0 + VR
⇒ V = 0.742 V
Substitute for α from Eq. (1.67):
NA ND
√
A 2 sq
N + ND
s
×√
Cj =
√ A
2 V0 + VR
s
1.94 Equation (1.72):
q N N 1 s
A D
Cj0 = A
2
NA + ND
V0
NA ND
V0 = VT ln
n2i
2 s
q
10 × 10
= 25.9 × 10−3 × ln 2
1.5 × 1010
= 0.754 V
=A s×
17
16
=
sA 2 s
q
=
sA
W
1
NA + ND
NA ND
1
1
1
+
NA
ND
(V0 + VR )
(V0 + VR )
Chapter 1–32
(b) The current I = Ip + In .
1.97 Equation (1.75):
2
L2p
10 × 10−4
=
τp =
Dp
10
−4
(Note: 1 μm = 10
Find current component Ip :
pn (xn ) = pn0 eV /V T and pn0 =
cm.)
τp = 100 ns
Ip = AJp = AqDp
QP = τ p Ip (Eq. 1.76)
n2i
ND
dp
dx
dp
pn (xn ) − pn0
pn0 eV /V T − pn0
=
=
dx
Wn − xn
Wn − xn
V /V
e T −1
= pn0
Wn − xn
2 eV /V T − 1
ni
=
ND (Wn − xn )
= 100 × 10−9 × 0.1 × 10−3
= 10 × 10−12 C
τp
I
Cd =
VT
100 × 10−9
=
× 0.1 × 10−3
25.9 × 10−3
∴ Ip = AqDp
= 386 pF
= Aqn2i
1.98 Equation (1.81):
τT
I
Cd =
VT
τT
× 1 × 10−3
5 pF =
25.9 × 10−3
dp
dx
Dp
× eV /V T − 1
(Wn − xn )ND
Similarly,
Dn
× eV /V T − 1
Wp − xp NA
In = Aqn2i I = Ip + In
τ T = 5 × 10−12 × 25.9
Dp
Dn
=
+
(Wn − xn ) ND
Wp − xp NA
× eV /V T − 1
Aqn2i
= 129.5 ps
For I = 0.1 mA:
τT
×I
Cd =
VT
129.5 × 10−12
=
× 0.1 × 10−3 = 0.5 pF
25.9 × 10−3
The excess change, Qp , can be obtained by
multiplying the area of the shaded triangle of the
pn (x) distibution graph by Aq.
1.99
(a)
pn, np
n region
p region
pn(xn)
pn(x)
np (xp)
np (x)
pn0
np0
Wp
xp
0
xn
Depletion
region
Widths of p and n regions
Wn
Chapter 1–33
Qp = Aq ×
1
[pn (xn ) − pn0 ] (Wn − xn )
2
Thus, τT =
1 Wn2
, and
2 Dp
=
1 Aq pn0 eV /V T − pn0 (Wn − xn )
2
=
1
Aqpn0 eV /V T − 1 (Wn − xn )
2
dQ
dI
= τT
dV
dV
V /V
But I = IS e T − 1
=
ni 2
1
Aq
(Wn − xn ) eV /V T − 1
2
ND
IS eV /V T
dI
=
dV
VT
=
1 (Wn − xn )2
· Ip
2
Dp
I
so Cd ∼
.
= τT ·
VT
1 Wn2
· Ip for Wn
2 DP
(c) For Q
Q
1 Wn2
I
2 Dp
Qp , I
xn
Ip ,
Cd =
(d) Cd =
I
VT
1 Wn2 1 × 10−3
= 8 × 10−12 F
2 10 25.9 × 10−3
Solve for Wn :
Wn = 0.64 μm
Exercise 2–1
Ex: 2.1 The minimum number of terminals
required by a single op amp is 5: two input
terminals, one output terminal, one terminal for
positive power supply, and one terminal for
negative power supply.
The minimum number of terminals required by a
quad op amp is 14: each op amp requires two
input terminals and one output terminal
(accounting for 12 terminals for the four op
amps). In addition, the four op amps can all share
one terminal for positive power supply and one
terminal for negative power supply.
Therefore:
v 3 = μGm R(v 2 − v 1 )
That is, the open-loop gain of the op amp is
A = μGm R. For Gm = 10 mA/V and
μ = 100, we have:
A = 100 × 10 × 10 = 104 V/V, or equivalently,
80 dB.
Ex: 2.4 The gain and input resistance of the
inverting amplifier circuit shown in Fig. 2.5 are
R2
−
and R1 , respectively. Therefore, we have:
R1
Ex: 2.2 Relevant equations are:
v 3 = A(v 2 − v 1 ); v Id = v 2 − v 1 ,
1
v Icm = (v 1 + v 2 )
2
R1 = 100 k and
(a)
Thus:
2
v3
= 0 − 3 = −0.002 V = −2 mV
A
10
= v 2 − v 1 = 0 − (−0.002) = +0.002 V
v1 = v2 −
v Id
= 2 mV
1
v Icm = (−2 mV + 0) = −1 mV
2
−
R2
= −10 ⇒ R2 = 10 R1
R1
R2 = 10 × 100 k = 1 M
Ex: 2.5
R 10 k
(b) −10 = 103 (5 − v 1 ) ⇒ v 1 = 5.01 V
vi
v Id = v 2 − v 1 = 5 − 5.01 = −0.01 V = −10 mV
1
1
(v 1 + v 2 ) = (5.01 + 5) = 5.005 V
2
2
v Icm =
ii
vo
5V
(c)
v 3 = A(v 2 − v 1 ) = 103 (0.998 − 1.002) = −4 V
v Id = v 2 − v 1 = 0.998 − 1.002 = −4 mV
v Icm =
1
1
(v 1 + v 2 ) = (1.002 + 0.998) = 1 V
2
2
(d)
−3.6 = 10 [v 2 − (−3.6)] = 10 (v 2 + 3.6)
3
3
⇒ v 2 = −3.6036 V
v Id = v 2 − v 1 = −3.6036 − (−3.6)
= −0.0036 V = −3.6 mV
1
1
(v 1 + v 2 ) = [−3.6 + (−3.6036)]
2
2
−3.6 V
From Table 1.1 we have:
v o ; that is, output is open circuit
Rm =
i i
io = 0
The negative input terminal of the op amp (i.e.,
v i ) is a virtual ground, thus v i = 0:
v o = v i − Rii = 0 − Rii = −Rii
v o Rii
Rm =
=−
= −R ⇒ Rm = −R
ii io = 0
ii
= −10 k
vi
Ri =
and v i is a virtual ground (v i = 0),
ii
0
= 0 ⇒ Ri = 0 ii
v Icm =
thus Ri =
Ex: 2.3 From Fig. E2.3 we have: v 3 = μv d and
Since we are assuming that the op amp in this
transresistance amplifier is ideal, the op amp has
zero output resistance and therefore the output
resistance of this transresistance amplifier is also
zero. That is Ro = 0 .
v d = (Gm v 2 − Gm v 1 )R = Gm R(v 2 − v 1 )
Exercise 2–2
R 10 k
R1
10 k
0.5 mA
Rf
v1
vo
R2
vi
Ex: 2.7
v2
vO
Connecting the signal source shown in Fig. E2.5
to the input of this amplifier, we have:
v i is a virtual ground that is v i = 0, thus the
current flowing through the 10-k resistor
connected between v i and ground is zero.
Therefore,
v o = v i − R × 0.5 mA = 0 − 10 k × 0.5 mA
= −5 V.
Ex: 2.6
R1 1 k
v1
1V we want to have:
Rf
=1
and
R1
Rf
=5
R2
Therefore
10 V
10 V
⇒ Rf ≥ 10 k
≤ 1 mA ⇒ Rf ≥
Rf
1 mA
iO
iL
Since it is required that v O = −(v 1 + 5v 2 ),
It is also desired that for a maximum output
voltage of 10 V, the current in the feedback
resistor not exceed 1 mA.
i2 R2 10 k
i1
For the circuit shown above we have:
Rf
Rf
v1 +
v2
vO = −
R1
R2
vO
RL 1 k
Let us choose Rf to be 10 k, then
Rf
R1 = Rf = 10 k and R2 =
= 2 k
5
Ex: 2.8
v 1 is a virtual ground, thus v 1 = 0 V
ii =
1 V − v1
1−0
=
= 1 mA
R1
1 k
Assuming an ideal op amp, the current flowing
into the negative input terminal of the op amp is
zero. Therefore, i2 = i1 ⇒ i2 = 1 mA
v O = v 1 − i2 R2 = 0 − 1 mA × 10 k = −10 V
iL =
vo
−10 V
=
= −10 mA
RL
1 k
vO =
iO = iL − i2 = −10 mA − 1 mA = −11 mA
Voltage gain =
20 dB
Current gain =
20 dB
−10 V
vO
=
= −10 V/V or
1V
1V
−10 mA
iL
= −10 A/A or
=
i1
1 mA
Power gain
−10(−10 mA)
PL
= 100 W/W or 20 dB
=
Pi
1 V × 1 mA
PL Note that power gain in dB is 10 log10 .
Pi
=
Ra
Ra
Rc
Rc
v1 +
v2
R1
Rb
R2
Rb
Rc
−
v3
R3
We want to design the circuit such that
v O = 2v 1 + v 2 − 4v 3
Thus we need to have
Ra
R1
Rc
Rb
= 2,
Ra
R2
Rc
Rb
= 1, and
Rc
=4
R3
From the above three equations, we have to find
six unknown resistors; therefore, we can
arbitrarily choose three of these resistors. Let us
choose Ra = Rb = Rc = 10 k.
Exercise 2–3
Using the superposition principle to find the
contribution of v 1 to v O , we set v 2 = v 3 = 0.
Then we have (refer to the solution of Exercise
2.9): v O = 6v 1
Then we have
10
Rc
=
= 2.5 k
R3 =
4
4
Rc
10 10
Ra
×
= 2, ⇒
=2
R1
Rb
R1
10
To find the contribution of v 2 to v O , we set
v 1 = v 3 = 0, then: v O = 4v 2
⇒ R1 = 5 k
Rc
10 10
Ra
=1
×
=1⇒
R2
Rb
R2
10
To find the contribution of v 3 to v O we set
v 1 = v 2 = 0, then
9 k
v 3 = −9v 3
1 k
Combining the contributions of v 1 , v 2 , and
v 3 to v O we have: v O = 6v 1 + 4v 2 − 9v 3 .
vo = −
⇒ R2 = 10 k
Ex: 2.9 Using the superposition principle to find
the contribution of v 1 to the output voltage v O ,
we set v 2 = 0
Ex: 2.11
9 k
R2
i
1 k
R1
vO
vO
v1
2 k
vi
v2
3 k
v + (the voltage at the positive input of the op amp
3
v 1 = 0.6v 1
is: v + =
2+3
9 k
Thus v O = 1 +
v + = 10 × 0.6v 1 = 6v 1
1 k
To find the contribution of v 2 to the output
voltage v O we set v 1 = 0.
Then v + =
vO
R2
R2
=1+
=2⇒
= 1 ⇒ R1 = R2
vi
R1
R1
If v O = 10 V, then it is desired that i = 10 μA.
Thus,
i=
10 V
10 V
= 10 μA ⇒ R1 + R2 =
R1 + R2
10 μA
R1 + R2 = 1 M and
R1 = R2 ⇒ R1 = R2 = 0.5 M
2
v 2 = 0.4v 2
2+3
Ex: 2.12
Hence
9 k
vO = 1 +
v + = 10 × 0.4v 2 = 4v 2
1 k
(a)
R2
Combining the contributions of v 1 and v 2
R1
v
vI
to v O , we have v O = 6v 1 + 4v 2
vO
Ex: 2.10
9 k
v I − v − = v O /A ⇒ v − = v I − v O /A
1 k
2 k
v1
v3
But from the voltage divider across v O ,
vO
v− = vO
R1
R1 + R2
Equating Eq. (1) and Eq. (2) gives
v2
3 k
(1)
vO
R1
vO
= vI −
R1 + R2
A
(2)
Exercise 2–4
which can be manipulated to the form
1 + (R2 /R1 )
1 + (R2 /R1 )
1+
A
(b) For R1 = 1 k and R2 = 9 k the ideal value
9
for the closed-loop gain is 1 + , that is, 10. The
1
10
actual closed-loop gain is G =
.
1 + 10/A
vO
=
vI
If A = 103 , then G = 9.901 and
G − 10
× 100 = −0.99% −1%
10
For v I = 1 V, v O = G × v I = 9.901 V and
10 mA
iL
=
=∞
iI
0
v O × iL
10 × 10
PL
=∞
=
=
PI
v I × iI
1×0
Ex: 2.14
(a) Load voltage =
1 k
× 1 V 1 mV
1 k + 1 M
(b) Load voltage = 1 V
=
v O = A(v + − v − ) ⇒ v + − v − =
vO
10 V
=
= 10 V/V or 20 dB
vi
1V
Ex: 2.15
9.901
vO
=
A
1000
9.9 mV
If A = 104 , then G = 9.99 and = −0.1%.
For v I = 1 V, v O = G × v I = 9.99 V,
therefore,
v+ − v− =
9.99
vO
=
= 0.999 mV 1 mV
A
104
(a) R1 = R3 = 2 k, R2 = R4 = 200 k
If A = 105 , then G = 9.999 and = −0.01%
Since R4 /R3 = R2 /R1 we have:
For v I = 1 V, v O = G × v I = 9.999 thus,
Ad =
9.999
vO
=
= 0.09999 mV
v+ − v− =
A
105
0.1 mV
(b) Rid = 2R1 = 2 × 2 k = 4 k
Since we are assuming the op amp is ideal,
Ro = 0 Ex: 2.13
(c)
iI = 0 A, v 1 = v I = 1 V
Acm ≡
1V
v1
=
= 1 mA
1 k
1 k
i2 = i1 = 1 mA
i1 =
v1
vI 1 V iO
vO
1 k
9 k
i2
i1
vO
R2
200
= 100 V/V
=
=
vI2 − vI1
R1
2
iI
iL
1 k
vO
R4
=
v I cm
R3 + R4
1−
R2 R3
R1 R4
The worst-case common-mode gain (i.e., the
largest Acm ) occurs when the resistor tolerances
are such that the quantity in parentheses is
maximum. This in turn occurs when R2 and R3 are
at their highest possible values (each one percent
above nominal) and R1 and R4 are at their lowest
possible values (each one percent below
nominal), resulting in
Acm =
R4
R3 + R4
| Acm | 1−
1.01 × 1.01
0.99 × 0.99
The corresponding CMRR is
10 V
vO
=
= 10 mA
1 k
1 k
iO = iL + i2 = 11 mA
R4
200
×0.04 ×0.04 0.04 V/V
R3 + R4
202
v O = v 1 + i2 × 9 k = 1 + 1 × 9 = 10 V
iL =
CMRR =
or 68 dB.
| Ad |
100
=
= 2500
| Acm |
0.04
Exercise 2–5
Ex: 2.16 We choose R3 = R1 and R4 = R2 . Then
for the circuit to behave as a difference amplifier
with a gain of 10 and an input resistance of
20 k, we require
R2
= 10 and
R1
R
RId = 2R1 = 20 k ⇒ R1 = 10 k and
C
i
Ad =
Ex: 2.18
vi(t)
i
R2 = Ad R1 = 10 × 10 k = 100 k
vO (t) 1
CR
t
冮0vI (t)
Therefore, R1 = R3 = 10 k and
R2 = R4 = 100 k.
The signal waveforms will be as shown.
vI (t)
Ex: 2.17 Given v Icm = +5 V
10 V
v Id = 10 sin ωt mV
2R1 = 1 k, R2 = 0.5 M
2 ms
t
0
R3 = R4 = 10 k
1
1
v I 1 = v Icm − v Id = 5 − × 0.01 sin ωt
2
2
= 5 − 0.005 sin ωt V
10 V
1
v I 2 = v Icm + v Id
2
= 5 + 0.005 sin ωt V
10 V
vO (t)
t
v − (op amp A1 ) = v I 1 = 5 − 0.005 sin ωt V
v − (op amp A2 ) = v I 2 = 5 + 0.005 sin ωt V
v Id = v I 2 − v I 1 = 0.01 sin ωt
v Id
v O1 = v I 1 − R2 ×
2R1
= 5 − 0.005 sin ωt − 500 k ×
0.01 sin ωt
1 k
= (5 − 5.005 sin ωt) V
v Id
v O2 = v I 2 + R2 ×
2R1
When v I = +10 V, the current through the
capacitor will be in the direction indicated,
i = 10 V/R, and the output voltage will decrease
linearly from +10 V to −10 V. Thus in (T /2)
seconds, the capacitor voltage changes by 20 V.
The charge equilibrium equation can be
expressed as
i(T /2) = C × 20 V
= (5 + 5.005 sin ωt) V
v + (op amp A3 ) = v O2 ×
10 V
R4
10
= v O2
R3 + R4
10 + 10
1
1
v O2 = (5 + 5.005 sin ωt)
2
2
= (2.5 + 2.5025 sin ωt)V
10 T
10T
1
= 20C ⇒ CR =
= × 2 × 10−3
R 2
40
4
= 0.5 ms
=
Ex: 2.19
v − (op amp A3 ) = v + (op amp A3 )
= 10.01 sin ωt V
= 1(1 + 1000) × 0.01 sin ωt
R
Vi
= (2.5 + 2.5025 sin ωt) V
R4
R2
1+
v Id
vO =
R3
R1
0.5 M
10 k
1+
× 0.01 sin ωt
10 k
0.5 k
C
Vo
The input resistance of this inverting integrator is
R; therefore, R = 10 k.
Exercise 2–6
10−3 s
= 0.1 μF
10 k
From Eq. (2.27) the transfer function of this
integrator is:
C=
1
Vo ( jω)
=−
Vi ( jω)
jωCR
For ω = 10 rad/s, the integrator transfer function
has magnitude
Vo 1
=
V 1 × 10−3 = 100 V/V
i
◦
and phase φ = 90 .
For ω = 1 rad/s, the integrator transfer function
has magnitude
Vo 1
=
V 1 × 10−3 = 1000 V/V
i
and phase φ = 90◦ .
The frequency at which the integrator gain
magnitude is unity is
1
1
ωint =
= −3 = 1000 rad/s
CR
10
and phase φ = −90◦ .
If we add a resistor in series with the capacitor to
limit the high-frequency gain of the differentiator
to 100, the circuit would be:
R
C
R1
Vi
is 10−3 s, we have: CR = 10−3 s ⇒
For ω = 103 rad/s, the differentiator transfer
function has magnitude
Vo = 103 × 10−2 = 10 V/V
V i
Since the desired integration time constant
Vo
At high frequencies the capacitor C acts like a
short circuit. Therefore, the high-frequency gain
R
of this circuit is:
. To limit the magnitude of
R1
this high-frequency gain to 100, we should have:
1 M
R
R
=
= 10 k
= 100 ⇒ R1 =
R1
100
100
Ex: 2.20
Ex: 2.21
Refer to the model in Fig. 2.28 and observe that
R
v + − v − = VOS + v 2 − v 1 = VOS + v Id
Vi
C
Vo
and since v O = v 3 = A(v + − v − ), then
v O = A(v Id + VOS )
C = 0.01 μF is the input capacitance of this
differentiator. We want CR = 10−2 s (the time
constant of the differentiator); thus,
R=
10−2
= 1 M
0.01 μF
From Eq. (2.33), the transfer function of the
differentiator is
Vo (jω)
= −jωCR
Vi (jω)
Thus, for ω = 10 rad/s the differentiator transfer
function has magnitude
Vo = 10 × 10−2 = 0.1 V/V
V i
and phase φ = −90◦ .
(1)
where A = 104 V/V and VOS = 5 mV. From
Eq. (1) we see that v id = 0 results in v O = 50 V,
which is impossible; thus the op amp saturates
and v O = +10 V. This situation pertains for
v Id ≥ −4 mV. If v Id decreases below −4 mV, the
op-amp output decreases correspondingly. For
instance, v Id = −4.5 mV results in v O = +5 V;
v Id = −5 mV results in v O = 0 V; v Id = −5.5
mV results in v O = −5 V; and v Id = −6 mV
results in v O = −10 V, at which point the op amp
saturates at the negative level of −10 V. Further
decreases in v Id have no effect on the output
voltage. The result is the transfer characteristic
sketched in Fig. E2.21. Observe that the linear
range of the characteristic is now centered around
v Id = −5 mV rather than the ideal situation of
v Id = 0; this shift is obviously a result of the
input offset voltage VOS .
Exercise 2–7
VO = IOS R2 = 10 nA × 10 k = 0.01 V
Ex: 2.25 Using Eq. (2.41) we have:
2 mV
VOS
t ⇒ 12 = 2 mV +
t
CR
1 ms
12 V − 2 mV
× 1 ms 6 s
⇒t=
2 mV
v O = VOS +
RF
C
R
Vi
(b) If at room temperature (25◦ C), VOS is trimmed
to zero and (i) the circuit is operated at a constant
temperature, the peak of the input sine wave can
be increased to 10 mV. (ii) However, if the circuit
is to operate in the temperature range of 0◦ C to
75◦ C (i.e., at a temperature that deviates from
room temperature by a maximum of 50◦ C), the
input offset voltage will drift from by a maximum
of 10 μV/◦ C × 50◦ C = 500 μV or 0.5 mV. This
will reduce the allowed peak amplitude of the
input sinusoid to 9.5 mV.
With this value of R3 , the new value of the output
dc voltage [using Eq. (2.40)] is:
Ex: 2.23
VOS
(a) If the amplifier is capacitively coupled in the
manner of Fig. 2.31(a), then the input offset
voltage VOS will see a unity-gain amplifier [Fig.
2.31(b)] and the cc offset voltage at the output
will be equal to VOS , that is, 3 mV. Thus, almost
the entire output range of ±10 V will be available
for signal swing, allowing a sine-wave input of
approximately 10-mV peak without the risk of
output clipping. Obviously, in this case there is no
need for output trimming.
(b) We need to select a value of the coupling
capacitor C that will place the 3-dB frequency of
the resulting high-pass STC circuit at 100 Hz, thus
100 =
1
2πCR1
⇒C=
1
= 1.6 μF
2π × 100 × 1 × 103
Ex: 2.24 From Eq. (2.37) we have:
VO = IB1 R2 IB R2
= 100 nA × 1 M = 0.1 V
From Eq. (2.39) the value of resistor R3 (placed in
series with positive input to minimize the output
offset voltage) is
R3 = R1
Ex: 2.22 (a) The inverting amplifier of
−1000 V/V gain will exhibit an output dc offset
voltage of ±VOS (1 + R2 /R1 ) =
±3 mV × (1 + 1000) = ±3.03 V. Now, since the
op-amp saturation levels are ±10 V, the room left
for output signal swing is approximately ±7 V.
Thus to avoid op-amp saturation and the attendant
clipping of the peak of the output sinusoid, we
must limit the peak amplitude of the input sine
wave to approximately 7 V/1000 = 7 mV.
R2 =
R1 R2
10 k × 1 M
=
R1 + R2
10 k + 1 M
= 9.9 k
R3 = 9.9 k 10 k
Vo
With the feedback resistor RF , to have at least
±10 V of output signal swing available, we have
to make sure that the output voltage due to VOS
has a magnitude of at most 2 V. From Eq. (2.36),
we know that the output dc voltage due to VOS is
RF
RF
⇒ 2 V = 2 mV 1 +
VO = VOS 1 +
R
10 k
RF
= 1000 ⇒ RF 10 M
10 k
The corner frequency of the resulting STC
1
network is ω0 =
CRF
1+
We know RC = 1 ms and
R = 10 k ⇒ C = 0.1 μF
Thus ω0 =
f0 =
1
= 1 rad/s
0.1 μF × 10 M
1
ω0
=
= 0.16 Hz
2π
2π
Ex: 2.26
20 log A0 = 106 dB ⇒ A0 = 200,000 V/V
ft = 3 MHz
fb = ft /A0 =
3 MHz
= 15 Hz
200,000
Exercise 2–8
At fb , the open-loop gain drops by 3 dB below its
value at dc; thus it becomes 103 dB.
For f
fb , | A| ft /f ; thus
At f = 300 Hz, | A| =
3 MHz
= 104 V/V
300 Hz
or 80 dB
At f = 3 kHz, | A| =
3 MHz
= 103 V/V
3 kHz
or 60 dB
At f = 12 kHz, which is two octaves higher than
3 kHz, the gain will be 2 × 6 = 12 dB below its
value at 3 kHz; that is, 60 − 12 = 48 dB.
At f = 60 kHz, | A| =
3 MHz
= 50 V/V
60 kHz
or 34 dB
Since the nominal dc gain is much lower than A0 ,
f3dB ft
=
1+
R2
R1
2 MHz
= 20 kHz
100
Ex: 2.29 For the input voltage step of magnitude
V the output waveform will still be given by the
exponential waveform of Eq. (2.58) if
ωt V ≤ SR
SR
SR
⇒V ≤
resulting in
that is, V ≤
ωt
2πft
V ≤ 0.16 V
Ex: 2.27
From Appendix F we know that the 10% to 90%
rise time of the output waveform of the form of
2.2
.
Eq. (2.58) is tr 2.2 × time constant =
ωt
A0 = 106 V/V or 120 dB
Thus, tr 0.35 μs
The gain falls off at the rate of 20 dB/decade.
Thus, it reaches 40 dB at a frequency four
decades higher than fb ,
If an input step of amplitude 1.6 V (10 times as
large compared to the previous case) is applied,
the output will be slew-rate limited and thus
linearly rising with a slope equal to the slew rate,
as shown in the following figure.
104 fb = 10 kHz ⇒ fb = 1 Hz
The unity-gain frequency ft will be two decades
higher than 10 kHz, that is,
vo
ft = 100 × 10 kHz = 1 MHz
Alternatively, we could have found ft from
Slope SR
1.6 V
ft = A0 fb = 106 × 1 Hz = 1 MHz
At a frequency f
0
fb ,
tr
| A| = ft /f
tr =
For f = 1 kHz, | A| =
1 MHz
= 103 V/V or 60 dB
1 kHz
Ex: 2.28
20 log A0 = 106 dB ⇒ A0 = 200,000 V/V
ft = 2 MHz
For a noninverting amplifier with a nominal dc
gain of 100,
R2
1+
= 100
R1
0.9 × 1.6 − 0.1 × 1.6
1 V/μs
⇒ tr = 1.28 μs
Ex: 2.30 From Eq. (2.59) we have:
fM =
SR
= 15.915 kHz 15.9 kHz
2πVO max
Using Eq. (2.60), for an input sinusoid with
frequency f = 5 fM , the maximum possible
amplitude that can be accommodated at the
output without incurring SR distortion is:
fM
1
VO = VO max
= 10 × = 2 V (peak)
5fM
5
t
Chapter 2–1
2.1 The minimum number of pins required by
dual op amp is 8. Each op amp has 2 input
terminals (4 pins) and one output terminal (2
pins). Another 2 pins are required for power
supplies.
Similarly, the minimum number of pins required
by quad op amp is 14:
4 × 2 + 4 × 1 + 2 = 14
Gain A =
= 1 × 106 × 40 × 10−3
= 40,000 V/V
v1
Gmv1
i
2.2 Refer to Fig. P2.2.
v+ = vI ×
vO
= Rm Gm
v2 − v1
Rmi
vO
1 k
1
= vI
1 k + 1 M
1001
v2
1
v O = Av + = Av I
1001
vO
A = 1001
vI
Gmv2
4
1
A = 4004 V/V
= 1001 ×
2.5 Refer to Fig. E2.3.
v d = R(Gm2 v 2 − Gm1 v 1 )
v O = v 3 = μv d = μR (Gm2 v 2 − Gm1 v 1 )
2.3
vO =
vd = v2 − v1
vO
v O /v d
1 0.00 0.00
0.00
0.00
–
2 1.00 1.00
0.00
0.00
–
3
1.00
(b)
1.00
4 1.00 1.10
0.10
10.1
101
5 2.01 2.00
–0.01
–0.99
99
6 1.99 2.00
0.01
1.00
100
7 5.10
(d)
–5.10
#
v1
(a)
v2
(c)
we have v O = Ad v Id + Acm v Icm
Experiments 4, 5, and 6 show that the gain is
approximately 100 V/V.
The missing entry for experiment #3 can be
predicted as follows:
1.00
vO
=
= 0.01 V.
A
100
(b) v 1 = v 2 − v d = 1.00 − 0.01 = 0.99 V
(a) v d =
The missing entries for experiment #7:
−5.10
= −0.051 V
(c) v d =
100
(d) v 2 = v 1 + v d = 5.10 − 0.051 = 5.049 V
All the results seem to be reasonable.
2.4 i = Gm (v 2 − v 1 )
v O = Rm i
= Rm Gm (v 2 − v 1 )
1
1
μR(Gm v 2 + Gm v 2 − Gm v 1 + Gm v 1 )
2
2
1
v O = μRGm (v 2 − v 1 ) + μRGm (v 1 + v 2 )
2
v Id
2v Icm
⇒ Ad = μRGm , Acm = μRGm
Ad = 20 log Gm
CMRR = 20 log Acm Gm
For a CMRR ≥ 60 dB,
Gm
Gm
≥ 1000 ⇒
≤ 0.1%
Gm
Gm
1
(v 1 + v 2 )
2
v d = 0.005 sin(2π1000)t = v 1 − v 2
2.6 v cm = 2 sin(2π60)t =
v 1 = v cm − v d /2
= sin(120π)t − 0.0025 sin(2000πt)
v 2 = v cm + v d /2
= sin(120πt) + 0.0025 sin(2000πt)
2.7
Circuit
a
b
c
d
v o /v i (V/V)
−100
= −5
20
–5
–5
–5
Rin (k)
20
20
20
20
Chapter 2–2
10 k
10 k
vI
10 k
vO
= −0.5 V/V
vI
2.8
vO
Note that in circuit (b) the 20-k load resistance
has no effect on the closed-loop gain because of
the zero output resistance of the ideal op amp. In
circuit (c), no current flows in the 20-k resistor
connected between the negative input terminal
and ground (because of the virtual ground at the
inverting input terminal). In circuit (d), zero
current flows in the 20-k resistor connected in
series with the positive input terminal.
Rin = 10 k (smallest
gain magnitude)
R2 10 k
10 k
R1 10 k
vO
vO
vI vI
10 k 10 k
vO
= −0.5 V/V
vI
Closed-loop gain is
R2
10 k
vO
=−
=−
vI
R1
10 k
10 k
= −1 V/V
For v I = +1.00 V,
Rin = 20 k (smallest
gain magnitude)
10 k
10 k
vI
v O = −1 × 1.00
vO
= − 1.00 V
The two resistors are 1% resistors
vO = 10(1 − 0.01) = 0.98 V/V
v 10(1 + 0.01)
I min
vO = 10(1 + 0.01) = 1.02 V/V
v 10(1 − 0.01)
I max
vO
= −2 V/V
vI
Thus the measured output voltage will range from
−0.98 V to −1.02 V.
2.10
2.9 There are four possibilities:
10 k
10 k
vI
10 k
gain magnitude)
(a) G = −1 V/V
(b) G = −10 V/V
(c) G = −0.1 V/V (d) G = −100 V/V
(e) G = −10 V/V
2.11 (a) G = −1 V/V
=
vO
Rin = 10 k (largest gain
magnitude)
−R2
⇒ R1 = R2 = 10 k
R1
(b) G = −2 V/V
=
vO
= −2 V/V
vI
Rin = 5 k (largest
−R2
⇒ R1 = 10 k, R2 = 20 k
R1
(c) G = −5 V/V
=
−R2
⇒ R1 = 10 k, R2 = 50 k
R1
Chapter 2–3
46 dB = 20 log |G|
(d) G = −100 V/V
=
−R2
⇒ R1 = 10 k, R2 = 1 M
R1
|G| = 200
∴
R2
vO
= −200 V/V = −
vI
R1
⇒ R2 = 200R1 ≤ 1 M
2.12
For the largest possible input resistance, choose
R2
R2 = 1 M
1 M
= 5 k
200
Rin = R1 = 5 k
R1 =
R1
vI
vO
2.15 The circled numbers indicate the order of
the analysis steps. The additional current supplied
by the op amp comes from the power supplies
(not shown).
R2
vO
= −10 V/V = −
vI
R1
3 1 mA 10 k
⇒ R2 = 10R1
1 k
Total resistance used is 110 k
1 V
∴ R1 + R2 = 110 k
1 mA
2
6 6 mA
0V
1
10 V 4
5 mA
5
2 k
R1 + 10R1 = 110 k
R1 = 10 k and R2 = 10R1 = 100 k
2.13
2.16 The circuit will be as follows:
R
+10 V
R
15 V
15 k
Average = +5 V
Highest = +10 V
Lowest = 0 V
Variation of the −15-V supply by ±1% results in
a ±1% variation in the output voltage. Thus the
total variation in the output voltage can be ±3%,
resulting in VO in the range 4.85 V to 5.15 V.
R2
R1
V 5 V
If R1 and R2 have ±1% tolerance, then VO will
exhibit ±2% variability and thus will be in the
range of 5 × 1.02 = 5.1 V to 5 × 0.98 = 4.9 V.
2.14 Gain is 46 dB
vI
5 k
0V
vO
2.17 R1 = R1nominal (1 ± x%)
R2 = R2nominal (1 ± x%)
|G| =
R2
R2nominal 1 ± x%
=
R1
R1nominal 1 ± x%
Chapter 2–4
2.20
Thus,
|G|max R2nominal
× (1 + 2x%)
R1nominal
|G|min R2nominal
× (1 − 2x%)
R1nominal
ii
ii
vi
Thus, the tolerance of the closed-loop gain is
±2x%.
For Gnominal = −100 and x = 1, the closed-loop
gain will be in the range −98 V/V to −102 V/V.
Rf
vo
A
(a) For A = ∞: v i = 0
v o = −ii Rf
2.18 (a) Choose R1 = 1 k and R2 = 200 k.
(b) G = −
R2 /R1
1 + R2 /R1
1+
A
200
= −192.3 V/V
=−
1 + 200
1+
5000
To restore the gain to −200 V/V, we need to
change the effective value of R1 to R1 ,
−200 = −
200/R1
1 + 200/R1
1+
5000
Rm =
vo
= −Rf
ii
Rin =
vi
=0
ii
(b) For A finite: v i = −
vo
, v o = v i − ii Rf
A
Rf
−v o
vo
=−
− ii Rf ⇒ Rm =
1
A
ii
1+
A
Rf
vi
=
Ri =
ii
1+A
⇒ vo =
2.21
Thus,
200
200
200
1
+
=
200
+
R1
5000
R1
0.96 ×
200
= 200.04
R1
⇒ R1 = 0.960 k
This effective value can be realized by shunting
R1 (1 k) with Ra ,
1
1
1
= +
⇒ Ra = 24 k
0.960
1 Ra
(c) From Appendix J, we find the closest
available 1% resistor as either 23.7 k or
24.3 k.
v O = −Av − = v − − ii R2
ii R2 = v − (1 + A)
v− =
ii R2
1+A
Again v I = ii R1 + v −
= ii R1 + ii
2.19 Output voltage ranges from –10 V to +10 V
and open-loop gain is 5000 V/V
∴ Voltage at the inverting input terminal will
−10
10
vary from
to
(i.e., –2 mV to +2 mV).
5000
5000
Thus the virtual ground will depart by a
maximum of ±2 mV.
So Rin =
R2
1+A
vI
R2
= R1 +
ii
A+1
2.22 Closed-loop gain
G=
vO
=
vI
−(R2 /R1 )
1 + R2 /R1
1+
A
Q.E.D.
Chapter 2–5
Gain error =
1 + (R2 /R1 )
× 100
A
1
1
1
=
+
R1
R1
Rc
0.1%
1%
10%
R2
R2
R2
A 1000 1 +
100 1 +
10 1 +
R1
R1
R1
Substituting in Eq. (1),
R1
Rc
R2
R2
1+
+
R1
Rc
1+
A
1+
R2
Vo
=−
Vi
R1
Gain with resistance R1a
R2
R1
vI
R2
Vo
= − , we have to make
Vi
R1
To make
R1a
R1
=
Rc
1+
vO
That is,
A
R2
R2
+
R1
Rc
A
R1
R1
=1+G+G
Rc
Rc
which yields
R2
R1 R1a
R1 + R1a
|G| R2
1+
R1
1+
A
A−G
Rc
=
R1
1+G
2.24 (a) |G| =
where we have neglected the small effect of R1a
on the denominator.
R2
R2 R1 + R1a
R1
1+
R1
R1a
R1
R1a
=
|G| =
R2
R2
1+
1+
R1
R1
1+
1+
A
A
R2
, use
To restore the gain to its nominal value of
R1
R1
=
R1a
So R1a
R1a
1+
A
R2
R1
=
100
10%
1000R1 100R1 10R1
2.23 Refer to Fig. P2.23.
Vo
=
Vi
−R2 /R1
1 + R2 /R1
1+
A
where
R1 = R1 Rc
Thus,
|G| −
|G| =
(1)
R2 /R1
1 + R2 /R1
1+
A− A
Dividing Eq. (2) by Eq. (1), we have
1 + R2 /R1
1+
|G|
A
=
1−
1 + R2 /R1
|G|
1+
A− A
1
1
−
|G|
A− A A
=
1 + R2 /R1
|G|
1+
A− A
⎞
⎛
1
1 ⎜
R2
⎟
− 1⎠
1+
⎝
A
R1
A
1−
A
=
R2 /R1
1+
A− A
1+
1%
R2 /R1
1 + R2 /R1
1+
A
(1)
If A is reduced by A, |G| will be
correspondingly reduced by |G|,
Thus
100R1
=
0.1%
Q.E.D
For
A
A
|G|
|G|
R2
R1
1 and 1 +
1+
A
R2
R1
A
A
R2
R1
A,
(2)
Chapter 2–6
Thus,
|G| / |G|
1 + R2 /R1
A/ |A|
A
(b)
Q.E.D
|G|
A
R2
≤ 0.001
= 100,
= 0.1,
|G|
R1
A
A ≥ (1 + 100) × 0.1/0.001
2.26 From Example 2.2,
vO
R2
R4
R4
=−
1+
+
vI
R1
R2
R3
Here R1 = R2 = R4 = 1 M
1
1M
v
∴ O =− 1+1+
=− 2+
vI
R3
R3
That is, Amin 104 V/V.
vO
1 M
+2=−
vI
R3
2.25 (a) Equation (2.5):
R3 = − G=
vO
=
vI
−R2 /R1
R2
1+ 1+
A
R1
and Gnominal = −
R2
R1
Gain error
G − Gnominal G
=
−
1
= Gnominal Gnominal
− 1 + R2 /R1 1
A
− 1 = = (1
+
R
/R
)
1
+
R
/R
2
1
2
1
1 +
1 +
A
A
=
1
1+
1
=1+
R2
R1
R2
R1
Solving for A, we get
R2
1
A= 1+
−1
R1
1
= (1 − Gnominal )
−1
(b) Gnominal = −100 = −
R3 = −
(c)
1 M
= 125 k
(−10 + 2)
vO
1 M
= −2 V/V, R3 = −
=∞
vI
(−2 + 2)
(a) Rin = R1 = 200 vO
−R2
R4
R4
(b)
=
+
1+
= −500
vI
R1
R2
R3
A
1+
vO
= −100 V/V
vI
1 M
R3 = −
= 10.2 k
(−100 + 2)
vO
(b)
= −10 V/V
vI
(a)
2.27
R2 /R1 = 500, R2 = 100 k ⇒ R1 = 200 A
1+
1 M
vO
+2
vI
R2
R1
Rin = 1 k = R1
If R2 = R1 = R4 = 100 k ⇒ R3 =
200 Rin = R1 = 100 k
2.28 iI =
So
vI
vI
, v x = −iI R2 = − R2
R1
R1
vx
R2
=−
vI
R1
R1 = 1 k
R2
R2 = 100R1 = 100 k
Again Gnominal = −100 and max = 10%
1
∴ A = (1 − Gnominal )
−1
1
= [1 − (−100)]
−1
0.1
= 101 × 9
A = 909 V/V
100 k
500 − 2
R4
vx
R2
iI
iI
vI
R1
0V
vO
Chapter 2–7
Now, because of the virtual ground at the negative
input terminal of the op amp, v O appears across
the series combination of R4 and (R2 R3 ); thus
vx = vO
= vO
(R2 R3 )
(R2 R3 ) + R4
R2 R3
R2 R3 + R2 R4 + R3 R4
vO
R2 R3 + R2 R4 + R3 R4
=
vx
R2 R3
R4
R4
= 1+
+
R3
R2
vO
vO vx
=
vI
vx vI
R2
R4
R4
=−
+
1+
R1
R3
R2
See Fig. 2. We utilize the results of (a) above as
follows: At node 1 we have a resistance R to
ground and, looking left, a resistance R. These
two resistances must carry equal currents
⇒ I1 = I . A node equation at node 1 results in the
current through (R/2) as 2I . At node 2, we have a
resistance R to ground and an equal resistance
looking to the left. These two resistances must
carry equal currents ⇒ I2 = 2I .
A node equation at 2 results in the current leaving
node 2 as 4I . We continue in the same fashion to
find I3 = 4I and the current from 3 to 4 as 8I .
(c) V1 = −I1 R = −IR
V2 = −I2 R = −2IR
Q.E.D.
V3 = −I3 R = −4IR
2.29 (a) R1 = R
V4 = V3 −
R
R R
R2 = (R R) + = + = R
2
2
2
R
R
R3 = (R2 R) + = (R R) + = R
2
2
R
R
R4 = (R3 R) + = (R R) + = R
2
2
R
× 8I = −8IR
2
2.30 (a) I1 =
1V
= 0.1 mA
10 k
I2 = I1 = 0.1 mA
See Fig. 1.
−I 2 × 10 k = −I3 × 100 ≡ Vx
R
R/2 2
1
R/2 3
R/2 4
∴ I3 = I2 ×
10 k
100 = 0.1 × 100
I
R
I1
R
I2
R
I3
I4
= 10 mA
Now IL = I2 + I3 = 10.1 mA
and Vx = −I2 × 10 k = −0.1 × 10 k = −1 V
(b) Vx = RL IL + VO = 10.1 RL + VO
RL =
Figure 1
(b)
Vx − VO
−1 − (−13)
=
= 1.19 k
10.1 mA
10.1
(c) 100 ≤ RL ≤ 1 k
I
R
I
1
R
2
R
I1 I
0V
2I R/2
4I R/2
R
I2 2I
3
8I R/2
4
IL stays fixed at 10.1 mA.
VO = Vx − RL IL = −1 − RL × 10.1
I3 4I
RL = 100 , VO = −2.01 V; RL = 1 k,
VO = −11.1 V
Figure 2
∴ −11.1 V ≤ VO ≤ −2.01 V
Chapter 2–8
2.32
2.31
1.5 V
iI 10 k
I1
R1
Vx
IL
I2
I
i
RL
R
R2
which is independent of the value of RL . Now, for
our specific design:
IL = 3.1 mA
I = 0.1 mA
1.5V
= 15 k
0.1 mA
R1
3.1 = 0.1 1 +
R2
R=
R1
⇒
= 30
R2
Choosing R2 = 500 ⇒ R1 = 15 k. The
circuit will work properly as long as the op amp
does not saturate (i.e., as long as VO ≤ −10 V).
But
VO = Vx − IL RL
= −IR1 − IL RL
= −0.1 × 15 − 3.1RL
R
R1
R1
IL = I + I
= 1+
I
R2
R2
RL
iI
The circuit shown in Fig. P2.30 (redrawn above)
provides a constant current through RL that is
independent of the value of RL . The current
through RL is determined by the input current and
the ratio of the two resistors R1 and R2 .
Specifically, I1 = I , Vx = −I1 R1 , I2 = −Vx /R2 =
I1 (R1 /R2 ) = I (R1 /R2 ), thus
iL
vx
vO
(a) v x = −iI × 10
i = −v x /R = iI (10/R)
10
iL = iI + i = iI 1 +
R
Thus,
10
iL
=1+
iI
R
For
iL
= 11 ⇒ R = 1 k.
iI
(b) Rin = 0 (because of the virtual ground at
the input). Ro = ∞ (because iL is independent
of the value of RL ).
(c) If iI is in the direction shown in the figure
above, the maximum allowable value of iI will be
determined by v O reaching −12 V, at which point
v x = −iI max × 10
and
v O = −12 = v x − iLmax × 1 = −10 iI max − 11 iI max
⇒ iI max =
12
= 0.57 mA
21
If iI is in a direction opposite to that shown in the
figure, then
v x = 10iI
v O = v x + iL RL = 10iI + 11iI = 21iI
The maximum value of iI will result in
v O = +12 V. Thus
12 = 21iI max ⇒ iI max =
12
= 0.57 mA
21
The maximum allowed value for RL can now be
found by substituting VO = −10 V, thus
Thus, the allowable range of iI is
RL = 2.74 k
−0.57 mA ≤ iI ≤ +0.57 mA
Chapter 2–9
(d) Since Rin = 0, the value of the source
resistance will have no effect on the resulting iL ,
2.34
Rf
iL = 0.2 × 11 = 2.2 mA
i1
R1
v1
R2
2.33
v2
xR4
vO
To obtain an input resistance of 100 k, we select
R1 = 100 k. From Example 2.2 we have
R2
vO
=−
vI
R1
(1 − x)R4
(1 − x)R4
+
1+
R2
R3 + xR4
∴ R1 , R2 ≥ 20 k
Rf
Here
= 2, if R1 = 20 k, Rf = 40 k
R1
Rf
1
= ⇒ R2 = 2Rf = 80 k
R2
2
The minimum gain magnitude is obtained when
x = 1,
2.35
R2
vO
=−
= −1
vI
R1
v1
Thus, R2 = 100 k.
The maximum gain magnitude is obtained when
x = 0,
R2
vO
=−
vI
R1
⇒1+
R4
R4
1+
+
= −100
R2
R3
100 100
= 100
+
100
R3
⇒ R3 =
100
= 1.02 k
98
When the potentiometer is set exactly in the
middle, x = 0.5 and
R2
vO
=−
vI
R1
=−
100
100
0.5R4
0.5R4
+
1+
R2
R3 + 0.5R4
0.5 × 100
0.5 × 100
1+
+
100
1.02 + 0.5 × 100
= −2.48 V/V
10 k
Rf 50 k
10 k
v1
10 k
v2
vO
Rf
Rf
Rf
v1 + v1 + v2
R1
R2
R3
50
50
50
=−
v1 + v1 + v2
10
10
10
= −(10v 1 + 5v 2 )
vO = −
Now v 1 = 1 V and v 2 = −1 V
v O = −(10 × 1 − 5) = −5 V
2.36
v1
Rf
R1
R2
v2
For v 1 and v 2 , we assume
R1
The output of the weighted summer circuit is
Rf
Rf
vO = −
v1 + v2
R1
R2
v2 v O = − 2v 1 +
2
v1
v2
i1 =
and i2 =
R1
R2
Since i1 , i2 ≤ 50 μA for 1-V input signals
(1x) R4
vI
vO
i2
R3
R2
vO
Chapter 2–10
(b) v O = −(v 1 + v 2 + 2v 3 + 2v 4 )
v 2 = 1.5 V
100 k
v
The output signal required is
100 k
100 k
100 k
v 1 = 3 sin ωt
v
v
100 k
vO
v
v O = −3 sin ωt − 3
100 k
v
t
0
3
Rf
R1
Rf
R2
Rf
R3
Rf
R4
100 k
= 1 ⇒ R1 = 100 k
= 1 ⇒ R2 = 100 k
100
k
2
100
k
= 2 ⇒ R4 =
2
= 2 ⇒ R3 =
Ri1 = 100 k, Ri2 = 100 k,
Ri3 = 50 k, Ri4 = 50 k
For the summer circuit, we should have
(c) v O = −(v 1 + 5v 2 )
Rf
Rf
= 1 and
=2
R1
R2
100 k
Select Rf = 2R2 = 20 k.
Thus R2 = 10 k,
and R1 = 20 k.
v
100 k
v
2.37 (a) v O = −(v 1 + 2v 2 + 3v 3 )
100 k
Rf
= 2 ⇒ R2 = 50 k
R2
R1 = 100 k
100 k
5
Ri1 = 100 k
R2 =
Rf
100
k
= 1 ⇒ R3 =
R3
3
Ri2 = 20 k
100 k
v
v
(d) v O = −6v 1
R 100 k
R1 =
100 k
100 k
v
100 k
Rf
= 1 ⇒ R1 = 100 k,
R1
100 k
100 k
100 k
100 k
100 k
6
v
100 k
100 k
100 k
v
100 k
100 k
v1
100 k
Ri2 = 50 k
100 k
Ri3 = 33.3 k
100 k
Ri1 = 100 k
100 k
vO
Chapter 2–11
Ri1 =
100
= 1.67 k
6
To obtain v O = v 1 + 2v 2 − 3v 3 − 5v 4 , we can
arbitrarily select Rc = Rb , then
Suggested configurations:
Ra
=1
R1
v O = −(2v 1 + 2v 2 + 2v 3 )
100 k
Ra
=2
R2
If we select R2 = 10 k, then Ra = 20 k and
R1 = 20 k.
100 k
v1
and
100 k
For the second summer, to obtain
100 k
v2
100 k
vO
then
Rc
=3
R3
and
100 k
v3
vO
= −3
v3
vO
= −5
v4
100 k
requires
Rc
=5
R4
We can select Rc = Rb = 60 k, resulting in
R3 = 20 k and R4 = 12 k.
v O = −(3v 1 + 3v 2 )
100 k
100 k
2.39
100 k
100 k
v1
vO
100 k
v2
100 k
100 k
In order to have coefficient = 0.5, connect one of
vO
the input resistors to v O .
= 0.5.
v1
Here the first inverting amplifier simply inverts
v 1 , resulting at its output in
100 k
v1
100 k
−v 1 = −2 sin(2π × 60t) − 0.01 sin(2π × 1000t)
100 k
100 k
100 k
vO
The second amplifier provides the sum of −v 1
and v 2 , that is, (v 2 − v 1 ) multiplied by a gain of
100. Thus
100 k
v O = −100(v 2 − v 1 )
100 k
= 1 sin(2π × 1000t), V
2.38 Using the circuit of Fig. 2.11:
The value of R can be selected (arbitrarily but
conveniently) as R = 10 k.
2.40 This is a weighted summer circuit:
Rf
Rf
Rf
Rf
vO = −
vO + v1 + v2 + v3
R0
R1
R2
R3
We may write:
v 0 = 5V × a0 , v 2 = 5V × a2 ,
v 1 = 5V × a1 , v 3 = 5V × a3 ,
Chapter 2–12
5
5
5
5
a0 +
a1 +
a2 +
a3
80
40
20
10
2.42
R3 10 k
a
a1
a2
a3 0
v O = −Rf
+
+
+
16
8
4
2
R2 10 k
Rf 0
vO = −
2 a0 + 21 a1 + 22 a2 + 23 a3
16
R1 10 k
v O = −Rf
vI
vO
For −12 V ≤ v O ≤ 0,
Rf 0
2 × 1 + 2 × 1 + 2 2 × 1 + 23 × 1
16
=
Short-circuit R2 :
vO
=2
vI
Short-circuit R3 :
vO
=1
vI
15Rf
= 12
16
⇒ Rf = 12.8 k
R2
2.41
10 k
R3
R2
10 k
10 k
vI (a)
vO
R2
=1=1+
vI
R1
Set R2 = 0 and eliminate R1
vO
R2
(b)
=2=1+
vI
R1
R2
= 1; set R1 = R2 = 10 k
R1
(c)
vO
R2
= 21 = 1 +
vI
R1
R2
= 20; set R1 = 10 k, R2 = 200 k
R1
(d)
vO
2.43 V− = V+ = V ; thus the current in the
V
moving-coil meter will be I = , independent of
R
the resistance of the meter. To obtain I = 100 μA
when V = 10 V, we select
10
= 100 k
R=
0.1 mA
The meter resistance does not affect the voltmeter
calibration.
2.44 Refer to the circuit in Fig. P2.44:
(a) Using superposition, we first set
v P1 = v P2 , . . . , = 0. The output voltage that
results in response to v N 1 , v N 2 , . . . , v Nn is
Rf
Rf
Rf
v ON = −
vN1 +
vN2 + · · · +
v Nn
RN 1
RN 2
RNn
Then we set v N 1 = v N 2 = · · · = 0, then:
RN = RN 1 RN 2 RN 3 · · · RNn
The circuit simplifies to that shown below.
v OP = 1 +
vO
R2
= 100 = 1 +
vI
R1
R2
= 99; set R1 = 10 k, R2 = 990 k
R1
vO
R2
vO
=1+
vI
R1
R1 v
I
R1
+v P2
Rf
RN
⎛
⎜
×⎜
⎝v P1
1/RP1
1
1
1
+
+ ··· +
RP0
RP1
RPn
⎞
⎟
1/RP2
1/RPn
⎟
· · · + v Pn
1
1 ⎠
1
1
+ ··· +
+ ··· +
RP0
RPn
RP0
RPn
Chapter 2–13
Rf
2.45
Rf
RN
vI3
vOP
vP1
Rp1
RN
RP1
vI1
Rp2
vO
RP2
vP2
vI2
RP4
vPn
Rpn
vI4
RP0
RP0
RF
RP
v OP = 1 +
v P1
RN
RP1
RP
RP
+ v P2
+ ··· +
v Pn
RP2
RPn
Adapting the expression given in Problem 2.44 to
the circuit above yields
Rf
Rf
RP
vO = −
vI3 + 1 +
vI1
RN
RN
RP1
RP
RP
+
vI2 +
vI4
RP2
RP4
where
RP = RP0 RP1 · · · RPn
when all inputs are present:
where RP = RP0 RP1 RP2 RP3 .
v O = v ON + v OP
Rf
Rf
=−
vN1 +
vN2 + · · · +
RN 1
RN 2
Rf
RP
RP
vN1 +
vN2 + · · ·
1+
RN
RP1
RP2
We require
v O = −9v I 3 + v I 1 + 2v I 2 + 4v I 4
Equating the coefficients of v I 3 , we have
Rf
=9
RN
(b) v O = −4v N 1 + v P1 + 3v P2
Rf
= 4, RN 1 = 10 k ⇒ Rf = 40 k
RN 1
Rf
RP
RP
=1
=1⇒5
1+
RN
RP1
RP1
Rf
RP
RP
=3
=3⇒5
1+
RP2
RP2
RN
Selecting RN = 10 k ⇒ Rf = 90 k.
(1)
(2)
Thus,
1
1
1
1 1
,
=
+
+
in
Substituting for
RP RP
RP0
RP1
RP2
Eqs. (1) and (2) and selecting (arbitrarily)
RP0 = 10 k results in RP1 = 10 k and
RP2 = 3.33 k. The result is the following circuit:
40 k
vN
vp
10 k
3.33 k
vp
10 k
10
RP
RP
=1⇒
= 0.1
RP1
RP1
(1)
Similarly, equating the coefficients of v I 2 gives
10
RP
RP
=2⇒
= 0.2
RP2
RP2
(2)
and equating the coefficients of v I 4 gives
10 k
Equating the coefficients of v I 1 provides
Rf
RP
=1
1+
RN RP1
10
v
RP
RP
=4⇒
= 0.4
RP4
RP4
(3)
Now, summing Eqs. (1), (2), and (3) provides
1
1
1
+
+
= 0.7
(4)
RP
RP1
RP2
RP4
But,
1
1
1
1
1
=
+
+
+
RP
RP0
RP1
RP2
RP4
Chapter 2–14
1
R2
1−x
vO
=1+ −1
=1+
=1+
vI
R1
x
x
Thus,
1
1
1
1
1
−
=
+
+
RP
RP0
RP1
RP2
RP4
(5)
Equations (4) and (5) can be combined to obtain
∴
1
vO
=
vI
x
0≤x≤1⇒∞≥
RP
RP
= 0.7 ⇒ RP0 =
1−
RP0
0.3
(6)
vO
≥1
vI
Add a resistor as shown:
vO
(1 − x) × 10 k
=1+
vI
x × 10 k + R
vO
= 11
For
v I max
Selecting
RP0 = 10 k
Equation (6) ⇒ RP = 3 k
Equation (1) ⇒ RP1 = 30 k
Equation (2) ⇒ RP2 = 15 k
Equation (3) ⇒ RP4 = 7.5 k
x = 0,
10 =
R4
R3 + R4
R2
vO
R4
1 + R2 /R1
= 1+
=
vI
R1
R3 + R4
1 + R3 /R4
2.46 v + = v I
vO
10 k
= 11 = 1 +
vI
R
10 k
R
R = 1 k
2.49
10 k
v O1 = −10v 1
Setting v 1 = 0, we obtain the output component
due to v 2 as
10R
10R
v O2 = v 2 1 +
= 10v 2
R
10R + R
The total output voltage is
For v 1 = 10 sin(2π × 60t) − 0.1 sin(2π × 1000 t)
vO
10 k
vO = vI
v O = v O1 + v O2 = 10(v 2 − v 1 )
1 k
vI
1 k
2.47 Refer to Fig. P2.47. Setting v 2 = 0, we
obtain the output component due to v 1 as
10
10
1+
1 + 10
1
v O = 10v I
Rin = 11 k
v 2 = 10 sin(2π × 60t) + 0.1 sin(2π × 1000 t)
2.50
v O = 2 sin(2π × 1000t)
1 M
2.48
10 V 1 k v
x1 1x
vI
vO
(a) Source is connected directly.
v O = 10 ×
R
vI
vO
iL =
1
10 mV
1001
vO
10 mV
=
= 10 μA
1 k
1 k
Current supplied by the source is 10 μA.
Chapter 2–15
for a noninverting amplifier:
1 M
10 V Rin = ∞
1 k
Case
Gain (V/V)
Rin
R1
R2
a
–10
10 k
10 k
100 k
b
–1
100 k
100 k 100 k
c
–2
100 k
100 k 200 k
d
+1
∞
∞
0
e
+2
∞
100 k
100 k
f
+11
∞
10 k
100 k
g
–0.5
20 k
20 k
10 k
(b) Inserting a buffer.
v O = 10 V
10 V
= 10 mA
iL =
1 k
Current supplied by the source is 0.
The load current iL comes from the power supply
of the op amp.
G =1+
R2
R1
vO
2.53 For a non inverting amplifier [Eq. (2.11)]:
G0
G0
1+
A
G=
2.51
=
G0 − G
× 100
G0
for an inverting amplifier (Eq. 2.5):
vO/A
vO
=
vI
G0
1 − G0
1+
A
Case
G 0 (V/V)
a
b
c
d
e
f
g
–1
1
–1
10
–10
–10
+1
vO
A
vI vO = vI −
G=
vO
A
1
1
A
Error of gain magnitude
vO
−
1
v
1
I
=−
1
A+1
=
|G0 | − |G|
× 100
|G0 |
A (V/V) G (V/V) (%)
10
10
100
10
100
1000
2
–0.83
0.91
–0.98
5
–9
–9.89
0.67
17
9
2
50
10
1.1
33
1+
2.54
G=
A (V/V)
1000
100
10
vO
(V/V)
vO
0.999
0.990
0.909
Gain error –0.1%
–1%
–9.1%
2.52 For an inverting amplifier
Rin = R1 ,
R2
G=−
R1
G0
G0 /A × 100
G0 − G
× 100 =
,
≤x
G0
G0
G0
1+
1+
A
A
G0
A ≥ 100 ⇒ A ≥ 100 − 1
G0
x
G0
x
A
F
1+
or
⇒ A ≥ G0 F, where F =
x
F
0.01
4
10
0.1
3
10
1
10
2
10
10
100
100
−1
x
x
Chapter 2–16
Thus for:
10 102
x = 0.01: G0 (V/V) 1
A (V/V) 104 105 106
103 104
7
8
10
10
too high to
be practical
x = 0.1: G0 (V/V) 1
10 102 103 104
A (V/V) 103 104 105 106 107
x = 1: G0 (V/V) 1
10 10 10 10
A (V/V) 102 103 104 105 106
2
3
4
x = 10: G0 (V/V) 1 10 102 103 104
A (V/V) 10 102 103 104 105
2.55 Refer to Fig. P2.55. When potentiometer is
set to the bottom:
30 × 25
= −10 V
v O = v + = −15 +
25 + 100 + 25
and to the top:
30 × 25
= +10 V
v O = −15 +
25 + 100 + 25
⇒ −10 V ≤ v O ≤ + 10 V
2 × 10
=1V
20
1−
R3
R2
×
R1
R4
R4
R3
1 − 0.99 ×
R3
R4
Acm = 0.0095
Neglecting the effect of resistance variation on Ad ,
R2
100
= 20 V V
=
R1
5
Ad CMRR = 20 log Acm 20 = 20 log 0.0095 Ad =
= 66.4 dB
2.57 If we assume R3 = R1 , R4 = R2 , then
Eq. (2.20): Rid = 2R1 ⇒ R1 =
(b) Ad =
20
= 10 k
2
R2
= 1 V/V ⇒ R2 = 10 k
R1
(c) Ad =
R2
= 100 V/V ⇒ R2 = 1 M = R4
R1
R1 = R3 = 10 k
R2
v id
R1
vO
R2
Ad =
=
= 20 V/V
v id
R1
(d) Ad =
R2
= 0.5 V/V ⇒ R2 = 5 k = R4
R1
R1 = R3 = 10 k
From Eq. (2.20)
2.58 Refer to Fig. P2.58:
Rid = 2R1 = 2 × 5 k = 10 k
Considering that v − = v + :
R2
vO − v1
v2
=
⇒ vO = v2 − v1
2
2
v1
=R
v 1 only: Ri =
I
v1 +
R1
vO
R4
R
I
v1
R
R3
R2
= 5 V/V ⇒ R2 = 50 k = R4
R1
R1 = R3 = 10 k
vO =
vO
The two resistance ratios
∴
R1 = R2 = R3 = R4 = 10 k
From Eq. (2.16),
vI2
100
×
100 + 5
(a) Ad =
2.56 R1 = R3 = 5 k, R2 = R4 = 100 k
R4
R2
Equation (2.15):
=
= 20
R3
R1
vI1
R4
R4 + R3
(Refer to Fig. 2.16.)
Pot has 20 turns, and for each turn:
v O =
Acm =
R2
R4
and
differ by 1%.
R1
R3
R4
R2
= 0.99
R1
R3
Now for this case, Acm can be found from
Eq. (2.19)
R
v 2 only: Ri =
0V
v2
= 2R
I
R
Chapter 2–17
R
Since
R
vO
R2
R4
=
:
R1
R3
Rs
Rs
+1=
+ 1 ⇒ R1 = R3 ⇒ R2 = R4
R1
R3
2.60
I
v2
R
R2
R
i1
v between 2 terminals:
v
Ri = = 2R
I
R1
vO
vicm
R
Ricm i2
R
0V
v
R3
R4
vO
I
R
R
When R2 /R1 = R4 /R3 , the output voltage v O will
be zero. Thus,
v icm
i1 =
R1 + R2
and
v I connected to both input terminals
vI
vI
vI
+
=
I=
2R 2R
R
Ri = R
i2 =
v icm
R3 + R4
Thus,
ii = v icm
R
1
1
+
R1 + R2
R3 + R4
and
vI/2R R
vI/2
I
vI
vI
2
Ricm = (R1 + R2 ) (R3 + R4 )
vO
vI/2R R
2.61 From Eq. (2.19),
vO
R4
R2 R3
=
1−
Acm ≡
v Icm
R4 + R3
R1 R4
R
The second factor in this expression is the one
that in effect determines Acm . Now, for the circuit
under consideration, all resistors are nominally
equal to 10 k, but each has a tolerance of ±x%.
Thus the second factor will have a maximum
magnitude when R2 and R3 are at their lowest
value and R1 and R4 are at their highest values,
that is,
2.59 For an ideal difference amp, we need:
Rs + R1
Rs + R3
=
R2
R4
Rs /R3 + 1
Rs /R1 + 1
=
R2 /R1
R4 /R3
R2 = R3 = 10(1 − 0.01x)
R1 = R4 = 10(1 + 0.01x)
R2
v1
Rs
R1
vO
v2
Rs
Q.E.D.
Substituting in the expression for Acm , we have
(1 − 0.01x)2
10(1 + 0.01x)
1−
Acm =
20
(1 + 0.01x)2
Now, for 0.01x
R3
1,
Acm = 0.5(1 + 0.01x) × 0.04x
R4
Acm 0.02x V/V
Chapter 2–18
To obtain CMRR = 80 dB,
Ad = 1
Ad 50
=
CMRR = Acm x
50
or 20 log
dB
x
x(%)
0.1
Acm (V/V)
1
5
0.002 0.02 0.1
CMRR (dB)
54
34
20
2.62 From Eq. (2.19),
R4
R2 R3
Acm =
1−
R4 + R3
R1 R4
The second factor in this expression in effect
determines Acm . The largest, |Acm |, will occur
when R2 and R3 are at their lowest (or highest)
values and R1 and R4 are at their highest (or
lowest) values,
as thiswill provide the maximum
R2 R3
deviation of
from unity. Thus,
R1 R4
R2 = R2nominal (1 − )
R1 = R1nominal (1 + )
R4 = R4nominal (1 + )
where
R4nominal
R2nominal
=
=K
R1nominal
R3nominal
Substituting in the expression for Acm ,
R4nominal (1 + )
×
R4nominal (1 + ) + R3nominal (1 − )
(1 − )2
1−
(1 + )2
Acm =
Acm
2.63 See solution to Problem 2.62 above.
Specifically, if the resistors have a tolerance of
x%, then
K +1
CMRR = 20 log
4(x/100)
where K is the nominal differential gain. Here we
are required to obtain
K = 1000
Rin = 2 k
Thus, R1 = R3 = 1 k and R2 = R4 = 1 M.
To obtain a CMRR of 88 dB, we write
1001
88 = 20 log
4(x/100)
1001 × 100
= 25, 118.86
4x
⇒ x 1%
R3 = R3nominal (1 − )
For 101
= 104
4
101
=
0.25 × 10−2
4 × 104
That is, the resistor tolerance should be a
maximum of 0.25%.
1,
2.64 (a) Refer to Fig. P2.64 and Eq. (2.19):
R4
R2 R3
1−
Acm =
R3 + R4
R1 R4
100.100
100
1−
=
100 + 100
100.100
Acm = 0
Refer to 2.17:
⇒ Ad =
R4
R2
=
R1
R3
R2
=1
R1
(b) v A = v B
K
× 4
K +1
100 k
Since
Ad = K
Ad
CMRR = A
cm
vcm
= K +1
4
which in dB becomes
K +1
CMRR = 20 log
4
vcm
100 k
100 k
A B
100 k
Q.E.D.
For Ad = 100 V/V and = 0.01,
101
CMRR = 20 log
= 68 dB
0.04
v A = v cm
100
100 + 100
vO
Chapter 2–19
v cm
v cm
and v B =
2
2
⇒ −5 V ≤ v cm ≤ 5 V
the range of v Icm will be
vA =
−3 V ≤ v Icm ≤ +3 V
(c) The circuit becomes as shown below:
2.65 Refer to Fig. P2.65. Using superposition:
100 kΩ
vI1
v O = v O1 + v O2
100 kΩ
10 kΩ
vI2
Calculate v O1 : v + =
A
vO
100 kΩ
10 kΩ
βv O1
= v−
2
βv O1
βυ O1
− vO
v1
2 = 2
⇒ v O1 =
R
R
β −1
B
v1 −
100 kΩ
Calculate v O2 :
v O2
v O2
v O2
= v+ ⇒ v2 −
=
− βv O2
2
2
2
v2
⇒ v O2 =
1−β
v− =
Applying Thévenin’s theorem to v I 1 together with
the associated (100-k, 10-k) voltage divider,
and similarly to v I 2 and the associated
(100-k, 10-k) voltage divider, we obtain the
following circuit:
100 k
(1011) v
(1011) v
I2
(100 // 10) k
=
vO
v1
v2
+
β −1 1−β
1
(v 2 − v 1 )
1−β
Ad =
(100 // 10) k
I1
v O = v O1 + v O2 =
vO
1
=
v2 − v1
1−β
Ad = 10 V/V ⇒ β = 0.9 =
Q.E.D
R6
R5 + R6
RId = 2R = 2 M ⇒ R = 1 M
R5 + R6 ≤
100 k
R
⇒ R5 + R6 ≤ 10 k
100
Selecting R6 = 6.8 k
vO =
100 k
(100 10) k
10
10
vI2 − vI1
11
11
= 10(v I 2 − v I 1 )
6.8
= 0.9 ⇒ R5 = 756 6.8 + R5
For v I 1 = v I 2 = v Icm , v O = 0, thus
2.66 See partial analysis on circuit diagram on
next page.
Acm = 0
From input loop:
For v I 2 − v I 1 = v Id ,
v Id = 2i1 R1
v O = 10 v Id
From the loop containing R2 , +, −, R2 :
Thus, Ad = 10.
To obtain the input common-mode range, we note
that for v I 1 = v I 2 = v Icm ,
v+ = v− =
10
100
v Icm ×
11
100 + (100 10)
= 0.833v Icm
For v + and v − in the range
−2.5 V ≤ v + , v − ≤ +2.5 V
v G = i1 R2 + 0 + i1 R2 = 2i1 R2
Thus, we can find the current through RG as
v G /RG = 2i1 (R2 /RG ). Finally, from the loop
containing v O , R2 , RG , and R2 :
R2
v O = −2i1 1 + 2
R2 − 2i1 R2
RG
R2
= −4i1 R2 1 +
RG
(1)
Chapter 2–20
This figure belongs to Problem 2.66.
i1
i1 2i1
i1
R1 0
R2
vId
vG
0
RG
2i1
i1
R2
R
RG 2
2i1 R2
R1
2i1
R2
RG
R2
RG
vO
R2
R2
i1
i1 2i1
Substituting for 2i1 from Eq. (1), we obtain the
gain as
R2
R2
vO
1+
Q.E.D.
= −2
v Id
R1
RG
R2
RG
The circuit on the left ideally has infinite input
resistance
(iii)
vO
= +2 V/V
vi
R2
= 1.
R1
Connect C and O together, and D to ground.
25 k
2.67 (a) Refer to Eq. (2.17): Ad =
vI
(iv)
25 k
25 k
25 k
C
O
vI
vO
25 k
B
25 k
25 k
B
D
2.68 Refer to the figure on next page:
v B = v A = 3 + 0.05 sin ωt, V
Two possibilities:
v C = v D = 3 − 0.05 sin ωt, V
25 k
A
25 k
vO
D
i = (v B − v C )/2R1
A
Current through R2 , 2R1 , and R2 is
C
C
25 k
vi
O
vO
25 k
D
B
C
O
D
vO
(ii)
= +1 V/V
vi
vO
25 k
A
25 k
B
D
25 k
vI
25 k
B
O
vO
1
= + V/V
vi
2
vO
= −1 V/V
vi
A
vI
25 k
C
A
(b) (i)
= 0.05 sin ωt, mA
v E = v B + iR2 = 3 + 2.55 sin ωt, V
v F = v C − iR2 = 3 − 2.55 sin ωt, V
vO
Chapter 2–21
This figure belongs to Problem 2.68.
1
v F = 1.5 − 1.275 sin ωt, V
2
v O = (v F − v E ) × 1 = −5.1 sin ωt, V
vG = vH =
R2
R2
1
= 1+
1+
v Icm +
v Id
R1
2
R1
R2
v Od = v O2 − v O1 = 1 +
v Id
R1
1
R2
(v O1 + v O2 ) = 1 +
v Icm
2
R1
2.69 (a) Refer to Fig. 2.20(a).
R2
= 101. If
The gain of the first stage is 1 +
R1
the op amps of the first stage saturate at ±12 V
then −12 V ≤ 101v Icm ≤ +12 V
v Ocm =
⇒ −0.12 V ≤ v Icm ≤ 0.12 V
Acm1 = 1 +
As explained in the text, the disadvantage of
circuit in Fig.2.20(a) isthat v Icm is amplified by a
R2
gain equal to 1 +
in the first stage and
R1
therefore a very small v Icm range is acceptable to
avoid saturation.
Ad 1
CMRR = 20 log A
(b) In Fig. 2.20(b), when v Icm is applied, v − for
both A1 and A2 is the same and therefore no
current flows through 2R1 . This means the voltage
at the output of A1 and A2 is the same as v Icm .
⇒ −12 V ≤ v Icm ≤ 12 V
This circuit allows for a much larger range of v Icm .
Ad 1 = 1 +
R2
R1
R2
R1
cm1
= 0 dB
(b) Refer to the circuit in Fig. 2.20(b):
1
v I 1 = v Icm − v Id
2
1
v I 2 = v Icm + v Id
2
1
v − (A1 ) = v I 1 = v Icm − v Id
2
1
v − (A2 ) = v I 2 = v Icm + v Id
2
2.70 (a) Refer to the circuit in Fig. 2.20(a).
1
v I 1 = v Icm − v Id
2
1
v I 2 = v Icm + v Id
2
R2
v O1 = 1 +
vI1
R1
R2
R2
1
1+
= 1+
v Icm −
v Id
R1
2
R1
R2
v O2 = 1 +
vI2
R1
Current through R1 in the upward direction is
i=
v − (A2 ) − v − (A1 )
v Id
=
2R1
2R1
v O1 = v − (A1 ) − iR2 = v Icm −
1
R2
v Id
1+
2
R1
v O2 = v − (A2 ) + iR2 = v Icm +
R2
1
1+
v Id
2
R1
R2
v Od = v O2 − v O1 = 1 +
v Id
R1
Chapter 2–22
v Ocm =
1
(v O1 + v O2 ) = v Icm
2
Ad 1 = 1 +
If 2R1 is reduced to 1 k, Ad increases to
201 V/V while Acm remains unchanged at
0.02 V/V. Thus, CMRR increases to about 80 dB.
We conclude that increasing the gain of the first
stage increases CMRR.
R2
R1
Acm1 = 1
= 20 log 1 + R2
R1
cm1
Ad 1
CMRR = 20 log A
2.72 (a)
Comment: In circuit (a), the first stage amplifies
the differential signal and the common-mode
signal equally. On the other hand, in circuit (b),
the
first stage
amplifies the differential signal by
R2
1+
and the common-mode signal by
R1
unity, thus providing a substantial CMRR. Circuit
(a) is useless as a differential amplifier!
2.71 Ideally,
R4
R2
Ad =
1+
R3
R1
(1)
Acm = 0
CMRR = ∞
For R2 = R3 = R4 = 100 k, and 2R1 = 10 k.
100
= 21 V/V
Ad = 1 1 +
5
Acm = 0
CMRR = ∞
If all resistors have ±1% tolerance, the
differential gain will be slightly affected; Eq. (1)
indicates that in the worst case Ad can deviate by
approximately ±4% of the nominal value. The
common-mode gain, however, undergoes
dramatic change because of the significant effect
of resistor tolerances on the operation of the
difference amplifier in the second stage. Equation
(2.19) can be employed to evaluate the worst-case
common-mode gain. For our
case,
Acm2 = 0.5[1 − (1 ± 0.04] = ± 0.02
The common-mode gain of the first stage will
remain approximately unity. Thus the ±1%
resistor tolerances will mainly affect the
common-mode gain of the instrumentation
amplifier, increasing it in the worst case to
|Acm | = 0.02
Correspondingly, the CMRR will be reduced to
CMRR = 20 log
20 log
21
0.02
| Ad |
| Acm |
= 60.4 dB
as opposed to the ideal infinite value!
vB
20
=1+
= 3 V/V
vA
10
30
vC
= −3 V/V
=−
vA
10
(b) v O = v B − v C = 6v A ⇒
vO
= 6 V/V
vA
Chapter 2–23
(c) v B and v C can be ±14 V, or 28 V P-P.
−28 V ≤ v O ≤ 28 V, or 56 V P-P
(d) The phase relation between input and output
remains unchanged.
28
v Orms = √ = 19.8 V
2
2.75 |T | =
2.73 See analysis on the circuit diagrams below:
Also,
Note that circuit (a) has the advantage of infinite
input resistance. However, it has the limitation
that the load impedance must be floating. This
constraint is removed in circuit (b), but the input
resistance is finite (2R1 ).
RC =
2.74
1
Vo (s)
=−
Vi (s)
sCR
1
Vo (jω)
=−
Vi (jω)
jωCR
Vo = 1
∠φ = +90◦
V ωCR
i
For C = 1 nF and R = 10 k,
CR = 1 × 10−9 × 10 × 104 = 10−4 s
1
= 104 rad/s.
(a) |Vo /Vi | = 1 at ω =
CR
104
= 1.59 kHz.
Correspondingly, f =
2π
(b) At f = 1.59 kHz, the output sine wave leads
the input sine wave by 90◦ .
(c) If the frequency is lowered by a factor of 10,
the gain increases by a factor of 10 and,
correspondingly, the output voltage increases by a
factor of 10.
This figure belongs to Problem 2.73.
1
. If |T | = 100 V/V at
ωRC
f = 10 kHz, then for |T | = 1 V/V, f has to be
10 kHz ×100 = 1 MHz.
1
1
= 0.159 μs
=
ωint
2π × 1 MHz
2.76 CR = 1 s and Rin = 100 k.
⇒ R = 100 k
1
= 10 μF
C=
100 × 103
When a dc voltage of −1 V is applied, a dc
current of 1 V/100 k = 0.01 mA will flow as
shown in the figure below.
C 10 F
100 k
1V
0.01 mA
0.01 mA
The capacitor voltage v O will rise linearly from
its initial value of −10 V. Thus,
vO =
=
It
− 10
C
10−5 t
− 10 = t − 10, V
10 × 10−6
vO
Chapter 2–24
Thus v O will reach 0 V at
t = 10 s
and will reach 10 V at
t = 20 s
See figure below.
1
1
= 1 at ωint =
.
ωRC
RC
1
For ωint = 10 krad/s, RC = 4 = 10−4 s. Now
10
Rin = 100 k, thus R = 100 k and
10−4 s
C= 5
= 10−9 F = 1 nF. For a 2-V, 100-μs
10 2V
input pulse, a current of
= 0.02 mA
100 k
flows into R and C, causing v O to decrease
linearly from its initial value of 0 V according to
2.77 |T | =
vO = −
=
I
t
C
−0.02 × 10−3
t = −0.02 × 106 t
1 × 10−9
At t = 100 μs, v O becomes
1
⇒ CR = 1.59 μs
CR
For Rin = 10 k, R = 10 k, and
2.78 2π × 100 × 103 =
1.59 × 10−6
= 159 pF
104
To limit the dc gain to 40 dB (i.e., 100 V/V), we
connect a resistance RF across C (as in Fig. 2.25)
with RF = 100 R = 1 M.
C=
The resulting low-pass filter will have a 3-dB
frequency of
1
1
=
f3dB =
2πCRF
2π × 159 × 10−12 × 106
= 1 kHz
When a 10-μs, 1-V pulse (see Fig. 1) is applied at
the input, a current of 1 V/10 k = 0.1 mA flows
into the integrator. Now we consider two cases:
with and without RF .
v O (100 μs) = −0.02 × 106 × 100 × 10−6
= −2 V
and the output voltage then remains constant at
this value. See figures on next column. When
v I = 2 sin 104 t, the output will be a sine wave of
the same frequency but phase-shifted by −270◦
(or +90◦ ), and its magnitude will be 2 V ×
integrator gain at ω = 104 rad/s. The gain is
given by
1
1
= 4
=1
|T | =
ωRC
10 × 10−4
Thus,
v O = −2 sin(104 t − 90◦ )
Figure 1
Chapter 2–25
(a) For an integrator without RF , the 0.1-mA
current flows through C and the output voltage
decreases linearly from 0 V as
v O (t) = −
where t is in μs. At the end of the pulse,
t = 10 μs,
v O (10 μs) = −100(1 − e−10/159 ) = −6.1 V
It
C
Beyond t = 10 μs, the capacitor discharges
through RF . Thus, including RF results in the
nonideal integrator response shown in Fig. 3.
0.1 × 10−3
=−
t
159 × 10−12
= −0.63 × 106 t, V
At the end of the pulse, t = 10 μs, resulting in
v O (10 μs) = −0.63 × 106 × 10 × 10−6
= −6.3 V
See Fig. 2.
vO (V)
Figure 3
10
t (s)
6.28
2.79 Each pulse provides a constant current of
1V
through the capacitor and thus deposits a
R
1V
charge of
× 10 μs on the capacitor, resulting
R
in a change of the output voltage of
−
Figure 2
10−5
1 × 10 × 10−6
= − −3 = −0.01 V
RC
10
Therefore a total of 100 pulses are required to
cause a change of −1 V in v O (t).
(b) For an integrator with RF , the 0.1-mA current
flows through the parallel combination of C and
RF . The result is
vi (t)
t (ms)
v O (t) = v Ofinal − (v Ofinal − v Oinitial )e−t/τ
where
vo (t), mV
v Ofinal = −IRF = −0.1 × 10−3 × 106 = −100 V
v Oinitial = 0
τ = CRF = 159 × 10−12 × 106 = 159 μs
Thus,
v O (t) = −100(1 − e−t/159 ), V
t (ms)
10
20
30
Chapter 2–26
2.80
1
= 0.16 nF
2π × 1 × 103 × 106
C=
C
From the Bode plot shown in previous column,
the unity-gain frequency is 100 kHz.
R2
R1
Vi
Vo
Let Z2 = R2 1
and Z1 = R1
sC
Vo
Z2
Y1
1/R1
=− =− =−
1
Vi
Z1
Y2
+ sC
R2
Vo
=−
Vi
This function is of the STC low-pass type, having
R2
a dc gain of −
and a 3-dB frequency
R1
1
CR2
Z2 /Z1
1 + Z2 /Z1
1+
A
For Z1 = R, Z2 = 1/sC, and A = A0 ,
Vo
=−
Vi
=−
(R2 /R1 )
=−
1 + sCR2
ω0 =
2.81 Equation (2.5) can be generalized as
follows:
=−
1/sCR
1
1
1+
+
A0
sA0 CR
1
1
1
1
CR(1 + ) s +
A0
(A0 + 1)CR
A0 /[(A0 + 1)CR]
1
s+
(A0 + 1)CR
which is low-pass STC function. The pole (or
3-dB) frequency is
Rin = R1 = 10 k
dc gain = 40 dB = 100
∴ 100 =
R2
⇒ R2 = 100R1 = 1 M
R1
ωP =
1
(A0 + 1)CR
The ideal integrator has ωP = 0. Observe that as
A0 → ∞, ωP → 0. The dc gain is −A0 , which is
the dc gain of the op amp.
If an ideal Miller integrator is fed with a −1-V
pulse signal of width T = CR, the output voltage
can be found as follows: The −1-V pulse will
cause a current I = 1 V/R to be drawn through R
and C. The capacitor voltage, which is v O , will
rise linearly according to
vO =
1
1
It =
t
C
CR
Thus, at t = T (the end of the pulse) the output
voltage reaches 1 V and then stays constant at this
value.
3-dB frequency at 1 kHz
1
∴ ω0 = 2π × 1 × 10 =
CR2
3
If the integrator is made with an op amp having a
finite A0 = 1000, the response to the −1-V step
will be that of an STC low-pass circuit. Thus,
Chapter 2–27
v O = v Ofinal − (v Ofinal − v Oinitial )e−t/τ
i=C
d vI
= 0.1 × 10−6 × slope
dt
where
= 0.1 × 10−6 ×
v Ofinal = −1 V × dc gain
= −1 V × −1000
= 0.4 mA
= 1000 V
v Oinitial = 0 V
1
= (A0 + 1)CR = 1001CR
τ=
ωP
The peak value of the output square wave in = iR
= 0.4 mA × 20 k
Thus,
=8V
v O = 1000(1 − e−t/1000CR )
At t = T , which is equal to CR,
vI (V)
v O (T ) = 1000(1 − e−0.001 )
= −0.9995 −1 V
2.82
2
0.5 × 10−3
1
Vo
= −sCR = −jωCR,
Vi
Vo = ωCR
V i
2
0
For R = 10 k and C = 1 nF,
CR = 1 × 10−9 × 10 × 103 = 10 μs
t (ms)
1
1
1
1
Vo
= 1 at ω = ω0 =
=
Vi
CR
10 × 10−6
= 100 krad/s
100
= 15.9 kHz
or f0 =
2τ
Vo = ωCR = ω = f
V ω0
f0
i
Vo For f = 10 f0 ; = 10, and the output sine
Vi
wave will have 10-V peak-to-peak amplitude. The
(−jω) factor in the transfer function means
inversion and +90◦ phase shift, thus
vO (V)
8V
0
1
2
t (ms)
8 V
v O = −5 sin (106 t + 90◦ ), V
The output wave has the same frequency as the
input signal.
2.83
R 20 k
i
i
vI
The average value of the output is zero.
C 0.1 μF
0
vO iR
To increase the value of the output to
12 V = 8 V × 1.5, the value of R has to be
increased by 1.5 times:
20 k × 1.5 = 30 k
Chapter 2–28
ω0 (unity-gain frequency) = 103 rad/s
2.84
Vo At ω = 0.1 ω0 , = 0.1 V/V, φ = 270◦
V
vI
i
Vo At ω = 10 ω0 , = 10 V/V, φ = 270◦
V
1V
i
0
0.2 ms
When a series input resistor R1 is added as shown,
then the high-frequency gain is limited to R2 /R1 .
Thus,
t
R
vO (V)
C
R1
Vi
0.2 ms
Vo
t
100 k
R2
=
= 1 k
100
100
The circuit now has an STC high-pass response
with a lower 3-dB frequency
R1 =
5
v O = −CR
1
1
= −8
= 100 krad/s
CR1
10 × 103
100 s
100 s
Vo
=−
=−
Vi
s + ω3dB
s + 105
For s = jω,
ω3dB =
d vI
dt
−jω100
100
Vo
=
= −j
Vi
jω + 105
(105 /ω) + j
Therefore:
For 0 ≤ t ≤ 0.2 ms:
v O = −1 ms ×
1V
= −5 V
0.2 ms
and v O = 0 otherwise.
At ω = 104 rad/s,
Vo 10
= √ 100
= √
9.95 V/V
V 100 + 1
1 + 0.01
i
φ = 180◦ + 90◦ − tan−1 0.1 = 180◦ + 84.3◦
Both these results differ slightly from the ideal
values.
2.85
Vo
= −sCR = −10−3 s
Vi
2.86
R2
C = 10 nF = 10−8 F
R=
10−3 s
= 100 k
10−8 F
ω
Vo
= −j10−3 ω = −j 3
Vi
10
R1
C
Vi
Vo = ω
V 103
i
φ = 180◦ + 90◦ (an inversion + a phase lead
of 90◦ )
Vo
Z2
=− =−
Vi
Z1
R2
R1 +
1
sC
Vo
Chapter 2–29
Vo
R2 /R1
(jω) = −
Vi
[1 + (ω1 /jω)][1 + j(ω/ω2 )]
Thus,
(R2 /R1 )s
Vo
=−
1
Vi
s+
CR1
where
which is that of an STC high-pass type.
R2
High-frequency gain (s → ∞) = −
R1
ω1 =
1
C1 R1
and
(a) For ω
For a high-frequency input resistance of 1 k, we
select R1 = 1 k. For a high-frequency gain of
40 dB,
R2 /R1
Vo
−
Vi
1 + (ω1 /jω)
R2
= 100 ⇒ R2 = 100 k
R1
(b) For ω1
For f3dB = 2 kHz,
Vo
−(R2 /R1 )
Vi
Q.E.D.
ω1 ,
ω
ω2
(c) For ω ω2
⇒ C = 79 nF
The magnitude of the transfer function reduces
from 40 dB to unity (0 dB) in two decades. Thus
f (unity gain) =
1
C2 R2
Assuming ω2 ω1 , then
1
3-dB frequency (ω3dB ) =
CR1
1
= 2 × 103
2πCR1
ω2 =
2000
f3dB
=
= 20 Hz
100
100
R2 /R1
Vo
−
Vi
1 + j(ω/ω2 )
The resulting Bode plot will be as shown:
Design: Gain of 40 dB ⇒
f1 = 200 Hz ⇒
R2
= 100
R1
1
= 200
2πC1 R1
2.87 Refer to the circuit in Fig. P2.87.
f2 = 200 kHz ⇒
Z2
1
Vo
=− =−
Vi
Z1
Z1 Y2
= −
1
R1 +
sC1
1
1
+ sC2
R2
R2 /R1
= −
1
1+
(1 + sC2 R2 )
sC1 R1
1
= 200 × 103
2πC2 R2
Input resistance (at ω ω1 ) = 2 k
⇒ R1 = 2 k
Thus, R1 = 2 k, R2 = 200 k, C1 0.4 μF,
and C2 4 pF.
Chapter 2–30
2.88 Inverting configuration:
2.91
(a) IB = (IB1 + IB2 )/2
R2
VO = VOS 1 +
R1
−0.2 = VOS 1 +
R2
R1
= VOS
Open input:
v O = v + + R2 IB1 = VOS + R2 IB1
100
1+
2
⇒ VOS 4 mV
2.89 VOS = ±2 mV
VO = 0.01 sin ωt × 100 + VOS × 100
= 1 sin ωt ± 0.2 V
5.3 = VOS + 10,000IB1
(1)
Input connected to ground:
v O = v + + R2
VOS
IB1 +
R1
R2
= VOS 1 +
+ R2 IB1
R1
5 = VOS × 101 + 10,000IB1
(2)
Equations (1), (2)
⇒ 100VOS = −0.3 ⇒ VOS = −3 mV
⇒ IB1 = 530 nA
IB IB1 = 530 nA
2.90 Input offset voltage = 3 mV
and both flow into the op-amp input terminals.
Output dc offset voltage
= 3 mV × closed loop gain
(b) VOS = −3 mV
= 3 mV × 1000
=3V
The maximum amplitude of an input sinusoid
that results in an output peak amplitude of
12 – 3 = 9 V is given by
vi =
9
= 9 mV
1000
If amplifier is capacitively coupled then
v i max =
12
= 12 mV
1000
(c) In this case, Since R is very large, we may
ignore VOS compared to the voltage drop across R.
VOS
RIB , Also Eq. (2.46) holds:
R3 = R1 R2
Chapter 2–31
5-k resistance in series with R3 . The resulting dc
offset voltage at the output will be
therefore from Eq. (2.40):
VO = IOS × R2 ⇒ IOS =
−0.6
10 M
VO = IOS R2 = 0.2 × 100 = 20 mV
Since IOS can be of either polarity,
IOS = −60 nA
VO = ±20 mV
The same result could have been found by
replacing R3 in Eq. (1) by (R3 + R4 ) where
R4 = 5 k.
2.92
If the signal source resistance is 15 k, then the
resistances can be equalized by adding a 5-k
resistor in series with the negative input lead of
the op amp.
R2 = 100 k
R1 =
100 k
9
R3 = 5 k
2.93
IB1 = 2 ± 0.1, μA, VOS = 0
IB2 = 2 ± 0.1, μA
R3
IB1 − IB2
R1
C1
R1
VO = −IB2 R3 + R2
R2
From Eq. (2.38):
Thus,
R2
VO = IB1 R2 − IB2 R3 1 +
R1
C2
(1)
R3
The maximum value of VO is obtained when
IB1 = 2.1 μA and IB2 = 1.9 μA,
100
VOmax = 2.1 × 100 − 1.9 × 5 1 +
100/9
= 210 − 95 = 115 mV
The minimum value of VO is obtained when
IB1 = 1.9 μA and IB2 = 2.1 μA,
R2 = R3 = 100 k
1+
R2
= 100
R1
VOmin = 1.9 × 100 − 2.1 × 5 × 10
= 190 − 105 = 85 mV
Thus the dc offset at the output will be in the
range of 85 mV to 115 mV. The bulk of the dc
offset at the output, that due to IB , can be reduced
to zero by making the dc resistances seen by the
two input terminals equal. Currently, the positive
input terminal sees a resistance R3 = 5 k and
the negative input terminal sees a resistance equal
100
to R1 R2 =
100 = 10 k. Thus the two
9
resistances can be made equal by connecting a
R1 =
100 k
= 1.01 k
99
1
1
= 2π × 100 ⇒ C1 =
R1 C1
1.01 × 2π × 105
= 1.58 μF
1
1
= 2π × 10 ⇒ C2 =
R3 C2
2π × 106
= 0.16 μF
vO
Chapter 2–32
= 1001VOS
2.94
1 M VA 1 M
= 1001 × 3 mV 3V
I
A large capacitor placed in series with the 1-k
resistor results in
1 k
1 M
VOS
I
VO
VOS
v − = v + = VOS
VA = 2VOS = 6 mV
I=
VOS
6 mV
=
= 6 nA
1 M
1 M
VO = VA + 1 M ×
I+
= 2 VOS + 1 M ×
VA
1 k
v + = v − = VOS
VOS
2 VOS
+
1 M
1 k
No dc current flows through R1 , C branch
∴ VO = VA + VOS
= 2 VOS + VOS
= 2003 VOS
= 3 VOS
= 2003 × 3 mV
= 3 × 3 mV
∼
=6V
= 9 mV
For capacitively coupled input,
1 M
I0
VA
2.95
1 M
1 M
1 k
(1000/99) k
VO
VOS
100 = 1 +
v + = v − = VOS
I =0
VO
(a) VO = 200 × 10−9 × 1 × 106 = 0.2 V
VA = VOS
VO = VA + 1 M ×
R2
⇒ R1 = 10.1 k
R1
(b) Largest output offset is
VOS
= VOS + 1000VOS
1 k
VO = 2 mV × 100 + 0.2 V = 400 mV = 0.4 V
Chapter 2–33
(c) For bias current compensation, we connect a
resistor R3 in series with the positive input
terminal of the op amp, with R3 = R1 R2 ,
R3 = 10 k 1 M 10 k
IOS =
0.4 V
= 0.4 μA. Thus, the possible
1 M
range of IOS is 0.2 μA to 0.4 μA.
case, IOS =
2.98
200
= 20 nA
10
1 M
The offset current alone will result in an output
offset voltage of
10 nF
10 k
IOS × R2 = 20 × 10−9 × 1 × 106 = 20 mV
R3
(d) VO = 200 mV + 20 mV = 220 mV = 0.22 V
IB1
Vos
Vo
IB2
2.96 At 0◦ C, we expect
±20 × 25 × 1000 μV = ±500 mV = ±0.5 V
◦
At 75 C, we expect
±20 × 50 × 1000 μ = ±1 V
We expect these quantities to have opposite
polarities.
2.97 R3 = R1 R2 = 10 k 1 M = 9.09 k
Now, with the input grounded and assuming
VOS = 0, the measured +0.3-V at the output is
entirely due to IOS , that is,
(a) R3 = R RF = 10 k 1 M
⇒ R3 = 9.9 k
(b) As discussed in Section 2.8.2, the dc output
voltage of the integrator
when the
input is
RF
grounded is VO = VOS 1 +
+ IOS RF
R
1 M
VO = 2 mV 1 +
+ 20 nA × 1 M
10 k
= 0.202 V + 0.02 V
VO = 0.222 V
0.3 = IOS R2 = IOS × 1 M
Thus,
IOS = 0.3 μA
If VOS = ±1 mV, then it alone will result in an
output
voltageof
R2
VOS 1 +
= VOS × 101 = ±101 mV or
R1
+0.1 V
If VOS is positive, 0.1 V of the output 0.3-V offset
will be due to VOS , leaving 0.2 V as the result of
0.2 V
IOS ; thus in this case, IOS =
= 0.2 μA. On
1 M
the other hand, if VOS is negative, then −0.1 V of
the output 0.3 V is due to VOV , with the result that
IOS must be causing 0.4 V of output offset. In this
2.99 ft = A0 fb
A0
fb (Hz)
ft (Hz)
105
102
107
106
1
106
105
103
108
107
10−1
106
2 × 105
10
2 × 106
2.100 At very low frequencies, the gain is A0 ,
thus
20 log A0 = 98 dB ⇒ A0 80,000 V/V
Chapter 2–34
At f = 100 kHz, the gain is 40 dB or 100 V/V.
Thus
2.102 The gain drops by 20 dB at f 10fb . Thus
(a) A0 = 2 × 105 V/V
ft = 100 kHz × 100 = 10 MHz
fb =
10 MHz
= 125 Hz.
Since ft = A0 fb ⇒ fb =
80,000
5 × 102
= 50 Hz
10
ft = A0 fb = 2 × 105 × 50 = 107 Hz = 10 MHz
2.101 f = 10 kHz |A| = 20 × 103
(b) A0 = 20 × 105 V/V
f = 100 kHz |A| = 4 × 103
fb =
Thus, a change of a decade in f does not result in
a factor of 10 reduction in gain; in fact, the gain
reduces by only a factor of 5. It follows that the
first frequency (10 kHz) is less than fb . Therefore,
we must use the exact expression for |A|, that is,
A0
1 + (10/fb )2
= 20 × 103
(1)
A0
1 + (100/fb )2
= 4 × 103
(2)
1 + (100/fb )2
=5
1 + (10/fb )2
⇒1+
102
2500
1002
=
25
1
+
= 25 + 2
2
2
fb
fb
fb
fb =
0.1 GHz
= 10 MHz
10
ft = A0 fb = 100 × 10 = 1 GHz
(e) A0 = 25 V/mV = 25 × 103 V/V
fb =
250
= 25 kHz
10
fb = A0 × fb = 25 × 103 × 25 × 103 = 625 MHz
2.103 Gnominal = −50 ⇒
10,000 2500
− 2 = 24
fb2
fb
0.1 MHz
= 10 kHz
10
(d) A0 = 100 V/V
fb =
Dividing Eq. (1) by Eq. (2), we have
(c) A0 = 1800 V/V
ft = A0 fb = 1800 × 10 = 18 MHz
Substituting the given data, we obtain
ft = A0 fb = 20 × 105 × 1 = 2 MHz
fb =
A0
|A| = 1 + (f /fb )2
10
= 1 Hz
10
R2
= 50
R1
A0 = 104
7500
= 17.68 kHz
24
ft = 106 Hz
Now, substituting in Eq. (1) yields
A0 = 20 × 103 1 +
10
17.68
f3dB of closed-loop amplifier =
2
= 22,976 V/V
and the unity-gain frequency is
ft = A0 fb = 22.976 × 103 × 17.68 × 103
= 406.2 MHz
=
106
= 19.61 kHz
51
G=−
50
1+j
f
f3dB
ft
1+
R2
R1
Chapter 2–35
50
|G| = 1 + (f /f3dB )2
f3dB =
50
= 49.75 V/V
For f = 0.1 f3dB , |G| = √
1.01
For f3dB = 5 MHz, ft = 10 MHz
50
For f = 10 f3dB , |G| = √
= 4.975 V/V
1 + 100
which is a 20-dB reduction.
2.104 ft = 20 MHz and closed-loop gain
1+
R2
= 100 V/V
R1
f3dB =
ft
1+
R2
R1
=
1+j
⇒ φ = −tan−1
R2
1+
R1
=
ft
2
(d) G = −2 V/V ⇒
f3dB =
ft
R2
1+
R1
=
20 MHz
= 200 kHz
100
ft
3
For f3dB = 5 MHz, ft = 15 MHz
f3dB =
ft
R2
1+
R1
=
f
f3db
ft
1001
(f) G = +1 V/V ⇒
f
f3dB =
f3dB
ft
1+
R2
R1
= ft
(g) G = −1 V/V ⇒
φ = 84◦ , f = f3dB × tan 84◦ = 1.9 MHz
f3dB =
2.105 (a) G = −50 V/V ⇒
R2
1+
R1
=
R2
= 50
R1
1+
R2
R1
R2
1+
R1
=
ft
2
For f3dB = 1 MHz, ft = 2 MHz
2.106 f3dB = ft = 1 MHz
(b) G = +50 V/V ⇒ 1 +
ft
ft
R2
=1
R1
ft
51
For f3dB = 100 kHz ⇒ ft = 100 × 51 = 5.1 MHz
f3dB =
R2
=0
R1
For f3dB = 1 MHz, ft = 1 MHz
f = f3dB × tan 6◦ = 21 kHz
ft
R2
= 1000
R1
For f3dB = 10 kHz, ft = 10 × 1001 = 10.1 MHz
For φ = −6◦
f3dB =
R2
=2
R1
(e) G = −1000 V/V ⇒
100
G( jω) =
ft
=
R2
= 50
R1
1+
1
2 = 1 + f 2 with
f
f3dB
f in MHz
ft
50
|G| = 0.99 ⇒ f = 0.142 MHz
For f3dB = 100 kHz, ft = 5 MHz
(c) G = +2 V/V ⇒ 1 +
1
|G| = R2
=2
R1
The follower behaves like a low-pass STC circuit
1
1
μs
=
with a time constant τ =
2π
2π × 106
tr = 2.2τ = 0.35 μs.
Chapter 2–36
2.107 1 +
R2
= 10 ⇒ R1 = 1 k and R2 = 9 k
R1
When a 100-mV (i.e., 0.1-V) step is applied at the
input, the output will be
v O = 0.1 × 10(1 − e−t/τ ), V
1+
f3dB
f1
f3dB = f1
2
=
√
√
2
2−1
Q.E.D
(b) 40 dB = 20 log G0 ⇒ G0 = 100 = 1 +
R2
R1
where
τ=
f3dB =
1
ω3dB
v O reaches 1% of the 1-V final value at time t,
ft
R2
1+
R1
=
2 MHz
= 20 kHz
100
1 − e−t/τ = 0.99
(c) Each stage should have 20-dB gain or
R2
1+
= 10 and therefore a 3-dB frequency of
R1
e−t/τ = 0.01
f1 =
2 × 106
= 2 × 105 Hz
10
t = 4.6τ
The overall f3dB = 2 × 105
√
2−1
For t to be 200 ns,
= 128.7 kHz,
200
= 43.49 ns
τ=
4.6
Thus we require a closed-loop 3-dB frequency
1
or
τ
ω3dB =
f3dB =
1
1
=
= 3.66 MHz
2πτ
2π × 43.49 × 10−9
Correspondingly, the op amp must have an ft of
ft = f3dB
R2
1+
R1
= 36.6 MHz
2.108 (a) Assume two identical stages, each with
a gain function:
G=
G0
ω =
jf
1+j
1+
ω1
f1
G0
2.109 ft = 100 × 5 = 500 MHz if a single op
amp is used.
With an op amp that has only ft = 40 MHz, the
possible closed-loop gain at 5 MHz is
|A| =
40
= 8 V/V
5
To obtain an overall gain of 100 would require
three such amplifiers, cascaded. Now, if each of
the stages has a low-frequency (dc) closed-loop
40
MHz.
gain K, then its 3-dB frequency will be
K
Thus for each stage the closed-loop gain is:
K
|G| = ⎛
⎞2
f
⎜
⎟
1 + ⎝
40 ⎠
G0
2
f
1+
f1
G= overall gain of the cascade is
which is 6.4 times greater than the bandwidth
achieved using a single op amp, as in case (b)
above.
K
G02
2
f
1+
f1
The gain will drop by 3 dB when
which at f = 5 MHz becomes
K
2
K
1+
8
|G5MHz | = Chapter 2–37
⎢
⎢
For overall gain of 100: 100 = ⎢
⎢
⎣
⎥
⎥
K
⎥
2 ⎥
K ⎦
1+
8
2.112
i
100 kΩ
1 kΩ
vI
⇒ K = 5.7
1
iO
⎤3
⎡
vO
Thus for each cascade stage: f3dB =
iL
40
5.7
RL
f3dB = 7 MHz
The 3-dB frequency of the overall amplifier, f1 ,
can be calculated as
⎡
⎢
⎢
⎢
⎢
⎣
⎤3
⎥
3
⎥
5.7
⎥ = (5.7)
⇒ f1 = 3.6 MHz
√
2 ⎥
2
⎦
f
1+
7
(a) RL = 1 k
for v Omax = 10 V: Vp =
Vp = 0.1 V
When the output is at its peak,
10
= 10 mA
iL =
1 k
i=
2.110 (a)
R2
= K, f3dB =
R1
ft
R2
1+
R1
=
ft
1+K
GBP = Gain × f3dB
GBP = K
(b) 1 +
ft
K
=
ft
1+K
K +1
R2
= K,
R1
GBP = K
f3dB =
ft
K
ft
= ft
K
10
100
−10
= −0.1 mA; therefore
100 k
iO = 10 + 0.1 = 10.1 mA is well under
iOmax = 20 mA.
At the negative peak of the output voltage,
v O = −10 V, iL = −10 mA, i = 0.1 mA, and
iO = −10.1 mA, again well under the 20-mA
maximum allowed.
(b) RL = 200 If output is at its peak: iL =
10 V
= 50 mA
0.2
which exceeds iOmax = 20 mA. Therefore v O
cannot go as high as 10 V. Instead:
For the same closed-loop gain, the noninverting
configuration realizes a higher GBP, and it is
independent of the closed-loop gain and equal to
ft of the op amp.
20 mA =
vp =
vO
20
vO
+
⇒ vO =
4V
200 100 k
5.01
4
= 0.04 V = 40 mV
100
(c) RL = ?, iOmax = 20 mA =
2.111 The peak value of the largest possible sine
wave that can be applied at the input without
output clipping is
±14 V
= 0.14 V = 140 mV.
100
140
Thus the rms value = √ 100 mV
2
20 − 0.1 =
10 V
10 V
+
RLmin
100 k
10
⇒ RLmin = 502 RLmin
2.113 Op-amp slew rate = 10 V/μs.
For the input pulse to rise 2 V, it will take
2
= 0.2 μs.
10
Chapter 2–38
∴ The minimum pulse width = W = 0.2 μs
dv O = SR ⇒ 10ωmax = 40 × 10+6 ⇒ ωmax
dt max
The output will be a triangular with 2-V peak and
10 V/μs slopes.
= 4 × 106 rad/s
⇒ fmax = 637 kHz
vi (V)
2.116 (a) Vi = 0.5, Vo = 10 × 0.5 = 5 V
2
Output distortion will be due to slew-rate
limitation and
will occur at the frequency for
dv O which
= SR
dt max
t
W
ωmax × 5 = 10 × 106
ωmax = 2 × 106 rad/s and fmax = 318.3 kHz
vO
(V)
(b) The output will distort at the value of Vi that
dv O results in
= SR.
dt max
2
ω × 10Vimax = SR
t
Vimax =
10 × 106
= 0.795 V
2π × 200 × 103 × 10
(c) Vi = 50 mV Vo = 500 mV = 0.5 V
2.114 Slope of the triangle wave =
Thus
10 V
= SR
T /2
10
× 2 = 20 V/μs
T
⇒ T = 1 μs or f =
⇒f =
1
= 1 MHz
T
For a sine wave vO = V̂o sin (2π × 1 × 106 t)
dv O = 2π × 1 × 106 V̂o = SR
dt max
⇒ V̂o =
20 × 106
= 3.18 V
2π × 106 × 1
2.115 v O = 10 sin ωt ⇒
= 10ω cos ωt ⇒
Slew rate begins at the frequency for which
ω × 0.5 = SR
dv O
dt
dv O dt max
10 × 106
= 3.18 MHz
2π × 0.5
However, the small-signal 3-dB frequency is
f3dB =
ft
1+
R2
R1
=
20 × 106
= 2 MHz
10
Thus the useful frequency range is limited to
2 MHz.
(d) For f = 50 kHz, the slew-rate limitation
occurs at the value of Vi given by
ωi × 10Vi = SR ⇒ Vi =
10 × 106
2π × 50 × 103 × 10
= 3.18 V
= 10ω
Such an input voltage, however, would ideally
result in an output of 31.8 V, which exceeds VOmax .
The highest frequency at which this output is
possible is that for which
Thus Vimax =
VOmax
= 1 V peak.
10
Exercise 3–1
Ex: 3.1 Refer to Fig. 3.3(a). For v I ≥ 0, the
diode conducts and presents a zero voltage drop.
Thus v O = v I . For v I < 0, the diode is cut off,
zero current flows through R, and v O = 0. The
result is the transfer characteristic in Fig. E3.1.
(c)
V5V
I0A
Ex: 3.2 See Fig. 3.3a and 3.3b. During the
positive half of the sinusoid, the diode is forward
biased, so it conducts resulting in v D = 0. During
the negative half cycle of the input signal v I , the
diode is reverse biased. The diode does not
conduct, resulting in no current flowing in the
circuit. So v O = 0 and v D = v I − v O = v I . This
results in the waveform shown in Fig. E3.2.
2.5 k
5 V
(d)
V0V
10 V
vˆI
=
= 10 mA
R
1 k
1
dc component of v O = vˆO
π
1
10
= vˆI =
π
π
= 3.18 V
05
2.5
2 mA
Ex: 3.3 îD =
I
2.5 k
5 V
(e)
I
3V
Ex: 3.4
0
V3V
2V
(a)
0
1V
5 V
I
2.5 k
I
1 k
50
2 mA
2.5
(f)
3
3 mA
1
5 V
V0V
1 k
0
3 V
(b)
0
2 V
5 V
1 V
2.5 k
I0A
V5V
I
Ex: 3.5 Vavg =
10
π
10
10
k
50 + R = π =
1 mA
π
∴ R = 3.133 k
51
1
4 mA
I
V1V
Exercise 3–2
R 10 k
Ex: 3.6
I2
V2 − V1 = 2.3 V T log
I1
At room temperature VT = 25 mV
VCC 5 V
10
V2 − V1 = 2.3 × 25 × 10−3 × log
0.1
I2
I1
I2
V2 = V1 + 2.3 × VT log
I1
V2 − V1 = 2.3 × VT log
Ex: 3.7 i = IS ev /VT
(1)
1 (mA) = IS e
(2)
0.7/VT
Dividing (1) by (2), we obtain
(v −0.7)/VT
⇒ v = 0.7 + 0.025 ln(i)
where i is in mA. Thus,
VD
= 115 mV
i (mA) = e
ID
First iteration
V2 = 0.7 + 2.3 × 25 × 10−3 log
= 0.679 V
Second iteration
5 − 0.679
= 0.432 mA
I2 =
10 k
V2 = 0.7 + 2.3 × 25.3 × 10−3 log
for i = 0.1 mA,
v = 0.7 + 0.025 ln(0.1) = 0.64 V
= 0.679 V 0.68 V
and for i = 10 mA,
we get almost the same voltage.
v = 0.7 + 0.025 ln(10) = 0.76 V
0.43
1
0.432
1
∴ The iteration yields
ID = 0.43 mA, VD = 0.68 V
Ex: 3.8 T = 125 − 25 = 100◦ C
b. Use constant voltage drop model:
IS = 10−14 × 1.15T
VD = 0.7 V
= 1.17 × 10−8 A
Ex: 3.9 At 20◦ C I =
constant voltage drop
5 − 0.7
= 0.43 mA
ID =
10 k
1V
= 1 μA
1 M
Ex: 3.11
Since the reverse leakage current doubles for
every 10◦ C increase, at 40◦ C
10 V
I
R
I = 4 × 1 μA = 4 μA
⇒ V = 4 μA × 1 M = 4.0 V
@ 0◦ C
I=
1
μA
4
2.4 V
1
⇒ V = × 1 = 0.25 V
4
Ex: 3.10 a. Use iteration:
Diode has 0.7 V drop at 1 mA current.
Assume VD = 0.7 V
ID =
5 − 0.7
= 0.43 mA
10 k
Diodes have 0.7 V drop at 1 mA
∴ 1 mA = IS e0.7/VT
(1)
At a current I (mA),
I = IS eVD /VT
Use Eq. (3.5) and note that
Using (1) and (2), we obtain
V1 = 0.7 V, I1 = 1 mA
I = e(VD −0.7)/VT
(2)
Exercise 3–3
For an output voltage of 2.4 V, the voltage drop
2.4
= 0.8 V
across each diode =
3
Now I, the current through each diode, is
(d)
V 0.7 V
I = e(0.8−0.7)/0.025
= 54.6 mA
10 − 2.4
R=
54.6 × 10−3
0.7 5
2.5
1.72 mA
I
2.5 k
= 139 5 V
(e)
Ex: 3.12
I
3V
(a)
0
5 V
V 3 0.7
2.3 V
2V
0
1V
2.5 k
5 0.7
I
1.72 mA
2.5
2.3
1
2.3 mA
I
V 0.7 V
1 k
(f)
5V
5 1.7
1
3.3 mA
I
(b)
5 V
3 V
2.5 k
V 1 0.7
0
2 V
I0A
1 k
1.7 V
0
1 V
I
V5V
(c)
Ex: 3.13 rd =
VT
ID
ID = 0.1 mA
rd =
25 × 10−3
= 250 0.1 × 10−3
ID = 1 mA
rd =
25 × 10−3
= 25 1 × 10−3
ID = 10 mA
rd =
25 × 10−3
= 2.5 10 × 10−3
V5V
Ex: 3.14 For small signal model,
iD = v D /rd
2.5 k
I0A
where rd =
VT
ID
For exponential model,
5 V
iD = IS eV /V T
(1)
Exercise 3–4
iD2
= e(V2 −V1 ) /V T = ev D /V T
iD1
iD = iD2 − iD1 = iD1 ev D /V T − iD1
= iD1 ev D /V T − 1
c. If iD = 5 − i L = 5 − 1 = 4 mA.
(2)
In this problem, iD1 = ID = 1 mA.
Using Eqs. (1) and (2) with VT = 25 mV, we
obtain
v D (mV) iD (mA) iD (mA)
small
exponential
signal
model
a
b
c
d
− 10
−5
+5
+ 10
− 0.4
− 0.2
+ 0.2
+ 0.4
− 0.33
− 0.18
+ 0.22
+ 0.49
Across each diode the voltage drop is
ID
VD = VT ln
IS
4 × 10−3
= 25 × 10−3 × ln
4.7 × 10−16
= 0.7443 V
Voltage drop across 4 diodes
= 4 × 0.7443 = 2.977 V
so change in VO = 2.977 − 3 = −23 mV.
Ex: 3.16 For a zener diode
VZ = VZ0 + IZ rZ
10 = VZ0 + 0.01 × 50
VZ0 = 9.5 V
Ex: 3.15
For IZ = 5 mA,
15 V
VZ = 9.5 + 0.005 × 50 = 9.75 V
For IZ = 20 mA,
R
IL
VO
VZ = 9.5 + 0.02 × 50 = 10.5 V
Ex: 3.17
15 V
R
I
5.6 V
a. In this problem,
VO
20 mV
= 20 .
=
iL
1 mA
∴ Total small-signal resistance of the four diodes
= 20 20
∴ For each diode, rd =
= 5 .
4
VT
25 mV
⇒5=
.
But rd =
ID
ID
∴ ID = 5 mA
15 − 3
= 2.4 k.
5 mA
b. For VO = 3 V, voltage drop across each diode
3
= = 0.75 V
4
and R =
iD = IS eV /VT
IS =
iD
eV /VT
=
5 × 10−3
= 4.7 × 10−16 A
e0.75/0.025
0 to 15 mA
The minimum zener current should be
5 × IZk = 5 × 1 = 5 mA
Since the load current can be as large as 15 mA,
we should select R so that with IL = 15 mA, a
zener current of 5 mA is available. Thus the
current should be 20 mA, leading to
R=
15 − 5.6
= 470 20 mA
Maximum power dissipated in the diode occurs
when IL = 0 is
Pmax = 20 × 10−3 × 5.6 = 112 mV
Exercise 3–5
a. The diode starts conduction at
Ex: 3.18
v S = VD = 0.7 V
15 V
√
v S = Vs sin ωt, here Vs = 12 2
I
200 15 5.1
49.5 mA
0.2 k
50 mA
At ωt = θ,
VZ
v S = Vs sin θ = VD = 0.7 V
√
12 2 sin θ = 0.7
0.7
θ = sin−1
2.4◦
√
12 2
Conduction starts at θ and stops at 180 − θ.
Thus, at no load VZ
5.1 V
∴ Total conduction angle = 180 − 2θ = 175.2◦
For line regulation:
b. v O,avg
vo
200 vi vo
7
mV
=
= 33.8
vi
200 + 7
V
200 VO
IL
rZ
V O
−IL (rZ 200 )
=
IL
IL mA
= −6.8
(Vs sin φ − VD ) d φ
θ
1
[−Vs cos φ − VD φ]φ=π−θ
φ−θ
2π
1
[Vs cos θ − Vs cos (π − θ) − VD (π − 2θ)]
=
2π
But cos θ 1, cos (π − θ) − 1, and
π − 2θ π
VD
2Vs
−
2π
2
VD
Vs
−
=
π
2
√
For Vs = 12 2 and VD = 0.7 V
√
12 2 0.7
v O,avg =
−
= 5.05 V
π
2
c. The peak diode current occurs at the peak
diode voltage.
√
12 2 − 0.7
V − VD
∴ îD = s
=
R
100
= 163 mA
√
PIV = +V S = 12 2
v O,avg =
For load regulation:
VZ0
(π−θ
)
=
7
Line regulation =
1
=
2π
17 V
mV
mA
Ex: 3.20
vS
input
Ex: 3.19
Vs
vS
Vs 12 2
output
VD
0
( )
VD
0
u
u
2
t
VS
a. As shown in the diagram, the output is zero
between (π − θ) to (π + θ)
= 2θ
t
Exercise 3–6
Here θ is the angle at which the input signal
reaches VD .
Vs
∴ Vs sin θ = VD
VD
θ = sin−1
Vs
VD
2θ = 2 sin−1
Vs
(a) VO,avg =
π
.
2
Peak current
Vs − VD
Vs sin (π /2) − VD
=
=
R
R
If v S is 12 V(rms),
√
√
then Vs = 2 × 12 = 12 2
√
12 2 − 0.7
Peak current =
163 mA
100
Nonzero output occurs for angle = 2 (π − 2θ )
The fraction of the cycle for which v O > 0 is
2 (π − 2θ)
× 100
2π
0.7
2 π − 2 sin−1
√
12 2
× 100
=
2π
=
(Vs sin φ − 2VD ) d φ
cos (π − θ) ≈ − 1
π − 2θ ≈ π. Thus
⇒ VO,avg 2Vs
− 2VD
π
√
2 × 12 2
− 1.4 = 9.4 V
=
π
Peak voltage
(b) Peak diode current =
R
√
Vs − 2VD
12 2 − 1.4
=
=
R
100
= 156 mA
√
PIV = Vs − VD = 12 2 − 0.7 = 16.3 V
Ex: 3.22 Full-wave peak rectifier:
D1
vO
vS
vS
97.4 %
Average output voltage VO is
√
Vs
2 × 12 2
VO = 2 − VD =
− 0.7 = 10.1 V
π
π
Peak diode current îD is
√
Vs − VD
12 2 − 0.7
îD =
=
R
100
1
2π
2
[−Vs cos φ − 2VD φ]π−θ
φ=θ
2π
1
= [Vs cos φ − Vs cos(π − θ) − 2VD (π − 2θ)]
π
But cos θ ≈ 1,
for θ small.
c. Peak current occurs when φ =
Vs
2V
sin–1 D
VS
=
1
−θ
[−Vs cos φ − VD φ]πφ=θ
π
Vs
− VD ,
π
input
t
0
θ
2
output
2VD
b. Average value of the output signal is given by
⎡
⎤
(π
−θ)
1 ⎣
2×
VO =
(Vs sin φ − VD ) d φ ⎦
2π
=
Ex: 3.21
R
C
D2
Vp
t
Vr{
assume
ideal diodes
t
= 163 mA
PIV = Vs − VD + VS
√
√
= 12 2 − 0.7 + 12 2
= 33.2 V
T
2
The ripple voltage is the amount of voltage
reduction during capacitor discharge that occurs
Exercise 3–7
when the diodes are not conducting. The output
voltage is given by
If t = 0 is at the peak, the maximum diode current
occurs at the onset of conduction or at t = −ωt.
v O = Vp e−t/RC
During conduction, the diode current is given by
T /2
Vp − Vr = Vp e− RC
←
discharge is only half
T
.
the period. We also assumed t
2
T /2
Vr = Vp 1 − e− RC
T /2
,
for CR
RC
T /2
Thus Vr Vp 1 − 1 +
RC
T /2
e− RC 1 −
Vr =
Vp
2fRC
(a)
T/2
Q.E.D.
QSUPPLIED = QLOST
iCav t = CV r
Vp
Vp
iD,av − IL t = C
=
2fRC
2fR
Vp π
ωR
iD,av =
Vp π
+ IL
ωtR
where ωt is the conduction angle.
Note that the conduction angle has the same
expression as for the half-wave rectifier and is
given by Eq. (3.30),
2Vr
∼
ωt =
(b)
Vp
Substituting for ωt, we get
⇒ iD,av = πVp
2Vr
·R
Vp
= IL 1 + π
d v S + iL
dt t=−ωt
assuming iL is const. iL Vp
= IL
R
d Vp cos ωt + IL
dt
= −C sin ω t × ωVp + IL
=C
= −C sin(−ωt) × ωVp + IL
For a small conduction angle
Vp
2Vr
⇒ iD,max = Cωt × ωVp + IL
Sub (b) to get
2V r
iD,max = C
ωVp + IL
Vp
Substituting ω = 2πf and using (a) together with
Vp /R IL results in
Vp
Q.E.D.
iDmax = IL 1 + 2π
2Vr
Ex: 3.23
D4
ac
line
voltage
D1
vO vS
R
D2
C
D3
+ IL
Since the output is approximately held at Vp ,
Vp
≈ IL · Thus
R
Vp
⇒ iD,av ∼
+ IL
= π IL
2Vr
iD,max = C
sin(−ωt) ≈ − ωt. Thus
To find the average diode current, note that the
charge supplied to C during conduction is equal
to the charge lost during discharge.
=
iD = iC + iL
Q.E.D.
The output voltage, v O , can be expressed as
v O = Vp − 2VD e−t/RC
At the end of the discharge interval
v O = Vp − 2VD − Vr
The discharge occurs almost over half of the time
period T /2.
For time constant RC
T
2
Exercise 3–8
e−t/RC 1 −
T
1
×
2
RC
Ex: 3.24
1
T
∴ VP − 2VD − Vr = Vp − 2VD 1 − ×
2
RC
⇒ Vr = Vp − 2VD
i
vI
i
T
×
2RC
iD
vO
√
Here Vp = 12 2 and Vr = 1 V
iR
VD = 0.8 V
T=
1 k
1
1
=
s
f
60
√
1 = (12 2 − 2 × 0.8) ×
1
2 × 60 × 100 × C
√
(12 2 − 1.6)
C=
= 1281 μF
2 × 60 × 100
Without considering the ripple voltage, the dc
output voltage
√
= 12 2 − 2 × 0.8 = 15.4 V
If ripple voltage is included, the output voltage is
√
Vr
= 14.9 V
= 12 2 − 2 × 0.8 −
2
IL =
vA
vD
14.9
0.15 A
100 The conduction angle ωt can be obtained
using
√
Eq. (3.30) but substituting Vp = 12 2 − 2 × 0.8:
2Vr
2×1
ωt =
=
√
Vp
12 2 − 2 × 0.8
The average and peak diode currents can be
calculated using Eqs. (3.34) and (3.35):
Vp
14.9 V
iDav = IL 1 + π
,
, where IL =
2Vr
100 √
Vp = 12 2 − 2 × 0.8, and Vr = 1 V; thus
iDmax = I 1 + 2π
iD = IS ev D /VT
iD
= e(v D −0.7)/V T
1 mA
iD
⇒ v D = VT ln
+ 0.7 V
1 mA
For v I = 10 mV, v O = v I = 10 mV
It is an ideal op amp, so i+ = i− = 0.
10 mV
= 10 μA
1 k
10 μA
+ 0.7 = 0.58 V
v D = 25 × 10−3 ln
1 mA
∴ iD = iR =
v A = v D + 10 mV
= 0.58 + 0.01
= 0.59 V
For v I = 1 V
= 0.36 rad = 20.7◦
iDav = 1.45 A
The diode has 0.7 V drop at 1 mA current.
Vp
2Vr
vO = vI = 1 V
1
vO
=
= 1 mA
1 k
1 k
v D = 0.7 V
iD =
VA = 0.7 V + 1 k × 1 mA
= 1.7 V
For v I = −1 V, the diode is cut off.
∴ vO = 0 V
v A = −12 V
= 2.76 A
PIV of the diodes
Ex: 3.25
√
= VS − VDO = 12 2 − 0.8 = 16.2 V
To provide a safety margin, select a diode capable
of a peak current of 3.5 to 4A and having a PIV
rating of 20 V.
vI
vO
R
IL
Exercise 3–9
v I ≥ 0 ∼ diode is cut off, loop is open, and the
opamp is saturated:
vO = 0 V
v I ≤ 0 ∼ diode conducts and closes the negative
feedback loop:
vO = vI
For v I ≤ −5 V, diode D1 conducts and
1
(+v I + 5)
2
vI V
= −2.5 +
2
For v I ≥ 5 V, diode D2 conducts and
v O = −5 +
1
(v I − 5)
2
vI V
= 2.5 +
2
v O = +5 +
Ex: 3.26
10 k
10 k
Both diodes are cut off
for −5V ≤ v I ≤ + 5V
and v O = v I
vO
5V v
O
vI
D2
D1
5V
Ex: 3.27 Reversing the diode results in the peak
output voltage being clamped at 0 V:
10 k
t
10 V
Here the dc component of v O = VO = −5 V
Chapter 3–1
3.3
3.1
1
(a)
I
1.5 V
VD
D1
1 V
(a)
Cutoff
D2
V2V
2 V
Conducting
1
I
2 k
1.5 V
I
VD
2 (3)
2 k
2.5 mA
3 V
(b)
(b)
3 V
(a) The diode is reverse biased, thus
I =0A
VD = −1.5 V
2 k
Conducting
3 (1)
2
1 mA
I
D1
1 V
V1V
(b) The diode is forward biased, thus
VD = 0 V
2 V
D2
1.5 V
= 1.5 A
I=
1
3.2 Refer to Fig. P3.2.
(a) Diode is conducting, thus
3.4
(a)
V = −3 V
I=
Cutoff
vO
+3 − (−3)
= 0.6 mA
10 k
5V
(b) Diode is reverse biased, thus
0
t
I =0
V = +3 V
V p+ = 5 V Vp− = 0 V f = 1 kHz
(c) Diode is conducting, thus
(b)
V = +3 V
I=
vO
+3 − (−3)
= 0.6 mA
10 k
(d) Diode is reverse biased, thus
I =0
V = −3 V
0
t
5 V
Vp+ = 0 V Vp− = −5 V f = 1 kHz
Chapter 3–2
(c)
D1 shorts to ground when v I > 0 and is cut off
when v I < 0 whereby the output follows v I .
vO
vO 0 V
(h)
0
t
t
Neither D1 nor D2 conducts, so there is no output.
v O = 0 V ∼ The output is always shorted to
ground as D1 conducts when v I > 0 and D2
conducts when v I < 0.
(d)
(i)
vO = 0 V
vO
vO
5V
5V
t
t
Vp+ = 5 V, Vp− = 0 V,
f = 1 kHz
2.5 V
Vp+ = 5 V, Vp− = −2.5 V,
f = 1 kHz
Both D1 and D2 conduct when v I > 0
When v I > 0, D1 is cut off and v O follows v I .
(e)
When v I < 0, D1 is conducting and the circuit
becomes a voltage divider where the negative
peak is
vO
1 k
× −5 V = −2.5 V
1 k + 1 k
5V
5 V
t
(j)
vO
5V
Vp+ = 5 V, Vp− = −5 V,
f = 1 kHz
D1 conducts when v I > 0 and D2 conducts when
v I < 0. Thus the output follows the input.
2.5 V
t
(f)
Vp+ = 5 V, Vp− = −2.5 V,
vO
5V
t
Vp+ = 5 V, Vp− = 0 V,
f = 1 kHz
When v I > 0, the output follows the input as D1
is conducting.
When v I < 0, D1 is cut off and the circuit
becomes a voltage divider.
(k)
f = 1 kHz
vO
D1 is cut off when v I < 0
5V
(g)
1V
vO
t
t
5 V
5 V
4 V
Vp+ = 1 V, Vp− = −4 V, f = 1 kH3
Vp+ = 0 V, Vp− = −5 V,
f = 1 kHz
When v I > 0, D1 is cut off and D2 is conducting.
The output becomes 1 V.
Chapter 3–3
When v I < 0, D1 is conducting and D2 is cut off.
The output becomes:
determine the conduction angle of D2 , (π − 2θ),
where
3
= 30◦
θ = sin−1
6
Thus
vO = vI + 1 V
3.5
A B X
0
0
1
1
0
1
0
1
0
0
0
1
Y
π − 2θ = 180◦ − 60 = 120◦
0
1
1
1
The average value of iB will be
60 × 120◦
= 20 mA
iB |av =
360◦
If the peak value of v I is reduced by 10%, i.e.
from 6 V to 5.4 V, the peak value of iB does not
change. The conduction angle of D2 , however,
changes since θ now becomes
3
θ = sin−1
= 33.75◦
5.4
and thus
X = AB, Y = A + B
X and Y are the same for
A=B
X and Y are opposite if A = B
π − 2θ = 112.5◦
3.6
Thus the average value of iB becomes
60 × 112.5◦
= 18.75 mA
iB |av =
360◦
3.7 The case for the highest current in a single
diode is when only one input is high:
VY = 5 V
VY
≤ 0.2 mA ⇒ R ≥ 25 k
R
3.8 The maximum input current occurs when one
input is low and the other two are high.
5−0
≤ 0.2 mA
R
R ≥ 25 k
From Fig. P3.6 we see that when v I < VB ; that is,
v I < 3 V, D1 will be conducting the current I and
iB will be zero. When v I exceeds the battery
voltage (3 V), D1 cuts off and D2 conducts, thus
steering I into the battery. Thus, iB will have the
waveform shown in the figure. Its peak value will
be 60 mA. To obtain the average value, we first
3.9 The analysis is shown on the circuit diagrams
below.
These figures belong to Problem 3.9.
reverse biased
10 10 5 k
5 k
5 k
V
I
10
10 10
2.5 V
5
20 k
I
2.5
0.1 mA
5 20
V 0.1 20 2 V
(a)
I0
2.5 V
V
1.5 V
V 1.5 2.5 1 V
(b)
Chapter 3–4
I = 0.25 mA
3.10
3 V
V =0V
0.33 mA
12 k
1 V
D1
OFF
I0
√
120 2
≥ 4.2 k
40
The largest reverse voltage appearing across the
diode is equal to the peak input voltage:
√
120 2 = 169.7 V
3.11 R ≥
D2
ON
V 1 V
0.33
mA
3.12 For v I > 0 V: D is on, v O = v I , iD = v I /R
For v I < 0 V: D is off, v O = 0, iD = 0
6 k
3 V
(a)
(a) If we assume that both D1 and D2 are
conducting, then V = 0 V and the current in D2
will be [0 − (−3)]/6 = 0.5 mA. The current in
the 12 k will be (3 − 0)/12 = 0.25 mA. A node
equation at the common anodes node yields a
negative current in D1 . It follows that our
assumption is wrong and D1 must be off. Now
making the assumption that D1 is off and D2 is on,
we obtain the results shown in Fig. (a):
I =0
V = −1 V
3 V
3.13
6 k
3 – 0 0.5 mA
6
0V
0.25 mA
D1
ON
D2
ON
0 – (–3)
12
0.25 mA
V0
12 k
3 V
(b)
(b) In (b), the two resistors are interchanged.
With some reasoning, we can see that the current
supplied through the 6-k resistor will exceed
that drawn through the 12-k resistor, leaving
sufficient current to keep D1 conducting.
Assuming that D1 and D2 are both conducting
gives the results shown in Fig. (b):
Chapter 3–5
Conduction stops at π − θ.
3.14
∴ Fraction of cycle that current flows is
R
D
vI
12 V
π − 2θ
× 100 = 25%
2π
Average diode current =
1 −17 cos φ − 12φ φ = 3π/4
= 103 mA
2π
8
φ = π/4
Peak diode current
17 − 12
= 0.625 A
=
8
Peak reverse voltage =
vI
A
12 V
0 A + 12 = 29 V
2
3.15
conduction occurs
V
RED
3V
ON
0
OFF
–3 V OFF
GREEN
OFF
- D1 conducts
OFF
- No current flows
ON
- D2 conducts
kT
q
v I = A sin θ = 12 ∼ conduction through D
occurs
3.16 VT =
For a conduction angle (π − 2θ ) that is 25% of a
cycle
where
k = 1.38 × 10−23 J/K = 8.62 × 10−5 eV/K
1
π − 2θ
=
2π
4
π
θ=
4
A = 12/sin θ = 17 V
T = 273 + x◦ C
q = 1.60 × 10−19 C
Thus
VT = 8.62 × 10−5 + (273 × x◦ C), V
∴ Peak-to-peak sine wave voltage
x [◦ C] VT [mV]
= 2A = 34 V
−55
0
+40
+125
Given the average diode current to be
1
2π
2π
A sin φ − 12
d φ = 100 mA
R
0
1
2π
−17 cos φ − 12φ
R
φ = 0.75π
= 0.1
φ = 0.25π
R = 8.3 A − 12
= 0.6 A
Peak diode current =
R
Peak reverse voltage = A + 12 = 29 V
For resistors specified to only one significant digit
and peak-to-peak voltage to the nearest volt,
choose A = 17 so the peak-to-peak sine wave
voltage = 34 V and R = 8 .
18.8
23.5
27.0
34.3
for VT = 25 mV at 17◦ C
3.17 I1 = IS e0.7/VT = 10−3
i2 = IS e0.5/VT
i2
i2
= −3 = e
i1
10
i2 = 0.335 μA
0.5 − 0.7
0.025
3.18 i = I S ev /0.025
∴ 10,000IS = IS ev /0.025
Conduction starts at v I = A sin θ = 12
v = 0.230 V
17 sin θ = 12
π rad
θ=
4
At v = 0.7 V,
i = IS e0.7/0.025 = 1.45 × 1012 IS
Chapter 3–6
3.19 I = IS eVD /VT
10−3 = IS e0.7/VT
(1)
For VD = 0.71 V,
I = IS e0.71/VT
(2)
(b) VD = 0.650 V, ID = 1 mA
⇒ IS = 5.11 × 10−15 A;
10% of ID gives VD = 0.59 V
(c) VD = 0.650 V, ID = 10 μA
⇒ IS = 5.11 × 10−17 A;
Combining (1) and (2) gives
10% of ID gives VD = 0.59 V
I = 10−3 e(0.71 − 0.7)/0.025
(d) VD = 0.700 V, ID = 100 mA
⇒ IS = 6.91 × 10−14 A;
= 1.49 mA
10% of ID gives VD = 0.64 V
For VD = 0.8 V,
I = IS e0.8/VT
(3)
Combining (1) and (3) gives
I = 10−3 × e(0.8 − 0.7)/0.025
3.21 The voltage across three diodes in series is
2.0 V; thus the voltage across each diode must be
0.667 V. Using ID = IS eVD /VT , the required
current I is found to be 3.9 mA.
If 1 mA is drawn away from the circuit, ID will be
2.9 mA, which would give VD = 0.794 V, giving
an output voltage of 1.98 V. The change in output
voltage is −22 mV.
= 54.6 mA
Similarly, for VD = 0.69 V we obtain
I = 10−3 × e(0.69 − 0.7)/0.025
= 0.67 mA
3.22
and for VD = 0.6 V we have
I
I = 10−3 e(0.6 − 0.7)/0.025
= 18.3 μA
To increase the current by a factor of 10, VD must
be increased by VD ,
10 = e
⇒
ID1
D1
VD /0.025
−VD /VT
Let a decrease by a factor of 10 in ID result in a
decrease of VD by V:
ID = IS eVD /VT
ID
= IS e(VD −V)/VT = IS eVD /VT · e−V /V T
10
Taking the ratio of the above two equations, we
have
10 = e
V /V T
⇒ V
60 mV
Thus the result in each case is a decrease in the
diode voltage by 60 mV.
(a) VD = 0.700 V, ID = 1 A
⇒ IS = 6.91 × 10−13 A;
10% of ID gives VD = 0.64 V
D2
VD
VD = 0.025 ln10 = 57.6 mV
3.20 IS can be found by using IS = ID · e
ID2
.
ID1 = IS1 eVD /VT
(1)
VD /VT
(2)
ID2 = IS2 e
Summing (1) and (2) gives
ID1 + ID2 = (IS1 + IS2 )eVD /VT
But
ID1 + ID2 = I
Thus
I = (IS1 + IS2 ) eVD /VT
(3)
From Eq. (3) we obtain
I
VD = VT ln
IS1 + IS2
Also, Eq. (3) can be written as
IS2
I = IS1 eVD /VT 1 +
IS1
(4)
Chapter 3–7
ID1 = 10I S eVD1 /VT
Now using (1) and (4) gives
ID1 =
I
IS1
=I
1 + (IS2 /IS1 )
IS1 + IS2
Taking the ratio of the two equations above, we
have
7
1 V /V T
1 (VD2 −VD1 )/VT
ID2
= =
=
e
e
ID1
3
10
10
70
⇒ V = 0.025 ln
= 78.7 mV
3
We similarly obtain
ID2 =
I
IS2
=I
1 + (IS1 /IS2 )
IS1 + IS2
3.23 Connecting an identical diode in parallel
would reduce the current in each diode by a factor
of 2. Writing expressions for the currents, we have
ID = IS eVD /VT
ID
= IS e(VD −V)/VT = IS eVD /VT · e−V /V T
2
Taking the ratio of the above two equations, we
have
2 = eV /V T ⇒ V = 17.3 mV
To instead achieve V = 60 mV, we need
I1 − I2
1 0.06/0.025
ID2
e
=
=
= 1.1
ID1
I2
10
Solving the above equation with I1 still at 10 mA,
we find I2 = 4.76 mA.
3.26 We can write the following node equation at
the diode anodes:
ID2 = 10 mA − V /R
Thus the result is a decrease in the diode voltage
by 17.3 mV.
ID1 = V /R
We can write the following equation for the diode
voltages:
3.24
V = VD2 − VD1
We can write the following diode equations:
I
ID2 = IS eVD2 /VT
ID1 = IS eVD1 /VT
D1
D2
D3
I1
2I1
4I1
D4
8I1
I1 0.1 mA
The junction areas of the four diodes must be
related by the same ratios as their currents, thus
Taking the ratio of the two equations above, we
have
10 mA − V /R
ID2
= e(VD2 −VD1 )/VT = eV /V T
=
ID1
V /R
To achieve V = 50 mV, we need
10 mA − 0.05/R
ID2
= e0.05/0.025 = 7.39
=
ID1
0.05/R
Solving the above equation, we have
R = 42 A4 = 2A3 = 4A2 = 8 A1
With I1 = 0.1 mA,
I = 0.1 + 0.2 + 0.4 + 0.8 = 1.5 mA
3.25 We can write a node equation at the anodes:
ID2 = I1 − I2 = 7 mA
ID1 = I2 = 3 mA
We can write the following equation for the diode
voltages:
V = VD2 − VD1
If D2 has saturation current IS , then D1 , which is
10 times larger, has saturation current 10IS . Thus
we can write
ID2 = IS eVD2 /VT
3.27 For a diode conducting a constant current,
the diode voltage decreases by approximately 2
mV per increase of 1◦ C.
T = −20◦ C corresponds to a temperature
decrease of 40◦ C, which results in an increase of
the diode voltage by 80 mV. Thus VD = 770 mV.
T = + 85◦ C corresponds to a temperature
increase of 65◦ C, which results in a decrease of
the diode voltage by 130 mV. Thus VD = 560 mV.
3.28 For a diode conducting a constant current,
the diode voltage decreases by approximately
2 mV per increase of 1◦ C.
A decrease in VD by 100 mV corresponds to a
junction temperature increase of 50◦ C.
Chapter 3–8
Taking the ratio of the above two equations, we
have
The power dissipation is given by
PD = (10 A) (0.6 V) = 6 W
ID1
= IS e(VD1 −VD2 )/VT ⇒ VD1 − VD2
ID2
ID1
= VT ln
ID2
The thermal resistance is given by
50◦ C
T
= 8.33◦ C/W
=
PD
6W
3.29
For ID = 1 mA, we have
1 × 10−3 A
= −230 mV
V = VT ln
10 A
10 V
I
R1
⇒ VD = 570 mV
D1
V1
D2
V2
For ID = 3 mA, we have
3 × 10−3 A
= −202 mV
V = VT ln
10 A
⇒ VD = 598 mV
Assuming VD changes by –2 mV per 1◦ C increase
in temperature, we have, for ±20◦ C changes:
For ID = 1 mA, 530 mV ≤ VD ≤ 610 mV
At 20◦ C:
For ID = 3 mA, 558 mV ≤ VD ≤ 638 mV
VR1 = V2 = 520 mV
R1 = 520 k
520 mV
= 1 μA
I=
520 k
Since the reverse current doubles for every 10◦ C
rise in temperature, at 40◦ C, I = 4 μA
ID2
40°C
4 μA
40 mV
520 mV
V2 = 480 + 2.3 × 1 × 25 log 4
= 514.6 mV
VR1 = 4 μA × 520 k = 2.08 V
1
μA
4
V2 = 560 − 2.3 × 1 × 25 log 4
At 0◦ C, I =
= 525.4 mV
1
VR1 = × 520 = 0.13 V
4
3.30 Given two different voltage/current
measurements for a diode, we can write
ID1 = IS eVD1 /VT
ID2 = IS eVD2 /VT
3.31 Given two different voltage/current
measurements for a diode, we have
ID1
= IS e(VD1 −VD2 )/VT ⇒ VD1 − VD2
ID2
ID1
= VT ln
ID2
20°C
For the first diode, with ID = 0.1 mA and
1 μA
480
Thus the overall range of VD is between 530 mV
and 638 mV.
V2
VD = 700 mV, we have
ID = 1 mA:
1.0
= 57.6 mV
0.1
⇒ VD = 757.6 mV
V = VT ln
ID = 3 mA:
V = VT ln
3
0.1
= 85 mV ⇒ VD = 785 mV
For the second diode, with
ID = 1 A and VD = 700 mV, we have
ID = 1.0 mA:
0.001
V = VT ln
= −173 mV
1
⇒ VD = 527 mV
Chapter 3–9
ID = 3 mA:
0.003
1
⇒ VD = 555 mV
= 0.661 V
For i = 0.4 mA, v = 0.668 V
= −145 mV
V = VT ln
Now we can refine the diagram to obtain a better
estimate
For both ID = 1.0 mA and ID = 3 mA, the
difference between the two diode voltages is
approximately 230 mV. Since, for a fixed diode
current, the diode voltage changes with
temperature at a constant rate (–2 mV per ◦ C
temp. increase), this voltage difference will be
independent of temperature!
0.4
i (mA)
0.35
Load line
3.32
R 1 kΩ
VDD
i
v
1V
0.30
0.660
0.664
v (V)
0.67
From this graph we get the operating point
IS = 10−15 A = 10−12 mA
i = 0.338 mA, v = 0.6635 V
Calculate some points
Now we compare graphical results with the
exponential model.
v = 0.6 V,
i = IS ev /V T
At i = 0.338 mA
i
0.338
= 0.025 × ln
v = VT ln
IS
10−12
= 10−12 e0.6/0.025
0.03 mA
v = 0.65 V,
v = 0.7 V,
i
i
0.2 mA
= 0.6637 V
1.45 mA
Make a sketch showing these points and load line
and determine the operating point. The points for
the load line are obtained using
ID =
VDD − VD
R
The difference between the exponential model
and graphical results is = 0.6637 − 0.6635
= 0.0002 V
= 0.2 mV
3.33
i (mA)
500 2.0
Diode characteristic
1V
1.0
0.8
0.6
0.4
0.2
0
i
v
Load line
0.4
0.6
0.8
1.0
v (V)
From this sketch one can see that the operating
point must lie between v = 0.65 V to v = 0.7 V
i
For i = 0.3 mA, v = VT ln
IS
3
= 0.025 × ln
10−12
1 − 0.7
= 0.6 mA
0.5 k
b) Diode has 0.7 V drop at 1 mA current. Use
Eq. (3.5):
i2
v 2 = v 1 + 2.3VT log
i1
a) ID =
1. v = 0.7 V
1 − 0.7
= 0.6 mA
1 i=
0.5 k
Chapter 3–10
2. v = 0.7 + 2.3 × 0.025 log
0.6
1
0.825 V. Applying this voltage to the diode gives
current ID = 20.1 mA. We can then find the
resistor value using
= 0.6872 V
1 − 0.6872
= 0.6255 mA
2 i=
0.5
0.6255
3. v = 0.7 + 2.3 × 0.025 log
1
R=
3.36 Constant voltage drop model:
= 0.6882 V
1 − 0.6882
= 0.6235 mA
3 i=
0.5 k
0.6235
4. v = 0.7 + 2.3 × 0.025 log
1
V − 0.7
R
V − 0.6
Using v D = 0.6 V, ⇒ iD2 =
R
For the difference in currents to be only 1%,
Using v D = 0.7 V, ⇒ iD1 =
= 0.6882 V
1 − 0.6882
= 0.6235 mA
4 i=
0.5 k
Stop as we are getting the same result.
3.34
⇒ iD2 = 1.01iD1
V − 0.6 = 1.01 (V − 0.7)
V = 10.7 V
R 1 k
1V
ID
15 V − 3.3 V
= 582 20.1 mA
VD
For V = 3 V and R = 1 k:
3 − 0.7
= 2.3 mA
At VD = 0.7 V, iD1 =
1
3 − 0.6
= 2.4 mA
At VD = 0.6 V, iD2 =
1
2.4
iD2
= 1.04
=
iD1
2.3
Thus the percentage difference is 4%.
IS = 10−15 A = 10−12 mA
Use the iterative analysis procedure:
1 − 0.7
= 0.3 mA
1. VD = 0.7 V, ID =
1K
ID
0.3
= 0.025 ln
2. VD = VT ln
IS
10−12
||
3.37 Available diodes have 0.7 V drop at 2 mA
current since 2VD = 1.4 V is close to 1.3 V, use N
parallel pairs of diodes to split the 1 mA current
evenly, as shown in the figure next.
N
= 0.6607 V
1 − 0.6607
= 0.3393 mA
1K
0.3393
= 0.6638 V
3. VD = 0.025 ln
10−12
ID =
1 − 0.6638
= 0.3362 mA
1K
0.3362
= 0.6635 V
4. VD = 0.025 ln
10−12
ID =
1 − 0.6635
= 0.3365 mA
1 k
Stop here as we are getting almost same value of
ID and VD
ID =
3.35 We first find the value of IS for the diode,
given by IS = ID e−VD /VT with ID = 1 mA and
VD = 0.75 V. This gives IS = 9.36 × 10−17 A.
In order to have 3.3 V across the 4
series-connected diodes, each diode drop must be
⫹
V
1 mA
⫺
The voltage drop across each pair of diodes is
1.3 V. ∴ Voltage drop across each diode
1.3
=
= 0.65 V. Using
2
I2 = I1 e(V2 −V1 )/VT
= 2e(0.65−0.7)/0.025
= 0.2707 mA
Thus current through each branch is 0.2707 mA.
The 1 mA will split in =
1
= 3.69 branches.
0.2707
Choose N = 4.
There are 4 pairs of diodes in parallel.
Chapter 3–11
∴ We need 8 diodes.
3.39
Current through each pair of diodes
1 mA
= 0.25 mA
=
4
∴ Voltage across each pair
0.25
= 2 0.7 + 0.025 ln
2
(a)
3 V
10 k
= 1.296 V
V
SPECIAL NOTE: There is another possible
design utilizing only 6 diodes and realizing a
voltage of 1.313 V. It consists of the series
connection of 4 parallel diodes and 2 parallel
diodes.
I
3 V
V = −3 + 0.7 = −2.3 V
3 + 2.3
I=
10
= 0.53 mA
3.38 Refer to Example 3.2.
(a)
(b)
10 V
5 I 1.861 10 k
0.86 mA
4
3 V
10 0
1 mA
10
10 k
V0V 3
V
1 0.7 V
5 k
2 0.7 10
5
1.86 mA
Cutoff
I
3 V
10 V
I =0A
(b)
V = 3 − I (10) = 3 V
10 V
5 k
ID2
I0
V
0.7 V
Cutoff
10 k
(c)
I
V
10 k
ID2
10 V
10 − (−10) − 0.7
= 1.29 mA
15
VD = −10 + 1.29 (10) + 0.7 = 3.6 V
ID2 =
3 V
3 V
V = 3 − 0.7 = 2.3 V
2.3 + 3
= 0.53 mA
I=
10
Chapter 3–12
3.41
(d)
3 V
+3V
I
Cutoff
ID2
12 k
V
I0
ON 0.7 V
D2
V
D1
ID2
Cutoff
3 V
6 k
I =0A
3 V
(a)
V = −3 V
3V
3.40
(a)
30.7
0.383 mA
6
Cutoff
1 V
0.7 V
D1
2 V
6 k
V
D2
2 k
I 0.383 0.25
0.133 mA
ON
D2
D1
ON
0(3)
12
0.25 mA
I
V0V
12 k
3 V
3 V
(b)
3 − 0.7 − (−3)
= 0.294 mA
12 + 6
V = −3 + 0.294 × 6 = −1.23 V
V = 2 − 0.7
(a) ID2 =
= 1.3 V
1.3 − (−3)
I=
2
= 2.15 mA
Check that D1 is off: Voltage at the anode of
D1 = V + VD2 = −1.23 + 0.7 = −0.53 V which
keeps D1 off.
(b)
(b) See analysis on Fig. (b).
3 V
I = 0.133 mA
I
2 k
V =0V
3.42
1 V
D1
V
10 10 5 k 0.7 V
V
2 V
D2
Cutoff
V = 1 + 0.7 = 1.7 V
3 − 1.7
= 0.65 mA
I=
2
10
5
10 10
2.5 V
I
20 k
(a)
Chapter 3–13
5 k
V 5 k
0 mA
1.5 V
2.5 V
Maximum allowable voltage signal change when
the current change is limited to ±10% is found as
follows:
The current varies from 0.9 to 1.1
iD2
= eV /VT
iD1
(b)
For 0.9, V = 25 ln (0.9) = −2.63 mV
2.5 − 0.7
(a) I =
= 0.072 mA
5 + 20
V = 0.072 × 20 = 1.44 V
For 1.1, V = 25 ln (1.1) = +2.38 mV
For ±10% current change the voltage signal
change is from –2.63 mV to +2.38 mV
(b) The diode will be cut off, thus
I =0
3.45 The dc current I flows through the diode
VT
and
giving rise to the diode resistance rd =
I
the small-signal equivalent circuit is represented
by
V = 1.5 − 2.5 = −1 V
3.43
Rs
vI iD
v I ,peak − 0.7
≤ 40 mA
R
√
120 2 − 0.7
R≥
= 4.23 k
40
√
Reverse voltage = 120 2 = 169.7 V.
iD,peak =
rd
vs
R
rd
VT /I
VT
= vs
= vs
VT
rd + RS
VT + IRS
+ RS
I
25 mV
Now, v o = 10 mV ×
25 mV + 103 I
vo = vs ×
I
vo
The design is essentially the same since the
supply voltage 0.7 V
1 mA 0.24 mV
0.1 mA 2.0 mV
1 μA
9.6 mV
3.44 Use the exponential diode model to find the
percentage change in the current.
1
0.025
vs = vs ×
2
0.025 + 103 I
⇒ I = 25 μA
iD = IS ev /VT
iD2
= e(V2 −V1 )/VT = ev /VT
iD1
For +5 mV change we obtain
iD2
= e5/25 = 1.221
iD1
% change
1.221 − 1
iD2 − iD1
× 100 =
× 100
=
iD1
1
= 22.1%
For –5 mV change we obtain
iD2
= e−5/25 = 0.818
iD1
0.818 − 1
iD2 − iD1
× 100
× 100 =
% change =
iD1
1
= −18.1%
vo
For v o =
3.46 As shown in Problem 3.45,
VT
0.025
vo
=
=
vi
VT + RS I
0.025 + 104 I
Here RS = 10 k
(1)
The current changes are limited ±10%. Using
exponential model, we get
iD2
= ev /VT = 0.9 to 1.1
iD1
iD2
and here
v = 25 × 10−3 ln
iD1
For 0.9, v = −2.63 mV
For 1.1, v = 2.38 mV
The variation is –2.63 mV to 2.38 mV for ±10%
current variation. Thus the largest symmetrical
Chapter 3–14
output signal allowed is 2.38 mV in amplitude. To
obtain the corresponding input signal, we divide
this by (v o /v i ):
vˆs =
2.38 mV
v o /v i
(2)
Now for the given values of v o /v i calculate I
and v̂ S using Equations (1) and (2)
vo
vi
I in mA v̂ s in mV
0.5
0.1
0.01
0.001
0.0025
0.0225
0.2475
2.4975
vo
= 900 × 10−3 = 0.9 V/V
vi
vo
= 990 × 10−3 = 0.99 V/V
I = 990 μA,
vi
I = 900 μA,
I = 1 mA
= 1000 μA,
vo
= 1000 × 10−3 = 1 V/V
vi
3.48
4.76
23.8
238
2380
I
D1
D3
3.47
vo
1 mA C
2
vo
C1
D1
vi
R
D2
D2
10 k
D4
vi
I
I
When both D1 and D2 are conducting, the
small-signal model is
rd1
vi
vo
rd2
where we have replaced the large capacitors C1
and C2 by short circuits:
rd 2
vo
=
vi
rd 1 + rd 2
Thus
vo
= I,
vi
VT
I
1
m
−I
=
=
VT
VT
1m
+
I
1m−I
where I is in mA
Now I = 0 μA,
vo
=0
vi
vo
= 1 × 10−3 = 0.001 V/V
vi
vo
= 10 × 10−3 = 0.01 V/V
= 10 μA,
vi
vo
= 100 × 10−3 = 0.1 V/V
= 100 μA,
vi
vo
= 500 × 10−3 = 0.5 V/V
= 500 μA,
vi
vo
= 600 × 10−3 = 0.6 V/V
= 600 μA,
vi
a. The current through each diode is
I
:
2
2VT
VT
0.05
=
=
I
I
I
2
From the equivalent circuit
rd =
R
vo
=
vi
R + (2rd
I
2rd )
=
R
R + rd
vo
vi
rd
0 μA
∞
0
1 μA 50 k 0.167
10 μA 5 k 0.667
100 μA 500 0.952
1 mA
50 0.995
10 mA
5 0.9995
I = 1 μA,
I
I
I
I
rd
rd
rd
rd
vo
vI
R
Equivalent Circuit
10 k
Chapter 3–15
b. For signal current to be limited to ±10% of I (I
is the biasing current), the change in diode
voltage can be obtained from the equation
v̂ i = v̂ o + 5 mV = 1 V + 5 mV = 1.005 V. See
also the figure below.
iD
= eVD /V T = 0.9 to 1.1
I
v D = −2.63 mV to +2.32 mV
±2.5 mV
so the signal voltage across each diode is limited
to 2.5 mV when the diode current remains within
10% of the dc bias current.
∴ v o = 10 − 2.5 − 2.5 = 5 mV
5 mV
= 0.5 μA
and i =
10 k
2.5
mV
2.5
mV
3.49
i
vo
10 mV R
2.5
mV
I
10 k
2.5
mV
D1
The current through each diode
0.5
μA = 0.25 μA
2
The signal current i is 0.5 μA, and this is 10% of
the dc biasing current.
=
vI
i2
D2
i1
i3
v1
v3 v
2
v4 D3
iO
vO
i4 R 10 k
D4
I
∴ DC biasing current I = 0.5 × 10 = 5 μA
c. Now I = 1 mA.
∴ ID = 0.5 mA
Maximum current derivation 10%.
0.5
= 0.05 mA
∴ id =
10
and i = 2id = 0.1 mA.
∴ Maximum v o = i × 10 k
= 0.1 × 10
=1V
I = 1 mA
Each diode exhibits 0.7 V drop at 1 mA current.
Using diode exponential model we have
i2
v 2 − v 1 = VT ln
i1
and v 1 = 0.7 V, i1 = 1 mA
i
⇒ v = 0.7 + VT ln
1
From the results of (a) above, for I = 1 mA,
v o /v i = 0.995; thus the maximum input signal
will be
= 700 + 25 ln(i)
v̂ i = v̂ o /0.995 = 1/0.995
v O = 0, iO = 0, and the current I = 1 mA divide
equally between the D3 , D4 side and the D1 , D2
side.
I
i1 = i2 = i3 = i4 = = 0.5 mA
2
v = 700 + 25 ln(0.5) 683 mV
= 1.005 V
The same result can be obtained from the figure
above where the signal across the two series
diodes is 5 mV, thus
Calculation for different values of v O :
Chapter 3–16
v 1 = v 2 = v 3 = v 4 = 683 mV
3.50 Representing the diode by the small-signal
resistances, the circuit is
From the circuit, we have
v I = −v 1 + v 3 + v O = −683 + 683 + 0 = 0 V
1
For v O = 1 V, iO =
= 0.1 mA
10 k
Because of symmetry of the circuit, we obtain
iO
I
= 0.5 + 0.05 = 0.55 mA and
i3 = i2 = +
2
2
i4 = i1 = 0.45 mA
i2
v 3 = v 2 = 700 + 25 ln
= 685 mV
1
i4
v 4 = v 1 = 700 + 25 ln
= 680 mV
1
(V)
iO
i3 = i2 i4 = i1 v 3 = v 2 v 4 = v 1
(mA) (mA) (mA) (mV)
(mV)
v I = −v 1 +
v 3 + v O (V)
vO
0
0
0.5
0.5
683
683
0
+1
0.1
0.55
0.45
685
680
1.005
+2
0.2
0.6
0.4
∼ 687
677
2.010
+5
0.5
0.75
0.25
∼ 693
665
5.028
+9
0.9
0.95
0.05
∼ 699
∼ 625
9.074
0.995
0.005
∼ 700
568
10.09
9.99
0.999 0.9995 0.0005 ∼ 700
510
10.18
10
1
0
10.7
rd
vi
C
vo
VT
rd ID
1
sC
1
=
1
1 + sCrd
rd +
sC
1
Vo
=
Vi
1 + jωCrd
ωCrd
Phase shift = −tan−1
1
VT
= −tan−1 ωC
I
Vo
=
Vi
v I = −v 1 + v 2 + v O = −0.680
For phase shift of −45◦ , we obtain
−45 = −tan−1 2π × 100 × 103 × 10
0.025
× 10−9 ×
I
+0.685 + 1 = 1.005 V
⇒ I = 157 μA
Similarly, other values are calculated as shown in
the table. The largest values of v O on positive and
negative side are +10 V and −10 V, respectively.
This restriction is imposed by the current
I = 1 mA
157
μA to 157 × 10 μA
10
Range is 15.7 μA to 1570 μA
A similar table can be generated for the negative
values. It is symmetrical.
3.51
+ 9.9 0.99
1
0
700
Now I varies from
Range of phase shift is −84.3◦ to −5.71◦
For v I > +10.7, v O will be saturated at +10 V
and it is because I = 1 mA. Similarly, for
v I < −10.7 V, v O will be saturated at −10 V.
V
R
For I = 0.5 mA, the output will saturate at
0.5 mA ×10 k = 5 V.
vo (V )
I 1 mA
10
I 0.5 mA
5
(a)
10.7 5.68
5.68
5
VO
10.7
v1 (V)
=
VO
rd
=
=
+
V
R + rd
VT /I
VT
R+
I
VT
IR + VT
For no load, I =
V + − 0.7
V + − VO
=
.
R
R
Chapter 3–17
∴
VT
VO
=
V +
VT + (V + − 0.7)
(b) At no load, ID =
rd =
R
V
rd
VT
ID
VO
= − (rd
IL
R) = −
VO
(b) If m diodes are in series, we obtain
VO
mr d
mVT
=
=
V +
mr d + R
mVT + IR
1
ID
ID
+
V + − 0.7 VT
=−
VT
×
ID
=−
V + − 0.7
VT
×
ID
VT + V + − 0.7
For
mVT
mVT + (V + − 0.7m)
1
1
1
+
rd
R
=−
Small-signal model
=
V + − 0.7
R
1
VT
+1
V + − 0.7
mV
VO
≤5
IL
mA
5 mV
VT
V + − 0.7
≤
×
ID
VT + V + − 0.7
mA
mV
15 − 0.7
25
≤5
×
ID
0.025 + 15 − 0.7
mA
i.e.,
(c) For m = 1
VO
VT
=
= 1.75 mV/V
V +
VT + V + − 0.7
For m = 4
ID ≥ 4.99 mA
ID
5 mA
VO
mVT
=
= 8.13 mV/V
V +
mVT + 15 − m × 0.7
R=
15 − 0.7
V + − 0.7
=
ID
5 mA
3.52
R = 2.86 k
V
Diode should be a 5-mA unit; that is, it conducts
5 mA at VD = 0.7 V, thus 5 × 10−3 = IS e0.7/0.025 .
R
⇒ IS = 3.46 × 10−15 A
IL
(c) For m diodes connected in series we have
VO
ID =
V + − 0.7m
R
and rd =
VO
So now
IL
VT
ID
VO
= −(R
IL
mrd ) = −
rd
R
=−
1
ID
ID
+
V + − 0.7m mVT
=−
mV T
ID
Small-signal model
(a) From the small-signal model
VO = −I L (rd R)
VO
= − (rd R)
IL
mV T
+1
− 0.7m
V+
=−
V + − 0.7m
mVT
+
ID V − 0.7m + mVT
1
1
1
+
R mrd
Chapter 3–18
choose the 15-mA supply. Note, however, that the
price paid is increased power dissipation.
3.53
3.54
5 V
I
vO 1.5 V VO
I
IL
R
IL
ID
Vo
ID
RL
IL varies from 2 to 7 mA
To supply a load current of 2 to 7 mA, the current
I must be greater than 7 mA. So I can be only
10 mA or 15 mA.
Now let us evaluate VO for both 10-mA and
15-mA sources. For the 10-mA source:
Since IL varies from 2 to 7 mA, the current ID will
varry from 8 to 3 mA.
Diode has 0.7 V drop at 1 mA current
VO = 1.5 V when RL = 1.5 k
ID = IS eV /V T
1 × 10−3 = IS e0.7/0.025
⇒ IS = 6.91 × 10−16 A
1.5
= 0.75 V.
2
= 6.91 × 10−16 × e0.75/0.025
Voltage drop across each diode =
Correspondingly, the voltage across each diode
changes by VD where
∴ ID = IS eV /V T
3
=e
8
IL = 1.5/1.5 = 1 mA
⇒
VD /VT
3
VD = 25 ln
= −24.5 mV
8
and the output voltage changes by
VO = 2 ×
VD = −49 mV
With I = 15 mA, the diodes current changes from
13 to 8 mA. Correspondingly, the voltage across
each diode changes by VD where
8
=e
13
⇒
VD /VT
8
VD = 25 ln
= −12.1 mV
13
and the output voltage changes by
VO = 2 ×
VD = −24.2 mV
which is less than half that obtained with the
10-mA supply. Thus, from the point of view of
reducing the change in VO as IL changes, we
= 7.38 mA
I = ID + IL = 7.39 mA + 1 mA
= 8.39 mA
∴R=
5 − 1.5
= 417 8.39 mA
Use a small-signal model to find voltage VO
when the value of the load resistor, RL , changes:
rd =
VT
0.025
= 3.4 =
ID
7.39
When load is disconnected, all the current I flows
through the diode. Thus
ID = 1 mA
VO = ID × 2rd
= 1 × 2 × 3.4
= 6.8 mV
With RL = 1 k,
Chapter 3–19
IL
1.5 V
= 1.5 mA
1
IL =
IL = 0.5 mA
I=
ID = −0.5 mA
5 − 1.4
5 − VO
=
= 18 mA
R
0.2
ID = I − IL = 18 − 9.33 = 8.67 mA
VO = −0.5 × 2 × 3.4
Iteration #2:
= −3.4 mV
8.67
= 0.696 V
VD = 0.7 + 0.025 ln
10
With RL = 750 ,
IL
VO
1.4
= 9.33 mA
=
RL
0.15
1.5
= 2 mA
0.75
VO = 1.393 V
IL = 9.287 mA
IL = 1 mA
ID = −1 mA
I=
VO = −1 × 2 × 3.4
5 − 1.393
= 18.04 mA
0.2
ID = 18.04 − 9.287 = 8.753 mA
= −6.8 mV
Iteration #3:
With RL = 500 ,
IL
8.753
= 0.697
VD = 0.7 + 0.025 ln
10
1.5
= 3 mA
0.5
VO = 1.393 V
IL = 2.0 mA
IL = 9.287
ID = −2.0 mA
I = 18.04 mA
VO = −2 × 2 × 3.4
ID = 8.753
= −13.6 mV
No further iterations are necessary and
VO = 1.39 V
3.55
5 V
(b) With no load:
Iteration #1:
I
R 200 VD = 0.7 V
VO = 1.4 V
D1
ID
D2
IL
RL 150 VO
I=
5 − 1.4
= 18 mA
0.2
ID = I = 18 mA
Iteration #2:
18
VD = 0.7 + 0.025 ln
= 0.715 V
10
(a) Iteration #1:
VO = 1.429 V
VD = 0.7 V
I = 17.85 mA
VO = 2VD = 1.4 V
ID = 17.85 mA
Chapter 3–20
Iteration #3:
Iteration #3:
17.85
VD = 0.7 + 0.025 ln
= 0.714 V
10
17.18
VD = 0.7 + 0.025 ln
= 0.714 V
10
VO = 1.43 V
VO = 1.428 V
I = 17.86 mA
No further iterations are needed and
ID = 17.86 mA
VO = 1.43 V
No further iterations are warranted and
(e) From the above we see that as VSupply changes
from 5 V to 3.232 V (a change of −35.4%) the
output voltage changes from 1.39 V to 1.29 V (a
change of −7.19%).
VO = 1.43 V
(c) VO = 1.39 − 0.1 = 1.29 V
IL =
VD =
1.29
= 8.6 mA
0.15
1.29
= 0.645 V
2
As VSupply changes from 5 V to 6.786 V (a change
of +35.4%) the output voltage changes from 1.39
V to 1.43 V (a change of +2.88%).
Thus the worst-case situation occurs when VSupply
is reduced, and
ID = 10 × e(0.645−0.7)/0.025
= 1.11 mA
I = IL + ID = 8.6 + 1.11 = 9.71 mA
VSupply = VO + IR = 1.29 + 9.71 × 0.2
= 3.232 V
which is a reduction of 1.768 V or −35.4%.
(d) For VSupply = 5 + 1.786 = 6.786 V,
Iteration #1:
VD = 0.7 V
VO = 1.4 V
IL = 9.33 mA
6.768 − 1.4
I=
= 26.84
0.2
ID = I − IL = 26.84 − 9.33 = 17.51 mA
Iteration #2:
17.51
VD = 0.7 + 0.025 ln
= 0.714 V
10
Percentage change in VO per 1% change in
7.19
= 0.2%
VSupply =
35.4
3.56 VZ = VZ0 + IZT rz
(a) 10 = 9.6 + 0.05 × rz
⇒ rz = 8 For IZ = 2IZT = 100 mA,
VZ = 9.6 + 0.1 × 8 = 10.4 V
P = 10.4 × 0.1 = 1.04 W
(b) 9.1 = VZ0 + 0.01 × 30
⇒ VZ0 = 8.8 V
At IZ = 2IZT = 20 mA,
VZ = 8.8 + 0.02 × 30 = 9.4 V
P = 9.4 × 20 = 188 mW
(c) 6.8 = 6.6 + IZT × 2
VO = 1.428 V
⇒ IZT = 0.1 A
IL = 9.52 mA
At IZ = 2IZT = 0.2 A,
I = 26.70 mA
VZ = 6.6 + 0.2 × 2 = 7 V
ID = 17.18 mA
P = 7 × 0.2 = 1.4 W
Chapter 3–21
(d) 18 = 17.6 + 0.005 × rz
At knee,
⇒ rz = 80 IZK = 0.25 mA
At IZ = 2IZT = 0.01 A,
VZ = 17.6 + 0.01 × 80 = 18.4 V
P = 18.4 × 0.01 = 0.184 W = 184 mW
(e) 7.5 = VZ0 + 0.2 × 1.5
rz = 750 FIRST DESIGN: 9-V supply can easily supply
current
Let IZ = 20 mA, well above knee.
⇒ VZ0 = 7.2 V
∴ R=
At IZ = 2IZT = 0.4 A,
VZ = 7.2 + 0.4 × 1.5 = 7.8 V
9 − 6.8
= 110 20
Line regulation =
P = 7.8 × 0.4 = 3.12 W
=
3.57 VZ = VZ0 + IZT rZ
9.1 = VZ0 + 0.02 × 10
VO
rZ
=
VS
rZ + R
5
5 + 110
= 43.5
⇒ VZ0 = 8.9 V
mV
V
SECOND DESIGN: limited current from 9-V
supply
At IZ = 10 mA,
VZ = 8.9 + 0.01 × 10 = 9.0 V
At IZ = 50 mA,
VZ = 8.9 + 0.05 × 10 = 9.4 V
IZ = 0.25 mA
VZ = VZK
VZO − calculate VZ0 from
VZ = VZ0 + rZ IZT
3.58 (a) Three 6.8-V zeners provide 3 × 6.8 =
20.4 V with 3 ×10 = 30- resistance. Neglecting
R, we have
Load regulation = −30 mV/mA.
(b) For 5.1-V zeners we use 4 diodes to provide
20.4 V with 4 ×30 = 120- resistance.
Load regulation = −120 mV/mA
3.59
6.8 = VZ0 + 5 × 0.02
VZ0 = 6.7 V
∴R=
8 − 6.7
= 5.2 k
0.25
LINE REGULATION =
750
VO
=
VS
750 + 5200
mV
V
= 126
9V±1V
3.60
10 V
R
VO
I
R
IZ
VO VZ
IZ
IL
GIVEN PARAMETERS
VZ = 6.8V, rz = 5 (a)
IZ = 20 mA
RL
Chapter 3–22
11 V
I
=
R
VO VZ
(1.5
1.5 0.03
= 0.15
0.03) + 0.167
For VS = +1 V (10% high),
and VO = 7.65 V.
VO = +0.15 V
For VS = −1 V (10% low),
and VO = 7.35 V.
VO = −0.15 V
rZ
When the load is removed and VS = 11 V, we can
use the zener model to determine VO . Refer to
Fig. (b). To determine VZ0 , we use
VZ0
VZ = VZ0 + IZT rz
7.5 = VZ0 + 0.01 × 30
(b)
⇒ VZ0 = 7.2 V
From Fig. (b) we have
9 V
I=
11 − 7.2
= 19.3 mA
0.167 + 0.03
Thus
I
R
VO = VZ0 + Irz
VO VZ
0.5 mA
IL
RL
= 7.2 + 0.0193 × 30 = 7.78 V
To determine the smallest allowable value of RL
while VS = 9 V, refer to Fig. (c). Note that
IZ = 0.5 mA, thus
VZ = VZK
I=
(c)
To obtain VO = 7.5 V, we must arrange for
IZ = 10 mA (the current at which the zener is
specified).
VZ0 = 7.2 V
9 − 7.2
= 10.69 mA
0.167
IL = I − IZ = 10.69 − 0.5 = 10.19 mA
RL =
VO
7.2
=
= 707 IL
10.19
VO = 7.2 V
Now,
IL =
VO
7.5
=
= 5 mA
RL
1.5
3.61
VS 15 V
10%
Thus
I = IZ + IL = 10 + 5 = 15 mA
I
R
and
VO VZ
10 − VO
10 − 7.5
R=
=
= 167 I
15
When the supply undergoes a change VS , the
change in the output voltage, VO , can be
determined from
VO
(RL rz )
=
VS
(RL rz ) + R
IZ
IL
RL
Chapter 3–23
VZ = VZ0 + IZT rz
and RL is at its lowest value, to maintain
regulation, the zener current must be at least equal
to IZK , thus
9.1 = VZ0 + 0.009 × 40
⇒ VZ0 = 8.74 V
IZ = 0.5 mA
For IZ = 10 mA,
VZ = VZK
VZ = 8.74 + 0.01 × 40 = 9.14 V
IL =
I=
9.14
= 9.14 mA
1 k
8.74
13.5 − 8.74
= 15.87 mA
0.3
IL = I − IZ = 15.87 − 0.5 = 15.37 mA
I = IZ + IL = 10 + 9.14 = 19.14 mA
R=
VZ0
15 − 9.14
= 306 19.4
RL =
VZ
8.74
= 589 =
IL
15.37
Select R = 300 The lowest value of output voltage = 8.74 V
Denoting the resulting output voltage VO , we
obtain
Line regulation =
I=
IL =
15 − VO
0.3
(1)
VO
1
(2)
VO − VZ0
VO − 8.74
=
IZ =
rz
0.04
= 113 mV/V
Load regulation = −(rz
= −(40
(3)
Since I = IZ + IL , we can use (1)–(3) to obtain
VO :
VO − 8.74
15 − VO
=
+ VO
0.3
0.04
VS
rz
(rz
RL
RL ) + R
(0.04 1)
= ±1.5 ×
(0.04 1) + 0.3
= ±0.17 V
If IL is reduced by 50%, then
IL =
I=
IZ =
1 9.15
×
= 4.6 mA
2
1
15 − VO
0.3
Or using the results obtained in this problem:
For a reduction in IL of 4.6 mA,
thus
Load regulation = −
⇒ VO = 9.31 V
which is an increase of 0.16 V. When the supply
voltage is low,
VS = 13.5 V
VO = +0.16 V,
160
= −35 mV/mA
4.6
3.62 (a) VZT = VZ0 + rz IZT
10 = VZ0 + 7 (0.025)
⇒ VZ0 = 9.825 V
(b) The minimum zener current of 5 mA occurs
when IL = 20 mA and VS is at its minimum of
20(1 − 0.25) = 15 V. See the circuit below:
VS 15 V
R
VO − 8.74
0.04
15 − VO
VO − 8.74
=
+ 4.6
0.3
0.04
R)
300) = −35 mV/mA
⇒ VO = 9.15 V
VO =
170 mV
1.5 V
20 mA
VO
IZmin 5 mA
IZ
RL
Chapter 3–24
R≤
15 − VZ0
20 + 5
where we have used the minimum value of VS , the
maximum value of load current, and the minimum
required value of zener diode current, and we
assumed that at this current VZ VZ0 . Thus,
R≤
15 − 9.825 + 7
25
⇒ VZ = 10.32 V
25 − 10.32
= 70.9 mA
IZmax =
0.207
PZ = 10.32 × 70.9
= 732 mW
3.63
≤ 207 .
∴ use R = 207 (c) Line regulation =
7
mV
= 33
207 + 7
V
vS vO
R
±25% change in v S ≡ ± 5 V
VO changes by ±5 × 33 = ±0.165 mV
±0.165
× 100 = ±1.65%
10
corresponding to
(d) Load regulation = − (rZ
= −(7
Using the constant voltage drop model:
R)
ideal
207) = −6.77 VD
0.7 V
or –6.77 V/A
VO = −6.77 × 20 mA = −135.4 mV
R
1 k
vS 0.1354
× 100 = −1.35%
corresponding to −
10
(e) The maximum zener current occurs at no load
IL = 0 and the supply at its largest value of
1
20 + (20) = 25 V.
4
vO
(a) v O = v S + 0.7 V,
v O = 0,
For v S ≤ − 0.7 V
for v S ≥ −0.7 V
VZ = VZ0 + rZ IZ
vO
25 V
0.7 V
0
vS
207 slope 1
VZ
IL 0
(b)
10 V
vS
vO
t
0.7 V
25 − VZ
= 9.825 + 7 ×
207
207VZ = 207 (9.825) + 7 (25) − 7VZ
10 V
0.7 V
u
Chapter 3–25
3.65
(c) The diode conducts at an angle
0.7
θ = sin−1
= 4◦ and stops
10
0.7 V at π − θ = 176◦
vS R 1 k vO
Thus the conduction angle is π − 2θ
= 172◦ or 3 rad.
v O,avg =
=
−1
2π
π −θ
vS (V)
(10 sin φ − 0.7) d φ
θ
2.5
1.8
−1
[−10 cos φ − 0.7φ]πθ −θ
2π
= −2.85 V
0.7
0
(d) Peak current in diode is
10 − 0.7
= 9.3 mA
1
t1
T
4
t2 T
2
t
T
2.5
(e) PIV occurs when v S is at its the peak and
v O = 0.
PIV= 10 V
3.64
D
vD vS vO
R
iD = IS ev D /V T
= 0.324 V
iD
= e[v D −v D (at 1 mA)]/V T
iD (1 mA)
iD
v D − v D (at 1 mA) = VT ln
1 mA
v D = v D (at 1 mA) + VT ln
v O /R
1
vO = vS − vD
= v S − v D (at 1 mA) − VT ln
where R is in k.
First find t1 and t2
0.7
2.5
=
T
t1
4
⇒ t1 = 0.07 T
T
t2 = − t1
2
T
= − 0.07 T
2
t2 = 0.43 T
1
v O (ave.) = × area of shaded triangle
T
T
1
− t1
= × (2.5 − 0.7) ×
T
4
1
1
− 0.07
= × 1.8 × T
4
T
v 3.66
ideal 0.7 V
12 : 1
vS
10 Vrms
O
R
120 Vrms
60 Hz
1 k vO
Chapter 3–26
√
vˆO = 10 2 − 0.7 = 13.44 V
fraction of a cycle for which one of the two
2(3.04)
diodes conduct =
× 100 = 96.8%
2π
Conduction begins at
√
10 2 sin θ = 0.7
0.7
−1
= 2.84◦
θ = sin
√
10 2
Note that during 96.8% of the cycle there will be
conduction. However, each of the two diodes
conducts for only half the time, i.e., for 48.4% of
the cycle.
= 0.0495 rad
v O,avg
Conduction ends at π − θ .
1
=
π
∴ Conduction angle = π − 2θ = 3.04 rad
= 8.3 V
The diode conducts for
iL,avg =
3.04
× 100 = 48.4% of the cycle
2π
v O,avg
1
=
2π
π −θ
√
(10 2sinφ − 0.7) d φ
θ
θ
8.3
= 8.3 mA
1 k
3.68
12 : 1
D4
= 4.15 V
iD,avg
π−θ √
(10 2sinφ − 0.7)d φ
10 Vrms
vs
120 Vrms
v O,avg
=
= 4.15 mA
R
D1
R
1 k
D3
D2
VD 0.7 V
3.67
√
Peak voltage across R = 10 2 − 2VD
√
= 10 2 − 1.4
= 12.74 V
vS
10 2 V
1.4 V
t
θ = sin−1
1.4
√ = 5.68◦ = 0.1 rad
10 2
Fraction of cycle that D1 & D2 conduct is
π − 2θ
× 100 = 46.8%
2π
√
vˆO = 10 2 − VD = 13.44 V
Conduction starts at θ = sin−1
0.7
√ =
10 2
2.84◦ = 0.05 rad
and ends at π − θ . Conduction angle =
π − 2θ = 3.04 rad in each half cycle. Thus the
Note that D3 & D4 conduct in the other half cycle
so that there is 2 (46.8) = 93.6% conduction
interval.
v O,avg =
2
2π
π−θ
θ
√
(10 2sinφ − 2VD ) d φ
Chapter 3–27
√
π −θ
1
−12 2 cos φ − 1.4φ
θ
π
√
2(12 2 cos θ ) 1.4 (π − 2θ )
−
=
π
π
=
(b) For VO,avg = 100 V
= 7.65 V
2
· Vs − 1.4
π
π ⇒ Vs = 101.4
= 159 V
2
√
120 2
= 1.07 to 1
Turns ratio =
159
iR,avg =
100 V =
v O,avg
7.65
=
= 7.65 mA
R
1
3.69
vS
vS
120 Vrms
R
vO
3.71 The circuit is a full-wave rectifier with
center tapped secondary winding. The circuit can
−
be analyzed by looking at v +
O and v O separately.
vS
vS
D1
D3
Refer to Fig. 3.24.
For VD Vs , conduction angle
v O,avg =
π, and
vO
vS
vS
2
2
Vs − VD = Vs − 0.7
π
π
(a) For v O,avg = 10 V
π
× 10.7 = 16.8 V
2
√
120 2
= 10.1 to 1
Turns ratio =
16.8
D4
R
D2
Vs =
(b) For v O,avg = 100 V
π
× 100.7 = 158.2 V
2
√
120 2
= 1.072 to 1
Turns ratio =
158.2
Vs =
3.70 Refer to Fig. 3.25
For 2VD Vs
VO,avg =
2
2
Vs − 2VD = Vs − 1.4
π
π
(a) For VO,avg = 10 V
2
10 V = · Vs − 1.4
π
π ∴ V̂s = 11.4
= 17.9 V
2
√
120 2
= 9.5 to 1
Turns ratio =
17.9
v O, avg =
=
1
2π
(VS sinφ − 0.7) d φ = 12
2Vs
− 0.7 = 12
π
where we have assumed Vs
0.7 V and thus the
conduction angle (in each half cycle) is almost π.
Vs =
12 + 0.7
π = 19.95 V
2
Thus voltage across secondary winding
= 2VS
40 V
Chapter 3–28
(b) (i) Using Eq (3.30), we have the conduction
angle =
Looking at D4 ,
PIV = VS − VO−
ωt ∼
=
= VS + (VS − 0.7)
= 2VS − 0.7
=
= 39.2 V
=
If choosing a diode, allow a safety margin by
moving a factor of 1.5, thus
PIV
2Vr / Vp − VD
2 × 0.1 Vp − 0.7
Vp − 0.7
√
0.2
= 0.447 rad
60 V
∴ Fraction of cycle for
conduction =
3.72
R
12 : 1
120 Vrms
10 Vrms VS
R
1 k
C vO
0.447
× 100
2π
= 7.1%
2 × 0.01
(ii) ωt
Fraction of cycle =
Vp
Vr
VpVD
(i) Vr ∼
= Vp − VD
T
CR
0.1 Vp − VD = Vp − VD
C=
[Eq. (3.28)]
T
CR
1
= 166.7 μF
0.1 × 60 × 103
Vr = 0.01 Vp − VD
Vp − VD T
=
CR
C = 1667 μF
1
(a) (i) v O, avg = Vp − VD − VΓ
2
√
1 √
10 2 − 0.7 0.1
= 10 2 − 0.7 −
2
√
0.1
= 10 2 − 0.7 1 −
2
(ii) v O, avg
= 13.37 V
0.141
× 100 = 2.24%
2π
(c) (i) Use Eq (3.31):
⎛
⎞
2 Vp − VD
⎠
iD,avg = IL ⎝1 + π
Vr
2 Vp − VD
v O,avg
1+π
=
R
0.1 Vp − VD
=
12.77
2
1
+
π
0.1
103
= 192 mA
(ii) For
= 12.77 V
Vp − 0.7
= 0.141 rad
Vp − 0.7
√
0.01
= 10 2 − 0.7 1 −
2
(ii) iD,avg =
√
13.37 1 + π 200
3
10
= 607 mA
(d) Adapting ⎛
Eq. (3.32),
we obtain ⎞
2 Vp − VD
⎠
(i) iD,peak = IL ⎝1 + 2π
Vr
2
12.77
=
1 + 2π
0.1
103
= 371 mA
(ii) iD,peak
13.37
2
1 + 2π
=
0.01
103
= 1201 mA
1.2 A
Chapter 3–29
Vp − VD
2fCR
3.73 (i) Vr = 0.1 Vp − VD =
The factor of 2 accounts for discharge occurring
1
.
only during half of the period, T /2 =
2f
C=
1
1
= 83.3 μF
=
(2fR) 0.1
2 (60) 103 × 0.1
(ii) C =
1
= 833 μF
2 (60) × 103 × 0.01
1
(a) (i) VO = Vp − VD − Vr
2
0.1
= Vp − VD 1 −
2
0.1
= (13.44) 1 −
2
= 12.77 V
0.01
(ii) VO = (13.44) 1 −
2
(b) (i) Fraction of cycle =
2Vr / Vp − VD
=
π
= 13.37 V
2ωt
× 100
2π
× 100
1
2 (0.1) × 100 = 14.2%
π
√
2 2 (0.01)
(ii) Fraction of cycle =
× 100
2π
= 4.5%
=
(c) Use Eq. (3.34):
(i) iD, avg = IL 1 + π
=
12.77
1+π
1
(ii) iD, avg
= 310 mA
1
= 833 μF
2 (0.01) fR
1
(a) VO = Vp − 2VD − Vr
2
1
Vp − 2VD × 0.1
(i) VO = Vp − 2VD −
2
= Vp − 2VD × 0.95
√
= (10 2 − 2 × 0.7) × 0.95 = 12.1 V
√
(ii) VO = (10 2 − 2 × 0.7) × 0.995 = 12.68 V
2ωt
× 100
(b) (i) Fraction of cycle =
2π
√
2 (0.1)
=
× 100 = 14.2%
π
√
2 (0.01)
(ii) Fraction of cycle =
× 100 = 4.5%
π
12.1
1
1+π
= 97 mA
(c) (i) iD, avg =
1
0.2
√
12.68 1 + π/ 0.02 = 249 mA
(ii) iD, avg =
1
12.1
1
1 + 2π
= 182 mA
(d) (i) îD =
1
0.2
12.68
1
1 + 2π
= 576 mA
(ii) îD =
1
0.02
3.75
0.7 V
Vp − VD
2Vr
1
= 102.5 mA
2 (0.1)
1
13.37
1+π√
=
1
2 (0.01)
(d) Use Eq. (3.35):
1
(i) îD = IL 1 + 2π √
= 192 mA
2 (0.1)
1
= 607 mA
(ii) îD = IL 1 + 2π √
0.02
3.74 (i) Vr = 0.1 Vp − VD × 2 =
C=
(ii) C =
Vp − 2VD
2fCR
Vp − 2VD
1
= 83.3 μF
Vp − 2VD 2 (0.1) fR
120 Vrms
60 Hz
vS
R
200 VO = 12 V ± 1 V (ripple)
RL = 200 (a) VO = Vp − VD − 1
⇒ Vp = 13 + 0.7 = 13.7 V
13.7
Vrms = √ = 9.7 V
2
Vp − VD
(b) Vr =
fCR
2=
13.7 − 0.7
60 × C × 200
⇒C=
13
= 542 μF
2 × 60 × 200
C vO
Chapter 3–30
This voltage appears across each half of the
transformer secondary. Across the entire
secondary we have 2 × 9.7 = 19.4 V (rms).
Vp
VpVD
t
Vp
PIV
(c) When the diode is cut off, the maximum
reverse voltage across it will occur when
v S = −Vp . At this time, v O = VO and the
maximum reverse voltage will be
PIV
Maximum reverse voltage = VO + Vp
= 12 + 13.7 = 25.7 V
(b) Vr =
Using a factor of safety of 1.5 we obtain
2=
PIV = 1.5 × 25.7
= 38.5 V
(d) iDav = IL 1 + π
2(Vp − VD )
Vr
In specifying the PIV for the diodes, one usually
uses a factor of safety of about 1.5,
2(Vp − VD )
(e) iDmax = IL 1 + 2π
Vr
2(13.7 − 0.7)
12
1 + 2π
=
0.2
2
PIV = 1.5 × 25.7 = 38.5 V
Vp − VD
(d) iDav = IL 1 + π
2 Vr
13.7 − 0.7
12
1+π
=
0.2
2×2
= 399 mA
= 1.42 A
D1
120 Vrms
60 Hz
C
R
D2
(a) VO = Vp − VD − 1
⇒ Vp = VO + VD + 1 = 13 + 0.7 = 13.7 V
Vrms
13.7
= √ = 9.7 V
2
Vp − VD
(e) iDmax = IL 1 + 2π
2 Vr
13.7 − 0.7
12
1 + 2π
=
0.2
2×2
3.76
Vs 0.7 V
Vs 0.7 V
12
= 271 μF
2 × 2 × 60 × 200
(c) Maximum reverse voltage across D1 occurs
when v S = −Vp . At this point v O = VO . Thus
maximum reverse voltage = VO + Vp =
12 + 13.7 = 25.7. The same applies to D2 .
2(Vp − VD )
VO
1+π
=
RL
Vr
2(13.7 − 0.7)
12
1+π
=
0.2
2
= 739 mA
13.7 − 0.7
2 × 60 × 200 × C
⇒C=
Vp − VD
2fCR
vO
= 739 mA
3.77
120 Vrms
60 Hz
D4
D1
C
R
vS
vO D2
D3
Chapter 3–31
12 V
11.3
11.3 Vr
10.2 V
(a) VO = Vp − 2VD − 1
⇒ Vp = VO +2VD +1 = 12+2×0.7+1 = 14.4 V
14.4
Vrms = √ = 10.2 V
2
Vp − 2 VD
(b) Vr =
2fCR
}
T
0
14.4 − 1.4
= 271 μF
2 × 2 × 60 × 200
(c) The maximum reverse voltage across D1
occurs when Vs = −Vp = −14.4 V. At this time
D3 is conducting, thus
⇒C=
Vr 1.13 V
4
t
(c)
During the diode’s off interval (which is almost
equal to T ) the capacitor discharges and its
voltage is given by
Maximum reverse voltage = −Vp + VD3
= −14.4 + 0.7 = −13.7 V
v O (t) = 11.3 e−t/CR
The same applies to the other three diodes. In
specifying the PIV rating for the diode we use a
factor of safety of 1.5 to obtain
where C = 100 μF and R = 100 , thus
PIV = 1.5 × 13.7 = 20.5 V
Vp − 2 VD
(d) iDav = IL 1 + π
2 Vr
14.4 − 1.4
12
1+π
=
0.2
2×2
At the end of the discharge interval, t
= 400 mA
Vp − 2 VD
2 Vr
14.4 − 0.7
12
1 + 2π
=
0.2
2×2
CR = 100 × 10−6 × 100 = 0.01 s
T and
v O = 11.3 e−T /CR
Since T = 0.001 s is much smaller than CR,
T
v O 11.3 1 −
CR
The ripple voltage Vr can be found as
T
Vr = 11.3 − 11.3 1 −
CR
(e) iDmax = IL 1 + 2π
11.3 × 0.001
11.3T
=
= 1.13 V
CR
0.01
The average dc output voltage is
=
= 740 mA
1.13
Vr
= 11.3 −
= 10.74 V
2
2
To obtain the interval during which the diode
conducts, t, refer to Fig. (c).
v O = 11.3 −
3.78
vI
C
100
F
R
100 vO
Vr
12
=
T /4
t
⇒
(a)
1.13 × 1
Vr × (T /4)
=
12
12 × 4
= 23.5 μs
vI
12 V
11.3 V
t=
Vr
vO
Now, using the fact that the charge gained by the
capacitor when the diode is conducting is equal to
the charge lost by the capacitor during its
discharge interval, we can write
vI
iCav ×
t
t = C Vr
⇒ iCav =
C Vr
100 × 10−6 × 1.13
= 4.8 A
=
t
23.5 × 10−6
iDav = iCav + iLav
T
(b)
1 ms
12 V
where iLav is the average current through R during
the short interval t. This is approximately
11.3
11.3
=
= 0.113 A. Thus
R
100
Chapter 3–32
iDav = 4.8 + 0.113 = 4.913 A
Finally, to obtain the peak diode current, we use
iDmax = iCmax + iLmax
dv I
11.3
=C
+
dt
R
11.3
12
+
=C×
T /4
R
= 100 × 10−6 ×
12 × 4
11.3
+
−3
1 × 10
100
= 4.8 + 0.113 = 4.913 A
which is equal to the average value. This is a
result of the linear v I which gives rise to a
constant capacitor current during the diode
conduction interval. Thus iCmax = iCav = 4.8 A.
Also, the maximum value of iL is approximately
equal to its average value during the short
interval t.
3.79 Refer to Fig. P3.71 and let a capacitor C be
connected across each of the load resistors R. The
−
two supplies v +
O and v O are identical. Each is a
full-wave rectifier similar to that of the
tapped-transformer circuit. For each supply,
VO = 12 V
Vr = 1 V (peak to peak)
Thus
v O = 12 ± 0.5 V
It follows that the peak value of v S must be
12.5 + 0.7 = 13.2 V and the total rms voltage
across the secondary will be
=
2 × 13.2
= 18.7 V (rms)
√
2
120
= 6.43:1
18.7
To deliver 100-mA dc current to each load,
Transformer turns ratio =
12
= 120 0.1
Now, the value of C can be found from
R=
Vr =
1=
Vp − 0.7
2fCR
12.5
2 × 60 × C × 120
iDmax = IL (1 + 2π (Vp − 0.7)/2 Vr )
= 0.1(1 + 2π 12.5/2 )
= 1.671 A
To determine the required PIV rating of each
diode, we determine the maximum reverse
voltage that appears across one of the diodes, say
D1 . This occurs when v S is at its maximum
negative value −Vp . Since the cathode of D1 will
be at +12.5 V, the maximum reverse voltage
across D1 will be 12.5 + 13.2 = 25.7 V. Using a
factor of safety of 1.5, then each of the four
diodes must have
PIV = 1.5 × 25.7 = 38.6 V
3.80 Refer to Fig. P3.80. When v I is positive, v A
goes positive, turning on the diode and closing the
negative feedback loop around the op amp. The
result is that v − = v I , v O = 2v − = 2v I , and
v A = v O + 0.7. Thus
(a) v I = +1 V, v − = +1 V, v O = +2 V, and
v A = +2.7 V.
(b) v I = +3 V, v − = +3 V, v O = +6 V, and
v A = +6.7 V.
When v I goes negative, v A follows, the diode
turns off, and the feedback loop is opened. The op
amp saturates with v A = −13 V, v − = 0 V and
v O = 0 V. Thus
(c) v I = −1 V, v − = 0 V, v O = 0 V, and
v A = −13 V.
(d) v I = −3 V, v − = 0 V, v O = 0 V, and
v A = −13 V.
Finally, if v I is a symmetrical square wave of
1-kHz frequency, 5-V amplitude, and zero
average, the output will be zero during the
negative half cycles of the input and will equal
twice the input during the positive half cycles.
See figure.
vO
10 V
5 V
⇒ C = 868 μF
To specify the diodes, we determine iDav and iDmax ,
iDav = IL (1 + π (Vp − 0.7)/2 Vr )
= 0.1(1 + π 12.5/2 )
= 785 mA
0
vI
5 V
1 ms
t
Chapter 3–33
Thus, v O is a square wave with 0-V and +10-V
levels, i.e. 5-V average and, of course, the same
frequency (1 kHz) as the input.
3.81 v I > 0: D1 conducts and D2 cutoff
(b) See figure (b) on next page. Here v O = v I for
v I ≥ 2.5 V. At v I = 2.5 V, v O = 2.5 V and the
diode begins to conduct. The diode will be
conducting 1 mA and exhibiting a drop of 0.7 at
v O = 2.3 V. The corresponding value of v I
v I = v O − iR = 2.3 − 1 × 1 = +1.3 V
v I < 0: D1 cutoff,
vO
= −1
D2 conducts ∼
vI
As v I decreases below 1.3 V, the diode current
increases, but the diode voltage remains constant
at 0.7 V. Thus v O flattens at about 2.3 V.
vO
(a) v I = +1 V
(c) See figure (c) on next page. For v I ≤ −2.5 V,
the diode is off, and v O = v I . At v I = −2.5 V the
diode begins to conduct and its current reaches 1
mA at v I = −1.3 V (corresponding to v O = −2.3
V). As v I further increases, the diode current
increases but its voltage remains constant at 0.7 V.
Thus v O flattens, as shown.
vO = 0 V
(d) See figure (d) on next page.
slope 1
vI
v A = −0.7 V
Keeps D2 off so no current flows through R
3.83
3 V
⇒ v− = 0 V
Virtual ground as feedback loop is closed
through D1
(b) v I = +3 V
D1
vO = 0 V
v A = −0.7 V
v− = 0 V
R = 0.5 k
vI
vo
i
(c) v I = −1 V
D2
v O = +1 V
v A = 1.7 V
v− = 0 V
3 V
∼ Virtual ground as negative feedback loop is
closed through D2 and R.
(d) v I = −3 V ⇒ v O = +3 V
v A = +3.7 V
v− = 0 V
3.82 (a) See figure (a) on next page. For
v I ≤ 3.5 V, i = 0 and v O = v I . At v I = 3.5 V, the
diode begins to conduct. At v O = 3.7 V, the diode
is conducting i = 1 mA and thus
v I = v O + i × 1 k = 4.7 V
For v I > 4.7 V the diode current increases but the
diode voltage remains constant at 0.7 V, thus v O
flattens and v O vs. v I becomes a horizontal line.
In practice, the diode voltage increases slowly
and the line will have a small nonzero slope.
(a)
From Fig. (a) we see that for
−3.5 V ≤ v I ≤ +3.5 V, diodes D1 and D2 will be
cut off and i = 0. Thus, v O = v I . For v I ≥ +3.5
V, diode D1 begins to conduct and its voltage
reaches 0.7 V (and thus v O = +3.7 V) at
i = 1 mA. The corresponding value of v I is
v I = v O − iR
v I = 3.7 + 1 × 0.5 = +4.2 V
For v I ≥ 4.2 V, the voltage of diode D1 remains
0.7 V and v O saturates at +3.7 V.
A similar description applies for v I ≤ −3.5 V.
Here D2 conducts at v I = −3.5 V and its voltage
becomes 0.7 V, and hence v O = −3.7 V,
at i = 1 mA (in the direction into v I )
at v I = −4.2 V. For v I ≤ −4.2 V, v O = −3.7 V.
Chapter 3–34
These figures belong to Problem 3.82.
vO (V)
3.7
3.5
3 V
D
i
vI (V)
vO
vI
R 1 k
slope 1
3.5
4.7
(a)
vO (V)
3 V
slope 1
2.5
2.3
D
i
vO
vI
R 1 k
1.3
vI (V)
2.5
(b)
vO (V)
2.5
vI
R 1 k
1.3
vI (V)
vO
i
2.3
D
2.5
3 V
slope 1
(c)
vO (V)
vI
R 1 k
i
vO
4.7
3.5
vI (V)
D
slope 1
3.5
3 V
3.7
(d)
Chapter 3–35
This figure belongs to Problem 3.83, part b.
vO (V)
3.7
3.5
4.2
3.5
3.5
0
4.2
vI (V)
slope 1
(Not to scale)
3.5
3.7
D1 and D2 OFF
D1 OFF
D2 ON
D1 ON
D2 OFF
(b)
Figure (b) shows a sketch of the transfer
characteristic of this double limiter.
3.85
3.84 See figure.
3 V
vI
D1
D1
Z
vO
R 0.5 k
vO
D4
D2
vI
1 k
(a)
D2
D3
vO (V)
3.7
3.5
slope 1
(a)
2.5
2.3
(Not to scale)
1.8 2.5
D1 ON
D2 OFF
3.5 4.2
D1 &
D2 OFF
(b)
D1 OFF
D2 ON
vI (V)
The limiter thresholds and the output saturation
levels are found as 2 × 0.7 + 6.8 = 8.2 V. The
transfer characteristic is given in Fig. (b). See
figure on next page.
Chapter 3–36
This figure belong to Problem 3.85, part b.
Z
All diodes and zener are OFF
Z
3.86
3.87
(a)
10 k
vI
vO
1 k
vI
vO
D1
D2
(b)
10 k
Diodes have 0.7 V drop at 1 mA current
vO
vI
∴ For diode D1
iD
= e(v O −0.7)/VT
1 mA
iD = 1 × 10−3 e(v O −0.7)/VT
(c)
v O = 0.7 + VT ln
10 k
vI
vO
iD
1 mA
v I = v O + iD × 1 k
v I for the different values of v O . For D2 ,
v I = v O − iD × 1 k
Chapter 3–37
3.89
From the figure we see that
√
v Oav = −5 2 = −7.07 V
3.90
vO (V)
0.8
(a)
to 55.4
10 V
10 V
2
1
1
vI (V)
2
(b)
20 V
0V
0.8
(c)
0V
It is a soft limiter with a gain K
L+ 0.7 V, L− −0.7 V
1 and
20 V
(d)
0V
3.88
20 V
R
(e)
1.5 V
vO
1 k
vI
1.5 V
10 V
10 V
(f) Here there are two different time constants
involved. To calculate the output levels, we shall
consider the discharge and charge wave forms.
In the nonlimiting region
1000
vO
=
≥ 0.94
vI
1000 + R
R ≤ 63.8 During T1 ,
v O = V1 e−t/RC
At = T1 = T , v O = V1
= V1 e−T /RC
Chapter 3–38
V1
0
From (1) and (2) we find that
V1́
V2
T1
V1 = 2|V2 |
t
V2́
Then using (1) and neglecting αV1 yields
T2
3 |V2 | = 20 ⇒ |V2 | = 6.67 V
V1 = 13.33 V
where for T CR
V1 (1 − T /CR) = V1 (1 − α)
V1
The result is
where α 1
13.33 V
During the interval T2 , we have
6.67 V
|v O | = |V2 | e−t/(CR/2)
At the end of T2 , t = T , and v O = |V2 |
(g)
where
18 V
|V2 | = |V2 | e−T /(CR/2)
T
|V2 | 1 −
= |V2 | (1 − 2α)
RC/2
2 V
Now
V1 + |V2 | = 20 ⇒ V1 + |V2 | − αV 1 = 20
(1)
and
V2 + V1 = 20 ⇒ V1 + |V2 | − 2α |V2 | = 20 (2)
(h) Using a method similar to that employed for
case (f) above, we obtain
13.33 V
6.67 V
Exercise 4–1
IS
10−16
=
= 10−18 A
β
100
IC
1 mA
= VT ln
= 25 ln
IS
10−16
Ex: 4.1 iC = IS ev BE /VT
iC2
v BE2 − v BE1 = VT ln
iC1
0.1
v BE2 = 700 + 25 ln
1
= 25 × 29.9336
= 642 mV
= 748 mV
v BE3
10
= 700 + 25 ln
1
ISB =
VBE
Ex: 4.6
= 758 mV
VCC 5 V
Ex: 4.2 ∴ α =
β
β +1
10 A
150
50
<α<
50 + 1
150 + 1
RC
C
B
0.980 < α < 0.993
bIB
Ex: 4.3 IC = IE − IB
= 1.460 mA − 0.01446 mA
= 1.446 mA
1.446
IC
= 0.99
=
α=
IE
1.460
E
v BE = 690 mV
1.446
IC
= 100
=
β=
IB
0.01446
IC = 1 mA
For active range VC ≥ VB ,
IC = IS ev BE /VT
IS =
IC
=
RCmax =
1.446
e700/25
ev BE /VT
1.446
= 28 mA = 10−15 A
e
Ex: 4.4 β =
α
1−α
For α = 0.99, β =
IB =
IB =
5 − 0.69
1
= 4.31 k
=
and
IC = 10 mA
0.99
= 99
1 − 0.99
IC
10
=
= 0.1 mA
β
99
For α = 0.98, β =
VCC − 0.690
IC
0.98
= 49
1 − 0.98
IC
10
=
= 0.2 mA
β
49
Ex: 4.5 Given:
IS = 10−16 A, β = 100, I C = 1 mA
Ex: 4.7 IS = 10−15 A
AreaC = 100 × AreaE
ISC = 100 × IS = 10−13 A
Ex: 4.8 iC = IS ev BE /VT − ISC ev BC /VT
for iC = 0
IS ev BE /VT = ISC ev BC /VT
ISC
ev BE /VT
= v /V
IS
e BC T
= e(v BE −v BC )/VT
ISC
IS
We write
∴ VCE = VBE − VBC = VT ln
= 10−16 × 1.01 = 1.01 × 10−16 A
For collector Area = 100 × Emitter area
100
= 115 mV
VCE = 25 ln
1
1
ISE = ISC /α = IS = 1 +
β
Exercise 4–2
Ex: 4.9 IC = IS ev BE /VT − ISC ev BC /VT
Ex: 4.12
1.5 V
IS
IB = ev BE /VT + ISC ev BC /VT
β
IC β forced = < β
IB sat
2 mA
VC 0.5 V
IS ev BE /VT − ISC ev BC /VT
= β v /V
IS e BE T + βI SC ev BC /VT
VBE
IS e(v BE −v BC )/VT − ISC
= β (v −v )/V
IS e BE BC T + βISC
=β
e
− ISC /IS
eVCE sat /VT + βISC /IS
Q.E.D.
e200/25 − 100
+ 100 × 100
RE
1.5 V
e200/25
= 100 × 0.2219 ≈ 22.2
RC =
Ex: 4.10
1.5 − VC
1.5 − 0.5
=
IC
2
= 0.5 k = 500 2 mA
E
IS /a
B
Since at IC = 1 mA, VBE = 0.8 V, then at
IC = 2 mA,
2
VBE = 0.8 + 0.025 ln
1
= 0.8 + 0.017
= 0.817 V
IS ev EB /VT
aiE
C
10 V
IS v BE /VT
e
α
51 −14 v BE /VT
2 mA =
10 e
50
2
50
14
×
10
VBE = 25 ln
×
51
103
IE =
VE = −VBE = −0.817 V
2
2 mA
=
= 2.02 mA
α
0.99
VE − (−1.5)
IE =
RE
IE =
Thus,
−0.817 + 1.5
= 0.338 k
2.02
= 338 RE =
Ex: 4.13
10 V
= 650 mV
β
50
IE =
×2
IC =
β +1
51
= 1.96 mA
IC
1.96
=
⇒ 39.2 μA
IB =
β
50
Ex: 4.11 IC = IS ev BE /VT = 1.5 A
∴ VBE = VT ln 1.5/10−11
IC
5 k
VC
IB
VE 0.7 V
10 k
IE
= 25 × 25.734
= 643 mV
VE VBE
2
IE ( a ) mA
VCE sat /VT
β forced = 100
RC
10 V
Exercise 4–3
IE =
−0.7 + 10
VE − (−10)
=
10
10
and
VC = −10 + 1.65 × 5 = −1.75 V
= 0.93 mA
Since VC < VB , the transistor is indeed operating
in the active mode.
Assuming active-mode operation,
IB =
0.93
IE
=
= 0.0182 mA
β +1
50 + 1
Ex: 4.15
= 18.2 μA
IC = IE − IB = 0.93 − 0.0182 = 0.91 mA
2 mA
VC = 10 − IC × 5
VE
= 10 − 0.91 × 5 = 5.45 V
Since VC > VB , the transistor is operating in the
active mode, as assumed.
VC
RC 1 k
IC
Ex: 4.14
10 V
5 V
IE
5 k
VE
IB
The transistor is operating at a constant emitter
current. Thus, a change in temperature of +30◦ C
results in a change in VEB by
VEB = −2 mV × 30 = −60 mV
VB
IB
VC
100 k
IC
5 k
Thus,
VE = −60 mV
Since the collector current remains unchanged at
αIE , the collector voltage does not change:
10 V
VB = 1.0 V
Thus,
IB =
VB
= 0.01 mA
100 k
VE = +1.7 V
Thus,
IE =
10 − 1.7
10 − VE
=
= 1.66 mA
5 k
5
and
β +1=
1.66
IE
= 166
=
IB
0.01
⇒ β = 165
VC = 0 V
Ex: 4.16 Refer to Fig. 4.19(a):
v CE
iC = IS ev BE /VT +
ro
(1)
Now using Eqs. (4.21) and (4.22), we can express
ro as
ro =
VA
IS ev BE /VT
Substituting in Eq. (1), we have
v CE
iC = IS ev BE /VT 1 +
VA
which is Eq. (4.18).
Ex: 4.17 ro =
Q.E.D.
VA
100
=
IC
IC
165
β
=
= 0.994
α=
β +1
165 + 1
At IC = 0.1 mA, ro = 1 M
Assuming active-mode operation,
At IC = 1 mA, ro = 100 k
IC = αIE = 0.994 × 1.66 = 1.65 mA
At IC = 10 mA, ro = 10 k
Exercise 4–4
Ex: 4.18 IC =
VCE
ro
Ex: 4.20 For VBB = 0 V, IB = 0 and the transistor
is cut off. Thus,
where
VA
100
= 100 k
=
ro =
IC
1
IC = 0
11 − 1
= 0.1 mA
100
Thus, IC becomes 1.1 mA.
VC = VCC = +10 V
and
IC =
Ex: 4.21 Refer to the circuit in Fig. 4.22 and let
VBB = 1.7 V. The current IB can be found from
IB =
Ex: 4.19
VCC 10 V
VBB
IB
IC
RB 10 k
Assuming operation in the active mode,
IC = β IB = 50 × 0.1 = 5 mA
RC 10 k
VBE 0.7 V
VBB − VB
1.7 − 0.7
= 0.1 mA
=
RB
10
VCE
(a) For operation in the active mode with
VCE = 5 V,
Thus,
VC = VCC − RC IC
= 10 − 1 × 5 = 5 V
which is greater than VB , verifying that the
transistor is operating in the active mode, as
assumed.
(a) To obtain operation at the edge of saturation,
RC must be increased to the value that results in
VCE = 0.3 V:
IC =
VCC − VC
10 − 5
= 0.5 mA
=
RC
10
RC =
IB =
IC
0.5
=
= 0.01 mA
β
50
=
VBB = VBE + IB RB
VCC − 0.3
IC
10 − 0.3
= 1.94 k
5
(b) For operation at the edge of saturation,
(b) Further increasing RC results in the transistor
operating in saturation. To obtain saturation-mode
operation with VCE = 0.2 V and βforced = 10,
we use
VCE = 0.3 V
IC = βforced × IB
VCC − VCE
10 − 0.3
=
= 0.97 mA
IC =
RC
10
= 10 × 0.1 = 1 mA
= 0.7 + 0.01 × 10 = 0.8 V
IB =
0.97
IC
=
= 0.0194 mA
β
50
VBB = VB + IB RB
= 0.7 + 0.0194 × 10 = 0.894 V
(c) For operation deep in saturation with
βforced = 10, we have
VCE 0.2 V
10 − 0.2
= 0.98 mA
10
IC
0.98
= 0.098 mA
=
IB =
βforced
10
IC =
VBB = VB + IB RB
= 0.7 + 0.098 × 10 = 1.68 V
The value of RC required can be found from
RC =
=
VCC − VCE
IC
10 − 0.2
= 9.8 k
1
Ex: 4.22 Refer to the circuit in Fig. 4.23(a) with
the base voltage raised from 4 V to VB . If at this
value of VB , the transistor is at the edge of
saturation then,
VC = VB − 0.4 V
Since IC IE , we can write
VE
VB − 0.7
10 − VC
=
=
RC
RE
RE
Exercise 4–5
10 − (VB − 0.5)
4.7
VB − 0.7
IE = 6IB =
3.3
Dividing Eq. (1) by Eq. (2), we have
Thus,
IC = 5IB =
VB − 0.7
10 − (VB − 0.4)
=
4.7
3.3
⇒ VB = +4.7 V
(1)
(2)
10.5 − VB
3.3
5
=
×
6
VB − 0.7
4.7
Ex: 4.23
⇒ VB = +5.18 V
10 V
0.5 mA
RC
VC 6 V
Ex: 4.25 Refer to the circuit in Fig. 4.26(a). The
largest value for RC while the BJT remains in the
active mode corresponds to
VC = +0.4 V
VB 4 V
VE 3.3 V
RE
0.5 mA
Since the emitter and collector currents remain
unchanged, then from Fig. 4.26(b) we obtain
IC = 4.6 mA
Thus,
RC =
To establish a reverse-bias voltage of 2 V across
the CBJ,
VC = +6 V
=
VC − (−10)
IC
+0.4 + 10
= 2.26 k
4.6
Ex: 4.26
From the figure we see that
10 V
10 − 6
= 8 k
RC =
0.5
and
3.3
= 6.6 k
RE =
0.5
where we have assumed α 1.
1 mA
RE
VE 0.7 V
VC 4 V
1 mA
Ex: 4.24
10 V
10 V
IC 5IB
4.7 k
VB 0.5
RC
For a 4-V reverse-biased voltage across the CBJ,
VC = −4 V
VB
Refer to the figure.
IB
VB 0.7
6IB
IC = 1 mA =
3.3 k
VC − (−10)
RC
−4 + 10
= 6 k
1
10 − VE
RE =
IE
⇒ RC =
The figure shows the circuit with the base voltage
at VB and the BJT operating in saturation with
VCE = 0.2 V and βforced = 5.
Assuming α = 1,
RE =
10 − 0.7
= 9.3 k
1
Exercise 4–6
Ex: 4.27 Refer to the circuit in Fig. 4.27:
IB =
Ex: 4.30
15 V
5 − 0.7
= 0.043 mA
100
To ensure that the transistor remains in the active
mode for β in the range 50 to 150, we need to
select RC so that for the highest collector current
possible, the BJT reaches the edge of saturation,
that is, VCE = 0.3 V. Thus,
2.78 mA
2 k
9.44 V
Q2
IC3
2.75 mA
Q3
VC2
VCE = 0.3 = 10 − RC ICmax
IC3 /b
where
VE3
2.7 k ICmax = βmax IB
470 IC3
a
= 150 × 0.043 = 6.45 mA
Thus,
RC =
10 − 0.3
= 1.5 k
6.45
From the figure we see that
IC3
× 0.47
α
For the lowest β,
VE3 =
IC = βmin IB
IC3
× 0.47 + 0.7
(1)
α
A node equation at the collector of Q2 yields
= 50 × 0.043 = 2.15 mA
and the corresponding VCE is
VCE = 10 − RC IC = 10 − 1.5 × 2.15
= 6.775 V
VC2 = VE3 + 0.7 =
2.75 =
IC3
VC2
+
2.7
β
Substituting for VC2 from Eq. (1), we obtain
2.75 =
Thus, VCE will range from 0.3 V to 6.8 V.
(0.47 IC3 /α) + 0.7 IC3
+
2.7
β
Substituting α = 0.99 and β = 100 and solving
for IC3 results in
Ex: 4.28 Refer to the solution of Example 4.10.
VBB − VBE
IE =
RE + [RBB /(β + 1)]
5 − 0.7
= 1.177 mA
=
3 + (33.3/51)
IC3 = 13.4 mA
Now, VE3 and VC2 can be determined:
IC3
13.4
× 0.47 =
× 0.47 = +6.36 V
α
0.99
= VE3 + 0.7 = +7.06 V
VE3 =
VC2
IC = αIE = 0.98 × 1.177 = 1.15 mA
Thus the current is reduced by
Ex: 4.31
5 V
IC = 1.28 − 1.15 = 0.13 mA
which is a −10% change.
Q1 off
Ex: 4.29 Refer to the circuit in Fig. 4.30(b). The
total current drawn from the power supply is
I = 0.103 + 1.252 + 2.78 = 4.135 mA
10 k
5 V
0
IE
IB
Q2 on IE
Thus, the power dissipated in the circuit is
P = 15 V × 4.135 mA = 62 mW
5 V
VE IE 1
1 k
Exercise 4–7
From the figure we see that Q1 will be off and Q2
will be on. Since the base of Q2 will be at a
voltage higher than −5 V, transistor Q2 will be
operating in the active mode. We can write a loop
equation for the loop containing the 10-k
resistor, the EBJ of Q2 and the 1-k resistor:
−IE × 1 − 0.7 − IB × 10 = −5
Substituting IB = IE /(β + 1) = IE /101 and
rearranging gives
IE =
5 − 0.7
= 3.9 mA
10
+1
101
Q1 will be saturated. Assuming this to be the case,
the analysis steps will be as follows:
VCEsat |Q1 = 0.2 V
VE = 5 V − VCEsat = +4.8 V
4.8 V
= 4.8 mA
1 k
= VE + VBE1 = 4.8 + 0.7 = +5.5 V
IE1 =
VB1
10 − 5.5
= 0.45 mA
10
= IE1 − IB1 = 4.8 − 0.45 = 4.35 mA
IB1 =
IC1
βforced =
Thus,
IC
4.35
=
= 9.7
IB
0.45
VE = −3.9 V
which is lower than βmin , verifying that Q1 is
indeed saturated.
VB2 = −4.6 V
Finally, since Q2 is off,
IC2 = 0
IB = 0.039 mA
Ex: 4.32 With the input at + 10 V, there is a
strong possibility that the conducting transistor
Ex: 4.33 VO = +10 − BVBCO = 10 − 70
= −60 V
This figure belongs to Exercise 4.32.
5 V
4 5.5 V
Q1 on VCEsat 0.2 V
10 k
4.8 V
10 V
5 10 5.5 0.45 mA
10
1
3
Q2 off
5 V
4.8
mA
1 k
2
Chapter 4–1
4.1
1.
2.
3.
4.
5.
6.
Active
Saturation
Active
Saturation
Active
Cutoff
β=
IC
= 80
IB
α=
80
β
=
= 0.988
β +1
81
4.7
α
4.2 The EB junctions have a 4:1 area ratio.
0.5 0.8 0.9 0.95 0.98 0.99 0.995 0.999
α
β=
1−α
1
4
1
2
9
19
49
99
199
999
IC = IS eVBE /VT
0.5 × 10−3 = IS1 × e0.75/0.025
⇒ IS1 = 4.7 × 10−17 A
4.8
β
10
20
50
100
200
500
1000
IS2 = 4IS1 = 1.87 × 10−16 A
β
α=
0.5 0.67 0.91 0.95 0.98 0.99 0.995 0.998 0.999
β +1
4.3 IC1 = 10−13 e700/25 = 0.145A = 145 mA
4.9 β =
−18 700/25
IC2 = 10
e
= 1.45 μA
For the first transistor 1 to conduct a current of
1.45 μA, its VBE must be
1.45 × 10−6
VBE1 = 0.025 ln
10−13
= 0.412 V
4.4
AE1
200 × 200
IS1
=
=
= 250,000
IS2
AE2
0.4 × 0.4
IC1 = IS1 eVBE1 /VT
IC2 = IS2 e
VBE2 /VT
For IC1 = IC2 we have
e(VBE2 −VBE1) /VT =
IS1
= 250,000
IS2
VBE2 − VBE1 = 0.025 ln(250,000)
= 0.31 V
10−3 = 2 × 10−15 eVBE /VT
10−3
VBE = 0.025 ln
= 0.673 V
2 × 10−15
New technology:
10−3 = 2 × 10−18 eVBE /VT
10−3
VBE = 0.025 ln
= 0.846 V
2 × 10−18
(1)
α → α + α
β → β + β
β + β =
α + α
1 − α − α
(2)
Subtracting Eq. (1) from Eq. (2) gives
β =
α
α + α
−
1 − α − α
1−α
β =
α
(1 − α − α)(1 − α)
(3)
Dividing Eq. (3) by Eq. (1) gives
α
1
β
=
β
α
1 − α − α
For α 1, the second factor on the right-hand
side is approximately equal to β. Thus
α
β
β
Q.E.D.
β
α
For
4.5 Old technology:
α
1−α
β
= −10% and β = 100,
β
−10%
α
= −0.1%
α
100
4.10 Transistor is operating in active region:
β = 50 → 300
IB = 10 μA
IC = βIB = 0.5 mA → 3 mA
IE = (β + 1)IB = 0.51 mA → 3.01 mA
Maximum power dissipated in transistor is
4.6 IB = 10 μA
IB × 0.7 V + IC × VC
IC = 800 μA
= 0.01 × 0.7 + 3 × 10 30 mW
Chapter 4–2
4.11 For iB = 10 μA,
4.14 First we determine IS , β, and α:
iC = iE − iB = 1000 − 10 = 990 μA
1 × 10−3 = IS e700/25
β=
⇒ IS = 6.91 × 10−16 A
iC
990
= 99
=
iB
10
β
99
α=
=
= 0.99
β +1
100
β=
IC
1 mA
= 100
=
IB
10 μA
For iB = 20 μA,
α=
β
100
=
= 0.99
β +1
101
iC = iE − iB = 1000 − 20 = 980 μA
Then we can determine ISE and ISB :
β=
iC
980
= 49
=
iB
20
ISE =
IS
= 6.98 × 10−16 A
α
α=
β
49
=
= 0.98
β +1
50
ISB =
IS
= 6.91 × 10−18 A
β
For iB = 50 μA,
The figure below and on next page shows the four
large-signal models, corresponding to Fig. 4.5(a)
to (d), together with their parameter values.
iC = iE − iB = 1000 − 50 = 950 μA
β=
iC
950
= 19
=
iB
50
α=
β
19
=
= 0.95
β +1
20
4.12 iC = IS ev BE /VT
= 5 × 10−15 e0.7/0.025 = 7.2 mA
7.2
7.2
iB will be in the range
mA to
mA, that is,
50
200
144 μA to 36 μA.
iE will be in the range (7.2 + 0.144) mA to
(7.2 + 0.036) mA, that is, 7.344 mA to 7.236 mA.
4.13 See table below.
This table belongs to Problem 4.13.
Transistor
a
b
c
d
e
VBE (mV)
700
690
580
780
820
IC (mA)
1.000
1.000
0.230
10.10
73.95
IB (μA)
10
20
5
120
1050
IE (mA)
1.010
1.020
0.235
10.22
75
α
0.99
0.98
0.979
0.988
0.986
β
100
46
84
70
IS (A)
50
−16
6.9 × 10
−15
1.0 × 10
−14
1.9 × 10
−16
2.8 × 10
4.2 × 10−16
Chapter 4–3
C
(b)
The figure shows the circuit, where
α=
iC
aiE
100
β
=
= 0.99
β +1
101
5 × 10−15
IS
=
= 5.05 × 100−15 A
α
0.99
The voltage at the emitter VE is
ISE =
iB
B
VE = −VDE
v BE
= −VT ln(IE /ISE )
2 × 10−3
= −0.025 ln
5.05 × 10−15
DE
ISE IS /a
iE
= −0.668 V
E
a 0.99
ISE 6.98 1016 A
The voltage at the collector VC is found from
VC = 5 − IC × 2
= 5 − αIE × 2
= 5 − 0.99 × 2 × 2 = 1.04 V
4.16 Refer to the circuit in Fig. 4.6(b).
ISB =
5 × 10−15
IS
=
= 10−16 A
β
50
0.5 × 10−3
IC
=
= 10−5 A
β
50
IB
VB = VBE = VT ln
ISB
−5 10
= 0.025 ln
10−16
IB =
(d)
B
iC
iB
C
vBE
DB
IS
ISB b
biB
= 0.633 V
We can determine RB from
iE
RB =
E
b 100
ISB 6.91 1018 A
15 − 0.633
= 1.44 M
10−5
To obtain VCE = 1 V, we select RC according to
=
4.15
5 V
RC =
2 k
VC
C
aiE
DE
E
=
VCC − VCE
IC
15 − 1
= 28 k
0.5
4.17 IS = 10−15 A
B
iE
VCC − VB
IB
VE
2 mA
Thus, a forward-biased EBJ conducting a current
of 1 mA will have a forward voltage drop VBE :
I
VBE = VT ln
IS
−3 10
= 0.025 ln
= 0.691 V
10−15
ISC = 100IS = 10−13 A
Chapter 4–4
Thus, a forward-biased CBJ conducting a 1-mA
current will have a forward voltage drop VBC :
VBC = VT ln
−3
1 × 10
1 × 10−13
4.19 The equations utilized are
v BC = v BE − v CE = 0.7 − v CE
iBC = ISC ev BC /VT = 10−13 ev BC /0.025
= 0.576 V
iBE = ISB ev BE /VT = 10−17 e0.7/0.025
When forward-biased with 0.5 V, the emitter–base
junction conducts
iB = iBC + iBE
I = IS e0.5/0.025
Performing these calculations for v CE = 0.4 V,
0.3 V, and 0.2 V, we obtain the results shown in
the table below.
= 10−15 e0.5/0.025 = 0.49 μA
iC = IS ev BE /VT − iBC = 10−15 e0.7/0.025 − iBC
and the CBJ conducts
4.20
I = ISC e0.5/0.025
= 10−13 e0.5/0.025 = 48.5 μA
4.18 Dividing Eq. (4.14) by Eq. (4.15) and
substituting iC /iB = βforced gives
βforced =
IS ev BE /VT − ISC ev BC /VT
(IS /β)ev BE /VT + ISC ev BC /VT
Dividing the numerator and denominator of the
right-hand side by ISC ev BC /VT and replacing
v BE − v BC by VCEsat gives
IS
eVCEsat /VT − 1
ISC
βforced = 1 IS
eVCEsat /VT + 1
β ISC
This equation can be used to obtain eVCEsat /VT and
hence VCEsat as
IS
1 + βforced
eVCEsat /VT =
ISC
1 − βforced /β
⇒ VCEsat = VT ln
ISC 1 + βforced
IS 1 − βforced /β
50
10
5
where
Q.E.D.
10−14
IS
=
= 2 × 10−16 A
β
50
10 × 10−6
= 0.025 ln
2 × 10−16
ISB =
For β = 100 and ISC /IS = 100, we can use this
equation to obtain VCEsat corresponding to the
given values of βforced . The results are as follows:
βforced
The emitter–base voltage VEB is found as the
voltage drop across the diode DB , whose scale
current is ISB = IS /β, it is conducting a 10-μA
current. Thus,
10 μA
VEB = VT ln
ISB
VEB
= 0.616 V
Thus,
VB = −VEB = −0.616 V
The collector current can be found as
1
IC = βIB
VCEsat (V) 0.231 0.178 0.161 0.133
= 50 × 10 = 500 μA = 0.5 mA
This table belongs to Problem 4.19.
v CE (V) v BC (V) iBC (μA) iBE (μA) iB (μA) iC (mA) iC /iB
0.4
0.3
0.016
14.46
14.48
1.446
100
0.3
0.4
0.89
14.46
15.35
1.445
94
0.2
0.5
14.46
62.96
1.398
29
48.5
Chapter 4–5
The collector voltage can now be obtained from
VC = −5 + IC × 8.2 = −5 + 0.5 × 8.2 = −0.9 V
4.22
IB =
5
IE
=
= 0.238 A = 238 mA
β +1
20 + 1
The emitter current can be found as
IC = IS eVEB /VT
IE = IB + IC = 10 + 500 = 510 μA
αIE = IS eVEB /VT
= 0.51 mA
where
20
= 0.95
α=
21
IS = αIE e−VEB /VT
4.21
= 0.95 × 5e−(0.8/0.025)
= 6 × 10−14 A
A transistor that conducts IC = 1 mA with
VEB = 0.70 V has a scale current
IS = 1 × 10−3 e−0.70/0.025 = 6.9 × 10−16 A
The emitter–base junction areas of these two
transistors will have the same ratio as that of their
scale currents, thus
6 × 10−14
EBJ area of first transistor
= 87
=
EBJ area of second transistor
6.9 × 10−16
Referring to the figure, we see that
IE = IB + IC =
IC
+ IC
β
4.23 The two missing large-signal equivalent
circuits for the pnp transistor are those
corresponding to the npn equivalent circuits in
Fig. 4.5(b) and 4.5(d). They are shown in the
figure.
Thus,
IC =
IE
1+
1
β
=
E
1
1+
1
10
= 0.909 mA
IB = 0.091 mA
For direction of flow, refer to the figure.
IB
VEB = VT ln
ISB
iB
iE
v EB
DE
(IS /a)
B
where
IS
10−15
=
= 10−16 A
β
10
0.091 × 10−3
= 0.025 ln
10−16
aiE
ISB =
VEB
= 0.688 V
Thus,
VE = VB + VEB = 0 + 0.688 = 0.688 V
If a transistor with β = 1000 is substituted,
IC =
IE
1
1+
β
=
1
1+
1
1000
= 0.999 mA
Thus, IC changes by 0.999 − 0.909 = 0.09 mA, a
9.9% increase.
iC
C
Chapter 4–6
V7 − 0.7 + 10
V7 + 9.3
=
(1)
3
3
Since IB = 0, the collector current will be equal to
the current through the 9.1-k resistor,
4.24
=
+10 − V7
9.1
Since α1 1, IC = IE = I6 resulting in
IC =
4.25 (a) Refer to Fig. P4.25(a).
10.7 − 0.7
= 2 mA
5 k
Assuming operation in the active mode,
I1 =
IC = αI1 I1 = 2 mA
(2)
V7 + 9.3
10 − V7
=
9.1
3
⇒ V7 = −4.5 V
and
I6 =
−4.5 + 9.3
V7 + 9.3
=
= 1.6 mA
3
3
4.26 (a)
V2 = −10.7 + IC × 5
= −10.7 + 2 × 5 = −0.7 V
Since V2 is lower than VB , which is 0 V, the
transistor is operating in the active mode, as
assumed.
(b) Refer to Fig. P4.25(b).
Since VC = −4 V is lower than VB = −2.7 V, the
transistor is operating in the active mode.
−4 − (−10)
= 2.5 mA
2.4 k
IC
IC = 2.5 mA
IE =
α
V3 = +12 − IE × 5.6 = 12 − 2.5 × 5.6 = −2 V
Since VC is lower than VB , the transistor is
operating in the active region. From the figure
corresponding to Fig. P4.26(a), we see that
(c) Refer to Fig. P4.25(c) and use
IB = 0.0215 mA
IC =
0 − (−10)
= 0.5 mA
IC =
20
Assuming active-mode operation, and utilizing
the fact that β is large, IB 0 and
V4 2 V
IC = 1 mA
Thus,
β≡
1
IC
= 46.5
=
IB
0.0215
(b)
Since VC < VB , the transistor is indeed operating
in the active region.
IC
IC = 0.5 mA
α
(d) Refer to Fig. P4.25(d). Since the collector is
connected to the base with a 10-k resistor and β
is assumed to be very high, the voltage drop
across the 10-k resistor will be close to zero and
the base voltage will be equal to that of the
collector:
I5 = IE =
VB = V7
This also implies active-mode operation. Now,
VE = VB − 0.7
Thus,
VE = V7 − 0.7
I6 =
VE − (−10)
3
Observe that with VC at 3 V and VB at 4.3 V, the
transistor is operating in the active region. Refer
to the analysis shown in the figure, which leads to
β≡
3.952
IC
=
= 82.3
IB
0.048
Chapter 4–7
VE = +0.68 V
(c)
and
2.5 − 0.68
= 3.64 k
0.5
The maximum allowable value for RC while the
transistor remains in the active mode corresponds
to VC = +0.4 V. Thus,
0.4 − (−2.5)
= 5.86 k
RCmax =
0.495
RE =
4.28
VCC
IE
RC
Observe that the transistor is operating in the
active region and note the analysis performed on
the circuit diagram. Thus,
VC
IB
IC = IE − IB = 3 − 0.04 = 2.96 mA
VB
and
IB
IC
2.96
β≡
= 74
=
IB
0.04
4.27
IC
IE
2.5 V
IE 0.5 mA
RE
VE
Since the meter resistance is small, VC VB and
the transistor is operating in the active region. To
obtain IE = 1 mA, we arrange that VBE = 0.7 V.
Since VC VB , VC must be set to 0.7 by selecting
RC according to
VC = 0.7 = VCC − IE RC
Thus,
VC 0.5 V
IC
RC
2.5 V
From the figure we see that VC = −0.5 V is lower
than the base voltage (VB = 0 V); thus the
transistor will be operating in the active mode.
β
100
IE =
× 0.5
IC = αIE =
β +1
100 + 1
= 0.495 mA
VC − (−2.5)
RC =
IC
−0.5 + 2.5
=
= 4.04 k 4 k
0.495
The transistor VEB can be found from
0.5 mA
VEB = 0.64 + VT ln
0.1 mA
0.7 = 9 − 1 × RC
⇒ RC = 8.3 k
Since the meter reads full scale when the current
flowing through it (in this case, IB is 50 μA), a
full-scale reading corresponds to
1 mA
IC
= 20
β≡
IB
50 μA
If the meter reads 1/5 of full scale, then
IB = 10 μA and
1 mA
β=
= 100
10 μA
A meter reading of 1/10 full scale indicates that
1 mA
= 200
β=
5 μA
= 0.68 V
4.29 Refer to Fig. 4.15(a) with RC = 5.1 k and
RE = 6.8 k. Assuming VBE 0.7 V, then
VE = −0.7 V, and
−0.7 − (−15)
= 2.1 mA
IE =
6.8
IC = αIE 2.1 mA
Thus,
VC = 15 − 2.1 × 5.1 4.3 V
Chapter 4–8
4.30
1.5 V
(a)
IC a 0.26 0.98 0.26
0.255 mA
4
2.7 k
VC 1.5 0.255 2.7 0.81 V 5
6 I I I 0.005 mA
B
E
C
0.8 V
1
a
VE 0.8 V 2
0.8 (1.5)
2.7
0.26 mA
1.5 V
2.7 k
3 IE 1.5 V
(b)
1.5 0.8
2
0.35 mA
3
6
IE IB IE IC
0.007 mA
IB
1
0.8 V
2 k
VE 0.8 V
2
VC 1.5 2 0.343
0.81 V
5
2 k
IC a 0.35
4
0.98 0.35
0.343
1.5 V
3 V
(c)
3 IE 3 1.8
0.12 mA
10
10 k
VE 1.8 V 2
1 V
6
1
0.8 V
IB IC/50 2.4 A
4 IC a 0.12
0.98 0.12
0.118 mA
VC 0.118 2 0.236 V 5
2 k
3 V
(d)
4
IC a 0.15 0.147 mA
8.2 k
VC 3 0.147 8.2 1.8 V 5
1.5 V
0.15
6 IB 50 3 A
IB
3
V
IE E
4.7
0.8 V
1
0.7 0.15 mA
4.7
a
VE 1.5 0.8 0.7 2
4.7 k
Chapter 4–9
In all circuits shown in Fig. P4.30, we assume
active-mode operation and verify that this is the
case at the end of the solution. The solutions are
indicated on the corresponding circuit diagrams;
the order of the steps is shown by the circled
numbers.
1 v BE /VT
IE = IS 1 +
e
β
(3)
When the base is left open-circuited, iB = 0 and
Eq. (1) yields
IS v BE /VT
e
ICBO =
β
4.31 Refer to the circuit in Fig. P4.31. Since
VC = 0.5 V is greater than VB , the transistor will
be operating in the active mode. The transistor
VBE can be found from
0.2 mA
VBE = 0.8 + 0.025 ln
1 mA
or equivalently,
= 0.76 V
4.34 Since the BJT is operating at a constant
emitter current, its |VBE | decreases by 2 mV for
every ◦ C rise in temperature. Thus,
Thus,
VE = −0.76 V
IC
β +1
101
= IC
= 0.2 ×
IE =
α
β
100
= 0.202 mA
Substituting for IS e
(4)
v BE /VT
in Eqs. (2) and (3) gives
iC = iE = (β + 1)ICBO
|VBE | at 0◦ C = 0.7 + 0.002 × 25 = 0.75 V
|VBE | at 100◦ C = 0.7 − 0.002 × 75 = 0.55 V
The required value of RE can be found from
4.35 (a) If the junction temperature rises to
50◦ C, which is an increase of 30◦ C, the EB
voltage decreases to
VE − (−1.5)
RE =
IE
v EB = 692 − 2 × 30 = 632 mV
−0.76 + 1.5
= 3.66 k
0.202
To establish VC = 0.5 V, we select RC
according to
RE =
RC =
IS ev BE /VT = βICBO
(b) First, we evaluate VT at 20◦ C and at 50◦ C:
VT =
1.5 − 0.5
= 5 k
0.2
kT
q
where k = 8.62 × 10−5 eV/K.
Thus,
4.32 ICBO approximately doubles for every 10◦ C
rise in temperature. A change in temperature from
25◦ C to 125◦ C—that is, an increase of
100◦ C—results in 10 doublings or, equivalently,
an increase by a factor of 210 = 1024. Thus ICBO
becomes
ICBO = 10 nA × 1024 = 10.24 μA
At 20◦ C, T = 293 K and VT =
8.62 × 10−5 × 293 = 25.3 mV
At 50◦ C, T = 323 K and VT =
8.62 × 10−5 × 323 = 27.8 mV
If the transistor is operated at v BE = 700 mV,
then
(i) At 20◦ C, iE becomes
4.33
iE = 0.5e(700−692)/25.3 = 0.69 mA
(ii) At 50◦ C, iE becomes
iE = 0.5e(700−632)/27.8 = 5.77 mA
4.36 v BE = 0.7 V at iC = 10 mA
For v BE = 0.5 V,
From the figure we can write
IS v BE /VT
e
− ICBO
IB =
β
IC = IS ev BE /VT + ICBO
iC = 10e(0.5−0.7)/0.025 = 3.35 μA
(1)
At a current IC and a BE voltage VBE , the slope of
the iC –v BE curve is IC /VT . Thus,
(2)
Slope at VBE of 700 mV =
10 mA
= 400 mA/V
25 mV
Chapter 4–10
Slope at VBE of 500 mV =
= 0.134 mA/V
3.35 μA
25 mV
4.38
R2
68 k
I2
400
3000
Ratio of slopes =
0.134
I1
R1
6.8 k
IB
VBE
4.37 Use Eq. (4.18):
v CE
iC = IS ev BE /VT 1 +
VA
At 25◦ C, assume IE = 1 mA. Thus,
vBE 0.65 V 0.70 V 0.72 V 0.73 V 0.74 V
(V)
iC
(mA)
iC
(mA)
iC
(mA)
iC
(mA)
iC
(mA)
0
0.196
1.45
3.21
4.81
7.16
15
0.225
1.67
3.70
5.52
8.24
VBE
0.68 V
= 0.1 mA
=
R1
6.8 k
1
= 0.11 mA
101
Note that the currents in R1 and R2 differ only by
the small base current, 0.01 mA. Had I1 and I2
been equal, then we would have had
= 0.1 +
for the given value of v BE . The slope of each
straight line is equal to this value divided by 100
V (VA ). Thus we obtain
0.2
I1 =
which is the value assumed.
IE
I2 = I1 + IB = I1 +
β +1
iC = 10−15 ev BE /VT A
Intercept (mA)
VBE = 0.68 V
IE = I − I1 = 1.1 − 0.1 = 1 mA
To find the intercept of the straight-line
characteristics on the ic axis, we substitute
v CE = 0 and evaluate
v BE (V) 0.65
VE
I 1.1 mA
with IS = 10−15 A and VA = 100 V, to get
v CE iC = 10−15 ev BE /0.025 1 +
100
vCE
IE
0.70
0.72
0.73
0.74
1.45
3.22
4.80
7.16
Slope (mA/V) 0.002 0.015 0.032 0.048 0.072
I1 R1 = VBE
I2 R2 I1 R2 = VBE
R2
R1
VE = −(I1 R1 + I2 R2 )
R2
(1)
= −VBE 1 +
R1
6.8
= −11 VBE = −7.48 V
= −VBE 1 +
0.68
which gives this circuit the name “VBE
multiplier.” A more accurate value of VE can be
obtained by taking IB into account:
VE = −(I1 R1 + I2 R2 )
R2
= − VBE + VBE + IB R2
R1
R2
VBE − IB R2
=− 1+
R1
(2)
= −7.48 − 0.01 × 68 = −8.16 V
As temperature increases, an approximate
estimate for the temperature coefficient of VE can
be obtained by assuming that IE remains constant
and ignoring the temperature variation of β. Thus,
we would be neglecting the temperature change
of the (IB R2 ) terms in Eq. (2). From Eq. (2) we
Chapter 4–11
can obtain the temperature coefficient of VE by
utilizing the fact the VBE changes by – 2.2 mV/◦ C.
Thus,
4.41
iC (mA)
Temperature coefficient of VE
R2
=− 1+
× −2.2
R1
= −11 × −2.2 = +24.2 mV/◦ C
At 75◦ C, which is a temperature increase of 50◦ C,
1.3
1.1
VA
0 5
0.3
10 15
v CE (V)
VE = −8.16 + 24.2 × 50 = −6.95 V
As a check on our assumption of constant IE , let
us find the value of IE at 75◦ C:
I1 (75◦ C) =
=
VBE (75◦ C)
R1
0.68 − 2.2 × 10−3 × 50
6.8
Slope of iC –v CE line corresponding to
v BE = 710 mV is
0.2 mA
1.3 − 1.1
=
= 0.02 mA/V
Slope =
15 − 5
10 V
Near saturation, VCE = 0.3 V, thus
iC = 1.1 − 0.02 × (5 − 0.3)
= 1.006 1 mA
iC will be 1.2 mA at,
= 0.084 mA
IE (75◦ C) = I − I1 (75◦ C)
= 1.1 − 0.084 = 1.016 mA
which is reasonably close to the assumed value of
1 mA.
1.2 − 1.1
= 10 V
0.02
The intercept of the iC –v CE straight line on the iC
axis will be at
v CE = 5 +
iC = 1.1 − 5 × 0.02 = 1 mA
Thus, the Early voltage is obtained as
iC (at v CE = 0)
VA
1
= 50 V
⇒ VA =
0.02
VA
50 V
=
= 50 k
ro =
IC
1 mA
Slope =
4.39 ro =
VA
50 V
=
IC
IC
Thus,
At IC = 1 mA, ro =
At IC = 100 μA,
50 V
= 50 k
1 mA
ro =
50 V
= 500 k
0.1 mA
4.40 ro = 1/slope
= 1/(0.8 × 10−5 )
= 125 k
ro =
VA
IC
125 k =
VA
⇒ VA = 125 V
1 mA
At IC = 10 mA,
ro =
which is the inverse of the slope of the iC –v CE
line.
VA
125 V
=
= 12.5 k
IC
10 mA
4.42 The equivalent circuits shown in the figure
correspond to the circuits in Fig. 4.19.
Chapter 4–12
E
(b)
(c) For operation deep in saturation with
βforced = 10:
iE
vEB
B
VCE = 0.2 V
DB
(IS/b)
biB
ro
C
iB
iC
IC =
VCC − VCE
10 − 0.2
=
= 9.8 mA
RC
1
IB =
IC
9.8
= 0.98 mA
=
βforced
10
VBB = IB RB + VBE
iC
1 mA
= 100
=
iB
10 μA
iC 0.08 mA
βac =
=
= 80
iB v CE constant
1.0 μA
4.43 β =
iC = iB × βac +
v CE
ro
where
ro =
VA
100
=
= 100 k
IC
1
Thus,
iC = 2 × 80 +
2
× 103 = 180 μA
100
= 0.18 mA
= 0.98 × 10 + 0.7 = 10.5 V
4.45 Refer to the circuit in Fig. P4.44 (with
VBB = VCC ) and to the BJT equivalent circuit of
Fig. 4.21.
IC =
VCC − 0.2
RC
IB =
VCC − 0.7
RB
βforced ≡
IC
IB
Thus,
βforced =
VCC − 0.2
VCC − 0.7
RB
RC
(1)
Pdissipated = VCC (IC + IB )
4.44 Refer to the circuit in Fig. P4.44.
= VCC (βforced IB + IB )
(a) For active-mode operation with VC = 2 V:
= (βforced + 1)VCC IB
IC =
VCC − VC
10 − 2
=
= 8 mA
RC
1
IB =
8
IC
=
= 0.16 mA
β
50
VBB = IB RB + VBE
= 0.16 × 10 + 0.7 = 2.3 V
(b) For operation at the edge of saturation:
VCE = 0.3 V
IC =
VCC − VCE
10 − 0.3
= 9.7 mA
=
RC
1
IB =
9.7
IC
=
= 0.194 mA
β
50
(2)
For VCC = 5 V and βforced = 10 and
Pdissipated ≤ 20 mW, we can proceed as follows.
Using Eq. (1) we can determine (RB /RC ):
5 − 0.2
RB
10 =
5 − 0.7
RC
⇒
RB
= 8.96
RC
Using Eq. (2), we can find IB :
(10 + 1) × 5 × IB ≤ 20 mW
⇒ IB ≤ 0.36 mA
Thus,
VBB = IB RB + VBE
VCC − 0.7
≤ 0.36 mA
RB
= 0.194 × 10 + 0.7 = 2.64 V
⇒ RB ≥ 11.9 k
(3)
Chapter 4–13
From the table of 1% resistors in Appendix J we
select
Thus,
RB = 12.1 k
IC =
5 − 0.3
= 4.7 mA
1
RC = 1.35 k
IB =
4.7
IC
=
= 0.094 mA
β
50
From the table of 1% resistors in Appendix J we
select
RB =
4.3
4.3
= 45.7 k
=
IB
0.094
Substituting in Eq. (3), we have
RC = 1.37 k
For these values:
5 − 0.2
= 3.5 mA
IC =
1.37
5 − 0.7
= 0.36 mA
IB =
12.1
Thus,
4.47
3 V
1 k
IE 1.3 mA 3
IC
VC 3 1.3 1
1.7 V 4
3.5
= 9.7
βforced =
0.36
Pdissipated = VCC (IC + IB )
2 V
VE 2 0.7
1.3 V 1
1.3
IE 1.3 mA 2
1
= 5 × 3.86 = 19.2 mW
1 k
4.46
5 V
VB 4.3 V RB 10 k
V
ECsat
(a)
3 V
0.2 V
VC 3 1 1 2 V
VC 4.8 V
IB
4
1.7 V
IC
1 k
VE 1.0 V 1
1.0
IE 1
1 mA 2
1 k
Assume saturation-mode operation. From the
figure we see that
(b)
4.8
VC
=
= 4.8 mA
1 k
1
VB
4.3
= 0.43 mA
=
IB =
RB
10
3 V
IC =
0 3
1 k
Thus,
βforced ≡
IC
4.8
=
= 11.2
IB
0.43
Since 11.2 is lower than the transistor β of 50, we
have verified that the transistor is operating in
saturation, as assumed.
VC = VCC − VECsat = 5 − 0.2 = 4.8 V
To operate at the edge of saturation,
VEC = 0.3 V
and
IE 1 mA 3
IC
1 k
IC /IB = β = 50
VC 3 0 3 V 4
0V
VE 0 V
1 k
0 2
(c)
1
Chapter 4–14
The analysis and the results are given on the
circuit diagrams of Figs. 1 through 3 (see
preceding page). The circled numbers indicate the
order of the analysis steps.
4.48
For βforced = 2,
IC
=2
IB
3.5 − VB
=2
2VB − 4.2
3 V
1 k
3 (VB 0.4)
IC 1
VC VB 0.4
VCE 0.3 V
VB
V 0.7
IE B
1
IB = IE − IC = 2VB − 4.2
VB 0.7
1 k
⇒ VB = 2.38 V
4.49 Refer to the circuit in Fig. P4.49.
(a) For VB = −1 V,
VE = VB − VBE = −1 − 0.7 = −1.7 V
IE =
−1.7 + 3
VE − (−3)
=
= 1.3 mA
1
1
Assuming active-mode operation, we have
Figure 1
IC = αIE IE = 1.3 mA
Figure 1 shows the circuit with the value of VB
that results in operation at the edge of saturation.
Since β is very high,
IC IE
VC = +3 − IC × 1 = 3 − 1.3 = +1.7 V
Since VC > VB − 0.4, the transistor is operating in
the active mode as assumed.
(b) For VB = 0 V,
3 − (VB − 0.4)
VB − 0.7
=
1
1
VE = 0 − VBE = −0.7 V
⇒ VB = 2.05 V
IE =
3 V
IC
Assuming operation in the active mode, we have
1 k
IB
VB 0.5
VCEsat 0.2 V
VB
IE
−0.7 − (−3)
= 2.3 mA
1
VB 0.7
1 k
IC = αIE IE = 2.3 mA
VC = +3 − IC × 1 = 3 − 2.3 = +0.7 V
Since VC > VB − 0.4, the BJT is operating in the
active mode, as assumed.
(c) For VB = +1 V,
VE = 1 − 0.7 = +0.3 V
Figure 2
Figure 2 shows the circuit with the value of VB
that results in the transistor operating in
saturation, with
IE =
VB − 0.7
= VB − 0.7
1
IC =
3 − (VB − 0.5)
= 3.5 − VB
1
IE =
0.3 − (−3)
= 3.3 mA
1
Assuming operation in the active mode, we have
IC = αIE IE = 3.3 mA
VC = 3 − 3.3 × 1 = −0.3 V
Now VC < VB − 0.4, indicating that the transistor
is operating in saturation, and our original
assumption is incorrect. It follows that
Chapter 4–15
VC = VE + VCEsat
= 0.3 + 0.2 = 0.5 V
IC =
3 − VC
3 − 0.5
=
= 2.5 mA
1
1
IB = IE − IC = 3.3 − 2.5 = 0.8 mA
βforced =
IC
2.5
= 3.1
=
IB
0.8
(d) When VB = 0 V, IE = 2.3 mA. The emitter
current becomes 0.23 mA at
IE =
VB − 0.7 − (−3)
= VB + 2.3
1
VC = VE + VCEsat = VB − 0.7 + 0.2 = VB − 0.5
IC =
3 − (VB − 0.5)
= 3.5 − VB
1
IB = IE − IC = 2 VB − 1.2
IC
3.5 − VB
=
=2
IB
2 VB − 1.2
⇒ VB = +1.18 V
VB = −3 + 0.23 × 1 + 0.7 = −2.07 V
4.50 Refer to the circuit in Fig. P4.50.
(e) The transistor will be at the edge of
conduction when IE 0 and VBE = 0.5 V, that is,
VE = 1 V
VB = −3 + 0.5 = −2.5 V
IE =
In this case,
VB = VE − 0.7 = 0.3 V
VE = −3 V
VC = +3 V
(f) The transistor reaches the edge of saturation
when VCE = 0.3 V but IC = αIE IE :
VE = VB − 0.7
IE =
VB − 0.7 − (−3)
= VB + 2.3
1
VC = VE + 0.3 = VB − 0.4
IC =
3 − VC
3 − VB + 0.4
=
= 3.4 − VB
1
1
IB =
3−1
= 0.4 mA
5
VB
0.3
=
= 0.006 mA
50 k
50
IC = IE − IB = 0.4 − 0.006 = 0.394 mA
VC = −3 + 5 × 0.394 = −1.03 V
Observe that VC < VB , confirming our implicit
assumption that the transistor is operating in the
active region.
β=
IC
0.394
=
= 66
IB
0.006
α=
IC
0.394
= 0.985
=
IE
0.4
Since
IC IE
4.51
VCC 3 V
3.4 − VB = VB + 2.3
VB = 0.55 V
For this value,
VE = 0.55 − 0.7 = −0.15 V
0.1 mA
RC 1 k
R1
0
VB 1.2 V
VC = −0.15 + 0.3 = +0.15 V
(g) For the transistor to operate in saturation with
βforced = 2,
VE = VB − 0.7
RE 1 k
R2
Figure 1
Chapter 4–16
4.52
From Fig. 1 we see that
R1 + R2 =
VCC
3
VCC
=
= 30 k
0.1 mA
0.1
3 V
R2
= 1.2
R1 + R2
RE
IB
R2
3×
= 1.2
30
RB
20 k
R1 = 30 − 12 = 18 k
VC
IC
For β = 100, to obtain the collector current, we
replace the voltage divider with its Thévenin
equivalent, consisting of
R2
12
=3×
= 1.2 V
R1 + R2
18 + 12
3 V
Writing a loop equation for the EBJ loop, we have
= IE × 2.2 + 0.7 +
3 V
⇒ IE =
IC
RC
2.2 k
3 = IE RE + VEB + IB RB
RB = R1 R2 = 12 18 = 7.2 k
VBB
VE
VB
⇒ R2 = 12 k
VBB = 3 ×
2.2 k
IE
RC 1 k
VC
RB
(1)
IE
× 20
β +1
3 − 0.7
= 0.86 mA
20
2.2 +
41
VE = 3 − 0.86 × 2.2 = +1.11 V
VB = VE − 0.7 = +0.41 V
IB
Assuming active-mode operation, we obtain
IE
RE 1 k
IC = αIE =
40
× 0.86 = 0.84 mA
41
VC = −3 + 0.84 × 2.2 = −1.15 V
Figure 2
Refer to Fig. 2. Assuming active-mode operation,
we can write a loop equation for the base–emitter
loop:
VBB = IB RB + VBE + IE RE
1.2 =
IE
× 7.2 + 0.7 + IE × 1
β +1
⇒ IE =
1.2 − 0.7
= 0.47 mA
7.2
1+
101
IC = αIE = 0.99 × 0.47 = 0.46 mA
VC = +3 − 0.46 × 1 = +2.54 V
Since VB = IE RE + VBE = 0.47 + 0.7 = 1.17 V,
we see that VC > VB − 0.4, and thus the transistor
is operating in the active region, as assumed.
Since VC < VB + 0.4, the transistor is operating in
the active mode, as assumed. Now, if RB is
increased to 100 k, the loop equation [Eq. (1)]
yields
IE =
3 − 0.7
= 0.5 mA
100
2.2 +
41
VE = 3 − 0.5 × 2.2 = +1.9 V
VB = VE − VEB = 1.9 − 0.7 = +1.2 V
Assuming active-mode operation, we obtain
IC = αIE =
40
× 0.5 = 0.48 mA
41
VC = −3 + 0.48 × 2.2 = −1.9 V
Since VC < VB + 0.4, the transistor is operating in
the active mode, as assumed.
Chapter 4–17
If with RB = 100 k, we need the voltages to
remain at the values obtained with RB = 20 k,
the transistor must have a β value determined as
follows. For IE to remain unchanged,
4.54
5 V
IB
3 − 0.7
3 − 0.7
=
20
100
2.2 +
2.2 +
41
β +1
⇒
RB
RC
1 k
VC
20
100
=
41
β +1
β +1=
IC
VB
410
= 205
2
IE
VE
RE
1 k
β = 204
4.53
3 V
IE
A loop equation for the EB loop yields
5 = IB RB + VBE + IE RE
RE
⇒ IE =
VE 0.7 V
IE =
VBC 1 V
VC 1 V
IC
RC
5 − 0.7
RB
RE +
β +1
4.3
RB
1+
101
(a) For RB = 100 k,
IE =
3 V
4.3
= 2.16 mA
100
1+
101
VE = IE RE = 2.16 × 1 = 2.16 V
Refer to the figure. To obtain IE = 0.5 mA we
select RE according to
RE =
Assuming active-mode operation, we obtain
3 − 0.7
= 4.6 k
0.5
IC = αIE = 0.99 × 2.16 = 2.14 mA
To obtain VC = −1 V, we select RC according to
RC =
−1 − (−3)
= 4 k
0.5
and
VC = 5 − 2.14 × 1 = +2.86 V
Since VC > VB − 0.4, the transistor is operating in
the active region, as assumed.
where we have utilized the fact that α 1 and
thus IC IE = 0.5 mA. From the table of 5%
resistors in Appendix J we select
RE = 4.7 k
VB = VE + 0.7 = 2.86 V
RC = 3.9 k
For these values,
(b) For RB = 10 k,
IE =
4.3
= 3.91 mA
10
1+
101
VE = 3.91 × 1 = 3.91 V
VB = 3.91 + 0.7 = 4.61 V
3 − 0.7
IE =
= 0.49 mA
4.7
Assuming active-mode operation, we obtain
IC IE = 0.49 mA
IC = αIE = 0.99 × 3.91 = 3.87 mA
VBC = 0 − VC = −(−3 + 0.49 × 3.9) = −1.1 V
VC = 5 − 3.87 = +1.13 V
Chapter 4–18
Since VC < VB − 0.4, the transistor is operating in
saturation, contrary to our original assumption.
Therefore, we need to redo the analysis assuming
saturation-mode operation, as follows:
VB = VE + 0.7
VC = VE + VCEsat = VE + 0.2
5 − VB
IB =
RB
4.3 − VE
5 − VE − 0.7
=
=
10
10
5 − VC
5 − VE − 0.2
=
IC =
RC
1
= 4.8 − VE
IE =
VE
VE
= VE
=
RE
1
(1)
VC = 3.2 V
Now checking the currents,
IB =
5 − 3.7
= 1.3 mA
1
IC =
5 − 3.2
= 1.8 mA
1
Thus, the transistor is operating at a forced β of
βforced =
(2)
IC
1.8
=
= 1.4
IB
1.3
which is much lower than the value of β,
confirming operation in saturation.
(3)
Substituting from Eqs. (1), (2), and (3) into
IE = IB + IC
gives
4.55
For the solutions and answers to parts (a) through
(e), see the corresponding circuit diagrams.
VE = 0.43 − 0.1 VE + 4.8 − VE
⇒ VE = 2.5 V
VC = 2.7 V
IC
VB = 3.2 V
5 − 3.2
= 0.18 mA
IB =
10
5 − 2.7
= 2.3 mA
IC =
1
Thus,
2.3
IC
=
= 12.8
IB
0.18
3 V
(a)
0.5 mA
3.6 k
V2 3 0.5 3.6
1.2 V
43 k
IB
0
0V
V1 0.7 V
which is lower than the value of β, verifying
saturation-mode operation.
0.5 mA
(c) For RB = 1 k, we assume saturation-mode
operation:
VB = VE + 0.7
VC = VE + 0.2
5 − (VE + 0.7)
= 4.3 − VE
IB =
1
5 − (VE + 0.2)
IC =
= 4.8 − VE
1
VE
IE =
= VE
1
These values can be substituted into
(b)
3 V
3.6 k
~ 0.5 mA
V3 3 0.5 3.6
1.2 V
~0
IB IE = IB + IC
VE 0.7 V
to obtain
4.7 k
VE = 4.3 − VE + 4.8 − VE
I4 0.7 (3) 0.5 mA
4.7
⇒ VE = 3 V
VB = 3.7 V
3 V
Chapter 4–19
3 V
a (d)
3 V
(c)
3 1.45
6.2
0.25 mA
IE 0.5 mA
3.6 k
V8 0.75 0.7
1.45 V
0.75 V
~ 0 mA
V7 3 0.5 3.6
1.2 V
43 k
6.2 k
110 k
IB 0
V6
V5 0.7 V
0
V9 3 0.25 10
0.5 V
0.75 V
4.7 k
IE 0.7 (–3)
4.7
0.5 mA
3 V
10 k
0.25 mA
3 V
3 V
(e)
6
480
0.0125 mA
I
3 1.45
IE 0.25 mA
6.2
6.2 k
180 k
V11 0.75 0.7 1.45 V
V10 3 0.0125 300
0.75 V
0
V12 3 10 0.25
10 k 0.5 V
300 k
0.25 mA
3 V
4.56 (a)
3 V
IC a 0.5
0.99 0.5
0.495 mA
3.6 k
VB 0.005 43
0.215 V
V2 3 0.495 3.6
1.218 V
43 k
IB 0.5
101
0.005 mA
V1 0.215 0.7
0.915 V
0.5 mA
3 V
(a)
See solution and answer on the figure, which
corresponds to Fig. P4.55(a).
Chapter 4–20
(b)
3 V
a 0.5 0.495
mA
3.6 k
IB 0.5
101
V3 3 0.495 3.6 1.218 V
0.005 mA
VE 0.7
4.7 k
I4 0.7 (3)
4.7
0.5 mA
3 V
(b)
See solution and answer on the figure, which
corresponds to Fig. P4.55(b).
(c)
(d)
3 V
IC
3 V
3.6 k
IE
V7
V6
0.75 V
43 k
6.2 k
V8
IB
IB IE /(b 1)
110 k
V5
V9
4.7 k
IE
IC
3 V
10 k
3 V
(c)
(d)
Writing an equation for the loop containing the
BEJ of the transistor leads to
IE =
3 − 0.7
= 0.449 mA
43
4.7 +
101
V5 = −3 + 0.449 × 4.7 = −0.9 V
An equation for the loop containing the EBJ of
the transistor yields
IE =
3 − 0.75 − 0.7
= 0.213 mA
110
6.2 +
101
V6 = −0.9 + 0.7 = −0.2 V
V8 = +3 − 0.213 × 6.2 = +1.7 V
IC = αIE = 0.99 × 0.449 = 0.444 mA
IC = αIE = 0.99 × 0.213 = 0.21 mA
V7 = 3 − 0.444 × 3.6 = +1.4 V
V9 = −3 + 0.21 × 10 = −0.9 V
Chapter 4–21
This figure belongs to Problem 4.56, part (e).
3 V
3 V
IE
IE
6.2 k
6.2 k
180 k
V11
VBB
V10
3 V
V12
IC
10 k
3 V
(e)
(e) See figure above.
First, we use Thévenin’s theorem to replace the
voltage divider feeding the base with VBB and RB :
6
× 300 = +0.75 V
= −3 +
480
Since VC = 2 V is lower than VB , which is
+2.3 V, the transistor will be operating in the
active mode. Thus,
IC = βIB = 50 × 0.023 = 1.15 mA
To obtain VC = 2 V, we select RC according to
RC =
RB = 180 300 = 112.5 k
Next we write an equation for the loop containing
the EBJ to obtain
IE =
RB
10 k
300 k
VBB
V10
V12
IC
V11
IB
IB
VC
2V
= 1.74 k
=
IC
1.15 mA
Now, if the transistor is replaced with another
having β = 100, then
IC = 100 × 0.023 = 2.3 mA
3 − 0.75 − 0.7
= 0.212 mA
112.5
6.2 +
101
which would imply
VC = 2.3 × 1.74 = 4 V
V11 = +3 − 0.212 × 6.2 = +1.7 V
V10 = 1.7 − 0.7 = +1 V
which is impossible because the base is at 2.3 V.
Thus the transistor must be in the saturation mode
and
IC = αIE = 0.99 × 0.212 = 0.21 mA
VC = VE − VECsat
V12 = −3 + 0.21 × 10 = −0.9 V
= 3 − 0.2 = 2.8 V
4.58
4.57
5 V
3 V
RE
IE
2.3 V
IB
100 k
VC
IC
RC
RB
VC
IC
IB =
2.3 V
= 0.023 mA
100 k
RC
5 V
Chapter 4–22
We required IE to be nominally 1 mA (i.e., at
β = 100) and to remain within ±10% as β varies
from 50 to 150. Writing an equation for the loop
containing the EBJ results in
To obtain the value of RC , we note that at the
nominal emitter current value of 1 mA,
VC = −1 V,
5 − 0.7
IE =
RB
RE +
β +1
−1 − (−5)
= 4.04 k
0.99
Specified to the nearest kilohm,
Thus,
RC = 4 k
4.3
4.3
RE +
RB
51
(1)
= IEmin
(2)
4.3
RE +
RC =
=1
RB
RE +
101
RB
151
IC = αIE = 0.99 mA
Finally, for our design we need to determine the
range obtained for collector current and collector
voltage for β ranging from 50 to 150 with a
nominal value of 100. We compute the nominal
value of IE from
4.3
= 0.96 mA
50
4+
101
We utilize Eqs. (2) and (3) to compute IEmin and
IEmax ,
IEnominal =
= IEmax
(3)
If we set IEmin = 0.9 mA and solve Eqs. (1) and
(2) simultaneously, we obtain
RE = 3.81 k
4.3
= 0.86 mA
50
4+
51
4.3
= 0.99 mA
=
50
4+
151
IEmin =
IEmax
RB = 49.2 k
Substituting theses values in Eqs. (2) and (3) gives
Thus,
IEmin = 0.9 mA
0.99
IEmax
=
= 1.03
IEnominal
0.96
IEmax = 1.04 mA
0.86
IEmin
= 0.9
=
IEnominal
0.96
Obviously, this is an acceptable design.
Alternatively, if we set IEmax in Eq. (3) to 1.1 mA
and solve Eqs. (1) and (3) simultaneously, we
obtain
which meet our specifications. The collector
currents are
RE = 3.1 k
RB = 119.2 k
ICnominal = 0.99 × 0.96 = 0.95 mA
ICmin = 0.99 × 0.86 = 0.85 mA
ICmax = 0.99 × 0.99 = 0.98 mA
and the collector voltages are
Substituting these values in Eqs. (2) and (3) gives
VCnominal = −5 + 0.95 × 4 = −1.2 V
IEmin = 0.8 mA
VCmin = −5 + 0.85 × 4 = −1.6 V
IEmax = 1.1 mA
Obviously this is not an acceptable design (IEmin
is 20% lower than nominal).
Therefore, we shall use the first design.
Specifying the resistor values to the nearest
kilohm results in
RE = 4 k
RB = 50 k
VCmax = −5 + 0.98 × 4 = −1.1 V
4.59 Figure 1 on next page shows the circuit with
β = ∞; the required voltage values are indicated.
The resistor values are obtained as follows:
V2 = −0.7 V
V2 − (−5)
0.5 mA
⇒ R1 = 8.6 k
R1 =
Chapter 4–23
This figure belongs to Problem 4.59.
5 V
0.5
mA
0.5 mA
1 mA
R3
R2
R5
V4
0
V7 1 V
Q2
V3 = 0
Q1
0
0.5
mA
V2
Q3
R1
V5 = –2 V
R4
0.5 mA
V6
R6
1 mA
–5 V
Figure 1
This figure belongs to Problem 4.59.
5 V
I1
IE2
10 k
8.2 k
3.9 k
V4
IB2
V7
Q2
IC3
IC1
Q1
IC2
V3
V2
IE1
8.2 k
IB3
Q3
I2
V5
IE3
V6
2.4 k
6.2 k
–5 V
Figure 2
R2 =
5−0
5 − V3
=
= 10 k
0.5
0.5
V4 = 0 + 0.7 = 0.7 V
Consulting the table of 5% resistors in
Appendix J, we select the following resistor
values:
R3 =
5 − 0.7
5 − V4
=
= 8.6 k
0.5
0.5
R1 = 8.2 k R2 = 10 k R3 = 10 k
R4 =
−2 + 5
V5 − (−5)
=
= 6 k
0.5
0.5
R4 = 6.2 k R5 = 3.9 k R6 = 2.4 k
V6 = V5 − 0.7 = −2 − 0.7 = −2.7 V
R6 =
V6 − (−5)
−2.7 + 5
=
= 2.3 k
1
1
R5 =
5 − V7
5−1
=
= 4 k
1
1
The circuit with the selected resistor values is
shown in Fig. 2. Analysis of the circuit proceeds
as follows:
V2 = −0.7 V
Chapter 4–24
IE1 =
V2 − (−5)
−0.7 + 5
=
= 0.524 mA
8.2
8.2
IC1 = αIE1 = 0.99 × 0.524 = 0.52 mA
(b) For v I = +2 V, Q1 will be conducting and
Q2 will be cut off, and the circuit reduces to that
in Fig. 1.
2.5 V
The current I1 through the 10-k resistor is
given by
IE2
101
I1 = IC1 − IB2 = IC1 −
10 k
2 V
Q1
IB
VB
Noting that the voltage drop across the 10 k
resistor is equal to (IE2 × 8.2 + 0.7), we can write
VE
IE
I1 × 10 = 8.2IE2 + 0.7
1 k
Thus,
IE2
= 8.2IE2 + 0.7
10 0.52 −
101
⇒ IE2 = 0.542 mA
V4 = 5 − 0.542 × 8.2 = 0.56 V
V3 = 0.56 − 0.7 = −0.14 V
Figure 1
Since VB will be lower than +2 V, VC will be
higher than VB and the transistor will be operating
in the active mode. Thus,
IE =
IC2 = αIE2 = 0.99 × 0.542 = 0.537 mA
I2 = IC2 − IB3 = 0.537 −
IE3
101
Since the voltage drop across the 6.2-k resistor
is equal to (0.7 + IE3 × 2.4),
I2 × 6.2 = 0.7 + 2.4IE3
2 − 0.7
= 1.1 mA
10
1+
51
VE = +1.1 V
VB = 1.8 V
(c) For v I = −2.5, Q1 will be off and Q2 will be
on, and the circuit reduces to that in Fig. 2.
IE3
= 0.7 + 2.4IE3
6.2 0.537 −
101
⇒ IE3 = 1.07 mA
V6 = −5 + 1.07 × 2.4 = −2.43 V
V5 = V6 + 0.7 = −1.73
IC3 = α × IE3 = 0.99 × 1.07 = 1.06 mA
Figure 2
V7 = −3.9 × 1.06 = 0.87 V
Since VB > −2.5, VC will be lower than VB and
Q2 will be operating in the active region. Thus
4.60 Refer to the circuit in Fig. P4.60.
IE =
(a) For v I = 0, both transistors are cut off and all
currents are zero. Thus
VE = −IE × 1 = −1.5 V
VB = 0 V
VB = −1.5 − 0.7 = −2.2 V
and
VE = 0 V
2.5 − 0.7
= 1.5 mA
10
1+
51
Chapter 4–25
(d) For v I = −5 V, Q1 will be off and Q2 will be
on, and the circuit reduces to that in Fig. 3.
Assuming saturation-mode operation, the
terminal voltages are interrelated as shown in the
figure, which corresponds to Fig. P4.61(a). Thus
we can write
IE =
VE
= VE
1
IC =
5 − (VE + 0.2)
= 0.5 − 0.1(VE + 0.2)
10
IB =
5 − (VE + 0.7)
= 0.25 − 0.05(VE + 0.7)
20
Now, imposing the constraint
Figure 3
Here we do not know whether Q2 is operating in
the active mode or in saturation. Assuming
active-mode operation, we obtain
5 − 0.7
= 3.6 mA
10
1+
51
VE = −3.6 V
IE = IC + IB
results in
VE = 0.5 − 0.1(VE + 0.2) + 0.25 − 0.05(VE + 0.7)
IE =
⇒ VE = 0.6 V
VB = −4.3 V
VC = 0.8 V
which is impossible, indicating that our original
assumption is incorrect and that Q2 is saturated.
Assuming saturation-mode operation, we obtain
VB = 1.3 V
VE = VC + VECsat = −2.5 + 0.2 = −2.3 V
−VE
= 2.3 mA
IE =
1 k
VB = VE − 0.7 = −3 V
−3 − (−5)
= 0.2 mA
IB =
10
IC = IE − IB = 2.3 − 0.2 = 2.1 mA
IC
2.1
=
= 10.5
βforced =
IB
0.2
IC =
5 − 0.8
= 0.42 mA
10
IB =
5 − 1.3
= 0.185 mA
20
βforced =
0.42
= 2.3
0.185
which is less than the value of β1 verifying
saturation-mode operation.
(b)
which is lower than β, verifying that Q2 is
operating in saturation.
5 V
IE
4.61 (a)
5 V
20 k
VE
IC
10 k
IB
1 k
VE + 0.2
VE – 0.7
VE – 0.2
IB
10 k
IC
1 k
VE + 0.7 V
VE
IE
1 k
(a)
–5 V
(b)
Assuming saturation-mode operation, the
terminal voltages are interrelated as shown in the
Chapter 4–26
shown in the figure, which corresponds to Fig.
P4.61(c), we denote the voltage at the emitter of
Q3 as V and then obtain the voltages at all other
nodes in terms of V , utilizing the fact that a
saturated transistor has |VCE | = 0.2 V and of
course |VBE | = 0.7 V. Note that the choice of the
collector node to begin the analysis is arbitrary;
we could have selected any other node and
denoted its voltage as V . We next draw a circle
around the two transistors to define a “supernode.”
A node equation for the supernode will be
figure, which corresponds to Fig. P4.61(b). We
can obtain the currents as follows:
IE =
5 − VE
= 5 − VE
1
IC =
VE − 0.2
= VE − 0.2
1
IB =
VE − 0.7 − (−5)
= 0.1 VE + 0.43
10
Imposing the constraint
IE3 + IC4 = IB3 + I + IE4
IE = IB + IC
(1)
where
results in
IE3 =
5 − (V + 0.2)
= 0.48 − 0.1V
10
(2)
⇒ VE = +2.27 V
IC4 =
5 − (V − 0.5)
= 0.183 − 0.033V
30
(3)
VC = +2.07 V
IB3 =
5 − (V − 0.5)
= 0.1V − 0.05
10
(4)
5 − VE = VE − 0.2 + 0.1 VE + 0.43
VB = 1.57 V
I=
2.07
IC =
= 2.07 mA
1
IE4 =
1.57 − (−5)
IB =
= 0.657 mA
10
βforced =
V
= 0.05V
20
(5)
V − 0.7
= 0.1V − 0.07
10
(6)
Substituting from Eqs. (2)–(6) into Eq. (1) gives
0.48 − 0.1V + 0.183 − 0.033V
= 0.1V − 0.05 + 0.05V + 0.1V − 0.07
IC
2.07
= 3.2
=
IB
0.657
⇒ V = 2.044 V
which is lower than the value of β, verifying
saturation-mode operation.
Thus
(c) We shall assume that both Q3 and Q4 are
operating in saturation. To begin the analysis
VC3 = V = 2.044 V
This figure belongs to Problem 4.61, part (c).
5 V
IE3
IC4
10 k
30 k
Supernode
V + 0.2
V – 0.5
Q3
IB3
10 k
V – 0.5
V
I
Q4
20 k
V – 0.7
10 k
IE4
(c)
Chapter 4–27
VC4 = V − 0.5 = 1.54 V
Thus,
Next we determine all currents utilizing
Eqs. (2)–(6):
ID1 × 40 = IE1 × 2
IE3 = 0.276 mA IC4 = 0.116 mA
⇒ ID1 = 0.05IE1
IB3 = 0.154 mA I = 0.102 mA
But
IE4 = 0.134
ID1 =
The base current of Q4 can be obtained from
IB4 = IE4 − IC4 = 0.134 − 0.116 = 0.018 mA
Thus,
Finally, the collector current of Q3 can be
found as
IE1 =
IC3 = I + IB4 = 0.102 + 0.018 = 0.120
βforced4
0.069
= 1.38 mA 1.4 mA
0.05
VE1 = IE1 × 2 = 2.77 V 2.8 V
The forced β values can now be found as
βforced3 =
9 − 0.7
= 0.069 mA 0.07 mA
80 + 40
VB1 = VE1 + 0.7 = 3.5 V
IC3
0.120
= 0.8
=
IB3
0.154
IC1 = IE1 = 1.38 mA 1.4 mA
IC4
0.116
=
=
= 6.4
IB4
0.018
V2 = 9 − IC1 × 2 = 9 − 1.38 × 2 6.2 V
Both βforced values are well below the β value of
50, verifying that Q3 and Q4 are in deep
saturation.
VC1 = V2 − VD2 = 6.2 − 0.7 = 5.5 V
VE2 = V2 = 6.2 V
9 − 6.2
= 28 mA
100 4.62 (a) Consider first the case β = ∞ and R
open circuited. The circuit is shown in Fig. 1
below, where β = ∞ and R is open circuited.
Since VD1 = VBE1 , we have
IE2 =
V1 = VE1
VC2 = 28 × 0.1 = 2.8 V
IC2 = IE = 28 mA
This figure belongs to Problem 4.62, part (a).
9 V
2 k
IC1
80 k
IE2
100 V2
ID1
VC1
0
VB1
ID1
D1
V1
40 k
Q2
0
IC1
Q1
IC2 IE2
IE1
VE1
VC2
100 2 k
Figure 1
VE2
D2
β = ∞, and R is open circuited
Chapter 4–28
VE1 = 1.22 × 2 = 2.44 V
VB1 = 2.44 + 0.7 = 3.14 V
IC1 = αIE1 = 0.99 × 1.22 = 1.21 mA
R 2 k
2.8 V
Observing that VE2 = V2 , we see that the voltage
drops across the 2-k resistor and the 100-
resistor are equal, thus
2.8 V
0
ID2 × 2 = IE2 × 0.1
⇒ ID2 = 0.05IE2
Figure 2
As the base current of Q2 is approximately
0.01IE2 , a node equation at C1 yields
Now connecting the resistance R = 2 k between
C1 and E2 (see Fig. 2) both of which at 2.8 V, will
result in zero current through R; thus all voltages
and currents remain unchanged.
ID2 = IC1 − 0.01IE2
Thus,
(b) We next consider the situation with β = 100,
first with R disconnected. The circuit is shown in
Fig. 3 below.
0.05IE2 = IC1 − 0.01IE2
⇒ 0.06IE2 = IC1
Once again we observe that VE1 = V1 , thus
IE2 =
IE1 × 2 = ID1 × 40
ID2 = 0.05 × 20.13 = 1 mA
⇒ ID1 = 0.05IE1
VC1 = 9 − 1 × 2 − 0.7 = 6.3 V
The base current of Q1 is IE1 /101 0.01IE1 .
Thus, the current through the 80-k resistor is
0.05IE1 + 0.01IE1 = 0.06IE1 and
VE2 = 6.3 + 0.7 = 7 V
IC2 = αIE2 = 0.99 × 20.13 = 20 mA
VB1 = VE1 + 0.7 = 2IE1 + 0.7
0.06IE1
IC1
1.21
=
= 20.13 mA
0.06
0.06
VC2 = 20 × 0.1 = 2 V
9 − (2IE1 + 0.7)
9 − VB1
=
=
80
80
Finally, with the resistance R connected between
E1 and C2 , it will conduct a current that we can
initially estimate as
⇒ IE1 = 1.22 mA
9 V
VE 2
D2
Q2
IC1
VB1
ID1 0.05 IE1
100 V2
0.06 IE1
D1
IE 2
2 k
ID2
80 k
0.01IE 2
Q1
0.01IE
IE1
V1
40 k
VE1
2 k
Figure 3
VC2
100 Chapter 4–29
9V
IE 2
100 2 k
80 k
V2 VE2
(ID1 IB1)
(IC1 IB2)
VC1
VB1
D1
ID1
VE2
D2
IC1
Q2
IB2
Q1
IB1
V1
40 k
IC2
I
IE1
VE1
R
VC2
2 k
100 2 k
Figure 4
I=
2.44 − 2
VE1 − VC2
=
= 0.22 mA
R
2
This is a substantial amount compared to
IE1 = 1.22 mA, requiring that we redo the
analysis with R in place. The resulting circuit is
shown in Fig. 4 above.
Denoting the emitter voltage of Q1 , VE1 , and the
current through R as I , the analysis proceeds as
follows:
IC2
= 10.1VE1 − 21.2I
α
ID2 × 2 = IE2 × 0.1
IE2 =
2(0.395VE1 + 1.2I ) = 0.1(10.1VE1 − 21.2I )
⇒ I = 0.05VE2
Voltage drop across 80-k resistor =
(0.03 VE1 + 0.01I ) × 80 = 9 − VE1 − 0.7
Substituting I = 0.05 VE2 gives
V1 = VE1
VE1 = 2.41 V
VE1
V1
=
= 0.025VE1
ID1 =
40
40
VE1
+ I = 0.5VE1 + I
IE1 =
2
IE1
IB1 =
= 0.005VE1 + 0.01I
101
I = 0.12 mA
I80 k = ID1 + IB1 = 0.03VE1 + 0.01I
IC1 = 1.31 mA
VC2 = VE1 − I × 2 = VE1 − 2I
ID1 = 1.09 mA
IC2 = −I +
IB2 =
VC2
= 10VE1 − 21I
0.1
IC2
= 0.1VE1 − 0.21I
101
IC1 = αIE1 = 0.495VE1 + 0.99I
ID2 = IC1 − IB2 = 0.395VE1 + 1.2I
Substituting these quantities in the equations
above gives
VB1 = 2.41 + 0.7 = 3.11 V
IE1 = 1.325 mA
VC1 = 9 − 1.09 × 2 − 0.7 = 6.12 V
VE2 = 6.82 V
9 − 6.82
= 21.8 mA
0.1
= 0.99 × 21.8 = 21.6 mA
IE2 =
IC2
VC2 = 2.17 V
Exercise 5–1
Ex: 5.1
ox
34.5 pF/m
= 8.625 fF/μm2
=
Cox =
tox
4 nm
Similarly, VDS = 1 V results in saturation-mode
operation and ID = 0.25 mA.
μn = 450 cm2 /V · S
Ex: 5.6 VA = VA L = 50 × 0.8 = 40 V
k n = μn Cox = 388 μA/V2
λ=
VOV = (v GS − Vt ) = 0.5 V
1
W
W
= k n VOV ⇒
= 5.15
gDS =
1 k
L
L
L = 0.18 μm, so W = 0.93 μm
Ex: 5.2 Cox =
ox
34.5 pF/m
= 8.6 fF/μm2
=
tox
4 nm
μn = 450 cm2 /V · s
k n = μn Cox = 387 μA/V2
ID =
1 W 2
W
k
V = 0.3 mA,
= 20
2 n L OV
L
∴ V OV = 0.28 V
VDS, min = VOV = 0.28 V, for saturation
1
= 0.025 V−1
VA
VDS = 1 V > VOV = 0.5 V
⇒ Saturation: I D =
1 W 2
k
V (1 + λVDS )
2 n L OV
1
16
× 200 ×
× 0.52 (1 + 0.025 × 1)
2
0.8
= 0.51 mA
VA
40
=
= 80 k
ro =
ID
0.5
ID =
where ID is the value of ID without channel-length
modulation taken into account.
V DS
2V
⇒ IO =
= 0.025 mA
ro =
I O
80 k
Ex: 5.7
5 V
1 W 2
k
V in saturation
2 n L OV
Change in ID is:
Ex: 5.3 ID =
VG
ID
(a) double L, 0.5
VD
(b) double W , 2
(c) double VOV , 22 = 4
Vtp = −1 V
(d) double VDS , no change (ignoring length
modulation)
k p = 60 μA/V2
(e) changes (a)–(d), 4
W
= 10 ⇒ k p = 600 μA/V2
L
(a) Conduction occurs for VSG ≥ |Vtp | = 1 V
Case (c) would cause leaving saturation if
VDS < 2VOV
Ex: 5.4 For saturation v DS ≥ VOV , so VDS must
be changed to 2VOV
ID =
1 W 2
k
V , so ID increases by a factor of 4.
2 n L OV
Ex: 5.5 VOV = 0.5 V
1
VOV =
gDS =
L
1 k
W
1
∴ k n = k n
=
= 2 mA/V2
L
1 × 0.5
W
k n
For v DS = 0.5 V = VOV , the transistor operates in
saturation, and
ID =
1 W 2
k
V = 0.25 mA
2 n L OV
⇒ VG ≤ 5 − 1 = 4 V
(b) Triode region occurs for VDG ≥ |Vtp | = 1 V
⇒ VD ≥ VG + 1
(c) Conversely, for saturation
VDG ≤ |Vtp | = 1 V
⇒ VD ≤ VG + 1
(d) Given λ ∼
=0
ID =
1 W
k
|VOV |2 = 75 μA
2 pL
∴ |VOV | = 0.5 V = VSG − |Vtp |
⇒ VSG = |VOV | + |Vtp | = 1.5 V
VG = 5 − |VSG | = 3.5 V
VD ≤ VG + 1 = ≤4.5 V
Exercise 5–2
(e) For λ = −0.02 V−1 and |VOV | = 0.5 V,
ID = 75 μA and ro =
1
= 667 k
|λ|ID
(f) At VD = 3 V, VSD = 2 V
1 W
k
|VOV |2 (1 + |λ||VSD |)
2 nL
= 75 μA (1.04) = 78 μA
ID =
Saturation mode (v GD = 0 < Vtn ) :
VD = 0.7 V = 1.8 − ID RD
1
W
μ Cox (VD − Vtn )2 = 0.032 mA
2 n
L
1.8 − 0.7
∴R=
= 34.4 k
0.032 mA
ID =
Ex: 5.10
At VD = 0 V, VSD = 5 V
1.8 V
ID = 75 μA (1.10) = 82.5 μA
ro =
VDS
3V
= 667 k
=
ID
4.5 μA
R2
R1
which is the same value found in (c).
Ex: 5.8
1
1
60
W 2
⇒ 0.3 = ×
ID = μn Cox VOV
2
L
2 1000
120 2
V ⇒
×
3 OV
VOV = 0.5 V ⇒ VGS = VOV + Vt = 0.5 + 1
= 1.5 V
VS = −1.5 V ⇒ RS =
Q1
Since Q2 is identical to Q1 and their VGS values
are the same,
ID2 = ID1 = 0.032 mA
For Q2 to operate at the triode–saturation
boundary, we must have
VS − VSS
ID
VD2 = VOV = 0.2 V
−1.5 − (−2.5)
0.3
RS = 3.33 k
=
RD =
Q2
∴ R2 =
VDD − VD
2.5 − 0.4
= 7 k
=
ID
0.3
1.8 V − 0.2 V
= 50 k
0.032 mA
Ex: 5.11 RD = 12.4 × 2 = 24.8 k
VGS = 5 V, assume triode region:
⎫
1 2 ⎪
W
ID = k n
(VGS − Vt )VDS − VDS ⎪
⎬
L
2
⇒
⎪
⎪
VDD − VDS
⎭
ID =
R
V2
5 − VDS
= 1 × (5 − 1)VDS − DS
24.8
2
Ex: 5.9
1.8 V
R
VD
2
− 8.08VDS + 0.4 = 0
⇒ VDS
⇒ VDS = 0.05 V < VOV ⇒ triode region
ID =
5 − 0.05
= 0.2 mA
24.8
Ex: 5.12 As indicated in Example 5.6,
Vtn = 0.5 V
μn Cox = 0.4 mA/V2
VD ≥ VG − Vt for the transistor to be in the
saturation region.
VDmin = VG − Vt = 5 − 1 = 4 V
0.72 μm
W
=
= 4.0
L
0.18 μm
ID = 0.5 mA ⇒ RDmax =
λ=0
=
10 − 4
= 12 k
0.5
VDD − VDmin
ID
Exercise 5–3
2.5 V
Ex: 5.13
ID = 0.32 mA =
1 W 2
1
2
k n VOV = × 1 × VOV
2 L
2
QN
⇒ VOV = 0.8 V
VGS = 0.8 + 1 = 1.8 V
VI 2.5 V
VO
VG = VS + VGS = 1.6 + 1.8 = 3.4 V
RG2 =
3.4
VG
=
= 3.4 M
I
1 μA
RG1 =
5 − 3.4
= 1.6 M
1 μA
RS =
10 k
VS
= 5 k
0.32
VD = 3.4 V, then RD =
IDN =
5 − 3.4
= 5 k
0.32
RL
1
× 1(2.5 − VO − 1)2
2
IDN = 0.5(1.5 − VO )2
Also: VO = RL IDN = 10IDN
IDN = 0.5(1.5 − 10IDN )2
Ex: 5.14
2
⇒ 100IDN
− 32IDN + 2.25 = 0 ⇒ IDN
1.8 V
= 0.104 mA
RD
IDP = 0, V O = 10 × 0.104 = 1.04V
ID
VO
IDP
QP
10 k
–2.5 V
Vtp = −0.4 V
–2.5 V
k p = 0.1 mA/V2
W
10 μm
=
⇒ k p = 5.56 mA/V2
L
0.18 μm
VSG = |Vtp | + |VOV |
= 0.4 + 0.6 = 1 V
VS = +1 V
Since VDG = 0, the transistor is operating in
saturation, and
1
2
ID = k p VOV
= 1 mA
2
1.8 − 1
∴ R=
= 0.8 k = 800 1
Ex: 5.15 v I = 0: since the circuit is perfectly
symmetrical, v O = 0 and therefore VGS = 0,
which implies that the transistors are turned off
and IDN = IDP = 0.
v I = 2.5 V: if we assume that the NMOS is
turned on, then v O would be less than 2.5 V, and
this implies that PMOS is off (VSGP < 0) .
IDN =
1 W
k
(VGS − Vt )2
2 nL
VI = −2.5 V: Again if we assume that Qp is
turned on, then VO > −2.5 V and VGS1 < 0,
which implies that the NMOS QN is turned off.
IDN = 0
Because of the symmetry,
IDP = 0.104,
VO = −IDP × 10 k
= −1.04 V
√
√
0.7 + 3 − 0.7
Ex: 5.16 Vt = 0.8 + 0.4
= 1.23 V
Ex: 5.17 v DSmin = v GS + |Vt |
=1+2=3V
1
× 2 [1 − (−2)]2
2
= 9 mA
ID =
Chapter 5–1
5.1 Cox = 9 fF/μm2 , VOV = 0.2 V
VGS
(V)
L = 0.36 μm, VDS = 0 V
W = 3.6 μm
Q = Cox .W .L.VOV = 2.33 fC
5.2 k n = μn Cox
C/V
C 1
m2 F
F
=
=
=
=
V · s m2
V·s
V·s
s V2
=
VOV
(V)
gDS
rDS
(mA/V) ()
0.5
0
0
∞
1.0
0.5
2.5
400
1.5
1.0
5.0
200
2.0
1.5
7.5
133
2.5
2.0
10
100
A
V2
Since k n = k n W/L and W/L is dimensionless, k n
has the same dimensions as k n ; that is, A/V2 .
5.5 The transistor size will be minimized if W/L
is minimized. To start with, we minimize L by
using the smallest feature size,
5.3 With v DS small, compared to VOV ,
Eq. (5.13a) applies:
L = 0.18 μm
rDS
1
=
W
(μn Cox )
(VOV )
L
rDS =
1
k n (W/L) (v GS − Vt )
rDS =
1
k n (W/L) v OV
(a) VOV is doubled → rDS is halved. factor = 0.5
(b) W is doubled → rDS is halved. factor = 0.5
(c) W and L are doubled → rDS is unchanged.
factor = 1.0
(d) If oxide thickness tox is halved, and
ox
tox
Cox =
Two conditions need to met for v OV and rDS
Condition 1:
rDS,1 =
= 250 ⇒ (W/L) v OV,1 = 10
then Cox is doubled. If W and L are also halved,
rDS is halved, factor = 0.5.
Condition 2:
rDS,2 =
5.4 k n = 5 mA/V2 , Vtn = 0.5 V,
iD = k n (v GS − Vt )v DS = k n v OV v DS
1
= k n v OV
rDS
iD
500 A
375 A
250 A
125 A
0
1
400 × 10−6 (W/L) v OV,2
= 1000 ⇒ (W/L) v OV,2 = 2.5
small v DS
gDS =
1
400 × 10−6 (W/L)v OV,1
vGS 2.5 V
vGS 2.0 V
If condition 1 is met, condition 2 will be met since
the over-drive voltage can always be reduced to
satisfy this requirement. For condition 1, we want
to decrease W/L as much as possible (so long as it
is greater than or equal to 1), while still meeting
all of the other constraints. This requires our
using the largest possible v GS,1 voltage.
v GS,1 = 1.8 V so v OV,1 = 1.8 − 0.5 = 1.3 V, and
W/L =
vGS 1.5 V
vGS 1.0 V
vGS 0.5 V
vDS
50 mV
10
10
=
= 7.69
v OV ,1
1.3
Condition 2 now can be used to find v GS,2
v OV ,2 =
2.5
2.5
=
= 0.325
W/L
7.69
⇒ v GS,2 = 0.825 V ⇒ 0.825 V ≤ v GS ≤ 1.8 V
Chapter 5–2
∂iD ∂v DS v DS = VDS
−1
∂
1
=
k n VOV v DS − v 2DS
∂v DS
2
∂ 2 −1
∂
= kn
v DS
(v OV v DS ) − 1/2
∂v DS
∂v DS
−1
1
= k n VOV − · 2VDS
2
1
=
k n (VOV − VDS )
1
If VDS = 0 ⇒ rds =
k n VOV
1.25
If VDS = 0.2VOV ⇒ rds =
VOV
1
If VDS = 0.5VOV ⇒ rds =
k n (VOV − 0.5VOV )
2
= 1/k n (0.5VOV ) =
k n VOV
1
If VDS = 0.8VOV ⇒ rds =
k n (VOV − 0.8VOV )
5
= 1/k n (0.2VOV ) =
k n VOV
If VDS = VOV ,
1
⇒∞
rds =
0
5.6 rds = 1/
VGS = 0.72 V
VDS ≥ 0.22 V
(c) gDS =
∴ VOV = 0.47 V.
VGS = 0.97 V.
5.9 Vtp = −0.7 V
(a) |VSG | = |Vtp | + |VOV |
= 0.7 + 0.4 = 1.1 V
⇒ VG = −1.1 V
(b) For the p-channel transistor to operate in
saturation, the drain voltage must not exceed the
gate voltage by more than |Vtp |. Thus
v Dmax = −1.1 + 0.7 = −0.4 V
Put differently, VSD must be at least equal to |VOV |,
which in this case is 0.4 V. Thus v Dmax = −0.4 V.
(c) In (b), the transistor is operating in saturation,
thus
ID =
5.7 VDS sat = VOV
VOV = VGS − Vt = 1 − 0.5 = 0.5 V
⇒ VDS sat = 0.5 V
2
1 4 mA
×
× (0.5 V)
2
2
V
iD = 0.5 mA
iD =
5.8 Lmin = 0.25 μm
tox = 6 nm
m2
cm2
= 460 × 10−4
V·s
V·s
ox
34.5 pF/m
(a) Cox =
=
tox
6 nm
pF
F
= 5.75 × 10−3 2
m
μm2
μn = 460
k n = μn Cox = 265 μA/V2
20
W
=
, k n = 21.2 mA/V2
L
0.25
∴ 0.5 mA = ID =
VOV = 0.22 V
1
k p |VOV |2
2
1
× k p × 0.42
2
0.5 =
⇒ k p = 6.25 mA/V2
In saturation:
1 W
1
2
2
= k n VOV
VOV
iD = k n
2
L
2
(b) For
1
= k n VOV
100 1
2
k n VOV
2
For VD = −20 mV, the transistor will be
operating in the triode region. Thus
1
ID = k p v SD |VOV | − v 2SD
2
1
= 6.25 0.02 × 0.4 − (0.02)2
2
= 0.05 mA
For VD = −2 V, the transistor will be operating in
saturation, thus
ID =
1
1
k p |VOV |2 = × 6.25 × 0.42 = 0.5 mA
2
2
5.10 iD =
1 W
k
|VOV |2
2 nL
For equal drain currents:
μn Cox
Wp
Wn
= μp Cox
L
L
Wp
μ
1
= 2.5
= n =
Wn
μp
0.4
k n = μn Cox
Chapter 5–3
5.11 For small v DS , iD k n
1
= 2.645 1 × 2 − × 1 = 4 mA
2
and
v DS = 1.5 V
(b) v GS = 2 V
W
(VGS − Vt )VDS ,
L1
1
W
k n (VGS − Vt )
L
1
=
100 × 10−6 × 20 × (5 − 0.7)
rDS = 116.3 VDS = rDS × iD = 116.3 mV
rDS =
VDS
=
iD
v OV = v GS − Vt = 2 − 0.5 = 1.5 V
Thus, v DS = v OV ⇒ saturation region,
1
1
iD = k n v 2OV = × 2.645 × 1.52
2
2
= 3 mA
For the same performance of a p-channel device:
Wp
Wp
μ
Wn
= n = 2.5 ⇒
=
× 2.5
Wn
μp
L
L
(c) v GS = 2.5 V
v OV = 2.5 − 0.5 = 2 V
5.12 tox = 6 nm, μn = 460 cm2 /V·s,
Vt = 0.5 V, and W/L = 10.
k n = μn Cox
3.45 × 10−11
W
= 460×10−4 ×
×10
L
6 × 10−9
v OV = 2.5 − 0.5 = 2 V
= 2.645 mA/V
2
(a) v GS = 2.5 V
Thus, v DS > v OV ⇒ saturation region,
1
iD = k n v 2OV
2
1
= × 2.645 × 22 = 5.3 mA
2
v DS = 1 V
and
v OV = v GS − Vt = 2 V
Thus v DS < v OV ⇒ triode region,
1
ID = k n v DS v OV − v 2DS
2
5.13 See Table below.
This table belongs to 5.13.
L (μm)
0.5
0.25
0.18
0.13
tox (nm)
fF
Cox
μm2
ox = 34.5 pF/m
μA
k n
V2
(μn = 500 cm2 /V·s)
mA
kn
V2
W
= 10
for
L
A(μm2 )
W
for
= 10
L
VDD (V)
10
5
3.6
2.6
3.45
6.90
9.58
13.3
173
345
479
665
1.73
3.45
4.79
6.65
2.50 0.625 0.324 0.169
Vt (V)
ID (mA)
for VGS = VDS = VDD ,
P(mW)
P mW
A μm2
Devices
Chip
ID =
P = VDD ID
1
k n (VDD − Vt )2
2
v DS = 0.2 V
Thus, v DS < v OV ⇒ triode region,
1
iD = k n v DS v OV − v 2DS
2
1 2
= 2.645[0.2 × 2 − 0.2 ] = 1 mA
2
(d) v GS = v DS = 2.5 V
Wp
= 50
L
= 20 × 2.5 ⇒
and
5
2.5
1.8
1.3
0.7
0.5
0.4
0.4
16
6.90
4.69
2.69
80
17.3
8.44
3.50
32
27.7
26.1
20.7
n
4n
7.72n 14.8n
Chapter 5–4
This figure belongs to 5.14, part (a).
Fig. 1
1
5.14 iD = k n v OV v DS − v 2DS
2
1
iD
= v OV v DS − v 2DS
kn
2
(1)
Figure 1 shows graphs for iD /k n versus v DS for
various values of v OV . Since the right-hand side
of Eq. (1) does not have any MOSFET
parameters, these graphs apply for any n-channel
MOSFET with the assumption that λ = 0. They
also apply to p-channel devices with v DS replaced
by v SD , k n by k p , and v OV with |v OV |. The slope of
each graph at v DS = 0 is found by differentiating
Eq. (1) relative to v DS with v OV = VOV and then
substituting v DS = 0. The result is
d (iD /k n ) = VOV
d v DS v DS =0, v OV =VOV
Figure 1 shows the tangent at v DS = 0 for the
graph corresponding to v OV = VOV 3 . Observe that
1 2
it intersects the horizontal line iD /k n = VOV
3 at
2
1
v DS = VOV 3 . Finally, observe that the curve
2
representing the boundary between the triode
region and the saturation region has the
equation
iD /k n =
iD /kn
(V2)
1 2
v
2 DS
Figure 2 shows the graph for the relationship
1
iD /kn v 2OV
2
0 1
V
VOV
2 OV
vOV
(V)
Fig. 2
Here also observe that this relationship (and
graph) is universal and represents any MOSFET.
The slope at v OV = VOV is
d (iD /k n ) = VOV
d v OV v OV =VOV
Replacing k n by k p and v OV by |v OV | adapts this
graph to PMOS transistors.
5.15 For triode-region operation with v DS small,
iD k n (v GS − Vt )v DS
Thus
1
iD /k n = v 2OV
2
rDS ≡
which describes the MOSFETs operation in the
saturation region, that is,
1=
v DS ≥ v OV
Slope VOV
1 2
V
2 OV
v DS
1
=
iD
k n (v GS − Vt )
1
1
=
k n (1.2 − 0.8)
0.4 k n
⇒ k n = 2.5 mA/V
Chapter 5–5
1
2.5(VGS − 0.8)
1
0.2 =
2.5(VGS − 0.8)
rDS =
5.19 iD = k n (v GS − Vt )v DS
(k)
⇒ VGS = 2.8 V
For a device with twice the value of W, k n will be
twice as large and the resistance values will be
half as large: 500 and 100 , respectively.
= 0.4 mA/V
and
⇒
Dividing Eq. (2) by Eq. (1), we have
2=
For k n = 50 μA/V2
W
= 20
L
Vt = 0.5 V
W
1
× 0.4 ×
× (1.8 − 0.5)2
2
L
For v GS = 2 V and v DS = 0.1 V,
1
iD = k n (v GS − Vt )v DS − v 2DS
2
1
= 1 (2 − 0.5) × 0.1 − × 0.12
2
= 0.145 mA = 145 μA
For v GS = 2 V, pinch-off will occur for
W
= 5.92
L
v DS = v GS − Vt = 2 − 0.5 = 1.5 V
For L = 0.18 μm
and the resulting drain current will be
W = 1.07 μm
iD =
5.18 For VGS = VDS = 1 V, the MOSFET is
operating in saturation,
=
1
k n (VGS − Vt )2
2
0.4 =
1
k n (1 − Vt )2
2
(1)
0.1 =
1
k n (0.8 − Vt )2
2
(2)
Dividing Eq. (1) by Eq. (2) and taking square
roots gives
1 − Vt
0.8 − Vt
⇒ Vt = 0.6 V
Substituting in Eq. (1), we have
0.4 =
1
k n × 0.42
2
⇒ k n = 5 mA/V2
1
k n (v GS − Vt )2
2
1
× 1 × (2 − 0.5)2
2
= 1.125 mA
ID =
2=
1.5 − Vt
1 − Vt
⇒ k n = 1000 μA/V2
For v GS = v DS = 1.8 V, the MOSFET is
operating in saturation. Thus, to obtain
ID = 2 mA, we write
2=
(2)
25 = k n × 0.5 × 0.05
VGS = 0.5 + 0.5 = 1 V
5.17
50 = k n (1.5 − Vt ) × 0.05
Substituting in Eq. (1) yields
VGS = 0.5 + 0.25 = 0.75 V
1
2
ID = 0.2 = × 1.6 × VOV
2
⇒ VOV = 0.5 V and VDS ≥ 0.5 V
2
(1)
⇒ Vt = 0.5 V
5.16 Vtn = 0.5 V, k n = 1.6 mA/V2
1
2
ID = 0.05 = × 1.6 × VOV
2
⇒ VOV = 0.25 V and VDS ≥ 0.25 V
k n
25 = k n (1 − Vt ) × 0.05
5.20 For the channel to remain continuous,
v DS ≤ v GS − Vt
Thus for v GS = 1.0 V to 1.8 V and Vt = 0.4,
v DS ≤ 1 − 0.4
That is, v DSmax = 0.6 V.
W
20
=
= 20 k n = 100 μA/V2
L
1
W
k n = k n
= 100 × 20 = 2000 μA/V2
L
5.21
= 2 mA/V2
Chapter 5–6
5.23
For operation as a linear resistance,
iD = k n (v GS − Vt )v DS
iD
and
rDS ≡
=
vDS
v DS
1
=
iD
k n (v GS − Vt )
1
2(v GS − 0.8)
At v GS = 1.0 V,
rDS =
v DS = v GS
1
= 2.5 k
2(1 − 0.8)
iD =
At v GS = 4.8 V,
rDS =
1
= 0.125 k
2(4.8 − 0.8)
1
k n (v DS − Vt )2
2
∴ v DS =
2iD
+ Vt
kn
Thus, rDS will vary in the range of 2.5 k to
125 .
(a) If W is halved, k n will be halved and rDS will
vary in the range of 5 k to 250 .
(b) If L is halved, k n will be doubled and rDS will
vary in the range of 1.25 k to 62.5 .
(c) If both W and L are halved, k n will remain
unchanged and rDS will vary in the original range
of 2.5 k to 125 .
5.22 (a) Refer to Fig. P5.22. For
saturation-mode operation of an NMOS
transistor, v DG ≥ −Vtn ; thus v DG = 0 results in
saturation-mode operation. Similarly, for a
p-channel MOSFET, saturation-mode operation is
obtained for v GD ≥ −|Vtp |, which includes
v GD = 0. Thus, the diode-connected MOSFETs of
Fig. P5.22 have the i−v relationship
1
W
i = k
(v − |Vt |)2
(1)
2
L
where k represents
in the PMOS case.
k n
in the NMOS case and
k p
(b) If either of the MOSFETs in Fig. P5.22 is
biased to operate at v = |Vt | + |VOV |, then its
incremental resistance r at the bias point can be
obtained by differentiating Eq. (1) relative to v
and then substituting v = |Vt | + |VOV | as follows:
W
∂i
= k
(v − |Vt |)
∂v
L
∂i W
=
k
VOV
∂v v =|Vt |+VOV
L
∂i
W
r=1
Q.E.D
=1
k VOV
∂v
L
5.24 VDS = VD – VS
VGS = VG − VS
VOV = VGS − Vt = VGS − 1.0
According to Table 5.1, three regions are possible.
Case VS
VG
VD
VGS VOV VDS Region of
operation
a
+1.0 +1.0 +2.0
b
+1.0 +2.5 +2.0 +1.5 +0.5 +1.0
Sat.
c
+1.0 +2.5 +1.5 +1.5 +0.5 +0.5
Sat.
d
+1.0 +1.5
Sat.∗
e
0
0
0
–1.0 +1.0
+0.5 –0.5 –1.0
+2.5 1.0 +2.5 +1.5 +1.0
f
+1.0 +1.0 +1.0
g
–1.0
0
h
–1.5
0
i
–1.0
0
j
+0.5 +2.0 +0.5 +1.5 +0.5
Cutoff
Triode
0
–1.0
0
Cutoff
0
+1.0
0
+1.0
Sat.
0
+1.5 +0.5 +1.5
Sat.
+1.0 +1.0
0
+2.0
Sat.
0
Triode
∗ With the source and drain interchanged.
Chapter 5–7
5.25 The cutoff–saturation boundary is
determined by v GS = Vt , thus v GS = 0.4 V at the
boundary.
The saturation–triode boundary is determined by
v GD = Vt , and v DS = VDD = 1 V, and since
v GS = v GD + v DS , one has
v GS = 0.4 + 1.0 = 1.4 V at the boundary.
5.27 ro =
VA
20
=
, 0.1 mA ≤ iD ≤ 1 mA
iD
iD
⇒ 20 k ≤ ro ≤ 200 k
ro =
v DS
v DS
1
⇒ iD =
=
iD
ro
ro
At iD = 0.1 mA, iD = 5 μA,
iD
= 5%
iD
At iD = 1 mA, iD = 50 μA,
iD
= 5%
iD
5.28
iD
0.52 mA
0.50 mA
vDS
1V
5.26 (a) Let Q1 have a ratio (W/L) and Q2 have a
ratio 1.03 (W/L). Thus
ID1 =
ID2
1 W
kn
(1 − Vt )2
2
L
W
1
× 1.03 × (1 − Vt )2
= k n
2
L
Thus,
ID2
= 1.03
ID1
That is, a 3% mismatch in the W/L ratios results
in a 3% mismatch in the drain currents.
(b) Let Q1 have a threshold voltage Vt = 0.6 V
and Q2 have a threshold voltage
Vt + Vt = 0.6 + 0.01 = 0.61 V.
Thus
ID1
1
W
= k n
(1 − 0.6)2
2
L
ID2 =
1 W
kn
(1 − 0.61)2
2
L
and
ID2
(1 − 0.61)2
=
= 0.95
ID1
(1 − 0.6)2
That is, a 10-mV mismatch in the threshold
voltage results in a 5% mismatch in drain currents.
ro =
2V
v DS 1
= 50 k
=
iD v GS const.
0.02
VA ∼
= ID ro = 0.5 × 50 = 25 V
λ=
1
= 0.04 V−1
VA
5.29 VA = VA L, where VA is completely process
VA
dependent. Also, ro = . Therefore, to achieve
iD
desired ro (which is 5 times larger), we should
increase L (L = 5 × 1 = 5 μm).
To keep ID unchanged, the
unchanged. Therefore:
W
ratio must stay
L
W
is kept at 10)
L
VA = ro iD = 100 k × 0.2 mA = 20 V (for the
standard device)
W = 5 × 10 = 50 μm (so
VA = 5 × 20 = 100 V (for the new device)
5.30 L = 1.5 μm = 3× minimum. Thus
0.03 V−1
= 0.01 V−1
3
If v DS is increased from 1 V to 5 V, the drain
current will change from
λ=
ID = 100 μA = ID (1 + λ × 1) = 1.01 ID
to
ID +
ID = ID (1 + λ × 5) = 1.05 ID
Chapter 5–8
where ID is the drain current without
channel-length modulation taken into account.
Thus
5.34 Refer to the circuit in Fig. P5.26 and let
VD1 = 2 V and VD2 = 2.5 V. If the two devices
are matched,
1
2
ID1 = k n (1 − Vt )2 1 +
2
VA
1
2.5
ID2 = k n (1 − Vt )2 1 +
2
VA
1
2 0.5
ID = ID2 − ID1 = k n (1 − Vt )
2
VA
100
1.01
ID =
and
100 +
ID = 1.05 ID =
1.05 × 100
= 104 μA
1.01
ID = 4 μA or 4%
⇒
To reduce ID by a factor of 2, we need to reduce
λ by a factor of 2, which can be obtained by
doubling the channel length to 3 μm.
0.5
ID
0.01 =
1
VA
2
k n (1 − Vt )
2
⇒ VA = 50 V (or larger to limit the mismatch in
ID to 1%).
5.31 VA = VA L = 20 × 1.5 = 30 V
If VA = 100 V/μm, the minimum required
channel length is 0.5 μm.
1
1
=
= 0.033 V−1
VA
30
1
W
2
ID = k n
(1 + λVDS )
VOV
2
L
15
1
× 0.52 (1 + 0.033 × 2)
= × 0.2 ×
2
1.5
|v GS | = 3 V, |v DS | = 4 V
= 0.267 mA
|v DS | > |VOV | ⇒ saturation mode
λ=
ro =
1 k
2 n
5.35 Vtp = 0.8 V, |VA | = 40 V
iD = 3 mA
|VOV | = |v GS | − |Vtp | = 2.2 V
v GS = −3 V
VA
30
=
1
15
W
2
× 0.2 ×
× 0.52
VOV
2
1.5
L
v SG = +3 V
v DS = −4 V
= 120 k
ID =
v SD = 4 V
VDS
1V
=
= 0.008 mA
ro
120 k
Vtp = −0.8 V
VA = −40 V
λ = −0.025 V−1
1
iD = k p (v GS − Vtp )2 (1 + λ v DS )
2
1
3 = k p [−3 − (−0.8)]2 (1 − 0.025 × −4)
2
5.32 Quadrupling W and L keeps the current ID
unchanged. However, the quadrupling of L
increases VA by a factor of 4 and hence increases
ro by a factor of 4.
Halving VOV results in decreasing ID by a factor
of 4. Thus, this alone increases ro by a factor of 4.
The overall increase in ro is by a factor of
4 × 4 = 16.
⇒ k p = 1.137 mA/V2
5.36 PMOS with Vtp = –1 V
Case VS VG
VD
5.33
NMOS
1
2
−1
3
−1
4
−1
−1
a
+2 +2
0
0
0
2
Cutoff
b
+2 +1
0
+1
0
2
Cutoff–Sat.
c
+2
0
0
+2
1
2
Sat.
+1
+2
1
1
Sat–Triode
+1.5 +2
1
λ
0.05 V
VA
20 V
50 V
10 V
100 V
d
+2
0
ID
0.5 mA
2 mA
0.1 mA
0.2 mA
e
+2
0
ro
40 k
25 k
100 k
500 k
f
+2
0
0.02 V
0.1 V
0.01 V
VSG |VOV | VSD Region of
operation
+2
+2
1
0.5 Triode
0
Triode
Chapter 5–9
5.37
VGD ≥ − 1.5 V
3 V
Case c –
vG
200
(2 − |Vt |)2
=
⇒ |Vt | = 1.0,
800
(3 − |Vt |)2
VGD ≥ − 1.0 V
1 V
∴ sat
∴ sat
Case d
1
k n (2 − Vt )2
72
sat
2
=
1 2
triode
270
k n (4 − Vt ) VDS − VDS
2
Vtp = −0.5 V
(after failing assumption that both cases are
sat.)
v G = +3 V → 0 V
As v G reaches +2.5 V, the transistor begins to
conduct and enters the saturation region, since
v DG will be negative. The transistor continues to
operate in the saturation region until v G reaches
0.5 V, at which point v DG will be 0.5 V, which is
equal to |Vtp |, and the transistor enters the triode
region. As v G goes below 0.5 V, the transistor
continues to operate in the triode region.
5.39 Refer to the circuits in Fig. P5.39.
(a) V1 = VDS = VGS = 1 V
(b) V2 = +1 − VDS = 1 − 1 = 0 V
(c) V3 = VSD = VSG = 1 V
(d) V4 = +1.25 − VSG = 1.25 − 1 = 0.25 V
5.38 Case a, assume, sat,
Now place a resistor R in series with the drain. For
the circuits in (a) and (b) to remain in saturation,
VD must not fall below VG by more than Vt .
Thus,
100
(1 − Vt )2
⇒ Vt = 0.5,
=
400
(1.5 − Vt )2
VGD ≤ Vt
IR ≤ Vt
∴ sat;
Rmax =
Case b — same procedure, except use
VSG and VSD .
0.5
Vt
=
= 5 k
I
0.1
For the circuits in (c) and (d) to remain in
saturation, VD must not exceed VG by more than
|Vt |. Thus
50
(2 − 1Vt 1)2
⇒ |Vt | = 1.5,
=
450
(3 − 1Vt 1)2
This table belongs to 5.38.
Case Transistor
a
b
c
d
1
2
3
4
VS
VG
VD
ID
(V) (V)
(V)
(μA)
0
1
2.5
100
0
1.5
2.5
400
5
3
–4.5
50
5
2
–0.5
450
5
3
4
200
5
2
0
800
–2
0
0
72
–4
0
–3
270
Type
NMOS
Mode
Sat.
W
L
(μ A/V2 )
(V)
800
0.5
400
–1.5
400
–1
100
+0.8
μCox
Vt
Sat.
PMOS
Sat.
Sat.
PMOS
Sat.
Sat.
NMOS
Sat.
Triode
Chapter 5–10
IR ≤ |Vt |
Since VDG > 0, the MOSFET is in saturation.
which yields Rmax = 5 k.
Now place a resistor RS in series with the
MOSFET source. The voltage across the current
source becomes
W 2
1
μn Cox VOV
2
L
5
1
2
× VOV
0.1 = × 0.4 ×
2
0.4
⇒ VOV = 0.2 V
(a) VCS = 2.5 − VDS − IRS
VGS = Vt + VOV = 0.5 + 0.2 = 0.7
ID =
(1)
To keep VCS at least at 0.5 V, the maximum RS
can be found from
VS = 0 − VGS = −0.7 V
RS =
VS − (−1)
−0.7 + 1
= 3 k
=
ID
0.1
RD =
0.7
1 − VD
1 − 0.3
=
= 7 k
=
ID
0.1
0.1
0.5 = 2.5 − 1 − 0.1 × RSmax
⇒ RSmax = 10 k
V1 = 2.5 − 0.5 = 2 V
(b) VCS = 1 − VDS − IRS − (−1.5)
5.41
= 2.5 − VDS − IRS
1 V
which is identical to Eq. (1). Thus
ID
RSmax = 10 k
RD
V2 = −1.5 + 0.5 = −1 V
0.2 V
(c) VCS = 2.5 − IRS − VSD
VGS 0.6 V
which yields
0.6 V
RSmax = 10 k
RS
V3 = 2.5 − 0.5 = 2 V
(d) VCS = 1.25 − IRS − VSD − (−1.25)
1 V
= 2.5 − VSD − IRS
which yields
RSmax = 10 k
V4 = −1.25 + 0.5 = −0.75 V
5.40
1 V
ID 0.1 mA
RD
RS =
VD 0.3 V
0.1 mA
VS
RS
1 V
Since VDG > 0, the MOSFET is operating in
saturation. Thus
1
ID = k n (VGS − Vt )2
2
1
= × 4 × (0.6 − 0.4)2
2
= 0.08 mA
0.8
1 − VD
1 − 0.2
=
= 10 k
=
RD =
ID
0.08
0.08
−0.6 − (−1)
−0.6 + 1
=
= 5 k
ID
0.08
For ID to remain unchanged from 0.08 mA, the
MOSFET must remain in saturation. This in turn
can be achieved by ensuring that VD does not fall
below VG (which is zero) by more than Vt (0.4 V).
Thus
1 − ID RDmax = −0.4
RDmax =
1.4
= 17.5 k
0.08
Chapter 5–11
5.43
5.42
1.3 V
VDD 1.8 V
RD
ID2
ID1
ID
R2
R
VD2
Q2
VGS
Q1
VD1
1 W
k
(VGS − Vt )2
2 nL
W
1
= × 0.4 × (1.3 − 0.4)2
2
L
W
= 0.162
L
ID =
(a) ID1 = 50 μA
0.05 =
1
1.44 2
× 0.4 ×
V
2
0.36 OV
⇒ VOV = 0.25 V
W
RD
L
VGS1 = Vt + VOV
VD = 1.3 − ID RD = 1.3 − 0.162
= 0.5 + 0.25 = 0.75 V
For the MOSFET to be at the edge of saturation,
we must have
VD1 = VGS1 = 0.75 V
VDD − VD1
1.8 − 0.75
= 21 k
R=
=
ID1
0.05
(b) Note that both transistors operate at the same
VGS and VOV , and
ID2 = 0.5 mA
But
ID2 =
1
W2
2
kn
VOV
2
L2
0.5 =
1
W2
× 0.4 ×
× 0.252
2
0.36
VD = VOV = 1.3 − 0.4 = 0.9
Thus
0.9 = 1.3 − 0.162
⇒
W
RD
L
W
RD 2.5 k
L
Q.E.D
5.44
1.3 V
RD
0.1 mA
VD
⇒ W2 = 14.4 μm
which is 10 times W1 , as needed to provide
ID2 = 10ID1 . Since Q2 is to operate at the edge of
saturation,
VDS2 = VOV
Thus,
VOV = VGS − Vt
VD2 = 0.25 V
= 1.3 − 0.4 = 0.9
and
To operate at the edge of saturation, we must have
R2 =
=
VDD − VD2
ID2
1.8 − 0.25
= 3.1 k
0.5
VD = VOV = 0.9 V
Thus,
RD =
1.3 − 0.9
= 4 k
0.1
Chapter 5–12
5.45
VDD 1.8 V
VD
ID
5.47 Refer to the circuit in Fig. P5.47. All three
transistors are operating in saturation with
ID = 90 μA. For Q1 ,
ID =
1
W1
μn Cox
(VGS1 − Vt )2
2
L1
90 =
W1
1
× 90 ×
(0.8 − 0.5)2
2
L1
R
⇒
W1
= 22.2
L1
W1 = 22.2 × 0.5 = 11.1 μm
ID = 180 μA
R=
and
VD = 1 V
1
VD
=
= 5.6 k
ID
0.18
Transistor is operating in saturation with
|VOV | = 1.8 − VD − |Vt | = 1.8 − 1 − 0.5 = 0.3 V:
ID =
1 W
k
|VOV |2
2 pL
180 =
⇒
W
1
× 100 ×
× 0.32
2
L
W
= 40
L
W = 40 × 0.18 = 7.2 μm
5.46 Refer to Fig. P5.46. Both Q1 and Q2 are
operating in saturation at ID = 0.5 mA. For Q1 ,
ID =
0.5 =
⇒
1
W1 2
μn Cox
V
2
L1 OV 1
W1 = 16 × 0.25 = 4 μm
For Q2 , we have
1
W2
2
ID = μn Cox
VOV
2
2
L2
⇒
ID =
1
W2
μn Cox
(VGS2 − Vt )2
2
L2
90 =
W2
1
× 90 ×
(1.5 − 0.8 − 0.5)2
2
L2
⇒
W2
= 50
L2
W2 = 50 × 0.5 = 25 μm
For Q3 ,
ID =
1
W3
μn Cox
(VGS3 − Vt )2
2
L3
90 =
1
W3
× 90 ×
(2.5 − 1.5 − 0.5)2
2
L3
⇒
W3
=8
L3
W3 = 8 × 0.5 = 4 μm
W1
1
× 0.25 ×
(1 − 0.5)2
2
L1
W1
= 16
L1
0.5 =
For Q2 ,
W2
1
× 0.25 ×
(1.8 − 1 − 0.5)2
2
L2
W2
= 44.4
L2
5.48 Refer to the circuits in Fig. 5.24
(page 338):
VGS = 5 − 6ID
ID =
=
1 W
k
(VGS − Vt )2
2 nL
1
× 1.5 × (5 − 6ID − 1.5)2
2
which results in the following quadratic equation
in ID :
36ID2 − 43.33ID + 12.25 = 0
W2 = 44.4 × 0.25 = 11.1
The physically meaningful root is
2.5 − 1.8
= 1.4 k
R=
0.5
ID = 0.45 mA
Chapter 5–13
This should be compared to the value of 0.5 mA
found in Example 5.6. The difference of about
10% is relatively small, given the large variations
in k n and Vt (50% increase in each). The new
value of VD is
5.50
VDD
iD
R
VD = VDD − RD ID = 10 − 6 × 0.45 = +7.3 V
vO
as compared to +7 V found in Example 5.6. We
conclude that this circuit is quite tolerant to
variations in device parameters.
5.49
VDD 10 V
1 A
RG1
0.5 mA
RS
VS
VG 6 V
5 V
RG2
RD
0.5 mA
vI
Assuming linear operation in the triode region, we
can write
vO
50 mV
= 1 mA
=
iD =
rDS
50 W
(v GS − Vt )v DS
iD = k n
L
1 = 0.5 ×
W
× (1.3 − 0.4) × 0.05
L
W
= 44.4
L
1.3 − 0.05
VDD − v O
=
R=
iD
1
⇒
= 1.25 k
Refer to the circuit in the figure above,
RG1 =
=
VDD − VG
1 μA
10 − 6
= 4 M
1
RG2 =
6
= 6 M
1 μA
RD =
5V
= 10 k
0.5 mA
To determine VS , we use
1
W
ID = k p
(VSG − |Vt |)2
2
L
0.5 =
1
× 4 × (VSG − 1.5)2
2
⇒ VSG = 2 V
Thus,
VS = VG + VSG = 6 + 2 = 8 V
RS =
10 − 8
= 4 k
0.5
5.51 (a) Refer to Fig. P5.51(a): Assuming
saturation-mode operation, we have
1
2
k n VOV
2
1
2
2 = × 4 VOV
2
⇒ VOV = 1 V
ID =
VGS = |Vt | + VOV = 1 + 1 = 2 V
V1 = 0 − VGS = −2 V
V2 = 5 − 2 × 2 = +1 V
Since VDG = +1 V, the MOSFET is indeed in
saturation.
Refer to Fig. P5.51(b): The transistor is operating
in saturation, thus
1
2
k n VOV
2
1
2
2 = × 4 × VOV
⇒ VOV = 1 V
2
VGS = 2 V
ID =
⇒ V3 = 2 V
Chapter 5–14
Refer to Fig. P5.51(c): Assuming saturation-mode
operation, we have
ID =
2=
1
k p |VOV |2
2
1
× 4 × |VOV |2
2
5.52 (a) Refer to Fig. P5.52(a): The MOSFET is
operating in saturation. Thus
ID =
1
2
k n VOV
2
10 =
1
2
× 500 × VOV
⇒ VOV = 0.2 V
2
⇒ |VOV | = 1 V
VGS = Vt + VOV = 0.8 + 0.2 = 1 V
VSG = |Vt | + |VOV | = 1 + 1 = 2 V
V1 = 0 − VGS = −1 V
V4 = VSG = 2 V
(b) Refer to Fig. P5.52(b): The MOSFET is
operating in saturation. Thus
V5 = −5 + ID × 1.5
= −5 + 2 × 1.5 = −2 V
Since VDG < 0, the MOSFET is indeed in
saturation.
Refer to Fig. P5.51(d): Both transistors are
operating in saturation at equal |VOV |. Thus
2=
1
× 4 × |VOV |2 ⇒ |VOV | = 1 V
2
VSG = |Vt | + |VOV | = 2 V
V6 = 5 − VSG = 5 − 2 = 3 V
V7 = +5 − 2 VSG = 5 − 2 × 2 = 1 V
(b) Circuit (a): The 2-mA current source can be
replaced with a resistance R connected between
the MOSFET source and the −5-V supply
with
R=
V1 − (−5)
−2 + 5
=
= 1.5 k
2 mA
2
Circuit (b): The 2-mA current source can be
replaced with a resistance R,
R=
5 − V3
5−2
=
= 1.5 k
2 mA
2
Circuit (c): The 2-mA current source can be
replaced with a resistance R,
5 − V4
5−2
R=
=
= 1.5 k
2 mA
2
Circuit (d): The 2-mA current source can be
replaced with a resistance R,
R=
V7
1
= = 0.5 k
2 mA
2
We use the nearest 1% resistor, which is
499 .
100 =
1
2
× 500 × VOV
⇒ VOV = 0.63 V
2
VGS = 0.8 + 0.63 = 1.43 V
V2 = −1.43 V
(c) Refer to Fig. P5.52(c). The MOSFET is
operating in saturation. Thus
1=
1
2
× 0.5 × VOV
⇒ VOV = 2 V
2
VGS = 0.8 + 2 = 2.8 V
V3 = −2.8 V
(d) Refer to Fig. P5.52(d). The MOSFET is
operating in saturation. Thus
10 =
1
2
× 500 × VOV
⇒ VOV = 0.2 V
2
VGS = 0.8 + 0.2 = 1 V
V4 = 1 V
(e) Refer to Fig. P5.52(e). The MOSFET is
operating in saturation. Thus
1=
1
2
× 0.5 × VOV
⇒ VOV = 2 V
2
VGS = 0.8 + 2 = 2.8 V
V5 = VGS = 2.8 V
(f) Refer to Fig. P5.52(f). To simplify our
solution, we observe that this circuit is that in Fig.
P5.56(d) with the 10-μA current source replaced
with a 400-k resistor. Thus VG = V4 = +1 V
5−1
= 0.01 mA = 10 μA.
and, as a check, ID =
400
(g) Refer to Fig. P5.52(g). Our work is
considerably simplified by observing that this
circuit is similar to that in Fig. P5.52(e) with the
Chapter 5–15
1-mA current source replaced with a 2.2-k
resistor. Thus V7 = V5 = 2.8 V and, as a check,
5 − 2.8
= 1 mA.
ID =
2.2
(h) Refer to Fig. P5.52(h). Our work is
considerably simplified by observing that this
circuit is similar to that in Fig. P5.52(a) with the
10-μA current source replaced with a 400-k
resistor. Thus V8 = V1 = −1 V and, as a check,
−1 + 5
ID =
= 0.01 mA = 10 μA.
400
V4 = 2.5 V
Now, compare the part of the circuit consisting
of Q2 and the 1-k resistor. We observe
the similarity of this part with the circuit
between the gate of Q2 and ground in
Fig. P5.53(a). It follows that for the circuit in
Fig. P5.53(b), we can use the solution of part (a)
above to write
ID2 = 0.66 mA
and
VGS2 = 1.84 V
Thus,
5.53 (a) Refer to the circuit in Fig. P5.53(a).
Transistor Q1 is operating in saturation. Assume
that Q2 also is operating in saturation,
V5 = V4 − VGS2 = 2.5 − 1.84 = 0.66 V
VGS2 = 0 − V2 = −V2
Since Q1 is conducting an equal ID and has the
same VGS ,
and
ID1 = 0.66 mA
V2 = −2.5 + ID × 1
⇒ V3 = V4 + VGS1 = 2.5 + 1.84 = 3.34 V
⇒ ID = V2 + 2.5
We could, of course, have used the circuit
symmetry, observed earlier, to write this final
result.
Now,
ID =
and
VGS1 = 1.84 V
1
k n (VGS2 − Vt )2
2
Substituting ID = V2 + 2.5 and VGS2 = −V2 ,
V2 + 2.5 =
5.54
10 V
1
× 1.5(−V2 − 0.9)2
2
2
(V2 + 2.5) = V22 + 1.8 V2 + 0.81
1.5
VSG
VSD
R
IR
V22 + 0.467 V2 − 2.523 = 0
⇒ V2 = −1.84 V
Thus,
I
ID = V2 + 2.5 = −1.84 + 2.5 = 0.66 mA
and
Fig. 1
VGS2 = 1.84 V
Since Q1 is identical to Q2 and is conducting the
same ID , then
VGS1 = 1.84 V
⇒ V1 = 2.5 − 1.84 = 0.66 V
which confirms that Q1 is operating in saturation,
as assumed.
(a) From Fig. 1 we see that
VDG = IR
Since for the PMOS transistor to operate in
saturation,
VDG ≤ |Vtp |
It follows the
(b) Refer to the circuit in Fig. P5.53(b). From
symmetry, we see that
IR ≤ |Vtp |
Q.E.D
Chapter 5–16
(b) (i) R = 0, the condition above is satisfied and
ID = I =
0.1 =
1
k p |VOV |2
2
1
× 0.2 × |VOV |2
2
Now, for triode-mode operation,
1 2
ID = k p (VSG − |Vtp |)VSD − VSD
2
1
0.1 = 0.2 (VSG − 1)(VSG − 3) − (VSG − 3)2
2
⇒ |VOV | = 1 V
VSG = |Vtp | + |VOV | = 1 + 1 = 2 V
2
− 2VSG − 4 = 0
⇒ VSG
VG = 10 − 2 = 8 V
⇒ VSG = 3.24 V
VD = VG = 8 V
VSD = VSG − 3 = 0.24 V
VSD = 2 V
(iv) R = 100 k
(ii) R = 10 k
10 V
IR = 0.1 × 10 = 1 V
VSG
which just satisfies the condition for
saturation-mode operation in (a) above.
Obviously ID and |VOV | will be the same as in (i)
above.
VSG = 2 V
100 k
VSD
10 V
VG = 8 V
VD = VG + IR = 8 + 1 = 9 V
0.1 mA
VSD = 1 V
(iii) R = 30 k
Fig. 3
IR = 0.1 × 30 = 3 V
which is greater than |Vtp |. Thus the condition in
(a) above is not satisfied and the MOSFET is
operating in the triode region. From
Fig. 2,
10 V
VSG
VSD
3V
30 k
Here also (see Fig. 3) the MOSFET will be
operating in the triode region, and
VSD = VSG − 10 V
Since we expect VSD to be very small, we can
2
neglect the VSD
term in the expression for ID and
write
ID k p (VSG − |Vt |)VSD
0.1 = 0.2(VSG − 1)(VSG − 10)
2
⇒ VSG
− 11VSG + 9.5 = 0
⇒ VSG = 10.055 V
VSD = VSG − 10 = 0.055 V
0.1 mA
Fig. 2
From Fig. 2, we see that
VSD = VSG − 3
5.55 (a) Refer to the circuit in Fig. P5.55(a).
Since the two NMOS transistors are identical and
have the same ID , their VGS values will be equal.
Thus
VGS =
3
= 1.5 V
2
V2 = 1.5 V
Chapter 5–17
VOV = VGS − Vt = 1.0 V
1
W
2
VOV
I1 = ID = μn Cox
2
L
=
5.56 Refer to the circuit in Fig. P5.56. First
consider Q1 and Q2 . Both are operating in
saturation and since they are identical, they have
equal VGS :
1
3
× 270 × × 1
2
1
VGS1 = VGS2 =
Thus,
= 405 μA
(b) Refer to the circuit in Fig. P5.55(b). Here QN
and QP have the same ID = I3 . Thus
1
W
2
VOVN
I3 = μn Cox
2
L
I3 =
(1)
(2)
Equating Eqs. (1) and (2) and using
2
2
= VOVP
:
μn Cox = 3μp Cox gives 3VOVN
√
ID2 = ID1 =
=
1
W
2
μp Cox
VOVP
2
L
|VOVP | =
5
= 2.5 V
2
3 VOVN
1
W
μn Cox (VGS1 − Vt )2
2
L
1
10
× 50 × (2.5 − 1)2
2
1
= 562.5 μA
Now, Q3 has the same VGS at Q1 and is matched
to Q1 . Thus if we assume that Q3 is operating in
saturation, we have
ID3 = ID1 = 562.5 μA
Thus,
I2 = 562.5 μA
Now,
VGSN = VOVN + Vt = VOVN + 0.5
√
VSGP = |VOVP | + |Vt | = 3 VOVN + 0.5
But
This is the same current that flows through Q4 ,
which is operating in saturation and is matched to
Q3 . Thus
VGS4 = VGS3 = VGS1 = 2.5 V
Thus,
VSGP + VGSN = 3
√
( 3 + 1)VOVN + 1 = 3
⇒ VOVN = 0.732 V
VOVP = 1.268 V
V2 = 5 − VGS4 = 2.5 V
This is equal to the voltage at the gate of Q3 ; thus
Q3 is indeed operating in saturation, as
assumed.
VSGP = 1.768 V
If Q3 and Q4 have W = 100 μm, nothing changes
for Q1 and Q2 . However, Q3 , which has the same
VGS as Q1 but has 10 times the width, will have a
drain current 10 times larger than Q1 .
Thus
V4 = VGSN = 1.232 V
ID2 = ID3 = 10 ID1 = 10 × 562.5 μA
VGSN = 1.232 V
I3 =
3
1
× 270 × × 0.7322 = 217 μA
2
1
(c) Refer to Fig. P5.55(c). Here the width of the
PMOS transistor is made 3 times larger than that
of the NMOS transistor. This compensates for the
factor 3 in the process transconductance
parameter, resulting in k p = k n , and the two
transistors are matched. The solution will be
identical to that for (a) above with
= 5.625 mA
Transistor Q4 will carry I2 but will retain the same
VGS as before, thus V2 remains unchanged at
2.5 V.
5.57 Refer to the circuit in Fig. P5.57.
3
V5 = = 1.5 V
2
(a) Q1 and Q2 are matched. Thus, from
symmetry, we see that the 200-μA current will
split equally between Q1 and Q2 :
I6 = 405 μA
ID1 = ID2 = 100 μA
Chapter 5–18
V1 = V2 = 2.5 − 0.1 × 20 = 0.5 V
2φf = 0.6 V
To find V3 , we determine VGS of either Q1 and Q2
(which, of course, are equal),
and
ID1 =
1
W
μn Cox
2
L
(VGS − Vt )2
1
VSB = 0 to 4 V
At
VSB = 0, Vt = Vt0 = 1.0 V
1
100 = × 125 × 20 × (VGS − 0.7)2
2
At
⇒ VGS = 0.983 V
VSB = 4 V,
√
√
Vt = 1 + 0.5[ 0.6 + 4 − 0.6 ]
Thus,
= 1.69 V
V3 = −0.983 V
(b) With VGS1 = VGS2 , but (W/L)1 = 1.5(W/L)2 ,
transistor Q1 will carry a current 1.5 times that in
Q2 , that is,
ID1 = 1.5ID2
If the gate oxide thickness is increased by a factor
of 4, Cox will decrease by a factor of 4 and Eq.
(5.31) indicates that γ will increase by a factor of
4, becoming 2. Thus at VSB = 4 V,
√
√
Vt = 1 + 2[ 0.6 + 4 − 0.6 ]
= 3.74 V
But,
ID1 + ID2 = 200 μA
5.59 |Vt | = |Vt0 | + γ
Thus
√
√
= 0.7 + 0.5[ 0.75 + 3 − 0.75 ]
ID1 = 120 μA
= 1.24 V
ID2 = 80 μA
Thus,
V1 = 2.5 − 0.12 × 20 = 0.1 V
Vt = −1.24 V
V2 = 2.5 − 0.08 × 20 = 0.9 V
To find V3 , we find VGS from the ID equation for
either Q1 or Q2 ,
ID1
W
1
= μn Cox
(VGS − Vt )2
2
L
1
120 =
2φf + |VSB | −
1
× 125 × 20 × (VGS − 0.7)2
2
⇒ VGS = 1.01 V
1 W
5.60 (a) iD = k n
(v GS − Vt )2
2
L
1 ∂k n W
∂iD
=
(v GS − Vt )2
∂T
2 ∂T
L
W
∂Vt
−k n
(v GS − Vt )
L
∂T
∂k /k 2
∂iD /iD
∂Vt
= n n −
∂T
∂T
VGS − Vt ∂T
V3 = −1.01 V
For
5.58 Using Eq. (5.30), we can write
and
Vt = Vt0 + γ [ 2φf + VSB −
∂iD /iD
= −0.002/◦ C, VGS = 5 V
∂T
∂Vt
= −2 mV/◦ C = −0.002 V/◦ C
∂T
2φf ]
where
and
Vt0 = 1.0 V
Vt = 1 V
γ = 0.5 V1/2
−0.002 =
∂k n /k n
2 × −0.002
−
∂T
5−1
2φf
Chapter 5–19
⇒
∂k n /k n
= −0.003/◦ C
∂T
or − 0.3%/◦ C
1 2
5.61 iD = k n (v GS − Vtn )v DS − v DS ,
2
for v DS ≤ v GS − Vtn
1
k n (v GS − Vtn )2 (1 + λ v DS ),
2
for v DS ≥ v GS − Vtn
iD =
For v DS = 2 V,
iD = 0.4(1 + 0.02 × 2) = 0.416 mA
For v DS = 3 V,
iD = 0.4(1 + 0.02 × 3) = 0.424 mA
For v DS = 10 V,
For our case,
Vtn = −2 V, k n = 0.2 mA/V2 , λ = 0.02 V−1
and v GS = 0. Thus
1
iD = 0.2 2 v DS − v 2DS ,
2
iD = 0.4(1 + 0.02 v DS ),
For v DS = 1 V,
1
= 0.3 mA
iD = 0.2 2 −
2
for v DS ≤ 2 V
for v DS ≥ 2 V
iD = 0.4(1 + 0.02 × 10) = 0.48 mA
If the device width W is doubled, k n is doubled,
and each of the currents above will be doubled. If
both W and L are doubled, k n remains unchanged.
However, λ is divided in half; thus for v DS = 2 V,
iD becomes 0.408 mA; for v DS = 3 V, iD becomes
0.412 mA; and for v DS = 10 V, iD becomes
0.44 mA.
Exercise 6–1
Ex: 6.1 Refer to Fig. 6.2(a) and 6.2(b).
Av = −k n VOV RD
Coordinates of point A: Vt and VDD ; thus 0.4 V
and 1.8 V. To determine the coordinates of
point B, we use Eqs. (6.7) and (6.8) as follows:
√
2k n RD VDD + 1 − 1
VOV B =
k n RD
√
2 × 4 × 17.5 × 1.8 + 1 − 1
=
4 × 17.5
−10 = −0.4 × 10 × VOV × 17.5
= 0.213 V
Thus,
VOV = 0.14 V
VGS = Vt + VOV = 0.4 + 0.14 = 0.54 V
1
W
2
VOV
ID = k n
2
L
1
× 0.4 × 10 × 0.142 = 0.04 mA
2
RD = 17.5 k
=
Thus,
VGS B = Vt + VOV B = 0.4 + 0.213 = 0.613 V
and
VDS = VDD − RD ID
VDS B = VOV B = 0.213 V
= 1.8 − 17.5 × 0.04 = 1.1 V
Thus, coordinates of B are 0.613 V and 0.213 V.
At point C, the MOSFET is operating in the triode
region, thus
1
iD = k n (v GS C − Vt )v DS C − v 2DS C
2
If v DS C is very small,
iD k n (v GS C − Vt )v DS C
= 4(1.8 − 0.4)v DS C
= 5.6v DS C , mA
Ex: 6.3
But
iD =
VDD − v DS C
VDD
1.8
= 0.1 mA
=
RD
17.5
RD
0.1
= 0.018 V = 18 mV, which
Thus, v DS C =
5.6
is indeed very small, as assumed.
Av = −
IC RC
VT
1 × RC
⇒ RC = 8 k
0.025
− IC RC
−320 = −
VC = VCC
= 10 − 1 × 8 = 2 V
Since the collector voltage is allowed to decrease
to +0.3 V, the largest negative swing allowed at
the output is 2 − 0.3 = 1.7 V. The corresponding
input signal amplitude can be found by dividing
1.7 V by the gain magnitude (320 V/V), resulting
in 5.3 mV.
Ex: 6.4
5 V
Ex: 6.2 Refer to Example 6.1 and Fig. 6.4(a).
RG
RD
vo
Design 1:
VOV = 0.2 V, VGS = 0.6 V
ID = 0.8 mA
vi
Now,
Av = −k n VOV RD
Thus,
⇒ RD = 12.5 k
Refer to the solution of Example 6.3. From
vo
Eq. (6.47), Av ≡
= −gm RD (note that RL
vi
is absent).
VDS = VDD − RD ID
Thus,
= 1.8 − 12.5 × 0.08 = 0.8 V
gm RD = 25
Design 2:
Substituting for gm = k n VOV , we have
RD = 17.5 k
k n VOV RD = 25
−10 = −0.4 × 10 × 0.2 × RD
Exercise 6–2
where k n = 1 mA/V2 , thus
vt
vt
+i =
+ gm v t
ro
ro
it =
VOV RD = 25
(1)
Next, consider the bias equation
∴ Req =
vt
1
= ro it
gm
VGS = VDS = VDD − RD ID
Thus,
Ex: 6.6
Vt + VOV = VDD − RD ID
Substituting Vt = 0.7 V, VDD = 5 V, and
VDD
1
1
1 2
2
2
k n VOV
= × 1 × VOV
= VOV
2
2
2
we obtain
1 2
RD
(2)
0.7 + VOV = 5 − VOV
2
Equations (1) and (2) can be solved to obtain
ID =
iD
RD
vDS
vgs
vGS
VOV = 0.319 V
and
VGS
RD = 78.5 k
The dc current ID can be now found as
1
2
k n VOV
= 50.9 μA
2
To determine the required value of RG we use Eq.
(6.48), again noting that RL is absent:
ID =
Rin =
RG
1 + gm RD
0.5 M =
VDD = 5 V
VGS = 2 V
Vt = 1 V
λ=0
k n = 20 μA/V2
RG
1 + 25
RD = 10 k
⇒ RG = 13 M
Finally, the maximum allowable input signal v̂ i
can be found as follows:
Vt
0.7 V
=
= 27 mV
v̂ i =
|Av | + 1
25 + 1
W
= 20
L
(a) VGS = 2 V ⇒ VOV = 1 V
VDS
Ex: 6.5
1 W 2
k
V = 200 μA
2 n L OV
= VDD − ID RD = +3 V
ID =
(b) gm = k n
(c) Av =
it
Req
D
0
vt
(d) v gs = 0.2 sinωt V
v ds = −0.8 sinωt V
ro
(e) Using Eq. (6.28), we obtain
G
i
S
v ds
= −gm RD = −4 V/V
v gs
v DS = VDS + v ds ⇒ 2.2 V ≤ v DS ≤ 3.8 V
i
1
gm
W
VOV = 400 μA/V = 0.4 mA/V
L
iD =
1
k n (VGS − Vt )2
2
1
+ k n (VGS − Vt )v gs + k n v 2gs
2
iD = 200 + 80 sinωt
+ 8 sin2 ωt, μA
Exercise 6–3
= [200 + 80 sinωt + (4 − 4 cos2ωt)]
= 204 + 80 sinωt − 4 cos2ωt, μA
ID shifts by 4 μA.
gm =
Thus,
2HD =
î2ω
îω
=
4 μA
= 0.05 (5%)
80 μA
Ex: 6.7
(a) gm =
16
1
× 60 ×
× (1.6 − 1)2
2
0.8
ID = 216 μA
=
2 ID
2 × 216
=
= 720 μA/V
|VOV |
1.6 − 1
= 0.72 mA/V
λ = 0.04 ⇒ VA =
ro =
2 ID
VOV
1
1
=
= 25 V/μm
λ
0.04
VA × L
25 × 0.8
= 92.6 k
=
ID
0.216
ID =
1 W 2
1
k
V = × 60 × 40 × (1.5 − 1)2
2 n L OV
2
ID = 300 μA = 0.3 mA, VOV = 0.5 V
Ex: 6.11
2 ID
VA
2VA
×
=
gm ro =
VOV
ID
VOV
2 × 0.3
= 1.2 mA/V
0.5
VA
15
= 50 k
=
ro =
ID
0.3
VA × L = VA
gm =
(b) ID = 0.5 mA ⇒ gm =
=
= 100 V/V
Ex: 6.12
Given: gm =
gm = 1.55 mA/V
VA
15
= 30 k
=
ID
0.5
∂iC ∂v BE iC = IC
where IC = IS eVBE /VT
∂iC
IS eVBE /VT
IC
=
=
∂v BE
VT
VT
Ex: 6.8
ID = 0.1 mA, gm = 1 mA/V, k n = 50 μA/V2
Thus,
gm =
2 ID
2 × 0.1
= 0.2 V
⇒ VOV =
VOV
1
gm =
ID =
1 W 2
W
2 ID
k n VOV ⇒
= 2
2 L
L
k n VOV
=
2 × 12.5 × 0.8
0.2
W
2 μn Cox ID
L
2 × 60 × 40 × 0.5 × 103
ro =
L = 0.8 μm ⇒ gm ro =
2 × 0.1
= 100
50
× 0.22
1000
IC
VT
Ex: 6.13
IC
0.5 mA
= 20 mA/V
=
gm =
VT
25 mV
Ex: 6.14
Ex: 6.9
W
VOV
L
Same bias conditions, so same VOV and also same
L and gm for both PMOS and NMOS.
gm = μn Cox
μn Cox Wn = μp Cox Wp ⇒
⇒
Wp
= 2.5
Wn
Ex: 6.10
1 W
ID = k p (VSG − |Vt |)2
2 L
μp
Wn
= 0.4 =
μn
Wp
IC = 0.5 mA (constant)
β = 50
gm =
β = 200
IC
0.5 mA
=
VT
25 mV
= 20 mA/V
= 20 mA/V
0.5 0.5
IC
=
=
IB =
β
50 200
= 10 μA
rπ =
= 2.5 μA
β
50
200
=
=
gm
20
20
= 2.5 k
= 10 k
Exercise 6–4
ic = βib = β
Ex: 6.15
β = 100
gm =
IC = 1 mA
=
1 mA
= 40 mA/V
25 mV
β
v be = gm v be
rπ
ie = ib + βib = (β + 1)ib = (β + 1)
VT
αVT
25 mV
= 25 =
re =
IE
IC
1 mA
rπ =
v be
rπ
=
β
100
=
= 2.5 k
gm
40
v be
rπ
v be
v be
=
rπ (β + 1)
re
Ex: 6.18
Ex: 6.16
IC
1 mA
=
= 40 mA/V
gm =
VT
25 mV
v ce
= −gm RC
Av =
v be
C
gmvbe
ib
= −40 × 10
B
= −400 V/V
re
VC = VCC − IC RC
vbe
= 15 − 1 × 10 = 5 V
v C (t) = VC + v c (t)
E
= (VCC − IC RC ) + Av v be (t)
v be
− gm v be
re
1
= v be
− gm
re
β
1
−
= v be
rπ/β+1
rπ
β +1
β
v be
= v be
−
=
rπ
rπ
rπ
ib =
= (15 − 10) − 400 × 0.005 sinωt
= 5 − 2 sinωt
iB (t) = IB + ib (t)
where
1 mA
IC
=
= 10 μA
IB =
β
100
and ib (t) =
=
gm v be (t)
β
Ex: 6.19
40 × 0.005 sinωt
100
10 V
= 2 sinωt, μA
Thus,
RE 10 k
iB (t) = 10 + 2 sinωt, μA
CC1
Ex: 6.17
vi
ib
B
ic
CC2
C
vbe
bib
rp
RC 7.5 k
E
10 V
vo
Exercise 6–5
10 − 0.7
= 0.93 mA
10
IC = αIE = 0.99 × 0.93
VE = −0.1 − 0.7 = −0.8 V
IE =
(b) gm =
= 0.92 mA
VC = −10 + IC RC
= −10 + 0.92 × 7.5 = −3.1 V
Av =
vo
αRC
=
vi
re
where re =
Av =
IC
0.99
=
40 mA/V
VT
0.025
rπ =
β
100
=
2.5 k
gm
40
ro =
VA
100
= 101 100 k
=
IC
0.99
(c) Rsig = 2 k RB = 10 k rπ = 2.5 k
25 mV
= 26.9 0.93 mA
gm = 40 mA/V
0.99 × 7.5 × 103
= 276.2 V/V
26.9
For v̂ i = 10 mV, v̂ o = 276.2 × 10 = 2.76 V
Ex: 6.20
10V
RC = 8 k
RL = 8 k ro = 100 k
Vy
Vy
Vπ
=
×
Vsig
Vsig
Vπ
=
RB rπ
× −gm (RC RL ro )
(RB rπ ) + Rsig
=
10 2.5
× −40(8 8 100)
(10 2.5) + 2
−0.5 × 40 × 3.846 = −77 V/V
8 k
If ro is negelected,
X
Y
10 k
Z
I 1 mA
Vy
= −80, for an error
Vsig
of 3.9%.
Ex: 6.21
2ID
2 × 0.25
= 2 mA/V
=
gm =
VOV
0.25
Rin = ∞
Av o = −gm RD = −2 × 20 = −40 V/V
Ro = RD = 20 k
RL
20
= −40 ×
RL + Ro
20 + 20
IE = 1 mA
Av = Av o
100
× 1 = 0.99 mA
101
1
× 1 = 0.0099 mA
IB =
101
(a) VC = 10 − 8 × 0.99 = 2.08 2.1 V
= −20 V/V
IC =
VB = −10 × 0.0099 = −0.099 −0.1 V
This figure belongs to Exercise 6.20c.
Gv = Av = −20 V/V
v̂ i = 0.1 × 2VOV = 0.2 × 2 × 0.25 = 0.05 V
v̂ o = 0.05 × 20 = 1 V
Exercise 6–6
Ex: 6.22
IC = 0.5 mA
gm =
IC
0.5 mA
= 20 mA/V
=
VT
0.025 V
rπ =
β
100
= 5 k
=
gm
20
Rin = rπ = 5 k
Av o = −gm RC = −20 × 10 = −200 V/V
Ro = RC = 10 k
Av = Av o
5
RL
= −200 ×
RL + Ro
5 + 10
= −66.7 V/V
Gv =
Rin
5
Av =
× −66.7
Rin + Rsig
5+5
= −33.3 V/V
For IC = 0.5 mA and β = 100,
v̂ π = 5 mV ⇒ v̂ sig = 2 × 5 = 10 mV
re =
v̂ o = 10 × 33.3 = 0.33 V
VT
αVT
0.99 × 25
=
=
50 IE
IC
0.5
rπ = (β + 1)re 5 k
Although a larger fraction of the input signal
reaches the amplifier input, linearity
considerations cause the output signal to be in
fact smaller than in the original design!
For v̂ sig = 100 mV, Rsig = 10 k and with v̂ π
limited to 10 mV, the value of Re required can be
found from
10
Re
+
100 = 10 1 +
50
5
Ex: 6.23 Refer to the solution to Exercise 6.21. If
v̂ sig = 0.2 V and we wish to keep v̂ gs = 50 mV,
3
then we need to connect a resistance Rs =
in
gm
the source lead. Thus,
⇒ Re = 350 3
= 1.5 k
Rs =
2 mA/V
= 40.4 k
Gv = −β
= −100
RD RL
Gv = Av = −
1
+ Rs
gm
=−
Rin = (β + 1)(re + Re ) = 101 × (50 + 350)
2020
= −5 V/V
0.5 + 1.5
v̂ o = Gv v̂ sig = 5 × 0.2 = 1 V (unchanged)
1
= 10 mA/V
0.1 k
But
Ex: 6.24
From the following figure we see that
gm =
v̂ sig = îb Rsig + v̂ π + îe Re
Thus,
2ID
VOV
2ID
0.2
⇒ ID = 1 mA
ie
Rsig + v̂ π + îe Re
β +1
v̂ π
v̂ π
Rsig + v̂ π +
Re
(β + 1)re
re
Rsig
Re
v̂ sig = v̂ π 1 +
+
rπ
re
10
= −19.8 V/V
10 + 101 × 0.4
Ex: 6.25
1
= Rsig = 100 gm
⇒ gm =
=
RC RL
Rsig + (β + 1)(re + Re )
10 =
=
Gv =
Q.E.D
Rin
× gm RD
Rin + Rsig
= 0.5 × 10 × 2 = 10 V/V
Exercise 6–7
1
= 200 gm
Ex: 6.26
IC = 1 mA
VT
VT
25 mV
= 25 =
re =
IE
IC
1 mA
Rin = re = 25 ⇒ gm = 5 mA/V
But
gm = k n
Av o = gm RC = 40 × 5 = 200 V/V
Ro = RC = 5 k
RL
5
= 100 V/V
= 200 ×
Av = Av o
RL + Ro
5+5
W
VOV
L
Thus,
5 = 0.4 ×
W
× 0.25
L
Ex: 6.27
W
= 50
L
1 W 2
ID = k n VOV
2 L
1
= × 0.4 × 50 × 0.252
2
= 0.625 mA
Rin = re = 50 RL = 1 k to 10 k
Rin
× Av
Gv =
Rin + Rsig
=
25
× 100 = 0.5 V/V
25 + 5000
⇒ IE =
VT
25 mV
=
= 0.5 mA
re
50 IC IE = 0.5 mA
Gv =
RC RL
re + Rsig
⇒
Correspondingly,
Gv =
RL
RL
=
RL + Ro
RL + 0.2
will range from
Gv =
RC RL
40 =
(50 + 50)
1
= 0.83 V/V
1 + 0.2
to
RC RL = 4 k
Gv =
10
= 0.98 V/V
10 + 0.2
Ex: 6.28 Refer to Fig. 6.41(c).
Ro = 100 Thus,
Ex: 6.30
1
= 100 ⇒ gm = 10 mA/V
gm
IC = 5 mA
But
gm =
VT
VT
25 mV
=5
=
IE
IC
5 mA
Rsig = 10 k RL = 1 k
2ID
VOV
Rin = (β + 1) (re + RL )
Thus,
10 × 0.25
= 1.25 mA
2
RL
1
= 0.91 V
=1×
v̂ o = v̂ i ×
RL + Ro
1 + 0.1
ID =
v̂ gs = v̂ i
re =
1
gm
1
+ RL
gm
Ex: 6.29
Ro = 200 =1×
0.1
= 91 mV
0.1 + 1
= 101 × (0.005 + 1)
= 101.5 k
Gv o = 1 V/V
Rout = re +
Rsig
β +1
10,000
= 104 101
RL
RL
=
Gv =
Rsig
RL + Rout
RL + re +
β +1
=5+
=
1
= 0.91 V/V
1 + 0.104
Exercise 6–8
vπ = vsig
v̂ sig
v̂ sig
re
re + RL +
Rsig
β +1
Rsig
RL
= v̂ π 1 +
+
(β + 1) re
re
1000
10,000
=5 1+
+
= 1.1 V/V
5
101 × 5
Correspondingly,
v̂ o = Gv × 1.1 = 0.91 × 1.1 = 1 V
VS = −5 + 6.2 × 0.49 = −1.96 V
VD = 5 − 6.2 × 0.49 = +1.96 V
RG should be selected in the range of 1 M to
10 M to have low current.
Ex: 6.33
2
⇒ VOV
Ex: 6.31
1 W
ID = k n (VGS − Vt )2
2 L
0.5 =
1
× 1(VGS − 1)2
2
⇒ VGS = 2 V
If Vt = 1.5 V, then
ID =
⇒
1
× 1 × (2 − 1.5)2 = 0.125 mA
2
0.125 − 0.5
ID
= −0.75 = −75%
=
ID
0.5
1 W 2
k
V
2 n L OV
0.5 × 2
=1
=
1
= 1 V ⇒ VGS = 1 + 1 = 2 V
ID = 0.5 mA =
⇒ VOV
5−2
= 6 k
0.5
⇒ RD = 6.2 k (standard value). For this RD we
have to recalculate ID :
= VD ⇒ RD =
ID =
1
× 1 × (VGS − 1)2
2
1
(VDD − RD ID − 1)2
2
(VGS = VD = VDD − RD ID )
=
1
(4 − 6.2 ID )2 ⇒ ID ∼
= 0.49 mA
2
VD = 5 − 6.2 × 0.49 = 1.96 V
ID =
Ex: 6.32
RD =
VDD − VD
5−2
= 6 k
=
ID
0.5
→ RD = 6.2 k
ID =
1 W 2
1
2
k
V ⇒ 0.5 = × 1 × VOV
2 n L OV
2
Ex: 6.34 Refer to Example 6.12.
(a) For design 1, RE = 3 k, R1 = 80 k, and
R2 = 40 k. Thus, VBB = 4 V.
IE =
⇒ VOV = 1 V
VBB − VBE
R1 R2
RE +
β +1
⇒ VGS = VOV + Vt = 1 + 1 = 2 V
For the nominal case, β = 100 and
⇒ VS = −2 V
4 − 0.7
= 1.01 1 mA
4080
3+
101
For β = 50,
RS =
VS − VSS
−2 − (−5)
= 6 k
=
ID
0.5
→ RS = 6.2 k
If we choose RD = RS = 6.2 k, then ID will
change slightly:
1
× 1 × (VGS − 1)2 . Also
2
= −VS = 5 − RS ID
ID =
VGS
2 ID = (4 − 6.2 ID )2
⇒ 38.44 ID2 − 51.6 ID2 + 16 = 0
⇒ ID = 0.49 mA, 0.86 mA
ID = 0.86 results in VS > 0 or VS > VG , which is
not acceptable. Therefore ID = 0.49 mA and
IE =
4 − 0.7
= 0.94 mA
4080
3+
51
For β = 150,
IE =
4 − 0.7
= 1.04 mA
4080
3+
151
Thus, IE varies over a range approximately 10%
of the nominal value of 1 mA.
IE =
(b) For design 2, RE = 3.3 k, R1 = 8 k, and
R2 = 4 k. Thus, VBB = 4 V. For the nominal
case, β = 100 and
Exercise 6–9
4 − 0.7
= 0.99 1 mA
48
3.3 +
101
For β = 50,
To maintain active-mode operation at all times,
the collector voltage should not be allowed
to fall below the value that causes the CBJ to
become forward biased, namely, −0.4 V.
Thus, the lowest possible dc voltage at the
collector is −0.4 V + 2V = +1.6 V.
Correspondingly,
IE =
4 − 0.7
= 0.984 mA
48
3.3 +
51
For β = 150,
IE =
RC =
4 − 0.7
= 0.995 mA
48
3.3 +
151
Thus, IE varies over a range of 1.1% of the
nominal value of 1 mA. Note that lowering
the resistances of the voltage divider considerably
decreases the dependence on the value of β, a
highly desirable result obtained at the expense
of increased current and hence power
dissipation.
10 − 1.6
10 − 1.6
= 8.4 k
IC
1 mA
IE =
Ex: 6.36 Refer to Fig. 6.54. For IE = 1 mA and
VC = 2.3 V,
VCC − VC
RC
IE =
1=
10 − 2.3
RC
⇒ RC = 7.7 k
Now, using Eq. (6.147), we obtain
Ex: 6.35 Refer to Fig. 6.53. Since the circuit is to
be used as a common-base amplifier, we can
dispense with RB altogether and ground the base;
thus RB = 0. The circuit takes the form shown in
the figure below.
10 V
IE =
VCC − VBE
RB
RC +
β +1
10 − 0.7
RB
7.7 +
101
⇒ RB = 162 k
1=
Selecting standard 5% resistors (Appendix J), we
use
RC
RB = 160 k
vo
and
RC = 7.5 k
The resulting value of IE is found as
10 − 0.7
= 1.02 mA
160
7.5 +
101
and the collector voltage will be
IE =
RE
vi
5V
To establish IE = 1mA,
IE =
5 − VBE
RE
1 mA =
5 − 0.7
RE
VC = VCC − IE RC = 2.3 V
Ex: 6.37 Refer to Fig. 6.55(b).
VS = 3.5 and ID = 0.5 mA; thus
RS =
VS
3.5
= 7 k
=
ID
0.5
VDD = 15 V and VD = 6 V; thus
RD =
VDD − VD
15 − 6
=
= 18 k
ID
0.5 mA
⇒ RE = 4.3 k
To obtain VOV , we use
IC
vo
= gm RC , where gm =
=
vi
VT
40 mA/V. To maximize the voltage gain, we
select RC as large as possible, consistent with
obtaining a ±2-V signal swing at the collector.
1
2
k n VOV
2
1
2
0.5 = × 4VOV
2
⇒ VOV = 0.5 V
The voltage gain
ID =
Exercise 6–10
Thus,
VGS = Vt + VOV = 1 + 0.5 = 1.5 V
We now can obtain the dc voltage required at the
gate,
VG = VS + VGS = 3.5 + 1.5 = 5 V
Using a current of 2 μA in the voltage divider, we
have
5V
= 2.5 M
RG2 =
2 μA
The voltage drop across RG1 is 10 V, thus
RG1 =
10 V
= 5 M
2 μA
This completes the bias design. To obtain gm and
ro , we use
2ID
2 × 0.5
=
= 2 mA/V
gm =
VOV
0.5
VA
100
= 200 k
=
ID
0.5
ro =
Ex: 6.38 Refer to Fig. 6.55(a) and (c) and to the
values found in the solution to Exercise 6.37
above.
Rin = RG1 RG2 = 52.5 = 1.67 M
Ro = RD ro = 18200 = 16.5 k
5V
= 100 k
0.05 mA
The base current is
IE
0.5 mA
= 5 μA
IB =
β +1
100
RB2 =
The current through RB1 is
IRB1 = IB + IRB2 = 5 + 50 = 55 μA
Since the voltage drop across RB1 is
VCC − VB = 10 V, the value of RB1 can be
found from
10 V
= 182 k
RB1 =
0.055 μA
The value of RE can be found from
IE =
VB − VBE
RE
5 − 0.7
= 8.6 k
0.5
The value of RC can be found from
⇒ RE =
VC = VCC − IC RC
6 = 15 − 0.99 × 0.5 × RC
RC 18 k
This completes the bias design. The values of gm ,
rπ , and ro can be found as follows:
Rin
gm (ro RD RL )
Rin + Rsig
gm =
IC
0.5 mA
= 20 mA/V
VT
0.025 V
1.67
× 2 × (2001820)
1.67 + 0.1
rπ =
β
100
= 5 k
=
gm
20
ro =
VA
100
= 200 k
IC
0.5
Gv = −
=−
Ex: 6.40 Refer to Fig. 6.56(a). For VB = 5 V and
50-μA current through RB2 , we have
= −17.1 V/V
Ex: 6.39 To reduce v gs to half its value, the
unbypassed Rs is given by
Rs =
1
gm
Rin = RB1 RB2 rπ
From the solution to Exercise 6.37 above,
gm = 2 mA/V. Thus
Rs =
1
= 0.5 k
2
Neglecting ro , Gv is given by
Gv = −
Ex: 6.41 Refer to Fig. 6.56(b) and to the solution
of Exercise 6.40 above.
Rin
RD RL
×−
1
Rin + Rsig
+ Rs
gm
1.67
1820
=−
×
1.67 + 0.1 0.5 + 0.5
= −8.9 V/V
= 182 100 5 = 4.64 k
Ro = RC ro = 18 200 = 16.51 k
Gv = −
Rin
gm (RC RL ro )
Rin + Rsig
Gv = −
4.64
× 20 × (18 20 200)
4.64 + 10
= −57.3 V/V
Ex: 6.42 Refer to the solutions of Exercises 6.40
and 6.41 above. With Re included (i.e., left
unbypassed), the input resistance becomes [refer
to Fig. 6.57(b)]
Exercise 6–11
50 × 20(88)
50 + 50 Rin = RB1 RB2 [(β + 1)(re + Re )]
=
Thus,
= 40 V/V
10 = 182 100 [101(0.05 + Re )]
VT
=
where we have substituted re =
IE
25
= 50 . The value of Re is found from the
0.5
equation above to be
Re = 67.7 RC RL
Rin
Rin + Rsig re + Re
Gv = −0.99 ×
18 20
10
10 + 10 0.05 + 0.0677
= −39.8 V/V
Ex: 6.43 Refer to Fig. 6.58.
Rin = 50 = re RE re
re = 50 =
VT
IE
⇒ IE = 0.5 mA
IC = αIE IE = 0.5 mA
VC = VCC − RC IC
For VC = 1 V and VCC = 5 V, we have
1 = 5 − RC × 0.5
⇒ RC = 8 k
To obtain the required value of RE , we note that
the voltage drop across it is (VEE − VBE ) = 4.3 V.
Thus,
4.3
= 8.6 k
0.5
Rin
gm (RC RL )
Gv =
Rin + Rsig
RE =
Ex: 6.44 Refer to Fig. 6.59. Consider first
the bias design of the circuit in Fig. 6.59(a).
Since the required IE = 1 mA, the base current
1
IE
=
0.01 mA. For a dc voltage
β +1
101
drop across RB of 1 V, we obtain
IB =
The overall voltage gain can be found from
Gv = −α
v̂ o = 40 v̂ sig = 40 × 10 mV = 0.4 V
1V
= 100 k
0.01 mA
The result is a base voltage of –1 V and an emitter
voltage of –1.7 V. The required value of RE can
now be determined as
−1.7 − (−5)
3.3
RE =
=
= 3.3 k
IE
1 mA
RB =
Rin = RB [(β + 1)[re + (RE ro RL )]
where ro =
VA
100 V
= 100 k
=
IC
1 mA
Rin = 100 (100 + 1)[0.025 + (3.3 100 1)]
= 44.3 k
Rin
44.3
vi
=
=
= 0.469 V/V
v sig
Rin + Rsig
44.3 + 50
RE ro RL
vo
=
= 0.968 V/V
vi
re + (RE ro RL )
vo
= 0.469 × 0.968 = 0.454 V/V
Gv ≡
v sig
RB + Rsig
Rout = ro RE re +
β +1
100 50
= 100 3.3 0.025 +
101
= 320 Chapter 6–1
6.1 Coordinates of point A: v GS = Vt = 0.5 V
and v DS = VDD = 5 V.
corresponding peak input signal is
v̂ gs =
0.78
0.78 V
=
= 19.5 mV
| Av |
40
To obtain the coordinates of
point B, we first use
Eq. (6.6) to determine VGS B as
√
2k n RD VDD + 1 − 1
VGS B = Vt +
k n RD
√
2 × 10 × 20 × 5 + 1 − 1
= 0.5 +
10 × 20
= 0.5 + 0.22 = 0.72 V
The vertical coordinate of point B is VDS B ,
VDS B = VGS B − Vt = VOV B = 0.22 V
VDD − VOV B
VOV B /2
2 − VOV B
14 =
VOV B /2
⇒ VOV B = 0.25 V
6.2 VDS B = VOV B = 0.5 V
Now, using Eq. (6.15) at point B, we have
Av = −k n VOV RD
Thus,
1
1
2 ID B = k n VDS
= × 5 × 0.52 = 0.625 mA
B
2
2
The value of RD required can now be found as
VDD − VDS B
RD =
ID B
5 − 0.5
= 7.2 k
=
0.625
If the transistor is replaced with
another having
twice the value of k n , then ID B will be twice as
large and the required value of RD will be half that
used before, that is, 3.6 k.
6.3 Bias point Q: VOV = 0.2 V and VDS = 1 V.
IDQ =
1
2
k n VOV
2
1
× 10 × 0.04 = 0.2 mA
2
VDD − VDS
5−1
RD =
=
= 20 k
IDQ
0.2
=
Coordinates of point B:
Equation (6.6):
√
2k n RD VDD + 1 − 1
VGS B = Vt +
k n RD
√
2 × 10 × 20 × 5 + 1 − 1
= 0.5 +
10 × 20
= 0.5 + 0.22 = 0.72 V
Equations (6.7) and (6.8):
√
2k n RD VDD + 1 − 1
VDS B =
= 0.22 V
k n RD
Av = −k n RD VOV
= −10 × 20 × 0.2 = −40 V/V
The lowest instantaneous
voltage allowed at the
output is VDS B = 0.22 V. Thus the maximum
allowable negative signal swing at the output is
VDSQ − 0.22 = 1 − 0.22 = 0.78 V. The
6.4 From Eq. (6.18):
| Av max | =
B
B
Thus,
−14 = −k n RD × 0.25
⇒ k n RD = 56
To obtain a gain of −12 V/V at point Q:
−12 = −k n RD VOV Q
= −56VOV Q
Thus,
12
VOV Q =
= 0.214 V
56
To obtain the required VDS Q , we use Eq. (6.17),
VDD − VDS Q
Av = −
VOV Q /2
2 − VDS Q
−12 = −
0.214/2
⇒ VDS = 0.714 V
Q
6.5 RD = 20 k
k n = 200 μA/V2
VRD = 1.5 V
VGS = 0.7 V
Av = −10 V/V
Av = −k n VOV RD
1
2
VRD = ID RD = k n VOV
RD
2
−2
−10
Av
=
=
VRD
VOV
1.5
∴ VOV = 0.30 V
Vt = VGS −VOV = 0.40 V
Av
−10
kn =
=
VOV RD
−0.3 × 20
= 1.67 mA/V2
Chapter 6–2
k n = k n
∴
W
= 1.67 mA/V2
L
remains in saturation is 1.61 V and the
corresponding output voltage is 0.61 V. Thus, the
maximum amplitude of input sine wave is
(1.61 − 1.5) = 0.11 V. That is, v GS ranges from
1.5 − 0.11 = 1.39 V, at which
W
= 8.33
L
iD =
6.6
1
× 1 × (1.39 − 1)2 = 0.076 mA
2
and
VDD
v DS = 5 − 0.076 × 24 = 3.175 V
and v GS = 1.5 + 0.11 = 1.61 V at which
v DS = 0.61 V.
iD
RD
vDS
Thus, the large-signal gain is
0.61 − 3.175
= −11.7 V/V
1.61 − 1.39
ⵑ
vgs
VGS
mA
W
=1 2
VDD = 5 V, k n
L
V
RD = 24 k, Vt = 1 V
(a) Endpoints of saturation transfer segment:
whose magnitude is slightly less (−2.5%) than
the incremental or small-signal gain (−12 V/V).
This is an indication that the transfer
characteristic is not a straight line.
6.7 At sat/triode boundary
v GS B = VGS + v̂ gs
v DS B = VDS − v̂ o
v̂ o = max downward amplitude , we get
Point A occurs at VGS = Vt = 1 V, iD = 0
v̂ o
v DS B = v GS B − Vt = VGS +
− Vt
| Av |
Point A = (1 V, 5 V) ( VGS , VDS )
= VDS − v̂ o
Point B occurs at sat/triode boundary ( VGD = Vt )
VOV +
VGD = 1 V ⇒ V GS − [ 5 − iD RD ] = 1
1
(1)(24) [ VGS − 1 ]2 − 1 = 0
VGS − 5 +
2
2
− 23VGS + 6 = 0
12VGS
VGS = 1.605 V
iD = 0.183 mA
VDS = 0.608 V
Point B = ( +1.61 V, 0.61 V )
v̂ o
= VDS − v̂ o
| Av |
VDS − VOV
v̂ o =
1 + | A1v |
(1)
For VDD = 5 V, VOV = 0.5 V, and
W
k n
= 1 mA/V2 , we use
L
−2(VDD − VDS )
Av =
VOV
and Eq. (1) to obtain
(b) For VOV = VGS −Vt = 0.5 V, we have
VGS = 1.5 V
1
ID = k n (VGS − Vt )2
2
1
= × 1(1.5 − 1)2
2
ID = 0.125 mA VDS = +2.00 V
v̂ o
v̂ i
V DS
Av
1V
−16
471 mV 29.4 mV
1.5 V −14
933 mV 66.7 mV
−12 1385 mV
115 mV
2.5 V −10 1818 mV
182 mV
2V
Point Q = ( 1.50 V, 2.00 V )
Av = −k n VOV RD = −12 V/V
For VDS = 1 V, Av = −16 = −k n VOV RD
(c) From part (a) above, the maximum
instantaneous input signal while the transistor
ID RD = 4 V, ID = 0.125 mA
∴ RD = 32 k
Chapter 6–3
solving the resulting quadratic equation
results in
6.8
k n RD = 213.7
vDS
which can be substituted into Eq. (2) to
obtain
VDS B = 0.212 V
The value of VDS at the bias point can now be
found from Eq. (1) as
VDS Q = 0.212 + 0.5 = 0.712 V
(b) The gain achieved can be found as
Q
VDSQ
Av = −k n RD VOV
= −213.7 × 0.2 = −42.7 V/V
0.5
0.5
v̂ gs =
=
= 11.7 mV
| Av |
42.7
0.5 V
B
VDSB
VOV
(c) ID = 100 μA
vˆ gs
Vt
vGS
VDSB
To obtain maximum gain while allowing for a
−0.5-V signal swing at the output, we bias the
MOSFET at point Q where
VDS Q = VDS B + 0.5 V
(1)
as indicated in the figure above. Now, VDS B is
given by Eq. (6.8) [together with Eq. (6.7)],
√
2k n RD VDD + 1 − 1
VDS B =
(2)
k n RD
RD =
VDD − VDS Q
ID
5 − 0.712
= 42.88 k
=
0.1
213.7
(d) k n =
= 4.98 mA/V2
42.88
4.98
W
=
= 24.9
L
0.2
6.9
VDD
From the figure we see that
VDS B = VOV + v̂ gs
Q2
where VOV = 0.2 V (given) and
v̂ gs
0.5 V
=
| Av |
=
0.5
0.5
2.5
=
=
k n RD VOV
k n RD × 0.2
k n RD
vO
vI
Q1
iD
(3)
Thus,
2.5
VDS B = 0.2 +
k n RD
Substituting for VDS B from Eq. (2), we obtain
√
2.5
2k n RD VDD + 1 − 1
= 0.2 +
k n RD
k n RD
Substituting VDD = 5 V, rearranging the equation
to obtain a quadratic equation in k n RD , and
given Vt1 = Vt2 = Vt
1
W
[ VDD − v O − Vt ]2
For Q2 , iD = k n
2
L 2
1
W
[ v I − Vt ]2
For Q1 , iD = k n
2
L 1
For Vt ≤ v I ≤ v O + Vt ,
equate iD1 and iD2
Chapter 6–4
W
L
=
Similarly,
[ VDD − v O + Vt ]2
2
W
L
[ v I − Vt ] 2
1
[ VDD − v O − Vt ] =
v O = VDD − Vt + Vt
−v I
For
( W/L )1
( W/L )2
IC
VCE
(mA) (V)
Av
(V/V)
POS
Neg
v O (V) v O (V)
( W/L)1
· [ v I − Vt ]
( W/L )2
0.5
4.5
–20
0.5
4.2
1.0
4.0
–40
1.0
3.7
( W/L )1
( W/L )2
2.5
2.5
–100
2.5
2.2
4.0
1.0
–160
4.0
0.7
4.5
0.5
–180
4.5
0.2
50
√
0.5
= 10,
5
0.5
( W/L )1
=
( W/L )2
6.12
√
Av = − 10 = −3.16 V/V
6.10 Refer to Fig. 6.6.
VCC − VCE
Av = −
VT
5−1
= −160 V/V
=−
0.025
The transistor enters saturation when v CE ≤ 0.3 V,
thus the maximum allowable output voltage
swing is 1 − 0.3 = 0.7 V. The corresponding
maximum input signal permitted v̂ be is
v̂ be =
0.7 V
0.7
=
= 4.4 mV
| Av |
160
IC RC
VCC − VCE
=−
VT
VT
On the verge of saturation
Av = −
6.11
VCE − v̂ ce = 0.3 V
For linear operation, v ce = Av v be
5 V
IC
VCE − | Av v̂ be | = 0.3
RC
1 k
vO
v
be
VBE
( 5 − IC RC ) − | Av | × 5 × 10−3 = 0.3
But
| Av | =
IC RC
VT
Thus,
IC RC = | Av |VT
and
5 − | Av |VT − | Av | × 5 × 10−3 = 0.3
For IC = 0.5 mA, we have
IC RC
0.5
Av = −
= −20 V/V
=−
VT
0.025
VCE = VCC − IC RC
| Av |( 0.025 + 0.005 ) = 5 − 0.3
| Av | = 156.67.
Note AV is negative.
∴ Av = −156.67 V/V
max +v O = 5 − 4.5 = 0.5 V
Now we can find the dc collector voltage.
Referring to the sketch of the output voltage, we
see that
max −v O = 4.5 − 0.3 = 4.2 V
VCE = 0.3 + | Av | 0.005 = 1.08 V
= 5 − 0.5 = 4.5 V
Chapter 6–5
This figure belongs to Problem 6.13.
5 V
2.5 V
10 k
5 k
Thévenin
vO
0.3 mA
vI
vO
In the results obtained, tabulated below, VCEsat =
0.3 V and VCC is the nearest 0.5 V to VCCmin .
6.13 See figure above
Av = −
0.3 mA
vI
10 k
IC RC
0.3 × 5
= −60 V/V
=−
VT
0.025
Case Av (V/V) P (V) | Av |VT VCCmin VCC
6.14 To obtain an output signal of peak
amplitude P volts and maximum gain, we bias the
transistor at
VCE = VCEsat + P
The resulting gain will be
VCC − VCE
Av = −
VT
which results in VCC of
a
−20
0.2
0.5
1.0
1.0
b
−50
0.5
1.25
2.05
2.5
c
−100
0.5
2.5
3.3
3.5
d
−100
1.0
2.5
3.8
4.0
e
−200
1.0
5.0
6.3
6.5
f
−500
1.0
12.5
13.8 14.0
g
−500
2.0
12.5
14.8 15.0
VCC = VCE + | Av |VT
Thus the minimum required VCC will be
VCCmin = VCEsat + P + | Av |VT
6.15 (a) See figure below
but we have to make sure that the amplifier
can support a positive peak amplitude of P,
that is,
(b) See figure on next page
Note that in part (b) the graph is shifted right by
+5 V and up by +5 V.
| Av |VT ≥ P
This figure belongs to Problem 6.15(a).
vO
0.5 V
0
B
vI
vI
0.3 V
vO
RC
5 V
A
5 V
Chapter 6–6
This figure belongs to Problem 6.15(b).
vO
5 V
5V
vI
B
4.7 V
vO
RC
A
0
0
v CE
6.16 iC = IS e
1+
VA
VCE
IC = IS eVBE /VT 1 +
VA
6.17 (a) Using Eq. (6.23) yields
| Av max | =
−60 = −
VCE
1
eVBE /VT
VA
VT
dv CE
1
−RC IS eVBE /VT
dv BE
VA
1
1
IC
− RC
A
= −RC IC
VCE VA v
VT
1+
VA
Thus,
= −RC IS 1 +
Av =
−IC RC /VT
IC RC
1+
VA + VCE
3 − VCE
VCC − VCE
=−
VT
0.025
⇒ VCE = 1.5 V
(c) IC = 0.5 mA
IC RC = VCC − VCE = 3 − 1.5 = 1.5 V
RC =
1.5
= 3 k
0.5
(d) IC = IS eVBE /VT
0.5 × 10−3 = 10−15 eVBE /0.025
⇒ VBE = 0.673 V
Q.E.D
(e) Assuming linear operation around the bias
point, we obtain
Substituting IC RC = VCC − VCE , we obtain
(VCC − VCE )/VT
Av = −
VCC − VCE
1+
VA + VCE
Q.E.D
5−3
Av (without the Early effect) = −
0.025
= −80 V/V
Av (with the Early effect) =
v ce = Av × v be
= −60 × 5 sin ωt = −300 sin ωt, mV
= −0.3 sin ωt, V
(f) ic =
For VCC = 5 V, VCE = 3 V, and VA = 100 V,
= −78.5 V/V
VCC − 0.3
3 − 0.3
= 108 V/V
=
VT
0.025
(b) Using Eq. (6.22) with Av = −60 yields
v CE = VCC − RC iC
BE v =V , v =V
BE
BE
CE
CE
vI
v BE /VT
VCE = VCC − RC IC
dv CE Av =
dv 4.5 V 5 V
−80
2
1+
100 + 3
−v ce
= 0.1 sin ωt, mA
RC
0.5 mA
IC
=
= 0.005 mA
β
100
ic
0.1
ib = =
sin ωt = 0.001 sin ωt, mA
β
100
(g) IB =
(h) Small-signal input resistance ≡
=
5 mV
= 5 k
0.001 mA
v̂ be
v̂ b
Chapter 6–7
Peak-to-peak v C swing = 4 − 1 = 3 V
(i)
vBE
For point Q at VCC /2 = 2.5 V, we obtain
vbe
VBE
5 mV
VCE = 2.5 V,
0.673 V
IC = 2.5 mA
IB = 25 μA
IB =
0
t
vCE
VCE
⇒ VBB = IB RB + 0.7 = 2.5 + 0.7 = 3.2 V
1.8 V
vce
VBB − 0.7
= 25 μA
RB
1.5 V
0.3 V
1.2 V
0
iC
(mA)
IC
6.20 See the graphical construction that follows.
t
0.6 mA
0.1 mA
0.5 mA
0.4 mA
0
t
iB
(A)
IB
ib
1 A
6 A
5 A
4 A
0
t
6.18 Av = −
But
Av ≡
IC
RC
VT
v O
− iC RC
=
= −gm RC
v BE
v BE
Thus,
gm = IC /VT
For a transistor biased at IC = 0.5 mA, we have
0.5
gm =
= 20 mA/V
0.025
6.19
For this circuit:
VCC = 10 V,
β = 100,
RC = 1 k,
VA = 100 V,
IB = 50 μA (dc bias),
At v CE = 0, iC = βiB
∴ IC = 50 × 100
= 5 mA (dc bias)
Given the base bias current of 50 mA, the dc or
bias point of the collector current IC , and voltage
VCE can be found from the intersection of the load
Chapter 6–8
line and the transistor line L1 of iB = 50 μA.
Specifically:
6.21 Substituting v gs = Vgs sin ωt in Eq. (6.28),
iD =
Eq. of L1 ⇒ iC = IC ( 1 + v CE /VA )
= 5 ( 1 + v CE /100 )
VCC − v CE
= 10 − v CE
RC
∴ 10 − v CE = 5 + 0.05v CE
VCE = v CE = 4.76 V
Now for a signal of 30-μA peak superimposed on
IB = 50 μA, the operating point moves along the
load line between points N and M. To obtain the
coordinates of point M, we solve the load line and
line L2 to find the intersection M, and the load
line and line L3 to find N:
6.22 ID =
v GS = VGS
For point M:
iC = 8 + (8/100)v CE and iC = 10 − v CE
∴ iC M = 8.15 mA,
1 Vgs
× 100
Q.E.D
4 VOV
For Vgs = 10 mV, to keep the second-harmonic
distortion to less than 1%, the minimum overdrive
voltage required is
1 0.01 × 100
= 0.25 V
VOV = ×
4
1
=
IC = iC = 10 − v CE = 5.24 mA
v CE M = 1.85 V
1
1
2
k n VOV
= × 10 × 0.22 = 0.2 mA
2
2
+ v gs , where v gs = 0.02 V
v OV = 0.2 + 0.02 = 0.22 V
1
1
iD = k n v 2OV = × 10 × 0.222 = 0.242 mA
2
2
Thus,
id = 0.242 − 0.2 = 0.042 mA
For point N:
iC = 2 + 0.02v CE and iC = 10 − v CE
v CE N = 7.84 V,
1
k n (VGS − Vt )2 + k n (VGS − Vt )Vgs sin ωt
2
1 1
1
+ k n Vgs2 ( − cos 2 ωt)
2
2 2
Second-harmonic distortion
1
k n Vgs2
4
× 100
=
k n (VGS − Vt )Vgs
=
= 5 + 0.05v CE
Load line ⇒ iC =
1
k n (VGS − Vt )2 + k n (VGS − Vt )Vgs sin ωt
2
1
+ k n Vgs2 sin2 ωt
2
iC N = 2.16 mA
Thus the collector current varies as follows:
For
v gs = −0.02 V,
v OV = 0.2 − 0.02 = 0.18 V
1
1
iD = k n v 2OV = × 10 × 0.182 = 0.162 mA
2
2
Thus,
id = 0.2 − 0.162 = 0.038 mA
2.91 mA
8.15 mA
5.24 mA
i 5.99 mA,
peak to peak
2.16 mA
3.08 mA
Thus, an estimate of gm can be obtained as
follows:
0.042 + 0.038
= 2 mA/V
gm =
0.04
Alternatively, using Eq. (6.33), we can write
gm = k n VOV = 10 × 0.2 = 2 mA/V
which is an identical result.
And the collector voltage varies as follows:
3.08 V
7.84 V
4.76 V
v 5.99 V
1.85 V
2.91 V
6.23 (a) ID =
1
k n (VGS − Vt2 )
2
1
× 5(0.6 − 0.4)2 = 0.1 mA
2
VDS = VDD − ID RD = 1.8 − 0.1 × 10 = 0.8 V
=
(b) gm = k n VOV = 5 × 0.2 = 1 mA/V
(c) Av = −gm RD = −1 × 10 = −10 V/V
1
(d) λ = 0.1 V−1 , VA = = 10 V
λ
Chapter 6–9
VA
10
= 100 k
=
ID
0.1
Av = −gm (RD ro )
To just maintain saturation-mode operation,
v GS max = v DS min + Vt
= −1(10 100) = −9.1 V/V
which results in
ro =
VOV + v̂ i = VDS − | Av |v̂ i
6.24 Av = −10 = −gm RD = −gm × 20
Substituting for | Av | from Eq. (1) yields
gm = 0.5 mA/V
To allow for a −0.2-V signal swing at the drain
while maintaining saturation-region operation,
the minimum voltage at the drain must be at least
equal to VOV . Thus
VDS = 0.2 + VOV
VDD − VDS
1
VOV
2
1.8 − 0.2 − VOV
−10 = −
0.5VOV
Av = −
2(VDD − VDS )
v̂ i
VOV
VDS [1 + 2(v̂ i /VOV )]
= VOV + v̂ i + 2VDD (v̂ i /VOV )
⇒ VDS =
Since
VOV + v̂ i + 2VDD (v̂ i /VOV )
1 + 2(v̂ i /VOV )
Q.E.D
For
VDD = 2.5 V, v̂ i = 20 mV and m = 15
VOV = mv̂ i = 15 × 20 = 0.3 V
⇒ VOV = 0.27 V
VDS =
The value of ID can be found from
gm =
VOV + v̂ i = VDS −
0.3 + 0.02 + 2 × 2.5 × (0.02/0.3)
1 + 2(0.02/0.3)
= 0.576 V
2ID
VOV
Av = −
2 × ID
0.27
⇒ ID = 0.067 mA
0.5 =
2(VDD − VDS )
2(2.5 − 0.576)
=−
VOV
0.3
= −12.82 V/V
v̂ o = | Av |v̂ i = 12.82 × 20 mV = 0.256 V
The required value of k n can be found from
1
2
k n VOV
2
1
0.067 = k n × 0.272
2
To operate at ID = 200 μA = 0.2 mA,
RD =
2.5 − 0.576
= 9.62 k
0.2
⇒ k n = 1.83 mA/V2
ID =
1
2
k n VOV
2
ID =
Since k n = 0.2 mA/V2 , the W/L ratio must be
0.2 =
W
1.83
kn
= =
= 9.14
L
kn
0.2
1
k n × 0.32
2
⇒ k n = 4.44 mA/V2
Finally,
The required W/L ratio can now be found as
VGS = Vt + VOV = 0.4 + 0.27 = 0.67 V
kn
4.44
W
= =
= 44.4
L
kn
0.1
6.25 Av = −gm RD
Upon substituting for gm from Eq. (6.42), we can
write
2ID RD
Av = −
VOV
=−
2(VDD − VDS )
VOV
Q.E.D
v GS max = VGS + v̂ i = Vt + VOV + v̂ i
v DS min = VDS − | Av |v̂ i
(1)
6.26 Given μn = 500 cm2 /V·s,
μp = 250 cm2 /V·s, and Cox = 0.4 fF/μm2 ,
k n = μn Cox = 20 μA/V2
k p = 10 μA/V2
See table on next page.
Chapter 6–10
v i = gm v gs
6.27
VDD
1
+ RS
gm
v d = −gm v gs RD
v s = +gm v gs RS
RD
vs
RS
+gm RS
=
=
1
vi
1 + gm RS
+ RS
gm
vd
−RD
−gm RD
=
=
1
vi
1 + gm RS
+ RS
gm
∴
vd
vi
vs
RS
6.28
VDD
VSS
G
vgs
vi
vo
RL
10 k
1
gm
S
vs
RS
RG
10 M
RD
gmvgs
vi
I 500 μA
vd
D
Vt = 0.5 V
VA = 50 V
Given VDS = VGS = 1 V. Also, ID = 0.5 mA.
2ID
VOV = 0.5 V, gm =
= 2 mA/V
VOV
Chapter 6–11
ro =
15 V
VA
= 100 k
ID
0.5 mA
vo
= −gm ( RG RL ro ) = −18.2 V/V
vi
For ID = 1 mA:
√
1
VOV increases by
= 2 to
0.5
√
2 × 0.5 = 0.707 V.
10 M
16 k
7 V
1.5 V
5 M
VGS = VDS = 1.207 V
gm = 2.83 mA/V, ro = 50 k and
vo
= −23.6 V/V
vi
0.5 mA
7 k
Figure 1
6.29 For the NMOS device:
1
W 2
ID = 100 = μn Cox VOV
2
L
10
1
2
× VOV
= × 400 ×
2
0.5
⇒ VOV = 0.16 V
2ID
2 × 0.1 mA
= 1.25 mA/V
=
gm =
VOV
0.16
VA = 5L = 5 × 0.5 = 2.5 V
VA
2.5
= 25 k
=
ro =
ID
0.1
For the PMOS device:
1
W 2
ID = 100 = μp Cox VOV
2
L
10
1
2
= × 100 ×
× VOV
2
0.5
⇒ VOV = 0.316 V
2ID
2 × 0.1
=
= 0.63 mA/V
gm =
VOV
0.316
VA = 6L = 6 × 0.5 = 3 V
VA
3
= 30 k
=
ro =
ID
0.1
From the voltage divider, we have
5
=5V
VG = 15
10 + 5
From the circuit, we obtain
VG = VGS + 0.5 × 7
= 1.5 + 3.5 = 5 V
which is consistent with the value provided by the
voltage divider.
Since the drain voltage (+7 V) is higher than the
gate voltage (+5 V), the transistor is operating in
saturation.
From the circuit
VD = VDD − ID RD = 15 − 0.5 × 16 = +7 V, as
assumed
Finally,
VGS = 1.5 V, thus VOV = 1.5 − Vt = 1.5 − 1
= 0.5 V
1
1
2
= × 4 × 0.52 = 0.5 mA
ID = k n VOV
2
2
which is equal to the given value. Thus the bias
calculations are all consistent.
2ID
2 × 0.5
(b) gm =
=
= 2 mA/V
VOV
0.5
VA
100
ro =
=
= 200 k
ID
0.5
(c) See Fig. 2 below.
6.30 (a) Open-circuit the capacitors to obtain the
bias circuit shown in Fig. 1, which indicates the
given values.
This figure belongs to Problem 6.30, part (c).
Rsig 200 k
vo
vsig
vgs
10 M
5 M
gmvgs
200 k
Rin
Figure 2
16 k
16 k
Chapter 6–12
(d) Rin = 10 M 5 M = 3.33 M
6.32
v gs
Rin
3.33
=
=
v sig
Rin + Rsig
3.33 + 0.2
5 V
= 0.94 V/V
vo
= −gm (200 16 16)
v gs
0.5 mA
VC
= −2 × 7.69 = −15.38 V/V
v gs
vo
vo
=
×
= −0.94 × 15.38
v sig
v sig
v gs
vBE
= −14.5 V/V
6.31 (a) Using the exponential characteristic:
ic = IC ev be /VT − IC
giving
VC = VCC − RC IC
For v BE = 705 mV ⇒ v be = 5 mV
iC = IC ev be /VT
(b) Using small-signal approximation:
Thus,
With v BE = 0.700 V
= 5 − 5 × 0.5 = 2.5 V
ic
= ev be /VT − 1
IC
ic = gm v be =
5 k
= 0.5 × e5/25 = 0.611 mA
IC
· v be
VT
v C = VCC − RC iC = 5 − 5 × 0.611 = 1.95 V
v ce = v C − VC = 1.95 − 2.5 = −0.55 V
v ce
0.55 V
Voltage gain, Av =
=−
v be
5 mV
ic
v be
=
IC
VT
See table below.
For signals at ±5 mV, the error introduced by the
small-signal approximation is 10%.
The error increases to above 20% for signals at
±10 mV.
= −110 V/V
Using small-signal approximation, we write
Av = −gm RC
where
IC
0.5 mA
= 20 mA/V
=
VT
0.025 V
gm =
Av = −20 × 5 = −100 V/V
v be
i c /I C
i c /I C
Error
(mV) Exponential Small signal (%)
Thus, the small-signal approximation at this
signal level (v be = 5 mV) introduces an error of
−9.1% in the gain magnitude.
+1
+0.041
+0.040
–2.4
–1
–0.039
–0.040
+2.4
+2
+0.083
+0.080
–3.6
–2
–0.077
–0.080
+3.9
+5
+0.221
+0.200
–9.7
–5
–0.181
–0.200
+10.3
re =
+8
+0.377
+0.320
–15.2
where
–8
–0.274
–0.320
+16.8
α=
+10
+0.492
+0.400
–18.7
–10
–0.330
–0.400
+21.3
+12
+0.616
+0.480
–22.1
0.99 × 25 mV
50 0.5 mA
At IC = 50 μA = 0.05 mA,
–12
–0.381
–0.480
+25.9
gm =
6.33 At IC = 0.5 mA,
IC
0.5 mA
= 20 mA/V
=
VT
0.025 V
β
100
= 5 k
=
rπ =
gm
20 mA/V
gm =
VT
αVT
=
IE
IC
100
β
=
= 0.99
β +1
100 + 1
re =
IC
0.05
=
= 2 mA/V
VT
0.025
Chapter 6–13
β
100
= 50 k
=
gm
2 mA/V
αVT
0.99 × 25 mV
re =
500 =
IC
0.5 mA
and
rπ =
| Av | = gm RC =
then
6.34 For gm = 30 mA/V,
IC
gm =
⇒ IC = gm VT = 30×0.025 = 0.75 mA
VT
β
β
=
rπ =
gm
30 mA/V
For rπ ≥ 3 k, we require
β ≥ 90
That is, βmin = 90.
IC
1 mA
= 40 mA/V
=
VT
0.025 V
α
0.99
re =
=
25 gm
40 mA/V
β
100
rπ =
=
= 2.5 k
gm
40 mA/V
Av = −gm RC = −40 × 5 = −200 V/V
6.35 gm =
v̂ o = | Av |v̂ be = 200 × 5 mV = 1 V
VC = 1 V,
6.36 VCC = 3 V,
3−1
IC =
= 1 mA
2
IC
1 mA
= 40 mA/V
=
gm =
VT
0.025 V
v be = 0.005 sin ωt
V̂be
IC RC = 0.3
VT
which can be manipulated to yield
VCC − 0.3
IC RC =
V̂be
1+
VT
Since the voltage gain is given by
IC RC
Av = −
VT
then
VCC − 0.3
Av =
VT + V̂be
VCC − IC RC −
(1)
For VCC = 3 V and V̂be = 5 mV,
3 − 0.3
= 2.25 V
IC RC =
5
1+
25
Thus,
VCE = VCC − IC RC
= 3 − 2.25 = 0.75 V
RC = 2 k
ic = gm v be = 0.2 sin ωt, mA
iC (t) = IC + ic = 1 + 0.2 sin ωt, mA
v C (t) = VCC − RC iC
= 3 − 2(1 + 0.2 sin ωt)
V̂o = VCE − 0.3 = 0.75 − 0.3 = 0.45 V
3 − 0.3
= −90 V/V
Av = −
0.025 + 0.005
Check:
IC RC
2.25
= −90 V/V
=−
Av = −gm RC = −
VT
0.025
V̂o = | Av | × V̂be = 90 × 5 = 450 mV = 0.45 V
6.38
Transistor
α
= 1 − 0.4 sin ωt, V
iB (t) = iC (t)/β
= 0.01 + 0.002 sin ωt, mA
vc
0.4
= −80 V/V
=−
Av =
v be
0.005
6.37 Since V̂be is the maximum value for
acceptable linearity, the largest signal at the
collector will be obtained by designing for
maximum gain magnitude. This in turn is
achieved by biasing the transistor at the lowest
VCE consistent with the transistor remaining in the
active mode at the negative peak of v o . Thus
VCE − | Av |V̂be = 0.3
a
b
1.000 0.990
c
d
0.980
1
50
∞
e
∞
100
IC (mA)
1.00
0.99
IE (mA)
1.00
1.00
IB (mA)
0
0.010
0.020
0
gm (mA/V)
40
39.6
40
40
25
24.5
25
100
re ()
25
rπ ()
∞
100
g
9
15.9
1.00 1.00 0.248
4.5
17.5
1.02 1.00 0.25
5
18.6
0.002
0.5
1.10
9.92
180
700
5
1.34
50
22.7
2.525 k 1.25 k ∞ 10.1 k
6.39 IC = 1 mA,
f
0.990 0.900 0.940
β
β = 100,
gm =
IC
1 mA
= 40 mA/V
=
VT
0.025 V
rπ =
β
100
=
= 2.5 k
gm
40 mA/V
ro =
VA
100 V
=
= 100 k
IC
1 mA
where we have assumed VCEsat = 0.3 V. Since
VCE = VCC − IC RC
IC
RC
VT
VA = 100 V
Chapter 6–14
These figures belong to Problem 6.39.
B
C
rp
vp
E
rp 2.5 k,
C
B
rp
ro
gmvp
ib
E
ro 100 k,
gm 40 mA/V
b 100
C
C
gmvp
B
vp
ro
ai
B
ro
re
re
i
E
E
re 24.75 , gm 40 mA/V
100
β
=
= 0.99
α=
β +1
100 + 1
VT
αVT
0.99 × 25 mV
=
=
= 24.75 re =
IE
IC
1 mA
6.40
gmvbe
B
ib
vbe vbe
re
ro 100 k, a 0.99
ib = v be
g
− gm
Q.E.D
6.41 Refer to Fig. 6.26.
v be
α
= v be
ic = αie = α
re
re
= gm v be
Q.E.D
6.42 The large-signal model of Fig. 4.5(d) is
shown in Fig. 1.
iB
E
C
vBE
v be
ib =
− gm v be
re
1
= v be
− gm
re
Since
α
re =
gm
m
α
1−α
= gm v be
α
gm v be
=
β
v be
β
=
= rπ
Rin ≡
ib
gm
B
Rin
ro
bib
DB
( ISB IS )
b
biB
E
Figure 1
For v BE undergoing an incremental change v be
from its equilibrium value of VBE , the current iB
Chapter 6–15
C
changes from IB by an increment ib , which is
related to v be by the incremental resistance of DB
at the bias current IB . This resistance is given by
VT /IB , which is rπ .
aiE
The collector current βiB changes from βIB to
β(IB + ib ). The incremental changes around the
equilibrium or bias point are related to each other
by the circuit shown in Fig. 2,
B
ie
re
vbe
ib
B
E
C
vbe
Figure 2
bib
rp
which is the small-signal T model of
Fig. 6.26(b).
Q.E.D.
E
6.44 Refer to Fig. P6.44:
Figure 2
which is the hybrid-π model of
Fig. 6.24(b).
Q.E.D.
6.43 The large-signal T model of Fig. 4.5(b) is
shown below in Fig. 1.
VC = 3 − 0.2 × 10 = 1 V
VT
25 mV
= 125 =
re =
IE
0.2 mA
Replacing the BJT with the T model of
Fig. 6.26(b), we obtain the equivalent circuit
shown below.
C
aiE
B
iE
DE
IS
ISE a
vBE
(
)
E
Figure 1
If iE undergoes an incremental change ie from its
equilibrium or bias value IE , the voltage v BE will
correspondingly change by an incremental
amount v be (from its equilibrium or bias value
VBE ), which is related to ie by the incremental
resistance of diode DE . The latter is equal to
VT /IE , which is re .
The incremental change ie in iE gives rise to an
incremental change αie in the current of the
controlled source.
The incremental quantities can be related
by the equivalent circuit model shown in Fig. 2,
v c = −ie × 10 k
where
ie = −
vi
vi
=−
re
0.125 k
Thus,
vc
10 k
=
vi
0.125 k
= 80 V/V
Chapter 6–16
This figure belongs to Problem 6.45.
6.45
C
vπ
= rπ
Rin ≡
ib
rπ
vπ
=
v sig
rπ + Rsig
aie
v o = −gm v π RC
vo
= −gm RC
vπ
v
x
B
ie
re
The overall voltage gain can be obtained as
follows:
vo
vo vπ
=
v sig
v π v sig
E
v
r
x
ix
rπ
= −gm RC
rπ + Rsig
= −gm rπ
=−
RC
rπ + Rsig
βRC
rπ + Rsig
ix
Since v x appears across re and ix = ie =
small-signal resistance r is given by
Q.E.D.
r≡
vx
, the
re
vx
vx
=
= re
ix
ie
6.46 v ce = | Av |v be
| Av | = gm RC = 50 × 2 = 100 V/V
For v ce being 1 V peak to peak,
1V
= 0.01 V peak to peak
100
v be =
ib =
6.48 Refer to Fig. P6.48. Replacing the BJT with
the T model of Fig. 6.26(b) results in the
following amplifier equivalent circuit:
v be
rπ
C
aie
where
β
100
= 2 k
=
gm
50
rπ =
B
ie
Thus,
ib =
ib
vi
0.01 V
= 0.005 mA peak to peak
2 k
re
E
Re
vo
Rin
6.47 Replacing the BJT with the T model of
Fig. 6.26(b), we obtain the circuit shown in next
column above.
Rin ≡
vi
vi
=
ib
(1 − α)ie
Chapter 6–17
6.50 Refer to Fig. P6.50. The transistor is biased
at IE = 0.33 mA. Thus
From the circuit we see that
vi
ie =
re + Re
Thus,
re + Re
Rin =
1−α
But
1
1−α =
β +1
Thus,
Rin = (β + 1)(re + Re )
re =
VT
25 mV
= 75 =
IE
0.33 mA
Replacing the BJT with its T model results in the
following amplifier equivalent circuit.
Q.E.D.
From the equivalent circuit, we see that v o and v i
are related by the ratio of the voltage divider
formed by re and Re :
Re
vo
=
Q.E.D.
vi
Re + re
6.49 Refer to Fig. P6.49.
200
β
=
= 0.995
α=
β +1
201
IC = α × IE = 0.995 × 10 = 9.95 mA
VC = IC RC = 9.95 × 0.1 k = 0.995 V
1V
Replacing the BJT with its hybrid-π model
results in the circuit shown below.
IC
10 mA
= 400 mA/V
gm =
VT
0.025 V
β
200
rπ =
= 0.5 k
=
gm
400
Rib = rπ = 0.5 k
The input resistance Rin can be found by
inspection to be
Rin = re = 75 To determine the voltage gain (v o /v i ) we first
find ie :
Rin = 10 k 0.5 k = 0.476 k
vπ
Rin
0.476
=
=
= 0.322 V/V
v sig
Rin + Rsig
0.476 + 1
vo
= −gm RC = −400 × 0.1 = −40 V/V
vπ
vo
= −40 × 0.322 = −12.9 V/V
v sig
ie = −
vi
vi
vi
=−
=−
Rsig + re
150 0.15 k
The output voltage v o is given by
v o = −α ie (RC RL )
= −0.99 ie × (12 12) = −0.99 × 6ie
For
= −0.99 × 6 ×
v o = ±0.4 V/V
±0.4
= ∓0.01 V = ∓10 mV
vb = vπ =
−40
±0.4
v sig =
= ∓31 mV
−12.9
Thus,
vo
= 39.6 V/V
vi
This figure belongs to Problem 6.49.
Rsig 1 k
vb
vo
vsig vp
Rin
10 k
Rib
rp
gmvp
RC
−v i
0.15
Chapter 6–18
This figure belongs to Problem 6.51.
B
vsig vp
gmvp
rp
ro
C
vo
RL very high
6.51 The largest possible voltage gain is obtained
when RL → ∞, in which case
IC VA
vo
= −gm ro = −
v sig
VT IC
To obtain maximum gain and the largest possible
signal swing at the output for v eb of 10 mV, we
select a value for RC that results in
VA
=−
VT
which is the highest allowable voltage at the
collector while the transistor remains in the active
region. Since
For VA = 25 V,
vo
25
=−
v sig
0.025
VC + | Av | × 0.01 V = +0.4 V
VC = −5 + IC RC
−5 + 0.5RC
= −1000 V/V
then
vo
125
For VA = 125 V,
=−
v sig
0.025
−5 + 0.5RC + gm RC × 0.01 = 0.4
Substituting gm = 20 mA/V results in
= −5000 V/V
RC = 7.7 k
The overall voltage gain achieved is
vo
Rin
=
× gm RC
v sig
Rin + Rsig
6.52
5 V
RE
Rsig 50 vsig
50
× 20 × 7.7
50 + 50
= 77 V/V
=
6.53 Refer to Fig. P6.53 on next page. Since β is
very large, the dc base current can be neglected.
Thus the dc voltage at the base is determined by
the voltage divider,
Rin re
50 vo
RC
100
= 2.5 V
100 + 100
and the dc voltage at the emitter will be
VB = 5
VE = VB − 0.7 = 1.8 V
5 V
VT
IE
⇒ IE = 0.5 mA
re = 50 =
Thus,
5 − VE
= 0.5 mA
RE
where
VE
0.7 V
⇒ RE = 8.6 k
The dc emitter current can now be found as
VE
1.8
IE =
= 0.5 mA
=
RE
3.6
and
IC
IE = 0.5 mA
Replacing the BJT with the T model of
Fig. 6.26(b) results in the equivalent circuit model
for the amplifier shown on next page.
vi
ie =
RE + re
RE
v o1 = ie RE = v i
RE + re
Chapter 6–19
This figure belongs to Problem 6.53.
vo2
aie
RC
ie
re
vi
RE
v o1
=
vi
RE + re
100
k
100
k
vi
RC
RE + re
v o2
αRC
=−
vi
RE + re
For α 1,
RE
v o Rsig + Rin
io
=
ii
v sig
RL
Q.E.D.
v o2 = −αie RC = −α
re =
vo1
= Gv
Q.E.D.
Rsig + Rin
RL
= 79.4 ×
VT
25 mV
=
= 50 IE
0.5 mA
6.55 (a)
v o1
3.6
= 0.986 V/V
=
vi
3.6 + 0.05
20 + 100
= 4762 A/A
2
Rin
= 0.95
Rin + Rsig
Rin
= 0.95
Rin + 100
v o2
3.3
= 0.904 V/V
=−
vi
3.6 + 0.05
⇒ Rin = 1.9 M
(b) With RL = 2 k,
If v o1 is connected to ground, RE will in effect be
short-circuited at signal frequencies, and v o2 /v i
will become
v o2
αRC
3.3
= −66 V/V
=−
=−
vi
re
0.05
v o = Av o v i
2
2 + Ro
With RL = 1 k,
v o = Av o v i
1
1 + Ro
Thus the change in v o is
6.54 See figures below and on next page.
Rin
RL
Av o
Gv =
Rin + Rsig
RL + Ro
v o = Av o v i
1
2
−
2 + Ro
1 + Ro
To limit this change to 5% of the value with
RL = 2 k, we require
2
1
2
−
= 0.05
2 + Ro
1 + Ro
2 + Ro
2
100
× 100 ×
100 + 20
2 + 0.1
= 79.4 V/V
vo
io =
RL
v sig
ii =
Rsig + Rin
=
⇒ Ro =
1
k = 111 9
This figure belongs to Problem 6.54.
Rsig 20 k
Ro 100 vsig vi
Rin
100 k
Av ovi
RL
vo
2 k
Av o 100
Chapter 6–20
This figure belongs to Problem 6.55.
Rsig
Ro
vsig Rin
vi
Av ovi
RL
(c) Gv = 10 =
=
vo
Rin
RL
Av o
Rin + Rsig
RL + Ro
To determine Gm (at least conceptually), we
short-circuit the output of the equivalent circuit in
Fig. 1(b). The short-circuit current will be
1.9
2
× Av o ×
1.9 + 0.1
2 + 0.111
io = Gm v i
⇒ Av o = 11.1 V/V
Thus Gm is defined as
io Gm = v i RL = 0
The values found about are limit values; that is,
we require
Rin ≥ 1.9 M
and is known as the short-circuit
transconductance. From Fig. 2 below,
Ro ≤ 111 Av o ≥ 11.1 V/V
Rin
vi
=
v sig
Rin + Rsig
v o = Gm v i (Ro RL )
6.56 The circuit in Fig. 1(b) (see figure below) is
that in Fig. P6.56, with the output current source
expressed as Gm v i . Thus, for equivalence, we
write
Av o
Gm =
Ro
Thus,
Rin
vo
=
Gm (Ro RL )
v sig
Rin + Rsig
These figures belong to Problem 6.56.
Ro
io
Rin
vi
Avovi
io
Norton
vo
equivalent
of output
circuit
vi
Avovi
Ro
Gmvi
Rin
(a)
(b)
Figure 1
Rsig
vsig vi
Figure 2
Rin
Gmvi
Ro
RL vo
Ro
vo
Chapter 6–21
6.58 Refer to Fig. P6.58. To determine Rin , we
simplify the circuit as shown in Fig. 1, where
vi
vi
Rin ≡
= R1 Rin , where Rin ≡
ii
if
6.57
v o Gv o =
v sig RL = ∞
Now, setting RL = ∞ in the equivalent circuit in
Fig. 1(b), we can determine Gv o from
Rin
Av o
Gv o =
Rin + Rsig RL =∞
Thus,
Denoting Rin with RL = ∞ as Ri , we can express
Gv o as
Rin ≡
Gv o =
Ri
Av o
Ri + Rsig
v i = if Rf + (if − gm v i )(R2 RL )
v i [1 + gm (R2 RL )] = if [Rf + (R2 RL )]
and
Q.E.D.
Rin = R1 Rin
From the equivalent circuit in Fig. 1(a), the
overall voltage Gv can be obtained as
Gv = Gv o
RL
RL + Rout
Rf + (R2 RL )
vi
=
if
1 + gm (R2 RL )
Rf + (R2 RL )
1 + gm (R2 RL )
= R1
Q.E.D.
Q.E.D.
This figure belongs to Problem 6.57.
Rsig
Rout
vsig vi
Rin
Gv ovsig
RL
vo
(a)
Rsig
Ro
vsig vi
Rin
This figure belongs to Problem 6.58.
Figure 1
RL
vo
(b)
Figure 1
Av ovi
Chapter 6–22
To determine Av o , we open-circuit RL and use the
circuit in Fig. 2, where
Rf
if
vi
gmvi
R1
vo
R2
R2
vo
With Rf ,
1
49.8
× −10 ×
49.8 + 100
1 + 0.1
= −3 V/V
Gv =
Without Rf ,
1
100
× −10 ×
= −4.5 V/V
Gv =
100 + 100
1 + 0.1
6.59 Rsig = 1 M, RL = 10 k
gm = 2 mA/V, RD = 10 k
Gv = −gm (RD RL )
Figure 2
vo
if = gm v i +
R2
= −2(10 10) = −10 V/V
6.60 RD = 2RL = 30 k
vo
v i = if Rf + v o = gm v i +
Rf + vo
R2
Rf
v i (1 − gm Rf ) = v o 1 +
R2
−10 = −gm (30 15)
Thus,
⇒ gm = 1 mA/V
1 − gm Rf
vo
=
Rf
vi
1+
R2
which can be manipulated to the form
2ID
VOV
2 × ID
1=
0.25
⇒ ID = 0.125 mA = 125 μA
Av o ≡
Av o = −gm R2
1 − 1/gm Rf
1 + (R2 /Rf )
Q.E.D.
Finally, to obtain Ro we short-circuit v i in the
circuit of Fig. P6.58. This will disable the
controlled source gm v i . Thus, looking between
the output terminals (behind RL ), we see R2 in
parallel with Rf ,
Ro = R2 Rf
Q.E.D.
For R1 = 100 k, Rf = 1 M, gm = 100 mA/V
R2 = 100 and RL = 1 k
1000 + (0.1 1)
= 100 99.1
Rin = 100
1 + 100(0.1 1)
= 49.8 k
Without Rf present (i.e., Rf = ∞), Rin = 100 k
and
1 − (1/100 × 1000)
Av o = −100 × 0.1
0.1
1+
1000
−10 V/V
Without Rf , −Av o = 10 V/V and
Ro = 0.1 1000
0.1 k = 100 Without Rf , Ro = 100 .
Thus the only parameter that is significantly
affected by the presence of Rf is Rin , which is
reduced by a factor of 2!
Rin
RL
Gv =
Av o
Rin + Rsig
RL + Ro
VOV = 0.25 V
Gv = −gm (RD RL )
gm =
If RD is reduced to 15 k,
Gv = −gm (RD RL )
= −1 × (15 15) = −7.5 V/V
6.61 Rin = ∞
1
W 2
ID = μn Cox VOV
2
L
1
2
320 = × 400 × 10 × VOV
2
⇒ VOV = 0.4 V
2ID
2 × 0.32
gm =
=
= 1.6 mA/V
VOV
0.4
Av o = −gm RD = −1.6 × 10 = −16 V/V
Ro = RD = 10 k
RL
Gv = Av o
RL + Ro
10
= −8 V/V
= −16 ×
10 + 10
0.2 V
Peak value of v sig =
= 25 mV.
8
6.62 (a) See figure on next page.
2ID
2 × 0.3
= 3 mA/V
=
(b) gm1 = gm2 =
VOV
0.2
RD1 = RD2 = 10 k
RL = 10 k
Chapter 6–23
This figure belongs to Problem 6.62.
Rsig 200 k
vsig vgs1
gm1vgs1
Gv =
gm2vgs2
RD2
R L vo
v gs2
vo
×
v gs1
v gs2
(b) β = 50, | Gv | =
= −gm1 RD1 × −gm2 (RD2 RL )
10
(10/50) + 0.025
= 44.4 V/V
= 3 × 10 × 3 × (10 10)
β = 150, | Gv | =
= 450 V/V
10
(10/150) + 0.025
= 109.1 V/V
IC
0.5 mA
= 20 mA/V
=
6.63 gm =
VT
0.025 V
β
100
rπ =
= 5 k
=
gm
20 mA/V
Rin = rπ = 5 k
Ro = RC = 10 k
Av o = −gm RC = −20 × 10 = −200 V/V
RL
10
= −200 ×
RL + Ro
10 + 10
= −100 V/V
Rin
Gv =
Av
Rin + Rsig
Av = Av o
5
× −100
5 + 10
= −33.3 V/V
=
For v̂ π = 5 mV, v̂ sig can be found from
v̂ π = v̂ sig ×
RD1 vgs2
Rin
5
= v̂ sig ×
Rin + Rsig
5 + 10
⇒ v̂ sig = 15 mV
Correspondingly, v̂ o will be
v̂ o = Gvv̂ sig
= 15 × 33.3 = 500 mV = 0.5 V
6.64 | Gv | =
RL
(Rsig /β) + (1/gm )
RL = 10 k, Rsig = 10 k, gm =
IC
VT
1
= 40 mA/V
0.025
Nominal β = 100
=
10
(a) Nominal | Gv | =
(10/100) + 0.025
= 80 V/V
Thus, | Gv | ranges from 44.4 V/V to 109.1 V/V.
(c) For | Gv | to be within ±20% of nominal (i.e.,
ranging between 64 V/V and 96 V/V), the
corresponding allowable range of β can be found
as follows:
10
64 =
(10/βmin ) + 0.025
⇒ βmin = 76.2
10
96 =
(10/βmax ) + 0.025
⇒ βmax = 126.3
(d) By varying IC , we vary the term 1/gm in the
denominator of the | Gv | expression. If β varies in
the range 50 to 150 and we wish to keep | Gv |
within ±20% of a new nominal value of | Gv |
given by
10
Gv =
nominal
(10/100) + (1/gm )
then
10
0.8 Gv nominal =
(10/50) + (1/gm )
That is,
10
8
=
0.1 + (1/gm )
0.2 + (1/gm )
1
= 0.3 or gm = 3.33 mA/V
⇒
gm
10
Gv =
= 25 V/V
nominal
0.1 + 0.3
10
Gv =
min
0.2 + 0.3
= 20 V/V (−20% of nominal)
We need to check the value obtained for
β = 150,
10
Gv =
= 27.3 V/V
max
10/150 + 0.3
Chapter 6–24
which
is less than the allowable value of
1.2 Gv nominal = 30 V/V. Thus, the new bias
current is
16 =
20
20
=
1 + gm Rs
1 + 2Rs
⇒ Rs = 125 IC = gm × VT = 3.33 × 0.025 = 0.083 mA
Gv = 25 V/V
6.68 gm =
6.65 (a) See figure below.
re
nominal
(b) RC1 = RC2 = 10 k
Rsig = 10 k
IC
0.25 mA
= 10 mA/V
=
VT
0.025 V
rπ 1 = rπ 2 =
β
100
= 10 k
=
gm
10
1
= 50 gm
Rin = (β + 1)(re + Re )
= 101(50 + 250) = 30.3 k
αRC
0.99 × 12
Av o = −
=−
re + Re
0.3
Ro = RC = 12 k
RL
Av = Av o
RL + Ro
12
= −20 V/V
= −40 ×
12 + 12
Rin
Gv =
× Av
Rin + Rsig
RL = 10 k
gm1 = gm2 =
IC
0.5
= 20 mA/V
=
VT
0.025
rπ 1
10
vπ1
=
=
= 0.5 V/V
v sig
rπ 1 + Rsig
10 + 10
vπ2
= −gm1 (RC1 rπ 2 ) = −10(10 10)
vπ1
= −50 V/V
vo
= −gm2 (RC2 RL )
vπ2
30.3
× −20 = −15 V/V
30.3 + 10
Rin + Rsig
v̂ π = 5 mV ⇒ v̂ sig = v̂ π
Rin
=
= −10(10 10) = −50 V/V
vo
vπ2
vπ1
vo
=
×
×
v sig
vπ2
vπ1
v sig
30.3 + 10
= 6.65 mV
30.3
v̂ o = v̂ sig × | Gv |
v̂ sig = 5 ×
= −50 × −50 × 0.5
= 1250 V/V
= 6.65 × 15
6.66 gm effective =
−40 V/V
gm
1 + gm Rs
100 mV
6.69 Rin = (β + 1)(re + Re )
5
2=
1 + 5Rs
⇒ Rs = 0.3 k = 300 15 = 75(re + Re )
15 k
re + Re =
= 200 75
Rin
re
v̂ π = v̂ sig
Rin + Rsig re + Re
re
15
5 = 150 ×
15 + 30 re + Re
re
= 0.1
⇒
re + Re
But re + Re = 200 , thus
6.67 Including Rs reduced the gain by a factor of
2, thus
1 + gm Rs = 2
1
1
= 2 mA/V
=
⇒ gm =
Rs
0.5
The gain without Rs is −20 V/V. To obtain a gain
of −16 V/V, we write
re = 20 This figure belongs to Problem 6.65.
Rsig 10 k
vsig vp1
rp1
vp2
gm1vp1
rp2
vo
gm2vp2
RC1
RC2
RL
Chapter 6–25
which requires a bias current IE of
VT
25 mV
=
= 1.25 mA
IE =
re
20 IC IE = 1.25 mA
Re = 180 Rin
Gv =
Rin + Rsig
−α × Total resistance in collector
×
Total resistance in emitter
−0.99 × 6
15
×
=
15 + 30
0.2
−10 V/V
v̂ 0 = 0.15 × | Gv | = 1.5 V
6.70 Using Eq. (6.113), we have
RC RL
Gv = −β
Rsig + (β + 1)(re + Re )
RC RL
−
(Rsig /β) + (re + Re )
10
| Gv | =
(10/β) + 0.025 + Re
Without Re ,
10
| Gv | =
(10/β) + 0.025
For the nominal case, β = 100,
10
Gv =
= 80 V/V
nominal
0.1 + 0.025
For β = 50,
10
Gv =
= 44.4 V/V
low
0.2 + 0.025
For β = 150,
10
Gv = 109.1 V/V
=
high
(1/15) + 0.025
Thus, | Gv | ranges from 44.4 V/V to 109.1 V/V
with a nominal value of 80 V/V. This is a range of
−44.5% to +36.4% of nominal.
To limit the range of | Gv | to ±20% of a new
nominal value, we connect a resistance Re and
find its value as follows. With Re ,
10
Gv =
nominal
(10/100) + 0.025 + Re
10
=
0.125 + Re
Now, β = 50,
10
Gv =
low
0.225 + Re
To limit this value to −20% of Gv nominal ,
we use
10
10
= 0.8 ×
0.225 + Re
0.125 + Re
⇒ Re = 0.275 k = 275 With this value of Re ,
10
Gv =
= 25 V/V
nominal
0.125 + 0.275
Gv 10
0.225 + 0.275
= 20 V/V (−20% of nominal)
10
Gv =
high
(1/15) + 0.025 + 0.275
= 27.3 V/V (+9.1% of nominal)
low
=
6.71 Rin =
1
1
= 0.5 k
=
gm
2 mA/V
Rin
× gm (RD RL )
Rin + Rsig
0.5
× 2(5 5)
=
0.5 + 0.75
= 2 V/V
Gv =
For Rin = Rsig = 0.75 k
1
= 0.75 ⇒ gm = 1.33 mA/V
gm
Since gm = 2k n ID , then to change gm by a factor
1.33
= 0.67, ID must be changed by a factor of
2
(0.67)2 = 0.45.
6.72 Refer to the circuit in Fig. P6.72. Since
Rsig re , most of isig flows into the emitter of the
BJT. Thus
ie
isig
and
ic = αie
isig
Thus,
v o = ic RC = isig RC
6.73 For Rin = Rsig = 50 ,
re = 50 and, with α 1,
VT
25 mV
=
= 0.5 mA
IC
re
50 gm = IC /VT = 20 mA/V
Rin
gm (RC RL )
Gv =
Rin + Rsig
50
× 20 × (10 10)
50 + 50
= 50 V/V
Gv =
VT
25 mV
=
= 125 IE
0.2 mA
0.2 mA
= 8 mA/V
0.025 V
6.74 Rin = re =
gm =
IC
VT
Rin
gm (RC RL )
Rin + Rsig
0.125
× 8(10 10) = 8 V/V
=
0.125 + 0.5
Gv =
Chapter 6–26
v̂ π = v̂ sig
Rin
Rin + Rsig
10 = v̂ sig
0.125
0.125 + 0.5
Av nominal =
Av high
= 0.93
⇒ v̂ sig = 50 mV
v̂ o = Gv v̂ sig = 8 × 50 = 400 mV = 0.4 V
6.75
Rsig
1
gm
RL
(+10% above nominal)
1.5
Av low =
1.5 + 0.357
= 0.81 (−5% from nominal)
1
= Ro = 0.357 k
gm
⇒ gm = 2.8 mA/V
To find ID , we use
gm = 2k n ID
i
i
vsig 2
= 0.85 V/V
2.357
5
=
5.357
50 mV (peak)
0.5 V (peak)
From the figure above, we have
1
= 0.1 × RL
gm
= 0.1 × 2 = 0.2 k
⇒ ID = gm2 /2k n
2.82
= 1.6 mA
2 × 2.5
1
2
ID = k n VOV
2
1
2
1.6 = × 2.5 × VOV
2
⇒ VOV = 1.13 V
=
6.77
Rsig/(b + 1)
gm = 5 mA/V
gm = 2k n ID
5 = 2 × 5 × ID
ID = 2.5 mA
vsig At the peak of the sine wave,
0.5 V
= 0.25 mA, thus
id =
2 k
iDmax = ID + 0.25 = 2.75 mA
re
RL
vbe
vo
iDmin = ID − 0.25 = 2.25 mA
v̂ sig = v̂ gs + v̂ o = 0.05 + 0.5 = 0.55 V
v̂ o = 0.5 V
RL = 2 k
RL
RL + Ro
2
Av nominal =
2 + Ro
1.5
Av low =
1.5 + Ro
5
Av high =
5 + Ro
For Av high = 1.1 Av nominal
6.76 Av =
5
1.1 × 2
=
5 + Ro
2 + Ro
⇒ Ro = 0.357 k
v̂ be = 5 mV
From the figure above we see that
re
5 mV
=
RL
500 mV
RL
= 20 100
VT
25 mV
IE =
=
= 1.25 mA
re
20 ⇒ re =
At the peak of the output sine wave, we have
îe =
v̂ o
0.5
= 0.25 mA
=
RL
2
Chapter 6–27
v̂ be = 10 mV
RL
× v̂ be
v̂ o =
re
500
=
× 10
12.5
= 400 mV = 0.4 V
v̂ o
0.4
=
= 0.488 V
v̂ sig =
Gv
0.82
Thus,
iEmax = 1.25 + 0.25 = 1.5 mA
and
iEmin = 1.25 − 0.25 = 1.0 mA
From the figure, we have
Gv =
=
vo
=
v sig
RL
RL + re +
2
2 + 0.02 +
200
101
Rsig
β +1
(c) Gv o = 1
Rout = re +
= 0.5 V/V
= 111.5 Thus,
v̂ sig
Thus,
v̂ o
0.5 V
=
=
=1V
Gv
0.5 V/V
RL
RL + Rout
500
=1×
= 0.82 V/V
500 + 111.5
which is the same value obtained in (a) above.
Gv = Gv o
6.78 IC = 2 mA
re =
Rsig
10,000
= 12.5 +
β +1
101
VT
IE
VT
25
=
= 12.5 IC
2
For RL = 250 ,
RL
Gv = Gv o
RL + Rout
250
=1×
= 0.69 V/V
250 + 111.5
(a) Rin = (β + 1) (re + RL )
= 101 × (12.5 + 500) = 51.76 k
Rin
51.76
vb
=
=
v sig
Rin + Rsig
51.76 + 10
6.79 Rout = re +
= 0.84 V/V
5000
β +1
10,000
250 = re +
β +1
150 = re +
vb
vo
vo
=
×
v sig
v sig
vb
= 0.84 ×
Rsig
β +1
RL
RL + re
Subtracting Eq. (1) from Eq. (2), we have
5000
β +1
β + 1 = 50
0.5
= 0.84 ×
0.5 + 0.0125
100 =
= 0.82 V/V
Substituting in Eq. (1) yields
(b)
5000
50
⇒ re = 50 RL
Gv =
Rsig
RL + re +
β +1
1000
= 0.8 V/V
=
10, 000
1000 + 50 +
50
150 = re +
Rsig
ai
B
i
re
vsig RL
Rin
vbe
vo
6.80 (a) Refer to Fig. P6.80.
vc
−ic RC
=
v sig
ib RB + ie (re + RE )
=−
ic
ib
RC
ie
RB +
(re + RE )
ib
(1)
(2)
Chapter 6–28
= −β
RC
RB + (β + 1)(re + RE )
=−
ve
−ie RE
=
v sig
ib RB + ie (re + RE )
=
RC RL ro
Rsig
1
+
β
gm
Thus,
10 ro
1
0.1 +
gm
| Gv | =
RE
RB
+ re + RE
β +1
where ro and
(b)
vc
ic
RC
ie
vsig
ie = −
1
are in kilohms and are given by
gm
VA
25 V
=
IC
IC mA
(2)
1
VT
0.025 V
=
=
gm
IC
IC mA
(3)
I C (mA) 1/g m (k) r o (k) | Gv | (V/V)
RE
Y
v sig
re + RE
ic = −ic RC = −αie RC
−ic RC
vc
RC
=
=α
v sig
ie (re + RE )
re + RE
6.81 With the Early effect neglected, we can
write
Gv = −100 V/V
With the Early effect taken into account, the
effective resistance in the collector is reduced
from RC = 10 k to (RC ro ), where
ro =
ro =
(1)
VA
100 V
=
= 100 k
IC
1 mA
(RC ro ) = 10 100 = 9.1 k
0.1
0.250
250
27.5
0.2
0.125
125
41.2
0.5
0.050
50
55.6
1.0
0.025
25
57.1
1.25
0.020
20
55.6
Observe that initially | Gv | increases as IC is
increased. However, above about 1 mA this trend
reverses because of the effect of ro . From the
table we see that gain of 50 is obtained for IC
between 0.2 and 0.5 mA and also for IC above
1.25 mA. Practically speaking, one normally uses
the low value to minimize power dissipation. The
required value of IC is found by substituting for ro
and 1/gm from Eqs. (2) and (3), respectively, in
Eq. (1) and equating Gv to 50. The result (after
some manipulations) is the quadratic equation.
IC2 − 2.25IC + 0.625 = 0
The two roots of this equation are IC = 0.325 mA
and 1.925 mA; our preferred choice is
IC = 0.325 mA.
6.83
Thus, Gv becomes
Gv = −100 ×
9.1 k
10 k
i
= −91 V/V
0
6.82 Adapting Eq. (6.114) gives
RC RL ro
Gv = −β
Rsig + (β + 1)re
RC RL ro
=−
Rsig
β +1
+
re
β
β
Rsig
G
vsig
ro
vg
i
1
gm
RL
vo
Chapter 6–29
v g = v sig
RS =
Noting that ro appears in effect in parallel with
RL , v o is obtained as the ratio of the voltage
divider formed by (1/gm ) and (RL ro ),
Gv =
vo
vo
=
=
v sig
vg
(RL ro )
(RL ro ) +
1
gm
Also,
With RL removed,
ro
= 0.98
Gv =
1
ro +
gm
(1)
With RL = 500 ,
(500 ro )
Gv =
= 0.49
1
(500 ro ) +
gm
(2)
ro
1
=
gm
49
VDD
=3V
3
3
⇒ RD = = 3 k
1
VG = VS + VGS
ID RD =
Q.E.D.
From Eq. (1), we have
3
= 3 k
1
=3+2=5V
Thus the voltage drop across RG2 (5 V) is
larger than that across RG1 (4 V). So we
select
RG2 = 22 M
and determine RG1 from
4V
RG1
=
RG2
5V
⇒ RG1 = 0.8RG2 = 0.8 × 22
= 17.6 M
Substituting in Eq. (2) and solving for ro gives
ro = 25,000 = 25 k
RG1 = 18 M
Thus
1
25,000
=
gm
49
⇒ gm = 1.96 mA/V
6.84
VDD 9 V
RG1
Using only two significant figures, we
have
ID
RD
VD
VG
VS
Note that this will cause VG to deviate
slightly from the required value of 5 V.
Specifically,
RG2
VG = VDD
RG2 + RG1
22
=9×
= 4.95 V
22 + 18
It can be shown (after simple but somewhat
tedious analysis) that the resulting ID will be
ID = 0.986 mA, which is sufficiently close to the
desired 1 mA. Since VD = VDD − ID RD +6 V
and VG 5 V, and the drain voltage can go down
to VG − Vt = 4 V, the drain voltage is 2 V above
the value that causes the MOSFET to leave the
saturation region.
RS
RG2
6.85
5 V
ID = 1 mA
1
2
k n VOV
2
1
2
1 = × 2 × VOV
2
⇒ VOV = 1 V
RD
ID =
VG 0
VGS = Vt + VOV = 1 + 1 = 2 V
Now, selecting VS =
ID RS = 3
VDD
=3V
3
0
ID
RG
RS
10 M
5 V
Chapter 6–30
For ID = 0.5 mA
1
2
0.5 = k n VOV
2
1
2
= × 1 × VOV
2
⇒ VOV = 1 V
6.87
5 V
VGS = Vt + VOV = 1 + 1 = 2 V
ID
RD
VD
Since
VG = 0 V,
VS = −VGS = −2 V
RG
which leads to
VS − (−5)
−2 + 5
RS =
= 6 k
=
IC
0.5
VD is required to be halfway between cutoff
(+5 V) and saturation (0 − Vt = −1 V). Thus
VS
ID
RS
VD = +2 V
5 V
and
5−2
RD =
= 6 k
0.5
ID = 0.5 mA =
6.86
⇒ VGS = 1.5 V
VDD
RG1
RD
ID
VG 5 V
ID
RG2
1
× 4(VGS − 1)2
2
RS
3 k
Since VG = 0 V, VS = −1.5 V, and
−1.5 − (−5)
RS =
= 7 k
0.5
Maximum gain is obtained by using the largest
possible value of RD , that is, the lowest possible
value of VD that is consistent with allowing
negative voltage signal swing at the drain of 1 V.
Thus
VD − 1 = v Dmin = VG − Vt = 0 − 1
⇒ VD = 0 V
VS = ID RS = 3ID
VGS = 5 − VS = 5 − 3ID
1
ID = k n (VGS − Vt )2
2
1
= × 2(5 − 3ID − 1)2
2
= 16 − 24ID + 9ID2
9ID2 − 25I + 16 = 0
where we have assumed that the signal voltage at
the gate is small. Now,
VD = 0 = VDD − ID RD
0 = 5 − 0.5 × RD
⇒ RD = 10 k
6.88
ID = 1.78 mA or 1 mA
VDD
The first answer is physically meaningless, as it
would result in VS = 5.33 V, which is greater
than VG , implying that the transistor is cut off.
Thus, ID = 1 mA.
If a transistor for which k n = 3 mA/V2 is used,
then
1
ID = × 3(5 − 3ID − 1)2
2
= 1.5(16 − 24I + 9ID2 )
9ID2 − 24.67ID + 16 = 0
whose physically meaningful solution is
ID = 1.05 mA
RD
ID
VG 5 V
VS 2 V
ID
RS 2 k
Chapter 6–31
ID =
2V
= 1 mA
2 k
RD = 3 k
1
ID = k n (VGS − Vt )2
2
1
1 = × 2(VG − VS − Vt )2
2
1 = (5 − 2 − Vt )2
ID =
1
k p (VSG − |Vt |)2
2
1=
1
× 0.5(VSG − 1)2
2
Vt = 2 V
VS = VG + 3 = 3 + 3 = 6 V
But
⇒ VSG = 3 V
If Vt = 1.5 V, then we have
RS =
VS = ID RS = 2ID
VGS = VG − VS = 5 − 2ID
1
ID = × 2(5 − 2ID − 1.5)2
2
=
VG = 4 − |Vt | = 2 V
ID = 1.2 mA
VS = 2.4 V
6.89
VDD 10 V
R2 =
VG
2V
= 0.2 M
=
IG
10 μA
R1 =
VDD − VG
8V
= 0.8 M
=
IG
10 μA
VD = 3 V
IG
RD = 3 k
RS
ID
VS
VG
R2
10 − 6
= 4 k
1
(b) |Vt | = 2 V and k p = 1.25 mA/V2
4ID2 − 15ID + 12.25 = 0
R1
VDD − VS
ID
VD 3 V
ID 1 mA
RD
ID =
1
k p (VSG − |Vt |)2
2
1=
1
× 1.25(VSG − 2)2
2
VSG = 3.265 V
VS = VG + 3.265 = 2 + 3.265
= 5.265 V
ID = 1 mA and VD = 3 V
RS =
10 − 5.265
= 4.7 k
1
Thus,
VD
3V
=
= 3 k
ID
1 mA
For the transistor to operate 1 V from the edge of
saturation
RD =
6.90
VDD
VD = VG + |Vt | − 1
Thus,
RD
ID
3 = VG + |Vt | − 1
VG + |Vt | = 4 V
(a) |Vt | = 1 V and k p = 0.5 mA/V2
VG = 3 V
VG
3V
R2 =
= 0.3 M
=
IG
10 μA
VDD − VG
7V
R1 =
= 0.7 M
=
IG
10 μA
VD = 3 V
0V
RG
VGS
VSS
ID
RS
Chapter 6–32
(a) VGS + ID RS = VSS
But
ID =
SVIDt ≡
1 W
kn
(VGS − Vt )2
2
L
k n (VGS − Vt )Vt
1
k n (VGS − Vt )2
2
2Vt
2Vt
=−
=−
VGS − Vt
VOV
=−
= K(VGS − Vt )2
ID
K
⇒ VGS = Vt +
Vt
= ±5%, and
Vt
VOV = 0.25 V, we have
ID
Vt
= SVIDt
ID
Vt
ID
+ ID RS = VSS
K
Differentiating relative to K, we have
Vt +
ID
1 ∂ID
− 2
K ∂K
K
∂ID K
1
=
√
∂K ID
1 + 2 KID RS
SKID = 1/[1 + 2 KID RS ]
+ RS
∂ID
=0
∂K
Q.E.D
K
= ±0.1, and
(b) K = 100 μA/V2 ,
K
Vt = 1 V. We require ID = 100 μA and
ID
= ±0.01. Thus,
ID
0.01
ID /ID
SKID =
=
= 0.1
K/K
0.10
Substituting in the expression derived in (a),
0.1 =
√
1
1 + 2 0.1 × 0.1RS
⇒ RS = 45 k
To find VGS ,
ID = K(VGS − Vt )2
100 = 100(VGS − 1)2
VGS = 2 V
VGS + ID RS = VSS
2 + 0.1 × 45 = 6.5 V
(c) For VSS = 5 V and VGS = 2 V,
ID RS = 3 V
3
= 30 k
RS =
0.1
1
1
=
SKID =
√
7
1 + 2 0.1 × 0.1 × 30
1 K
1
ID
= ×
= × ±10% = ±1.4%
ID
7
K
7
6.91 (a) With a fixed VGS ,
ID =
1
k n (VGS − Vt )2
2
∂ID
= −k n (VGS − Vt )
∂Vt
Q.E.D
For Vt = 0.5 V,
Thus,
1
0+ √
2 ID /K
∂ID Vt
k n (VGS − Vt )Vt
=−
∂Vt ID
ID
2 × 0.5
× ±5%
0.25
= ∓20%
=−
(b) For fixed bias at the gate VG and a resistance
RS in the source lead, we have
VG = VGS + ID RS
where VGS is obtained from
1
ID = k n (VGS − Vt )2
2
2ID
⇒ VGS = Vt +
kn
Thus
Vt +
2ID
+ ID RS = VG
kn
Differentiating relative to Vt , we have
1
2 ∂ID
∂ID
1+ √
+ RS
=0
∂Vt
2 2ID /k n k n ∂Vt
∂ID
∂Vt
1
+ RS = −1
√
2k n ID
1
∂ID
=−
1
∂Vt
+ RS
√
2k n ID
∂ID Vt
Vt
SVIDt =
=−
∂Vt ID
ID
+ ID RS
2k n
But
1
2ID
2
ID = k n VOV ⇒ VOV =
2
kn
Thus
2Vt
Q.E.D
VOV + 2ID RS
Vt
For Vt = 0.5 V,
= ±5%, and
Vt
ID
VOV = 0.25 V, to limit
to +5% we
ID
require
SVIDt = −
SVIDt = 1
Chapter 6–33
1
× 0.5(10 − 10 ID − 1)2
2
⇒ ID2 − 1.84ID + 0.81 = 0
Thus
ID =
2 × 0.5
0.25 + 2ID RS
⇒ ID RS = 0.375 V
−1 = −
ID = 1.11 mA or 0.73 mA
For ID = 0.1 mA,
0.375
RS =
= 3.75 k
0.1
The first root results in VD = −0.11 V, which is
physically meaningless. Thus
6.92
(b) Vt = 2 V and k n = 1.25 mA/V2
ID = 0.73 mA
VG = VD = 10 − 10 × 0.73 = 2.7 V
1
× 1.25(10 − 10ID − 2)2
2
⇒ ID2 − 1.616ID + 0.64 = 0
ID =
5V
ID = 0.92 mA or 0.695 mA
RD
ID
0
RG
VD VG VGS
The first root can be shown to be physically
meaningless, thus
ID = 0.695 mA
VG = VD = 10 − 10 × 0.695 = 3.05 V
6.94
VDD 5 V
1
× 10(VGS − Vt )2
2
⇒ VGS = 1.2 V
5 − 1.2
= 19 k
RD =
0.2
ID = 0.2 =
~
– 1 mA
RD
RG1
6.93
VD
IG
1 mA
VDD 10 V
RG2
RG
10 M
VGS
0
RD 10 k
ID
ID
VDS
1
2
k n VOV
2
1
2
1 = × 8VOV
2
⇒ VOV = 0.5 V
ID =
Since the transistor leaves the saturation region of
operation when v D < VOV , we select
VD = VOV + 2
VGS = VDD − ID RD
= 10 − 10ID
(a) Vt = 1 V and k n = 0.5 mA/V2
1
ID = k n (VGS − Vt )2
2
VD = 2.5 V
Since IG ID , we can write
VDD − VD
5 − 2.5
= 2.5 k
=
RD =
ID
1
VGS = Vt + VOV = 0.8 + 0.5 = 1.3 V
Chapter 6–34
Thus the voltage drop across RG2 is 1.3 V and that
across RG1 is (2.5 − 1.3) = 1.2 V. Thus RG2 is
the larger of the two resistances, and we select
RG2 = 22 M and find RG1 from
RG1
1.2
⇒ RG1 = 20.3 M
=
RG2
1.3
Specifying all resistors to two significant digits,
we have RD = 2.5 k, RG1 = 22 M, and
RG1 = 20 M.
6.95
RB1
× 3 = 0.710
RB1 + RB2
RB2
= 3.225
RB1
Given that RB1 and RB2 are 1% resistors, the
maximum and minimum values of the ratio
RB2 /RB1 will be 3.225 × 1.02 = 3.2895 and
3.225 × 0.98 = 3.1605. The resulting VBE will be
0.699 V and 0.721 V, respectively.
Correspondingly, IC will be
⇒
To obtain IC = 1 mA, we write
1 mA
IC
IB =
=
= 0.01 mA
β
100
Thus,
RB =
VCC − VBE
IB
3 − 0.7
= 230 k
0.01
Since β ranges from 50 to 150 and IB is fixed at
0.01 mA, the collector current IC will range from
0.01 × 50 = 0.5 mA to 0.01 × 150 = 1.5 mA.
Correspondingly, VCE will range from
(3 − 0.5 × 2) = 1 V to (3 − 1.5 × 2) = 0 V. The
latter value implies that the high-β transistor will
leave the active region of operation and saturate.
Obviously, this bias method is very intolerant of
the inevitable variations in β. Thus it is not a
good method for biasing the BJT.
6.97
VCC 9 V
ICmax = 1 × e(0.710−0.699)/0.025
= 1.55 mA
0.06 mA
and
ICmin = 1 × e
R1
(0.710−0.721)/0.025
0.6 mA
RC
3V
VCE 3 V
ICmin = 0.64 mA
VCE will range from
VCEmin = 3 − 1.55 × 2 = −0.1 V
which is impossible, implying that the transistor
will saturate at this value of dc bias!
R2
RE
3V
VCEmax = 3 − 0.64 × 2 = 1.72 V
It should be clear that this biasing arrangement is
useless, since even the small and inevitable
tolerances in RB1 and RB2 caused such huge
variations in IC that in one extreme the transistor
left the active mode of operation altogether!
Initial design: β = ∞
RC = RE =
3V
= 5 k
0.6
6.96
R1 + R2 =
9
= 150 k
0.06
VB = VE + VBE = 3 + 0.7 = 3.7 V
VCC 3 V
R2 =
RC 2 k
VCE
RB
IB
3.7
= 61.7 k
0.06
R1 = 150 − 61.7 = 88.3 k
Using 5% resistors from Appendix J, and
selecting R1 and R2 so as to obtain a VBB that is
slightly higher than 3.7 V, we write
R1 = 82 k and R2 = 62 k
RE = 5.1 k and RC = 5.1 k
Chapter 6–35
VBB = VCC
IE =
62
R2
= 3.875
=9×
R1 + R2
62 + 82
VBB − VBE
RB
RE +
β +1
where
RB = R1 R2 = 62 82 = 35.3 k
IE =
3.875 − 0.7
= 0.58 mA
35.3
5.1 +
91
VE = 0.58 × 5.1 = 3.18
VB = 3.88 V
IC = αIE =
90
× 0.58 = 0.57 mA
91
VC = 6.1 V
IR2
VB
3.88
=
= 0.063 mA
=
R2
62
IB =
0.58
IE
=
= 0.006 mA and
β +1
91
For this value,
VBB − VBE
IE nominal = 0.946
RE
VBB − VBE
IE low = 0.90
= 0.95 IE nominal
RE
V
BE − VBE
IE high = 0.963
= 1.02 IE nominal
RE
Thus, the maximum allowable ratio is
RB
= 5.73
RE
VBB − VBE
(b) IE =
RB /RE
RE 1 +
β +1
VBB − VBE
IE RE =
5.73
1+
β +1
VBB − VBE
VCC
=
5.73
3
1+
101
⇒ VBB = VBE + 0.352VCC
(c) VCC = 5 V
IR1 = 0.069 mA
VBB = 0.7 + 0.352 × 5 = 2.46 V
6.98 Refer to Fig. 6.52.
RE =
(a) IE =
VBB − VBE
RB
RE +
β +1
RB = 5.73 × RE = 19.08 k
VBB = VCC
VBB − VBE
IE nominal =
RB
RE +
101
IE high
2.46 = 5
VBB − VBE
VBB − VBE
=
RB
RB
RE +
RE +
101
51
RB /RE
101
0.95 =
RB /RE
1+
51
RB
⇒
= 5.73
RE
R2
R1 + R2
R1 R2
= 5RB
R1 + R2
= 5 × 19.08
high
1+
R2
R1 + R2
2.46R1 = 5
VBB − VBE
=
RB
RE +
151
VBE − VBE
IE low =
RB
RE +
51
Let’s constrain IE low to be equal to IE nominal ×
0.95 and then check IE :
0.95
VCC /3
5/3
= 3.33 k
=
IE
0.5
⇒ R1 = 38.8 k
1
1
−
= 37.5 k
R2 = 1
RB
R1
(d) VCE = VCC − RC IG
1 = 5 − RC × 0.99 × 0.5
⇒ RC = 8.1 k
Check design:
VBB = VCC
37.5
R2
=5×
R1 + R2
37.5 + 38.8
= 2.46 V
RB = R1 R2 = 37.5 38.8 = 19.07 k
Chapter 6–36
IE nominal =
2.46 − 0.7
= 0.5 mA
19.07
3.33 +
101
IE low =
2.46 − 0.7
= 0.475 mA
19.07
3.33 +
51
, and
which is 5% lower than IE Thus,
IC = 0.432 − 0.39 = 0.042 mA
for a percentage increase of
IC
0.042
× 100 =
× 100 = 10.8%
IC
0.39
nominal
IE 2.46 − 0.7
= 0.509 mA
=
high
19.07
3.33 +
151
.
which is 1.8% higher than IE 6.100
5 V
nominal
6.99
3 V
RC
IC
VC
IB
RC
VC
VE
RB
RE
0.7 V
RE
0.4 mA
IE
5 V
3 V
−0.7 − (−3)
RE =
0.4
= 5.75 k
To maximize gain while allowing for ±1 V signal
swing at the collector, design for the lowest
possible VC consistent with
VC − 1 = −0.7 + VCEsat
= −0.7 + 0.3 = −0.4 V
VC = 0.6 V
VCC − VC
3 − 0.6
= 6.2 k
=
RC =
IC
0.39
As temperature increases from 25◦ C to 125◦ C,
(i.e., by 100◦ C), VBE decreases by 2 mV × 100 =
0.2 V
− 200 mV. Thus IE increases by
=
RE
0.2 V
= 0.035 mA to become 0.435 mA. The
5.75 k
collector current becomes
β
× 0.435
IC =
β +1
where β is the increased value of 150,
150
IC =
× 0.435 mA
151
= 0.432 mA
Required: IC = 0.5 mA and VC = VE + 2.
(a) β = ∞
VB = 0
VE = −0.7 V
VE − (−5)
4.3
IE = 0.5 =
=
RE
RE
⇒ RE = 8.6 k
VC = VE + 2 = −0.7 + 2 = +1.3 V
VCC − VC
5 − 1.3
RC =
=
= 7.4 k
IC
0.5
(b) βmin = 50
IE
0.5
IBmax =
=
0.01 mA
51
51
IE RE = 0.5 × 8.6 = 4.3 V
IBmax RBmax = 0.1IE RE = 0.43 V
0.43
RBmax =
= 43 k
0.01
(c) Standard 5% resistors:
RB = 43 k
RE = 8.2 k
RC = 7.5 k
(d) β = ∞:
VB = 0,
VE = −0.7 V
Chapter 6–37
−0.7 − (−5)
= 0.52 mA
8.2
IC = 0.52 mA
An equal positive swing is just possible. For
β = 150:
3 − 0.7
IE =
= 0.56 mA
120
3.3 +
151
VC = 3 − IE RC = 3 − 0.56 × 3.3 = 1.15 V
IE =
VC = 5 − 0.52 × 7.5 = 1.1 V
β = 50:
5 − 0.7
= 0.48 mA
43
8.2 +
51
VE = −5 + 0.48 × 8.2 = −1.064 V
IE =
Allowable negative signal swing at the collector
= 1.15 − 0.3 = 0.85 V. An equal positive swing
is possible.
VB = −0.364 V
50
× 0.48 = 0.47 mA
IC = αIE =
51
VC = 5 − 0.47 × 7.5 = 1.475 V
6.102
3 V
6.101
1.01 mA
3 V
RC
0.01 mA
IE
IE/(b 1)
1.5 V
RC
1 mA
VC
RB
IC
RB
Figure 1
IE
VC = VCEsat + 1 V
= 1.3 V
3 − 1.3
= 0.5 mA
IE =
RC
⇒ RC = 3.4 k
IE
0.5
IB =
=
0.005 mA
β +1
101
VC = VBE + IB RB
(a) From the circuit diagram of Fig. 1, we can
write
3 − 1.5
RC =
1.5 k
1.01 mA
1.5 = 0.01RB + VBE
= 0.01RB + 0.7
⇒ RB = 80 k
(b) Selecting 5% resistors, we have
1.3 = 0.7 + 0.005 × RB
RC = 1.5 k
⇒ RB = 120 k
RB = 82 k
VCC − VBE
IE =
RB
RC +
β +1
3 − 0.7
=
= 0.99 mA
82
1.5 +
101
IC = αIE = 0.99 × 0.99 = 0.98 mA
Standard 5% resistors:
RC = 3.3 k
RB = 120 k
If the actual BJT has β = 50, then
3 − 0.7
VCC − VBE
= 0.41 mA
=
IE =
RB
120
RC +
3.3 +
β +1
51
VC = 3 − IE RC = 3 − 0.41 × 3.3 = 1.65 V
Allowable negative signal swing at the collector
is as follows:
VC − VCEsat = 1.65 − 0.3 = 1.35 V
VC = 3 − 1.5 × 0.99 = 1.52 V
(c) β = ∞:
VCC − VBE
3 − 0.7
IC = IE =
= 1.53 mA
=
RC
1.5
VC = 0.7 V
Chapter 6–38
(d) From the circuit diagram of Fig. 2, we can
write
3 V
IC 1 mA
I = 1.01 mA
VC = 1.5 V = IB RB + VBE
0.7 V
IB2 IB
IC
β
1
=1 1+
β
IC 2IB
RB1
I = IC + IB
= IC +
RC
2IB
IC = 1 mA
IB
1.5 = 0.01 × RB + 0.7
RB2
RB = 80 k
Figure 2
6.104 Refer to the circuit in Fig. P6.104.
Replacing VCC together with the voltage divider
(R1 , R2 ) by its Thévenin equivalent results in the
circuit shown below.
1
IC
=
= 0.01 mA
β
100
0.7
0.7
RB2 =
=
IB2
0.01
= 70 k
IB =
IO aIE
1.5 = 2IB RB1 + 0.7
0.8 = 2 × 0.01 × RB1
IE /(b1)
RB1 = 40 k
3 − 1.5
1.5
RC =
= 1.47 k
=
IC + 2IB
1.02
For β = ∞:
0.7
0.7
IB = 0, IB2 =
=
= 0.01 mA
RB2
70
IB1 = IB2 = 0.01 mA
RB
IE
VBB
RE
VC = 0.01RB1 + 0.7 = 0.01 × 40 + 0.7
= 1.1 V
3 − 1.1
3 − 1.1
= 1.29
=
RC
1.47
IC = 1.28 mA
IC + 0.01 =
6.103
where
VBB = VCC
R2
R1 + R2
and
RB = (R1 R2 )
I
Now,
VC
IB
RB
VBB =
IC
IE =
IE
RB + VBE + IE RE
β +1
VBB − VBE
RE + (R1 R2 )/(β + 1)
IC = αIE
=α
VCC [R2 /(R1 + R2 )] − VBE
RE + (R1 R2 )/(β + 1)
Chapter 6–39
To obtain IO = 0.5 mA,
6.105
0.5 =
VCC
R1
I
IO
0
Q1
10
VCC
=
2RE
2RE
⇒ RE = 10 k
R1 = R2 = 8.6 k
6.106
VB
5 V
I
Q2
IO
RE
50.7
R
IE R2
R
0.7 V
VCC − VBE1 − VBE2
R1 + R2
VB = IR2 + VBE2 + VBE1
I=
IO
VE3 = VB − VBE3
VE3 = IR2 + VBE2 + VBE1 − VBE3
R2
= (VCC − VBE1 − VBE2 )
+ VBE1
R1 + R2
+VBE2 − VBE3
VE
α
R2
IO =
=
(VCC − VBE1 − VBE2 )
RE
RE
R1 + R2
+ VBE1 + VBE2 − VBE3
Now, for R1 = R2 and the currents in all junctions
equal,
VBE1 = VBE2 = VBE3 = VBE
1
1
IO =
(VCC − 2VBE ) × + VBE
RE
2
VCC
Q.E.D
IO =
2RE
Thus,
VCC
IO RE =
2
VCC
+ VBE
VB =
2
VCC
I = (VB − 2VBE )/R2 =
− VBE
R2
2
But since I must be equal to IO , we have
VCC /2 − VBE
VCC
=
2RE
R2
Thus,
VCC − 2VBE
R1 = R2 = RE
VCC
For VCC = 10 V and VBE = 0.7 V,
10 − 1.4
= 0.86RE
R1 = R2 = RE
10
IO = αIE
0.5 mA
IE = 0.5 mA
5 − 0.7
= 8.6 k
0.5
= 0.7 − VECsat = 0.7 − 0.3
⇒R=
v Cmax
= +0.4 V
6.107 Refer to the equivalent circuit in
Fig. 6.55(b).
Rin
Gv = −
gm (RD RL ro )
Rin + Rsig
=−
RG
gm (RD RL ro )
RG + Rsig
10
× 3 × (10 20 100)
10 + 1
= −17 V/V
=−
6.108 (a) Refer to Fig. P6.108. The dc circuit can
be obtained by opening all coupling and bypass
capacitors, resulting in the circuit shown
in Fig. 1 on next page.
See analysis on figure.
VGS = 2 − 1 = 1 V
VOV = VGS − Vt = 1 − 0.7 = 0.3 V
Since VD at 2.5 V is 1.2 V higher than
VS + VOV = 1 + 0.3 = 1.3 V, the transistor is
indeed operating in saturation. (Equivalent
Chapter 6–40
To remain in saturation,
v̂ DS ≥ v̂ GS − Vt
2.5 − 8.1v̂ gs ≥ 2 + v̂ gs − 0.7
This is satisfied with equality at
2.5 − 1.3
= 0.132 V
v̂ gs =
9.1
The corresponding value of v̂ sig is
120 + 120
= 2 × 0.132 = 0.264 V
v̂ sig = v̂ gs
120
The corresponding amplitude at the output
will be
| Gv |v̂ sig = 4.1 × 0.264 = 1.08 V
Figure 1
VD = 2.5 V is higher than VG − Vt = 1.3 V by
1.2 V.)
1
2
ID = k n VOV
2
1
0.5 = k n × 0.33
2
⇒ k n = 11.1 mA/V2
(d) To be able to double v̂ sig without leaving
saturation, we must reduce v̂ gs to half of what
would be its new value; that is, we must keep v̂ gs
unchanged. This in turn can be achieved by
connecting an unbypassed Rs equal to 1/gm ,
1
= 300 Rs =
3.33 mA/V
Since v̂ gs does not change, the output voltage also
will not change, thus v̂ o = 1.08 V.
(b) The amplifier small-signal equivalent-circuit
model is shown in Fig. 2 below.
6.109 Refer to Fig. P6.109.
Rin = RG1 RG2 = 300 k 200 k = 120 k
2ID
2 × 0.5
gm =
= 3.33 mA/V
=
VOV
0.3
VA
50
= 100 k
=
ro =
ID
0.5
Rin
gm (ro RD RL )
Gv = −
Rin + Rsig
120
× 3.33 × (100 5 5)
=−
120 + 120
= −4.1 V/V
(c) VG = 2 V,
v̂ GS = 2 + v̂ gs ,
(a) DC bias:
|VOV | = 0.3 V ⇒ VSG = |Vtp | + |VOV | = 1 V
Since VG = 0 V, VS = VSG = +1 V, and
2.5 − 1
= 0.3 mA
ID =
RS
1.5
= 5 k
⇒ RS =
0.3
(b) Gv = −gm RD
where
VD = 2.5 V
gm =
v̂ DS = 2.5 − | Av |v̂ gs
2ID
2 × 0.3
=
= 2 mA/V
VOV
0.3
Thus,
where
−10 = −2RD ⇒ RD = 5 k
| Av | = gm (ro RD RL ) = 8.1 V/V
This figure belongs to Problem 6.108.
Rsig
vsig RG1
RG2
vgs
gmvgs
Rin RG RG1 // RG2
Figure 2
ro
RD
5 k
RL
5 k
vo
Chapter 6–41
(c) v G = 0 V (dc) + v sig
v Gmin = −v̂ sig
v̂ D = VD + | Gv |v̂ sig
where
VD = −2.5 + ID RD = −2.5 + 0.3 × 5 = −1 V
To remain in saturation,
v̂ D ≤ v̂ G + |Vtp |
−1 + 10 v̂ sig ≤ −v̂ sig + 0.7
Satisfying this constraint with equality gives
v̂ sig = 0.154 V
and the corresponding output voltage
v̂ d = | Gv |v̂ sig = 1.54 V
(d) If v̂ sig = 50 mV, then
VD + | Gv |v̂ sig = −v̂ sig + |Vtp |
where
VD = −2.5 + ID RD = −2.5 + 0.3RD
| Gv | = gm RD = 2RD
Thus
−2.5 + 0.3RD + 2RD v̂ sig = −v̂ sig + |Vtp |
−2.5 + 0.3RD + 2RD × 0.05 = −0.05 + 0.7
0.4RD = 3.15
⇒ RD = 7.875 k
Gv = −gm RD = −2 × 7.875 = −15.75 V/V
6.110 Refer to Fig. P6.110.
1
= 50 gm2
1
A/V = 20 mA/V
50
If Q1 is biased at the same point as Q2 , then
⇒ gm2 =
gm1 = gm2 = 20 mA/V
id 1 = gm1 × 5 (mV)
= 20 × 0.005 = 0.1 mA
v d 1 = id 1 × 50 = 0.1 × 50 = 5 mV
v o = id 1 RD = 1 V
RD =
v o = 14.3 × v i2 = 14.3 × 0.5v i
vo
= 7.15 V/V
vi
6.112 (a) DC bias: Refer to the circuit in Fig.
P6.112 with all capacitors eliminated:
Rin at gate = RG = 10 M
and
Ri2 =
6.111 (a) Refer to the circuit of Fig. P6.111(a):
v o1
10
10
Av o ≡
=
=
= 0.99 V/V
1
1
vi
10 +
10 +
gm
10
1
Ro =
10 k = 0.1 10 = 99 gm
(b) Refer to Fig. P6.111(b):
1
Rin = 10 k
= 10 0.1 = 99 gm
vo
5 2
=
= 10(5 2) = 14.3 V/V
v i2
1/gm
Rin
(c) v i2 = (Av o v i )
Rin + Ro
99
= 0.99 × v i ×
99 + 99
0.5v i
1V
= 10 k
0.1 mA
VG = 0, thus VS = −VGS , where VGS can be
obtained from
1
2
ID = k n VOV
2
1
2
0.4 = × 5 × VOV
2
⇒ VOV = 0.4 V
VGS = Vt + 0.4 = 0.8 + 0.4 = 1.2 V
VS = −1.2 V
−1.2 − (−5)
= 9.5 k
RS =
0.4
To remain in saturation, the minimum drain
voltage must be limited to VG − Vt =
0 − 0.8 = −0.8 V. Now, to allow for 0.8-V
negative signal swing, we must have
VD = 0 V
and
5−0
= 12.5 k
0.4
2ID
2 × 0.4
= 2 mA/V
(b) gm =
=
VOV
0.4
VA
40
=
= 100 k
ro =
ID
0.4
(c) If terminal Z is connected to ground, the
circuit becomes a CS amplifier,
vy
RG
=
× −gm (ro RD RL )
Gv = −
v sig
RG + Rsig
RD =
10
× 2 × (100 12.5 10)
10 + 1
= −9.6 V/V
=−
Chapter 6–42
(d) If terminal Y is grounded, the circuit becomes
a CD or source-follower amplifier:
vz
(RS ro )
=
1
vx
(RS ro ) +
gm
(9.5 100)
= 0.946 V/V
=
1
(9.5 100) +
2
Looking into terminal Z, we see Ro :
1
Ro = RS ro
gm
1
= 473 = 9.5 100
2
(e) If X is grounded, the circuit becomes a CG
amplifier.
VOV = 0.2 V
VGS = Vt + VOV
= 0.6 + 0.2 = 0.8 V
From the voltage divider (R1 , R2 : see Fig. 1), we
can write
R1
0.5
VD =
VD = 0.5VD
VGS =
R1 + R2
0.5 + 0.5
Thus
VD = 2VGS = 1.6 V
1
2
ID = k n VOV
2
1
= × 5 × 0.22 = 0.1 mA
2
VD
1.6 V
=
= 1.6 μA
Idivider =
1 M
1 M
IRD = 0.1 + 0.0016
RD
RD =
vy
0.102 mA
VDD − VD
10 − 1.6
=
= 82.4 k
IRD
0.102
2ID
2 × 0.1
= 1 mA/V
=
VOV
0.2
(c) Replacing the MOSFET with its T model
results in the amplifier equivalent circuit shown in
Fig. 2. At the output node,
(b) gm =
vsg
isig 50 A
RS
v o = i[RD (R1 + R2 )]
v o = iRD
Rsig 100 k
(1)
vo
The figure shows the circuit prepared for signal
calculations.
1
v sg = isig × Rsig RS
gm
1
(k)
= 50 × 10−3 (mA) 100 9.5
2
= 0.024 V
R2
i
0
bvo
i
1/gm
R1
v y = (gm RD )v sg
vsig
= (2 × 12.5) × 0.024 = 0.6 V
6.113 (a) DC bias:
Figure 2
VDD 10 V
RD
RD
R2 0.5 M
VD
R1 0.5 M
RD
where
= RD (R1 + R2 ). The voltage at the
gate is a fraction β of v o with
R1
β=
R1 + R2
Now, the current i can be found from
v sig − βv o
i=
= gmv sig − βgmv o
(2)
1/gm
Substituting for i from Eq. (2) into Eq. (1) yields
v o = (gm v sig − βgm v o )RD
VGS
Thus
gm RD
vo
=
v sig
1 + βgm RD
Figure 1
Chapter 6–43
=
=
1/β
1/β
1+
gm RD
1 + (R2 /R1 )
1 + R2 /R1
1+
gm RD
(3)
Q.E.D
The input resistance Rin can be obtained as
follows:
v sig
Rin =
i
Substituting for i from Eq. (1) yields
v sig R
Rin =
vo D
v sig
and replacing
by the inverse of the gain
vo
expression in Eq. (3) gives
Rin = RD
1
1
+
gm RD
1 + (R2 /R1 )
1
R1
1 + gm RD
Q.E.D
gm
R1 + R2
(d) Substituting numerical values:
1 + (0.5/0.5)
vo
=
1 + (0.5/0.5)
v sig
1+
1 × (82.4 1000)
2
= 1.95 V/V
=
2
1+
76.13
R2
Note that the gain 1 +
= 2, similar to that
R1
of an op amp connected in the noninverting
configuration!
Rin =
0.5
1
1 + 1 × (82.4 1000)
1
0.5 + 0.5
= 39.1 k
Rin =
6.114 (a) DC bias:
= 0.107 mA
The current in the voltage divider is
VD
4
=
= 1.6 μA = 0.0016 mA
R1 + R2
2.5
Thus the current through RD will be
(0.107 + 0.0016) 0.109 mA and
10 − 4
VDD − VD
RD =
=
= 55 k
0.109
0.109
2ID
2 × 0.107
(b) gm =
=
= 1.07 mA/V
VOV
0.2
VA
60
ro =
= 561 k
=
ID
0.107
(c) Upon replacing the MOSFET with its
hybrid-π model, we obtain the small-signal
equivalent circuit of the amplifier, shown in Fig. 2
on the next page.
I=
Node equation at the output:
v o − v gs
vo
vo
+
+
+ gm v gs = 0
RD
ro
R2
1
1
1
1
vo
+ +
= −gm 1 −
v gs
RD
ro
R2
gm R2
Thus,
v o = − gm (RD ro
VDD 10 V
VD
R1 0.5 M
Figure 1
VGS = Vt + VOV
= 0.6 + 0.2 = 0.8 V
1
R2 ) 1 −
v gs
gm R2
(1)
R2
R1
+ vo
(2)
R1 + R2
R1 + R2
Substituting for v gs from Eq. (2) into Eq. (1)
yields
R2
R1
v o = −Av sig
− Av o
R1 + R2
R1 + R2
where
1
A = gm (RD ro R2 ) 1 −
gm R2
Thus,
R1
R2
v sig
= −A
vo 1 + A
R1 + R2
R1 + R2
R2
−A
vo
R1 + R2
=
R1
v sig
1+A
R1 + R2
v gs = v sig
R2 2 M
ID
A
Next, we express v gs in terms of v sig and v o using
superposition:
RD
VGS
From the voltage divider (R1 , R2 : see Fig. 1), we
can write
R1
0.5
VGS = VD
= VD
R1 + R2
0.5 + 2
VD = 5VGS = 5 × 0.8 = 4 V
1
VDS
2
ID = k n VOV 1 +
2
VA
1
4
ID = × 5 × 0.22 1 +
2
60
Chapter 6–44
This figure belongs to Problem 6.114(c).
(vo vgs)⁄R2
R2
R1
vsig vo
gmvgs
vgs
RD
ro
Figure 2
−R2 /R1
1 + R2 /R1
1+
A
Thus,
R2 /R1
vo
=−
1 + R2 /R1
v sig
1+
gm (RD ro R2 )(1 − 1/gm R2 )
RB = R1 R2 = 15 27 = 9.643 k
=
IC =
Q.E.D
Substituting numerical values yields
vo
=
v sig
2/0.5
−
1 + (2/0.5)
1+
1.07(55 561 2000)(1 − 1/1.07 × 2000)
= −
4
5
1+
52.6
0.99(5.357 − 0.7)
= 1.85 mA
9.643
2.4 +
101
gm =
IC
1.85 mA
= 74 mA/V
=
VT
0.025 V
rπ =
β
100
=
= 1.35 k
gm
74
Replacing the BJT with its hybrid-π model
results in the equivalent circuit shown at the
bottom of the page:
Rin = R1 R2 rπ = RB rπ = 9.643 1.35
= 1.18 k
Rin
vπ
1.18
=
= 0.371 V/V
=
v sig
Rin + Rsig
1.18 + 2
= −3.65 V/V
vo
= −gm (RC RL )
vπ
Note that the gain is nearly equal to −R2 /R1 =
− 4, which is the gain of an op amp connected in
the inverting configuration.
= −74(3.9 2) = −97.83
vo
= −0.371 × 97.83 = −36.3 V/V
v sig
6.115 Refer to the circuit of Fig. P6.115.
IC =
α(VBB − VBE )
RB
RE +
β +1
6.116 Refer to the circuit of Fig. P6.116.
DC design:
VB = 5 V,
where
VBB = VCC
R2
15
= 5.357 V
= 15 ×
R2 + R1
15 + 27
VBE = 0.7 V
VE = 4.3 V
This figure belongs to Problem 6.115.
Rsig
vo
vsig R1
R2
vp
Rin
rp
gmvp
RC
RL
Chapter 6–45
For
VE
4.3
= 2.15 k
=
IE = 2 mA, RE =
IE
2
5
IR2 = 0.2 mA, R2 =
= 25 k
0.2
2
IE
=
0.02 mA
IB =
β +1
101
IR1 = IR2 + IB = 0.2 + 0.02 = 0.22 mA
VCC − VB
15 − 5
R1 =
= 45.5 k
=
IR1
0.22
Choosing 5% resistors:
RE = 2.2 k,
R1 = 47 k,
R2 = 24 k
For these values,
VBB − VBE
IE =
RB
RE +
β +1
where
24
R2
= 5.07 V
= 15 ×
VBB = VCC
R1 + R2
24 + 47
RB = R1 R2 = 47 24 = 15.89 k
5.07 − 0.7
= 1.85 mA
IE =
15.89
2.2 +
101
VB = IE RE + VBE = 1.85 × 2.2 + 0.7 = 4.8 V
IC = αIE = 0.99 × 1.85 = 1.84 mA
IC
1.84
gm =
= 73.4 mA/V
=
VT
0.025
β
100
rπ =
= 1.36 k
=
gm
73.4
Rin = R1 R2 rπ = 47 24 1.36 = 1.25 k
Rin
1.25
vπ
=
=
= 0.385 V/V
v sig
Rin + Rsig
1.25 + 2
For an overall gain of −40 V/V,
40
vo
= −104 V/V
=−
vπ
0.385
But
vo
= −gm (RC RL )
vπ
−104 = −73.4 (RC 2)
which is slightly higher than the required gain,
and we will obtain
VC = 15 − 5.1 × 1.84 = 5.6 V
which allows for only 1.2-V negative signal
swing.
6.117 Refer to the circuit of Fig. P6.117.
DC voltage drop across RB = 0.2 V, and
IB RB = 0.2 V
I
RB = 0.2 V
β +1
IRB = 0.2 × 101
(1)
Rin = RB rπ = 10 k
VT
RB
= 10
IB
0.025
RB
= 10
I /(β + 1)
0.025 × 101
RB
= 10
I
0.025 × 101
I
= 10
0.025 × 101
RB +
I
0.025 × 101RB
= 10
IRB + 0.025 × 101
Substituting for IRB from Eq. (1) yields
RB ×
0.025 × 101RB
= 10
0.2 × 101 + 0.025 × 101
0.025RB
= 10
0.225
⇒ RB = 90 k
0.2 × 101
I=
= 0.22 mA
90
To maximize the open-circuit voltage gain
between base and collector while ensuring that
the instantaneous collector voltage does not fall
below (v B − 0.4) when v be is as high as 5 mV, we
impose the constraint
(RC 2) = 1.416
VC − | Av o | × 0.005 = VB + 0.005 − 0.4
RC = 4.86 k
where
We can select either 4.7 k or 5.1 k. With
4.7 k, the gain will be
vo
= −0.385 × 73.4 × (4.7 2) = −39.6 V/V
v sig
which is slightly lower than the required
−40 V/V, and we will obtain
VC = VCC − IC RC
VC = 15 − 4.7 × 1.84 = 6.4 V
allowing for about 2 V of negative signal swing
at the collector. If we choose 5.1 k, the gain
will be
vo
= −0.385 × 73.4 × (5.1 2) = −40.6 V/V
v sig
(2)
= 5 − 0.99 × 0.22RC
= 5 − 0.22RC
| Av o | = gm RC =
0.99 × 0.22
RC = 8.7RC
0.025
and
VB = −
0.22
× 90 = −0.2 V
101
Thus,
5 − 0.22RC − 8.7RC × 0.005 = −0.2 − 0.395
Chapter 6–46
β
100
= 5 k
=
gm
20
vo
5
Gv =
=−
× 20 × (5 10)
v sig
5 + 2.5
⇒ RC = 21.2 k
rπ =
Selecting 5% resistors, we find
RB = 91 k
RC = 22 k
and specifying I to one significant digit gives
I = 0.2 mA
αIC
0.2
gm =
= 8 mA/V
VT
0.025
Av o = −gm RC = −8 × 22 = −176 V/V
β
100
=
= 12.5 k
rπ =
gm
8
Rin = RB rπ = 91 12.5 = 11 k
11
× 8(22 20)
Gv = −
20 + 11
= −29.7 V/V
6.119 Refer to the circuit of Fig. P6.119.
(a) DC analysis of each of the two stages:
VBB = VCC
47
R2
= 4.8 V
= 15
R1 + R2
100 + 47
RB = R1 R2 = 100 47 = 32 k
IE =
VBB − VBE
RB
RE +
β +1
4.8 − 0.7
= 0.97 mA
32
3.9 +
101
IC = αIE 1 mA
=
6.118 Refer to the circuit of Fig. P6.118.
(a) IE = 0.5 mA. Writing a loop equation for the
base–emitter circuit results in
IB Rsig + VBE + IE RE = 3
IE
Rsig + VBE + IE RE = 3
β +1
0.5
× 2.5 + 0.7 + 0.5RE = 3
101
⇒ RE = 4.6 k
(b) IC = αIE
= −44.4 V/V
VC = VCC − IC RC = 15 − 1 × 6.8 = 8.2 V
(b) See figure below.
IC
gm =
= 40 mA/V
VT
β
rπ =
= 2.5 k
gm
(c) Rin1 = R1 R2 rπ = RB rπ = 32 2.5
= 2.32 k
v b1
Rin
2.32
= 0.32 V/V
=
=
v sig
Rin + Rsig
2.32 + 5
0.5 mA
VC = 0.5 = 3 − 0.5RC
(d) Rin2 = R1 R2 rπ = Rin1 = 2.32 k
v b2
v b2
=
= −gm (RC Rin2 )
v b1
v π1
⇒ RC = 5 k
IC
0.5 mA
(c) gm =
= 20 mA/V
=
VT
0.025 V
= −40(6.8 2.32) = −69.2 V/V
This figure belongs to Problem 6.118.
Rsig
vo
vsig 1 mA
rp
vp
gmvp
This figure belongs to Problem 6.119.
RC
RL
Chapter 6–47
vo
vo
=
= −gm (RC RL )
v b2
vπ2
= −40(6.8 2) = −61.8 V/V
vo
v b2
v b1
vo
=
×
×
= −61.8
(f)
v sig
v b2
v b1
v sig
(e)
× − 69.2 × 0.32 = 1368.5 V/V
From Fig. 1 we see that
IC = 0.495 mA
VC = IB × 200 k + IE × 0.2 k + VBE
= 0.005 × 200 + 0.5 × 0.2 + 0.7
= 1.18 V
(b)
6.120 Refer to the circuit in Fig. P6.120:
Rin = 200 k (β + 1)(re + Re )
For v be to be limited to 5 mV, the signal between
base and ground will be 10 mV (because of the
5 mV across Re ). The limit on v sig can be obtained
by dividing the 10 mV by v b /v sig ,
10 mV
= 15 mV
0.668
Correspondingly, at the output we have
v̂ sig =
v̂ o = | Gv |v̂ sig = 13.4 × 15 = 200 mV = 0.2 V
6.121 (a)
0.5 mA
VC
0.495 mA
200 k
i
= 200 50.5 = 40.3 k
vb
Rin
40.3
= 0.668 V/V
=
=
v sig
Rin + Rsig
40.3 + 20
vo
Total resistance in collector
= −α
vb
Total resistance in emitter
20 20
−
= −20 V/V
0.25 + 0.25
vo
Gv =
= −0.668 × 20 = −13.4 V/V
v sig
i
200 k
vi
= 200 [101 × (0.25 + 0.25)]
vo
vo vi
200
IE = 0.1 mA
VT
25 mV
re =
=
= 250 IE
0.1 mA
IC
0.1 mA
gm =
= 4 mA/V
VT
0.025 V
Note that the emitter has a resistance
Re = 250 .
0.5 mA
200 Figure 1
re 50 200 Figure 2
From Fig. 2, we have
IC
0.495
=
20 mA/V
VT
0.025
VT
re =
= 50 IE
vi
vi
=
i=
re + Re
50 + 200
vi
vi
=
=
= 4 v i , mA
250 0.25 k
Node equation at the output:
vo
vo − vi
+ αi +
=0
20
200
vo
vi
vo
+ 0.99 × 4v i +
−
=0
20
200 200
1
1
1
vo
+
= −v i 4 × 0.99 −
20 200
200
vo
= −71.9 V/V
vi
gm =
6.122 (a) IE =
3 − 0.7
100
1+
β +1
β = 50:
2.3
= 0.78 mA
100
1+
51
VE = IE RE = 0.78 V
IE =
0.005 mA
20 k
VB = VE + 0.7 = 1.48 V
β = 200:
2.3
IE =
= 1.54 mA
100
1+
201
Chapter 6–48
VE = IE RE = 1.54 V
The dc emitter current is equal to 0.5 mA, and
IC = αIE 0.5 mA; also,
VT
25 mV
=
= 50 re =
IE
0.5 mA
Rin = re = 50 −v sig
−v sig
=
ie =
re + Rsig
50 + 50
−v sig
−v sig
=
=
100 0.1 k
At the output node,
VB = VE + 0.7 = 2.24 V
(b) Rin = 100 (β + 1)[re + (1 1)]
= 100 (β + 1)(re + 0.5)
β = 50:
VT
25 mV
re =
= 32.1 =
IE
0.78 mA
Rin = 100 [51 × (0.0321 + 0.5)]
= 21.3 k
v o = −αie (5 100)
v sig
(5 100)
=α
0.1
vo
5 100
47.6 V/V
=α
v sig
0.1
β = 200:
VT
25 mV
re =
= 16.2 =
IE
1.54 mA
Rin = 100 [201 × (0.0162 + 0.5)]
= 50.9 k
vb
Rin
(c)
=
v sig
Rin + Rsig
6.124 Refer to the circuit in Fig. P6.124.
For dc analysis, open-circuit the two coupling
capacitors. Then replace the 9-V source and the
two 20-k resistors by their Thévenin equivalent,
namely, a 4.5-V source and a 10-k series
resistance. The latter can be added to the 10-k
resistor that is connected to the base. The result is
the circuit shown in Fig. 1, which can be used to
calculate IE .
(1 1)
500
vo
=
=
(re in )
vb
(1 1) + re
500 + re
β = 50:
vb
21.3
= 0.68 V/V
=
v sig
21.3 + 10
vo
500
= 0.94 V/V
=
vb
500 + 32.1
vo
= 0.68 × 0.94 = 0.64 V/V
v sig
9 V
β = 200:
4.5 V 20 k
vb
50.9
=
= 0.836 V/V
v sig
50.9 + 10
vo
500
=
= 0.969 V/V
vb
500 + 16.2
vo
= 0.836 × 0.969 = 0.81 V/V
v sig
IE
2 k
Figure 1
6.123 Refer to the circuit in Fig. P6.123.
vo
100 k
ie
ie
5 k
4.5 − 0.7
20
2+
β +1
3.8
= 1.73 mA
20
2+
101
IC = αIE = 0.99 × 1.73 mA
=
re 50 Rsig 50 v
sig
Rin re 50 (a) IE =
= 1.71 mA
IC
gm =
= 68.4 mA/V
VT
VT
25 mV
re =
= 14.5 =
IE
1.73 mA
= 0.0145 k
Chapter 6–49
rπ = (β + 1)re = 101 × 0.0145
= 1.4645 k
(c) When CB is open-circuited, the equivalent
circuit becomes that shown in Fig. 3.
(b) Replacing the BJT with its T model (without
ro ) and replacing the capacitors with short circuits
results in the equivalent-circuit model shown in
Fig. 2.
Figure 3
Thus,
Figure 2
Rin = 20 k Rib
= 20 k (β + 1)(Re + 2)
From Fig. 2 we see that
re (10 2)
v e = ie + ie
10
re + ie re
v b = v e + ie re = ie (10 2) 1 +
10
re
ii = (1 − α)ie + ie
10
ie
re
+ ie
=
β +1
10
We can now obtain Rin from
re (10
2)
1
+
+ re
vb
10
Rin ≡
=
1
re
ii
+
β + 1 10
re + (β + 1)re
(β + 1)(10 2) 1 +
10
=
re
1 + (β + 1)
10
=
101 × (10 2) × (1 + 0.00145) + 101 × 0.0145
1 + 101 × 0.00145
168.577 + 1.4645
= 148.3 k
1 + 0.14645
vb
Rin
148.3
=
=
= 0.937
v sig
Rin + Rsig
148.3 + 10
re ie 1 +
(10 2)
ve
vo
10
=
= re
vb
vb
ie 1 +
(10 2) + ie re
10
1.00145 × (10 2)
=
1.00145 × (10 2) + 0.0145
= 0.991 V/V
vo
Gv ≡
= 0.937 × 0.991 = 0.93 V/V
v sig
=
= 20 101 × 2.0145
= 18.21 k
which is greatly reduced because of the absence
of bootstrapping. The latter causes the lower node
of the 10-k base-biasing resistor to rise with the
output voltage, thus causing a much reduced
signal current in the 10-k resistor and a
correspondingly larger effective resistance across
the amplifier input.
The reduced Rin will result in a reduction in
v b /v sig ,
Rin
vb
18.21
=
=
v sig
Rin + Rsig
28.21
= 0.646 V/V
2
vo
=
= 0.993
vb
2 + 0.0145
vo
= 0.646 × 0.993
Gv ≡
v sig
= 0.64 V/V
which is much reduced relative to the value
obtained with bootstrapping.
6.125
(a) Applying Thévenin’s theorem to the
base-biasing circuit of Q1 results in the dc circuit
shown below. From our partial analysis on the
figure, we can write
IE1 = 0.1 mA
IE2 = 5 mA
Chapter 6–50
VB1 can be obtained as
where
VB1 = 2.5 − 2 μA × 0.5 M = 1.5 V
re2 =
and VB2 can be found as
vo
v b2
VB2 = VB1 − 0.7 = 0.8 V
25 mV
=5
5 mA
1000
=
= 0.995 V/V
1000 + 5
Rib2 = (β2 + 1)(re2 + RL )
= 101 × 1.005 = 101.5 k
0.5 M
(c) Rin = 1 M 1 M (β + 1)(re1 + Rib2 )
100
51
2.5 V
2 A
100 A 0.1 mA
where
VT
25 mV
re =
=
= 250 = 0.25 k
IE1
0.1 mA
0.05 mA
50 A
50 A
Rin = 0.5 M [51 × (0.25 + 101.5)] k
5 mA
= 0.5 M 5.2 M
= 456 k
v e1
Rib
101.5
=
=
v b1
Rib + re1
101.5 + 0.25
(b) Refer to the circuit in Fig. P6.125. With a
load resistance RL = 1 k connected to the
output terminal, the voltage gain v o /v b2 can be
found as
vo
RL
=
v b2
RL + re1
= 0.9975 V/V
v b1
Rin
456
=
=
= 0.82 V/V
v sig
Rin + Rsig
456 + 100
vo
(e)
= 0.82 × 0.9975 × 0.995 = 0.814 V/V
v sig
(d)
Exercise 7–1
Ex: 7.1 In the current source of Example 7.1
(Fig. 7.1) we have IO = 100 μA and we want to
reduce the change in output current,
IO , corresponding to a 1-V change in output
voltage, VO , to 1%
of IO .
That is, IO =
VO
1V
= 0.01IO ⇒
ro2
ro2
= 0.01 × 100 μA
ro2 =
1V
= 1 M
1 μA
ro2 =
VA × L
20 × L
⇒ 1 M =
IO
100 μA
⇒L=
100 V
= 5 μm
20 V/ μm
To keep VOV of the matched transistors the same
W
of the transistor should
as that in Example 7.1,
L
remain the same. Therefore,
10 μm
W
=
⇒ W = 50 μm
5 μm
1 μm
So the dimensions of the matched transistors Q1
and Q2 should be changed to
W = 50 μm and L = 5 μm
Ex: 7.2 For the circuit of Fig. 7.4 we have
I2 = IREF
(W/L)2
(W/L)3
, I3 = IREF
(W/L)1
(W/L)1
and I5 = I4
(W/L)5
(W/L)4
Since all channel lengths are equal, that is,
L1 = L2 = · · · = L5 = 1 μm
and
IREF = 10 μA, I2 = 60 μA, I3 = 20 μA, I4 =
I3 = 20 μA, and I5 = 80 μA,
⇒
W
L
=
2
120
= 15 ⇒ W2
200 × (0.2)2
= 15 × L2
W2 = 15 μm,
W2
W2
= 6 ⇒ W1 =
= 2.5 μm
W1
6
W3
= 2 ⇒ W3 = 2 × W1 = 5 μm
W1
To allow the voltage at the drain of Q5 to go up to
within 0.2 V of positive supply, we need
VOV 5 = 0.2 V:
1
W
V2
I5 = k p
2
L 5 OV 5
μA W
1
80 μA = 80 2
(0.2)2 ⇒
2
V
L 5
2 × 80
W
=
= 50 ⇒ W5 = 50 L5
L 5
80 × (0.2)2
W5 = 50 μm
50 μm
W5
= 4 ⇒ W4 =
= 12.5 μm
W4
4
Thus:
W1 = 2.5 μm, W2 = 15 μm, W3 = 5 μm
W4 = 12.5 μm, and W5 = 50 μm
Ex: 7.3 From Eq. (7.21) we have
⎞
⎛
⎟
⎜
VO − VBE
m
⎟
⎜
1+
IO = IREF ⎝
m+1⎠
VA2
1+
β
⎞
⎛
5 − 0.7
1
⎟
⎜
1+
IO = 1 mA⎝
1+1⎠
100
1+
100
= 1.02 mA
IO = 1.02 mA
Ro = ro2 =
VA
100 V
=
= 98 k 100 k
IO
1.02 mA
we have
I2 = IREF
I2
W2
W2
60
=
=6
⇒
=
W1
IREF
W1
10
I3 = IREF
W3
I3
20
W3
⇒
=
=
=2
W1
W1
IREF
10
I5 = I4
W5
I5
80
W5
⇒
=
=
=4
W4
W4
I4
20
To allow the voltage at the drain of Q2 to go down
to within 0.2 V of the negative supply voltage, we
need VOV 2 = 0.2 V:
1
1 W
W
2
VOV
=
V2
k
I2 = μn Cox
2
2
L 2
2 n L 2 OV 2
1
μA W
60 μA = 200 2
(0.2)2
2
V
L 2
Ex: 7.4
VCC
R
IREF
IO
VO
Q1
Q2
From Eq. (7.23), we have
IREF
VO − VBE
1+
IO =
1 + (2/β)
VA
Exercise 7–2
IO
where VBE = VT ln
IS 0.5 × 10−3
= 0.025 ln
= 0.673 V
10−15
2 − 0.673
IREF
1+
⇒
0.5 mA =
1 + (2/100)
50
IREF =
W
L
= 12.5
1
To obtain
Ais = 5
(W/L)2
(W/L)1
5 = Ais =
1.02
= 0.497 mA
1.026 mA
− VBE
VCC − VBE
⇒R=
R
IREF
IREF = 0.5 mA
VCC
⇒
⇒
W
L
= 5 × 12.5 = 62.5
2
Ro = ro2 =
5 − 0.673
= 8.71 k
0.497 mA
VOmin = VCEsat = 0.3 V
R=
VA2
VA2
=
ID2
5ID1
Thus,
For VO = 5 V, From Eq. (7.23) we have
VO − VBE
IREF
1+
IO =
1 + (2/β)
VA
0.497
5 − 0.673 V
1+
= 0.53 mA
IO =
1 + (2/100)
50
40 k =
VA2
5 × 0.1
⇒ VA2 = 20 V
But
L2
VA2 = VA2
20 = 20 × L2
⇒ L2 = 1 μm
Ex: 7.5 I1 = I2 = · · · = IN = IC |QREF
Selecting L1 = L2 , then
At the input node,
IREF = IC |QREF + IB |QREF + IB1 + · · · + IBN
L1 = L2 = 1 μm
= IC |QREF + (N + 1) IB |QREF
W1 = 12.5 μm
= IC |QREF +
⇒ IC |QREF =
W2 = 62.5 μm
(N + 1)
IC |QREF
β
IREF
N +1
1+
β
Ex: 7.7
Thus,
I1 = I2 = · · · = IN =
IREF
N +1
1+
β
For β = 100, to limit the error to 10%,
0.1 =
N +1
N +1
=
β
100
Q.E.D
Using Eq. (7.42):
W
·
gm = 2μn Cox
L
For ID = 10 μA, we have
gm =
2(387 μA/V2 )(10)(10 μA)
= 0.28 mA/V
⇒N =9
Using Eq. (7.46):
Ex: 7.6
A0 = VA
Rin 1
gm1
=
Now, Rin = 1 k, thus
5 V/μm 2(387 μA/V2 )(10)(0.36)2
√
10 μA
Since gm varies with
But
2(μn Cox )
1=
2μn Cox (W/L)
√
ID
A0 = 50 V/V
gm1 = 1 mA/V
gm1 =
2 × 0.4 ×
W
L
W
L
ID
ID1
1
× 0.1
1
1
ID and A0 with √ ,
ID
for
ID = 100 μA ⇒ gm = 0.28 mA/V
= 0.88 mA/V
100
10
1/2
Exercise 7–3
A0 = 50
1/2
10
100
IC1 = I = 100 μA = 0.1 mA
= 15.8 V/V
For ID = 1 mA, we have
1/2
1
gm = 0.28 mA/V
= 2.8 mA/V
0.010
0.010 1/2
A0 = 50
= 5 V/V
1
Ex: 7.8
VDD
Q3
IC1
0.1 mA
= 4 mA/V
=
VT
25 mV
Rin = rπ1 =
β1
100
=
= 25 k
gm 1
4 mA/V
VA
50 V
=
= 500 k
I
0.1 mA
|VA |
50 V
=
= 500 k
ro2 =
I
0.1 mA
A0 = gm1 ro1 = (4 mA/V) (500 k) = 2000 V/V
ro1 =
Av = −gm1 (ro1 ro2 ) = −(4 mA/V) ×
Q2
vO
IREF
gm1 =
(500 k 500 k) = −1000 V/V
Q1
vI
Ex: 7.10 Refer to Fig. 7.18(b),
vo = iRL
vsig = i(Rs + Rin )
Thus,
Since all transistors have the same
7.2 μm
W
=
,
L
0.36 μm
RL
vo
=
vsig
Rs + Rin
Q.E.D
we have
Ex: 7.11 Since gm ro 1, we use Eq. (7.54),
IREF = ID3 = ID2 = ID1 = 100 μA
W
gm1 = 2μn Cox
ID1
L 1
=
2 387 μA/V2
Rin 7.2
(100 μA)
0.36
RL
0
ro
(gm ro )ro
∞
Rin
1
gm
2
gm
ro
∞
= 1.24 mA/V
ro1 =
ro2 =
1
RL
+
gm
gm ro
VAn
5 V/μm (0.36 μm)
L1
=
= 18 k
ID1
0.1 mA
Ex: 7.12 For gm ro 1, we use Eq. (7.58),
|VAp
|L2
Rout ro + (gm ro )Rs
=
ID2
6 V/μm (0.36 μm)
= 21.6 k
0.1 mA
to obtain
Voltage gain is
Av = −gm1 (ro1 ro2 )
Rs
Av = − (1.24 mA/V) (18 k 21.6 k)
Rout
0
ro
(gm ro )ro
∞
ro
(gm ro )ro
(gm ro ) ro
∞
2
= −12.2 V/V
Ex: 7.13 Av o remains unchanged at gm ro . With a
load resistance RL connected,
Ex: 7.9
VCC
VBIAS
Q2
I
vi
Rin
Av = Av o
RL
RL + Ro
= (gm ro )
RL
RL + (1 + gm Rs )ro
vo
Q1
Ex: 7.14 Use Eq. (7.63)
Rin re
ro + RL
RL
ro +
β +1
Exercise 7–4
Ex: 7.19
to obtain
RL
0
ro
(β + 1)ro
∞
Rin
re
2 re
1
rπ
2
rπ
VDD 1.8 V
VG4 1.1 V
Q4
VG3 0.8 V
Ex: 7.15 Using Eq. (7.68),
Q3
Rout ro + (gm ro )(Re rπ )
vO
we obtain
VG2 1.0 V
Re
0
re
Rout
ro
2 ro
rπ
Q2
∞
ro
β
+ 1 ro (β + 1)ro
2
(β + 1)ro
Q1
VI 0.7 V
Ex: 7.16 Ro = [1 + gm (Re rπ )]ro
where
gm = 40 mA/V, rπ =
β
= 2.5 k,
gm
Re = 0.5 k, and ro =
If all transistors are matched and are obviously
operating at the same ID , then all |VOV | will be
equal and equal to that of Q1 , namely,
|VOV | = 0.7 − 0.5 = 0.2 V
VA
10
=
= 10 k
IC
1
Thus,
VD1 = VS2 = VG2 − Vtn − VOV
Ro = [1 + 40(0.5 2.5)] × 10
= 1.0 − 0.5 − 0.2 = 0.3 V
= 177 k
The lowest vDS2 can go is |VOV | = 0.2 V
Without emitter degeneration,
∴ v O min = VDS1 + VDS2 = 0.3 + 0.2 = 0.5 V
Ro = ro = 10 k
Similarly, VSG4 = VSG3 = 0.7 V
VD4 = VS3 = VG3 + |Vt | + |VOV |
Ex: 7.17 Since the CG transistor Q2 increases the
output resistance by a factor approximately equal
to gm2 ro2 ,
= 0.8 + 0.5 + 0.2 = 1.5 V
K gm2 ro2
vO max = VD4 − vSD3min = 1.5 − 0.2 = 1.3 V
0.55 μm
and
Ex: 7.18 If L is halved L =
2
|VA | = VA · L, we obtain
0.55 μm
= 1.375 V
|VA | = 5 V/μm
2
Ex: 7.20 Refer to Fig. 7.33.
Ro =
Since ID =
W
=
L
gm1 = gm2 = gm3 = gm4 =
= 2 mA/V
ro1 = ro2 = ro3 = ro4 =
|VA |
2 (1.375 V)2
|VA |
=
·
|VOV |/2 ID
(0.3 V) (100 μA)
= 126 k
1
μ Cox
2 p
W
L
|VOV |2 1 +
VSD
|VA |
2 (100 μA)
0.3 V
2
2
90 μA/V (0.3 V) 1 +
1.375 V
W
= 20.3
L
vSD3 can go as low as |VOV | , so
2 ID
2 × 0.2
=
|VOV |
0.2
|VA |
2
= 10 k
=
ID
0.2
Ron = (gm2 ro2 )ro1 = (2 × 10) × 10 = 200 k
Rop = (gm3 ro3 )ro4 = (2 × 10) × 10 = 200 k
Ro = Ron Rop = 200 200 = 100 k
Av = −gm1 Ro = −2 × 100 = −200 V/V
Ex: 7.21 gm1 = gm2 = gm
=
0.1 mA
ID
=
= 1 mA/V
VOV
(0.2/2) V
2
Exercise 7–5
ro1 = ro2 = ro
=
(a) ID1 = I and ID2 = I
VA
2V
= 20 k
=
ID
0.1 mA
so, gm ro = 1 mA/V (20 k) = 20
(a) For RL = 20 k,
Rin2 =
RL + ro2
20 k + 20 k
= 1.9 k
=
1 + gm2 ro2
1 + 20
∴ Av1 = −gm1 (ro1 Rin2 )
= −1 mA/V (20 1.9) = −1.74 V/V
or
If we use the approximation of Eq. (7.83),
Rin2 ≈
RL
1
20 k
1
+
=
+
= 2 k
gm2 ro2
gm2
20
1 mA/V
then
Av1 = −1 mA/V (20 k 2 k) = −1.82 V/V
Continuing, from Eq. (7.80),
Av = −gm1 [(gm2 ro2 ro1 ) RL ]
Av = −1 mA/V {[(20) (20 k)] 20 k}
= −19.0 V/V
Av 2 =
Av
−19.0
= 10.5 V/V
=
Av 1
−1.82
(b) The minimum voltage required across current
source I1 would be |VOV | = 0.2 V, since it is
made with a single transistor. If a 0.1-VPP signal
swing is to be allowed at the drain of Q1 , the
highest dc bias voltage would be
0.1 Vpp
1
= 1.8 − 0.2 − (0.1)
2
2
= 1.55 V
(c) V SG2 = |VOV | + Vtp = 0.2 + 0.5 = 0.7 V
RL
1
400 k
1
+
=
+
gm2 ro2
gm2
20
1 mA/V
= 21 k
Av 1 = −1 mA/V (20 k 21 k) = −10.2 V/V
Av = −1 mA/V [(20) (20 k)] 400 k
= −200 V/V
Av 2 =
Thus,
W
kp
W
k W
L
2 = 1 ⇒
= n
W
L 2
kp L 1
k n
L 1
k n W
= kn L 1
4
W
W
or
=4
L 2
L 1
VDD − |VOV | −
(b) Now, for RL = 400 k,
Rin2 Since VOV 1 = VOV 2 = 0.2 V, we have
W
1
μ Cox
V2
I
ID2
2 p
L 2 OV 2
=
= =1
W
1
ID1
I
μ Cox
V2
2 n
L 1 OV 1
Av
−200
= 19.6 V/V
=
Av 1
−10.2
VG2 can be set at 1.55 – 0.7 = 0.85 V.
(d) Since current source I2 is implemented with a
cascoded current source, the minimum voltage
required across it for proper operation is
2VOV = 2 (0.2 V) = 0.4 V.
(e) From parts (c) and (d), the allowable range of
signal swing at the output is from 0.4 V to 1.55 V
– VOV or 1.35 V.
so, 0.4 V ≤ vO ≤ 1.35 V.
Ex: 7.23 Referring to Fig. 7.38,
Ex: 7.22
Rop = (gm3 ro3 ) (ro4 rπ3 ) and
VDD 1.8 V
Ron = (gm2 ro2 ) (ro1 rπ2 )
I1 2I
vi
Q1
VG2
Q2
vo
I2 I
The maximum values of these resistances are
obtained when ro rπ and are given by
Ron = (gm2 ro2 ) rπ2
max
Rop = (gm3 ro3 ) rπ3
max
Since gm rπ = β,
Ron = β 2 ro2
max
Rop = β 3 ro3
max
Exercise 7–6
Since Av = −gm1 Ron Rop ,
|Av max | = gm1 β 2 ro2 β 3 ro3
3.6
1
2
× 387 ×
× VOV
2
0.36
⇒ VOV = 0.227 V
100 =
VGS = 0.227 + 0.5 = 0.727 V
Ex: 7.24 For the npn transistors,
gm1 = gm2
|IC |
0.2 mA
=
= 8 mA/V
=
|VT |
25 mV
VOmin = VG3 − Vt3
= VGS4 + VGS1 − Vt3
β
100
= 12.5 k
=
gm
8 mA/V
Thus,
rπ 1 = rπ 2 =
ro1 = ro2 =
|VA |
5V
= 25 k
=
|IC |
0.2 mA
= Vt + 2 VOV
VOmin = 2VGS − Vt
= 0.5 + 2 × 0.227 = 0.95 V
From Fig. 7.38,
Ron = (gm2 ro2 ) (ro1 rπ 2 )
= (8 mA/V) (25 k) (25 k 12.5 k)
Ron = 1.67 M
For the pnp transistors,
gm3 = gm4 =
rπ 3 = rπ 4
|IC |
0.2 mA
= 8 mA/V
=
VT
25 mV
β
50
= 6.25 k
=
=
gm
8 mA/V
ro3 = ro4 =
|VA |
4V
= 20 k
=
|IC |
0.2 mA
Rop = (gm3 ro3 ) (ro4 rπ 3 )
= (8 mA/V) (20 k) (20 k 6.25 k)
Rop = 762 k
Av = −gm1 Ron Rop
= − (8 mA/V) (1.67 M 762 k)
Av = −4186 V/V
gm =
2 ID
2 × 0.1
= 0.88 mA/V
=
VOV
0.227
ro =
VA
VL
5 × 0.36
= 18 k
= A =
ID
ID
0.1
Ro = (gm3 ro3 )ro2 = (0.88 × 18) × 18
= 285 k
Ex: 7.26 For the Wilson mirror from Eq. (7.94),
we have
IO
1
= 0.9998
2
IREF
1+ 2
β
Thus
|IO − IREF |
× 100 = 0.02%
IREF
whereas for the simple mirror from Eq. (7.18) we
have
1
IO
= 0.98
=
2
IREF
1+
β
|IO − IREF |
× 100 = 2%
IREF
Av max occurs when ro1 and ro4 are rπ .
Hence
Then
For the Wilson current mirror, we have
Ron = (gm2 ro2 ) rπ 2 = β 2 ro2
Ron = 100 (25 k) = 2.5 M
Rop = (gm3 ro3 ) rπ 3 = β 3 ro3
100 × 100 k
βro
=
= 5 M
2
2
and for the simple mirror, Ro = ro
= 100 k.
Ro =
Rop = 50 (20 k) = 1 M
Finally,
Av max = −(8 mA/V) (2.5 M 1.0 M)
Av max = −5714 V/V
Ex: 7.27 For the two current sources designed in
Example 7.6, we have
gm =
IC
10 μA
mA
=
= 0.4
VT
25 mV
V
VA
100 V
=
= 10 M,
IC
10 μA
β
rn =
= 250 k
gm
ro =
Ex: 7.25 Refer to the circuit in Fig. 7.39. All
transistors are operating at ID = IREF = 100 μA
and equal VOV , found from
1
W
2
VOV
ID = μn Cox
2
L
For the current source in Fig. 7.43(b), we have
Ro = ro2 = ro = 10 M
Exercise 7–7
For the current source in Fig. 7.43, from
Eq. (7.102), we have
Rout [1 + gm (RE rn )] ro
From Example 7.6, RE = R3 = 11.5 k;
therefore,
mA
Rout 1 + 0.4
(11.5 k 250 k) 10 M
V
∴ Rout = 54 M
Gv ≡
vo
= −145.5 V/V
vsig
These results apply for both Rsig = 4 k and
Rsig = 400 k. If in the CC–CE amplifier of
Example 7.7, Rsig = 400 k, Gv becomes
Gv =
255
× 0.99 × −160
255 + 400
= −61.7 V/V
Ex: 7.30
Ex: 7.28
2ID
2 × 0.2
= 2 mA/V
gm =
=
VOV
0.2
gmb = χ gm = 0.2 × 2 = 0.4 mA/V
ro1 = ro3 =
VA
5
= 25 k
=
ID
0.2
RL = ro1 ro3 Rsig
Q1
vsig Ex: 7.29
Q2
vo
1
= 25 25 2.5 k
gmb
= 2.083 k
RL
2.083
vo
= 0.81 V/V
=
=
1
1
vi
RL +
2.083 +
gm
2
re1
Rin
RE
(b2 1) (re2 RE)
Rout
From the figure we can write
Rin = (β1 + 1)[re1 + (β2 + 1)(re2 + RE )]
re1 + Rsig /(β1 + 1)
Rout = RE re2 +
β2 + 1
vo
=
vsig
RE
re1 + Rsig /(β1 + 1)
RE + re2 +
β2 + 1
For IE2 = 5 mA, β1 = β2 = 100, RE = 1 k, and
Rsig = 100 k, we obtain
25 mV
=5
5 mA
5
5
=
=
0.05 mA
β2 + 1
101
re2 =
gm1 = 2k n ID
√
= 2×8×1
= 4 mA/V
1
= 0.25 k
gm1
gm2 = 40 mA/V
100
= 2.5 k
40
Rin = ∞
vsig
vsig
vi
=
=
ib =
1
1
0.25 + 2.5
+ rπ 2
+ rπ 2
gm1
gm1
vsig
=
2.75
100 × 4
vsig
vo = −βib RL = −
2.75
rπ 2 =
IE1
25 mV
= 500 0.05 mA
Rin = 101 × (0.5 + 101 × 1.005) = 10.3 M
0.5 + (100/101)
20 Rout = 1 0.005 +
101
re1 =
vo
=
vsig
1
0.5 + (100/101)
1 + 0.005 +
101
= 0.98 V/V
Ex: 7.31 Refer to Fig. 7.49.
re = 25 Rin = (β1 + 1)(2 re ) = 101 × 0.05 = 5.05 k
Exercise 7–8
α2 RL
5
vo
=
= 100 V/V
vi
2 re
0.05
vi
vo
vo
=
×
vsig
vsig
vi
Thus,
Rin
vo
=
×
Rin + Rsig
vi
1
vo
= gm RL
vi
2
=
and
vo = iRL
where
5.05
× 100 = 50 V/V
5.05 + 5
gm =
2ID
2I
=
VOV
VOV
Thus,
Ex: 7.32
2I
1
IRL
vo
= ×
RL =
vi
2 VOV
VOV
(b) I = 0.1 mA and RL = 20 k, to obtain a gain
of 10 V/V,
RL
i
vo
vi
Q1
1
gm1
(a) From the figure we see that
i=
1
vi
= gm v i
2/gm
2
10 =
0.1 × 20
VOV
⇒ VOV = 0.2 V
Q2
i
Q.E.D
1
gm2
The required W/L can be obtained from
W
1
2
VOV
ID = k n
2
L
W
1
0.1 = × 0.2 ×
× 0.04
2
L
⇒
W
= 25
L
Chapter 7–1
7.1 Referring to Fig. 7.1, VDD = 1.3 V,
IO = IREF = 100 μA, L = 0.5 μm, W = 5 μm,
VA = 5 V/μm, Vt = 0.4 V, k n = 500 μA/V2
1
W
2
IO = ID = k n
VOV
2
L
2I
D
VOV = W
kn
L
2 (100 μA)
= 0.2 V
=
5
500 μA/V2
0.5
VDS = VGS = Vt + VOV = 0.4 + 0.2 = 0.6 V
1.8 − 0.6
VDD − VGS
=
= 12 k
R=
IREF
0.1 mA
7.3
VDD
VDD
Q1
Q2
VO
IREF
R
IO
Set |VOV | = VDD − VOmax
= 1.3 − 1.1 = 0.2 V
The lowest VO will be
VG = VDD − Vtp − |VOV |
VDS2 = VOV = 0.2 V
= 1.3 − 0.4 − 0.2 = 0.7 V
RO = ro =
ID ≈
VA L
ID
=
5 V/ μm × 0.5 μm
= 25 k
100 μA
VO
0.5 V
=
= 20 μA
ro
25 K
7.2 Refer to Fig. 7.1.
IO
= 10%
IO
IO = 0.1 × 150 = 15 μA
VO = 1.8 − 0.3 = 1.5 V
ro =
VO
1.5 V
= 100 k
=
IO
15 μA
thus
2ID
2 × 80 μA
W
=
=
= 50
L
80 μA/V2 × 0.22
μp Cox |VOV |2
7.4 Referring to Fig. 7.2, if W2 = 5 W1 and we
let L1 = L2 , then we obtain
IO = ID2 = IREF
(W/L)2
= 20 μA × 5 = 100 μA
(W/L)1
VOmin = VOV = 0.2 V
But
ro =
0.7 V
VG
=
= 8.75 k
ID1
80 μA
1
W
|VOV |2
ID = μp Cox
2
L
R=
VA L
VA
=
IO
IO
10 × L
⇒ L = 1.5 μm
0.15
⇒ VA = 15 V
100 =
From Eq. (7.8):
IO =
VO − VGS
(W/L)2
· IREF 1 +
VA2
(W/L)1
VGS = Vt + VOV = 0.5 V + 0.2 V = 0.7 V
VOV = VDS2min = 0.3 V
Thus, ID equal 5IREF will be obtained at
VGS = Vt + VOV = 0.5 + 0.3 = 0.8 V
1
W
VDS
2
1+
VOV
ID = k n
2
L
VA
W
0.8
1
× 0.09 1 +
150 = × 400 ×
2
L
15
VO = VGS = 0.7 V
W
= 7.91
L
W = 7.91 × 1.5 = 11.9 μm
⇒
1.8 − 0.8
VDD − VGS
=
= 6.7 k
R=
IREF
0.15
For VO = VGS + 1 = 1.7 V
1.7 − 0.7
= 105 μA
IO = 100 1 +
20
The corresponding increase in IO , IO is, thus,
5 μA.
7.5 Referring to the figure on the next page,
suppose that Q1 has W = 10 μm, Q2 has
W = 20 μm, and Q3 has W = 40 μm.
Chapter 7–2
This figure belongs to Problem 7.5.
To find VSG , we use the following for the
diode-connected transistor(s):
1
W
ID = μp Cox
(VSG − |Vtp |)2
2
L
VDD
Q1
Q2
I1
Q3
I2
I3
IREF
and substitute ID = IREF = 100 μA. Thus
1
W
100 = × 100 ×
(VSG − 0.6)2
2
1 μm
⇒ VSG = 0.6 +
2
W (μm)
For the six cases above we obtain
(1) With Q1 diode connected,
20
(W/L)2
= 200 μA
= 100 μA
I2 = IREF
10
(W/L)1
40
= 400 μA
I3 = 100 μA
10
(2) With Q2 diode connected, and W = 20 μm,
10
= 50 μA
I1 = 100 μA
20
40
= 200 μA
I3 = 100 μA
20
(3) If Q3 with W = 40 μm is diode connected,
10
= 25 μA
I1 = 100 μA
40
20
= 50 μA
I2 = 100 μA
40
So, with only one transistor diode connected, we
can get 25 μA, 50 μA, 200 μA, and 400 μA, or
four different currents.
(1) W = W1 = 10 μm ⇒ VSG = 1.05 V
(2) W = W2 = 20 μm ⇒ VSG = 0.92 V
(3) W = W3 = 40 μm ⇒ VSG = 0.82 V
(4) W = W1 + W2 = 30 μm ⇒ VSG = 0.86 V
(5) W = W2 + W3 = 60 μm ⇒ VSG = 0.78 V
(6) W = W1 + W3 = 50 μm ⇒ VSG = 0.80 V
7.6 Refer to the circuit of Fig. P7.6. For Q2 to
operate properly (i.e., in the saturation mode) for
drain voltages as high as +0.8 V, and provided its
width is the minimum possible, we use
|VOV | = 0.2 V
Note that all three transistors Q1 , Q2 , and Q3 will
be operated at this value of overdrive voltage.
For Q1 ,
Weff = 20 + 10 = 30 μm, so that
40
= 133 μA
I3 = 100 μA
30
ID1 = IREF = 20 μA
1
W
ID1 = μp Cox
|VOV |2
2
L 1
W
1
20 = × 100 ×
× 0.04
2
L 1
W
= 10
⇒
L 1
(5) If Q2 and Q3 are diode connected, then
For L = 0.5 μm,
Weff = 20 + 40 = 60 μm, so that
10
= 16.7 μA
I1 = 100 μA
60
W1 = 5 μm
Now, if two transistors are diode connected, the
effective width is the sum of the two widths.
(4) If Q1 and Q2 are diode connected, then
(6) If Q1 and Q3 are diode connected,
Weff = 10 + 40 = 50 μm, so that
20
= 40 μA
I2 = 100 μA
50
So three different currents are obtained with
double-diode connects.
Now, for
I2 = 100 μA = 5IREF , we have
(W/L)2
=5
(W/L)1
W
⇒
= 5 × 10 = 50
L 2
W2 = 50 × 0.5 = 25 μm
Chapter 7–3
7.7 Referring to Fig. P7.5, we obtain
For
I3 = 40 μA = 2IREF , we obtain
(W/L)3
=2
(W/L)1
W
⇒
= 20
L 3
W3 = 10 μm
We next consider Q4 and Q5 . For Q5 to operate in
saturation with the drain voltage as low as
−0.8 V, and for it to have the minimum possible
W/L, we operate Q5 at
VGS1 = VGS2 so that
ID2 = IREF
ID2
(W/L)2
=
and
ID1
(W/L)1
(W/L)2
(W/L)1
ID3 = ID2
VGS3 = VGS4 , thus
IO = ID4 = IREF
ID4
(W/L)4
=
ID3
(W/L)3
(W/L)2 (W/L)4
.
(W/L)1 (W/L)3
VOV = 0.2 V
This is the same overdrive voltage at which Q4
will be operating. Thus, we can write for Q4 ,
I4 = I3 = 40 μA
and using
1
W
μn Cox
V2
2
L 4 OV
1
W
40 = × 400 ×
× 0.22
2
L 4
W
⇒
=5
L 4
ID4 =
W4 = 2.5 μm
Finally, since
I5 = 80 μA = 2 I4 ,
W
W
=2
L 5
L 4
W
⇒
= 10
L 5
W5 = 5 μm
To find the value of R, we use
|VSG1 | = |Vtp | + |VOV 1 |
= 0.5 + 0.2 = 0.7 V
R=
1 − |VSG1 |
0.3 V
=
IREF
0.02 mA
= 15 k
7.8 (a) If IS = 10−17 A and we ignore base
currents, then
IREF = IS eVBE /VT so that
IREF
VBE = VT ln
10−17
For IREF = 10 μA,
−5 10
VBE = 0.025 ln
= 0.691 V
10−17
For IREF = 10 mA,
−2 10
= 0.863 V
VBE = 0.025 ln
10−17
So for the range of
10 μA ≤ IREF ≤ 10 mA,
0.691 V ≤ VBE ≤ 0.863 V
(b) Accounting for finite β,
IO = IREF ·
For IREF = 10 μA,
IO =
|VAp
|×L
|VA2 |
=
I2
I2
10 μA
= 9.62 μA
2
1+
50
For IREF = 0.1 mA,
IO =
The output resistance of the current source Q2 is
ro2 =
1
1 + 2/β
0.1 mA
= 0.098 mA
2
1+
100
For IREF = 1 mA,
1 mA
= 0.98 mA
2
1+
100
5 × 0.5
= 25 k
=
0.1 mA
IO =
The output resistance of the current sink Q5 is
For IREF = 10 mA,
ro5
VA5
V × L
=
= An
I5
I5
=
5 × 0.5
= 31.25 k
80
IO =
10 mA
= 9.62 mA
2
1+
50
Chapter 7–4
7.11
7.9
VDD
VDD
Q1
Q2
IO
IREF
IO = mIC1
A node equation at the collector of Q1 yields
IREF
For identical transistors, the transfer ratio is
1
IO
=
=
IREF
1 + 2/β
IO + IC1
= IC1 +
β
1
1+
2
50
= 0.96
Substituting IC1 = IO /m results in
m
m+1
1+
β
IO
=
IREF
Q.E.D.
For β = 80 and the error in the current transfer
ratio to be limited to 10%, that is,
m
≥ 0.9m
m+1
1+
β
1+
m+1
β
≤
1
0.9
1
m+1
≤
−1
β
0.9
m≤β
1
−1 −1
0.9
1
− 1 − 1 = 7.88
m ≤ 80
0.9
Thus, the largest current transfer ratio possible
is 7.88.
7.10 Nominally, IO = IREF = 1 mA
ro2 =
VA2
90
=
= 90 k
IO
1
ro2 =
VO
10 − 1
⇒
= 90 ⇒ IO = 0.1 mA
IO
IO
0.1
IO
=
= 10% change
IO
1
7.12 Equation (7.21) gives the current transfer
ratio of an npn mirror with a nominal ratio of m:
VO − VBE
m
IO = IREF
1+
m+1
VA2
1+
β
This equation can be adapted for the pnp mirror
of Fig. P7.12 by substituting m = 1, replacing VO
with the voltage across Q3 , namely (3 − VO ),
replacing VBE with VEB , and VA2 with |VA |:
IO = IREF
1 + [(3 − VO − VEB )/|VA |]
1 + (2/β)
(1)
Now, substituting IO = 1 mA, VO = 1 V, β = 50,
|VA | = 50 V, and
−3 IO
10
= 0.691 V
VEB = VT ln = 0.025 ln
IS
10−15
results in
1 × (1 + 0.04)
= 1.013 mA
3 − 1 − 0.691
1+
50
3 − 0.691
VCC − VEB
= 2.28 k
=
R=
IREF
1.013
IREF =
Maximum allowed voltage VO = 3 − 0.3 = 2.7
V. For VO = 2.7 V, Eq. (1) yields
3 − 2.7 − 0.691
50
= 0.966 mA
IO = 1.013
1.04
For VO = −5 V, Eq. (1) yields
1+
3 − (−5) − 0.691
50
= 1.116 mA
IO = 1.013
1.04
Thus, the change in IO is 0.15 mA.
1+
Chapter 7–5
This figure belongs to Problem 7.13.
7.13 The solution is given in the circuit diagram.
Note that the starting point is calculating the
current I in the Q1 –R1 –Q2 branch. See figure
above.
Even without knowing exact circuitry, we can
find the total power dissipation as approximately
PT = PCC + PEE
PT = 5 V (0.1 + 0.2 + 0.4 + 0.8) mA
7.14 There are various ways this design could be
achieved, but the most straightforward is the one
shown:
4
2
Q1 1
8
+5 V (0.1 + 0.5 + 1 + 2) mA
PT = 7.5 mW + 18 mW = 25.5 mW
7.15 Refer to the circuit in Fig. P7.15.
V2 = 2.7 − VEB = 2.7 − 0.7 = +2 V
R
0.2 mA
0.4 mA
0.5 mA
Q2 1
5
1 mA
10
0.8 mA
2 mA
20
V3 = 0 + VEB = +0.7 V
Thus, Q3 and Q4 are operating in the active mode,
and each is carrying a collector current of I /2.
The same current is flowing in Q2 and Q1 ; thus
I
V1 = −2.7 + R
2
With this scheme,
But
5 − 0.7 − 0.7 − (−5)
= 86 k
0.1 mA
and each transistor has EBJ areas proportional to
the current required. Multiple, parallel transistors
are acceptable.
Thus,
Note: This large value of R is not desirable in
integrated form; other designs may be move
suitable.
⇒ IR = 4 V
R=
V1 = −VBE1 = −0.7
1
−0.7 = −2.7 + IR
2
Chapter 7–6
The current I splits equally between Q5 and Q6 ;
thus
V4 = −2.7 +
(b)
I
R = −2.7 + 2 = −0.7 V
2
I
R
= −2.7 + 1 = −1.7 V
V5 = −2.7 +
2
2
Thus, Q5 and Q6 are operating in the active mode
as we have implicitly assumed.
Note that the values of V1 , V2 , V3 , V4 , and V5 do
not depend on the value of R. Only I depends on
the value of R:
(a) R = 10 k ⇒ I =
4
= 0.4 mA
10
(b) R = 100 k ⇒ I =
4
= 0.04 mA
100
Figure 2
Figure 2 shows the special case of V = 0 V. As
before, the voltage at X, VX , will be equal to V .
Thus
VX = 0
7.16 (a)
That is, a virtual ground appears at X, and thus
the current I that flows into X can be found from
I=
5 − VX
5−0
=
= 0.5 mA
10 k
10
This is the current that will be mirrored to the
output, resulting in IZ = 0.5 mA.
(W/L)2
(W/L)1
7.17 Ais = 4 =
Since L1 = L2 , then
W2
=4
W1
Figure 1
1
gm1
Rin = ro1
1
gm1
For
Figure 1 shows the current conveyor circuit with
Y connected to a voltage V , X fed with a current
source I , and Z connected to a voltage VZ that
keeps Q5 operating in the active mode. Assuming
that all transistors are operating in the active
mode and that β 1, so that we can neglect all
base currents, we see that the current I through Q1
will flow through the two-output mirror Q3 , Q4 ,
and Q5 . The current I in Q5 will be drawn from
Q2 , which forms a mirror with Q1 . Thus
VEB2 = VEB1 and the voltage that appears at X will
be equal to V . The current in Q5 will be equal to
I , thus terminal Z sinks a constant current I .
Rin = 500 ⇒ gm1 = 2 mA/V
gm1 =
2μn Cox
W
L
ID1
1
Thus,
2=
⇒
2 × 0.4 ×
W
L
= 25
1
W
L
× 0.2
1
Chapter 7–7
RO = ro2 =
VA
VL
= A
ID2
ID2
Thus, the small-signal voltage gain will be
vo
= gm1 RL (W3 /W2 )
vi
Thus,
20 =
20 L
4 × 0.2
7.19 Replacing Q1 and Q2 with their small-signal
hybrid-π models results in the equivalent circuit
shown in the figure below. Observe that the
controlled source gm1 vπ1 appears across its
controlling voltage vπ1 ; thus the controlled source
can be replaced with a resistance (1/gm1 ). The
input resistance Rin can now be obtained by
inspection as
⇒ L = 0.8 μm
W1 = 25 × 0.8 = 20 μm
W2 = 4W1 = 80 μm
7.18 Refer to Fig. P7.18. Consider first the
diode-connected transistor Q2 . From the figure we
Rin = ro1
1
gm1
rπ1 rπ2
Since ro1 rπ1 ,
g2
d2
g2, d2
Rin
vgs2
1
gm2
gm2vgs2
S3
io = gm2 vπ2
Since vπ2 = vπ1 = ii Rin , then the short-circuit
current gain Ais is given by
see that from a small-signal point of view it is
equivalent to a resistance 1/gm2 . Thus the voltage
gain of Q1 will be
Ais =
vd 1
1
gm1
= −gm1 ×
=−
vi
gm2
gm2
io
= gm2 Rin
ii
= gm2
The signal current in the drain of Q1 , gm1 vi , will
be mirror in the drain of Q3 ;
1
gm1
(2)
rπ1 rπ2
For situations where β1 and β2 are large, we can
neglect rπ1 and rπ2 in Eqs. (1) and (2) to obtain
(W/L)3
W3
= gm1 vi
(W/L)2
W2
which flows through RL and produces the output
voltage vo ,
vo = id 3 RL = gm1 vi
(1)
rπ1 rπ2
The short-circuit output current io is given by
S2
id 3 = gm1 vi
1
gm1
Rin
1/gm1
Ais
gm1 /gm2
W3
RL
W2
This figure belongs to Problem 7.19.
C1
B1, B2
ii
vp1
ro1
Rin
gm1vp1 C2
rp1
io
rp2 vp2
ro2
gm2vp2
Ro
Chapter 7–8
7.21 Refer to Fig. 7.11.
7.20 (a)
IREF = 0.1 mA
IC1
g
vgs
d
1 mA
VBE1 = 0.7 − 0.025 ln
0.1 mA
g,d
s
= 0.642 V
1
gm
gmvgs
s
IC1
β
0.1
= 0.002 mA
100
1 mA
= 0.7 − 0.025 ln
0.002 mA
=2×
Figure 1
VBE3
Replacing the MOSFET with its hybrid-π model
but neglecting ro results in the equivalent circuit
in Fig. 1. Observing that the controlled-source
gm vgs appears across its control voltage vgs , we
can replace it by a resistance 1/gm , as indicated.
Thus the small-signal resistance of the
diode-connected MOS transistor is 1/gm . For the
given values,
W
ID
gm = 2μn Cox
L
√
= 2 × 0.2 × 10 × 0.1 = 0.632 mA/V
= 0.545 V
Vx = VBE3 + VBE1 = 1.187 V
If IREF is increased to 1 mA,
VBE1 = 0.7
IC3
0.02 mA
1
= 0.6 V
VBE3 = 0.7 − 0.025 ln
0.02
Vx = 1.3 V
Thus,
1
= 1.6 k
gm
Vx = 1.3 − 1.187 = 0.113 V
(b) Replacing the BJT with its hybrid-π model
results in the equivalent circuit in Fig. 2.
Observing that the controlled-source gm vπ
appears across its control voltage vπ , we can
replace it by a resistance 1/gm , as indicated. Next
the two parallel resistances 1/gm and rπ can be
combined as
1
× rπ
rπ
rπ
gm
= re
=
=
1
1 + gm rπ
β +1
+ rπ
gm
When VO = Vx , the Early effect on Q1 and Q2
will be the same, and
IO = IREF /(1 + 2/β 2 )
Thus, IO will be
100
=
1 + (2/1002 )
99.98 μA, for an error of −0.02 μA or −0.02%.
IREF = 100 μA ⇒ IO =
1
=
1 + (2/1002 )
0.9998 μA, for an error of −0.0002 mA or
−0.02%. For proper current-source operation, the
minimum required voltage at the output is the
value needed to keep Q3 in the active region,
which is approximately 0.3 V.
IREF = 1 mA ⇒ IO =
Thus, the diode-connected BJT has a small-signal
resistance re . For the given data,
re =
IB1 + IB2 = 2 IB1 = 2 ×
IC3
VT
25 mV
= 250 =
IE
0.1 mA
This figure belongs to Problem 7.20, part (b).
Figure 2
Chapter 7–9
7.22 Refer to Fig. 7.11 and observe that
IC1 IREF and IC2 = IC1 ; thus each of Q1 and Q2
is operating at a collector bias current
approximately equal to IREF . Transistor Q3 is
operating at an emitter bias current
IE3 = IB1 + IB2 = 2IB = 2IC /β =
2(1 − α)
IC
α
Now, using ix = αie from Eq. (1), we have
Thus,
vx
2VT
=
ix
IREF
Rin ≡
2(1 − α)
IREF
α
Replacing each of the three transistors with its T
model and applying an input test voltage vx to
determine Rin , we obtain the equivalent circuit
shown.
=
2VT
IREF
vx = ix ×
Q.E.D.
For IREF = 100 μA = 0.1 mA,
2 × 25 mV
= 500 0.1 mA
Rin =
7.23
IREF
C3
IB3
aie3
ix
B3
x
B1 i
b1
re1
ie1
ib2 B2
IO2
Q21
IO
aie2
E3
IO1
b
IO3
IOn
IE3
Q1
C2
re3
aie1
vx IC1
Out
ie3
C1
Q3
X
Q22
Q23
Q2n
nIO
b
ve
re2
ie2
IO1 = IO2 = IO3 · · · = IOn = IO = IC1
The emitter of Q3 supplies the base currents for
all transistor, so
IE3 =
In this equivalent circuit,
re1 = re2 = re =
re3 =
VT
αVT
αVT
=
=
IE
IC
IREF
IREF = IB3 + IO =
VT
αVT
=
IE3
2(1 − α)IREF
IO
=
IREF
ie1 = ie2 = ie
ix = αie1 + (1 − α)ie3
7.24 For I = 10 μA:
= ie [α + 2(1 − α)2 ]
α. Thus,
(1)
vx = ie3 re3 + ie1 re1
= 2(1 − α)ie
vx = αie
αVT
αVT
+ ie
2(1 − α)IREF
IREF
VT
VT
+
IREF
IREF
1
n+1
1+
β2
⇒ nmax = 0.002 × 1502 − 1 = 44
= αie + (1 − α) × 2(1 − α)ie
αie
1
(n + 1)
1+
β (β + 1)
n+1
≤ 0.002
β2
From the figure we obtain
ix
(n + 1) IO
+ IO
β (β + 1)
For the deviation from unity to be kept ≤ 0.2%
ie3 = ib1 + ib2 = 2(1 − α)ie
But 2(1 − α)2
(n + 1) IO
β
gm =
I
10 μA
=
= 0.4 mA/V
VT
25 mV
rπ =
β
100
=
= 250 k
gm
0.4 mA/V
ro =
10 V
VA
=
= 1 M
I
10 μA
A0 = gm ro =
VA
10 V
= 400 V/V
=
VI
0.025 V
Chapter 7–10
For I = 100 μA:
VA
100 V
= 200 k
=
IC
0.5 mA
ro =
100 μA
= 4 mA/V
25 mV
100
= 25 k
rπ =
4 mA/V
gm =
Rin = rπ =
β
100
=
= 5 k
gm
20 mA/V
Av o = −A0 = −gm ro = −20×200 = −4000 V/V
10 V
= 100 k
ro =
100 μA
Ro = ro = 200 k
A0 = 4 mA/V × 100 k = 400 V/V
To raise Rin by a factor of 5 by changing I , the
value of I must be lowered by the same factor to
I = 0.1 mA.
VCC
Now, gm is reduced by a factor of 5 and ro is
increased by a factor of 5, keeping Av o unchanged
at −4000 V/V. However, Ro will be increased to
I
Ro = 5 × 200 k = 1 M
vo
If the amplifier is fed with a signal source having
Rsig = 5 k and a 100-k load resistance is
connected to the output, the equivalent circuit
shown below results.
rπ
vo
=
× −gm (ro RL )
vsig
rπ + Rsig
Q1
vi
For I = 1 mA:
1 mA
= 40 mA/V
gm =
25 mV
100
= 2.5 k
rπ =
40 mA/V
=−
10 V
= 10 k
1 mA
A0 = 40 mA/V × 10 k = 400 V/V
A0 =
2VA
2VA L
2 × 10 × 0.5
= 50 V/V
=
=
VOV
VOV
0.2
gm =
2ID
VOV
= −303 V/V
7.26
ro =
I
gm
rπ
10 μA 0.4 mA/V 250 k
ro
A0
1 M
400 V/V
2=
40 mA/V 2.5 k
10 k 400 V/V
0.2 =
⇒
7.25 Refer to Fig. 7.13(b).
gm =
2ID
⇒ ID = 0.2 mA
0.2
ID =
100 μA 4.0 mA/V 25 k 100 k 400 V/V
1 mA
25
× 4 (1000 k 100 k)
25 + 5
IC
I
0.5 mA
=
= 20 mA/V
=
VT
VT
0.025 V
1 W 2
k
V
2 n L OV
1
W
× 0.4 ×
× 0.22
2
L
W
= 25
L
W = 12.5 μm
This figure belongs to Problem 7.25.
Rsig 5 k
vsig rp
25 k
vp
gmvp
gm 4 mA/V
ro
1 M
vo
RL
100 k Chapter 7–11
7.27 A0 =
2VA
2VA L
=
VOV
VOV
VA = 5 × 0.3 = 1.5 V
A0 = gm ro = 1 × 15 = 15 V/V
1
W 2
μn Cox VOV
2
L
W
1
× 0.22
100 = × 387 ×
2
L
W
⇒
= 13 ⇒ W = 3.9 μm
L
ID =
2ID
2I
=
gm =
VOV
VOV
2I
0.2
⇒ I = 0.2 mA
1
W
2
VOV
ID = μn Cox
2
L
2=
0.2 =
VA
1.5 V
= 15 k
=
ID
0.1 mA
ro =
2×5×L
0.2
⇒ L = 0.4 μm
20 =
7.31 gm =
W
1
× 0.4 ×
× 0.04
2
L
2ID
2 × 0.1
= 0.4 mA/V
=
VOV
0.5
W
= 25
⇒
L
From Table J.1 (Appendix J), we find that for the
0.5-μm process |VA | = 20 V/μm. Thus for our
1-μ-m long transistor, VA = 20 V.
7.28
ro =
VA
20 V
=
= 200 k
ID
0.1 mA
A0 = gm ro = 0.4 × 200 = 80 V/V
From Table J.1:
μn Cox = 190 μA/V2
Now,
ID =
1
W
2
μn Cox
VOV
2
L
100 =
The highest instantaneous voltage allowed at the
drain is that which results in a voltage equal to
(VOV ) across the transistor. Thus
vOmax = 1.8 − 0.2 = +1.6 V
IC
0.1 mA
=
= 4 mA/V
VT
0.025 V
ro =
For the NMOS transistor,
Rin = rπ =
2ID
4=
0.25
⇒ ID = 0.5 mA
2ID
2 × 0.1
= 1 mA/V
=
VOV
0.2
From Table K.1 (Appendix K), for the 0.18-μm
process we have
|VA |
= 5 V/μm, μn Cox = 387 μA/V
VA
100 V
=
IC
IC
A0 = gm ro =
2ID
gm =
VOV
7.30 gm =
W
= 4.21
L
⇒ W = 4.21 μm
⇒
7.32 For the BJT cell:
IC
IC
=
gm =
VT
0.025 V
7.29 For the npn transistor,
gm =
1
W
× 190 ×
× 0.25
2
L
2
Thus, for our NMOS transistor whose
L = 0.3 μm,
VA
100 V
= 4000 V/V
=
VT
0.025 V
β
100
=
gm
gm
For the MOSFET cell:
W
ID =
gm = 2μn Cox
L
=
ro =
2 × 0.2 × 40 × ID
16ID = 4 ID mA/V (ID in mA)
VA
10 V
=
ID
ID
40
A0 = gm ro = √ V/V (ID in mA)
ID
Rin = ∞
Chapter 7–12
BJT Cell
Bias
current
MOSFET Cell
IC = 0.1 IC = 1 ID = 0.1 ID = 1
mA
mA
mA
mA
gm = 80 × 3.16 = 253 μA/V = 0.253 mA/V
and ro decreases by a factor of 10 to
gm (mA/V)
4
40
1.26
4
0.18 M
= 18 k
10
Thus, A0 becomes
ro (k)
1000
100
100
10
A0 = 0.253 × 18 = 4.55 V/V
A0 (V/V)
4000
4000
126
40
Rin (k)
25
2.5
∞
∞
(c) If the device is redesigned with a new value
of W so that it operates at
ro =
VOV = 0.25 V for ID = 100 μA,
7.33 Using Eq. (7.46),
A0 =
18 =
2ID
0.2 mA
= 0.8 mA/V
=
VOV
0.25 V
ro =
VA L
5 × 0.36
=
= 18 k
ID
0.1
VA 2(μn Cox ) (WL)
ID
√
5 2 × 0.4 × 8 × 0.54 × 0.54
ID
⇒ ID = 0.144 mA
7.34
2VA
2VA L
2 × 6 × 0.5
=
=
= 40 V/V
VOV
VOV
0.15
1
W
2
VOV
ID = k n
2
L
A0 =
100 =
1
W
× 400 ×
× 0.152
2
L
W
= 22.2
L
Thus,
⇒
W = 22.2 × 0.5 = 11.1 μm
gm =
2ID
2 × 0.1
=
= 1.33 mA/V
VOV
0.15
ro =
VA L
6 × 0.5
=
= 30 k
ID
0.1
VA L
VA
=
ID
ID
From Appendix J, Table J.1,
(d) If the redesigned device in (c) is operated
√ at
10 μA, VOV decreases by a factor equal to 10 to
0.08
√ V, gm decreases by a factor of
10 to 0.253 mA/V, ro increases by a factor of
10 to 180 k, and A0 becomes
0.253 × 180 = 45.5 V/V
which is an increase by a factor of
√
10.
(e) The lowest value of A0 is obtained with the
first design when operated at ID = 100 μA. The
resulting A0 = 4.55 V/V. The highest value of A0
is obtained with the second design when operated
at ID = 10 μA. The resulting A0 = 45.5 V/V. If in
any design W/L is held constant while L is
increased by a factor of 10, gm remains
unchanged but ro increases by a factor of 10,
resulting in A0 increasing by a factor of 10.
100 =
2ID
2 × 10
= 80 μA/V
=
(a) gm =
VOV
0.25
VA
A0 = gm ro = 0.8 × 18 = 14.4 V/V
7.36 A0 = |Av o | = 100
7.35
L = 0.36 μm, VOV = 0.25 V, ID = 10 μA
ro =
gm =
= 5 V/μm,
5 × 0.36
= 0.18 M
10
A0 = gm ro = 80 × 0.18 = 14.4 V/V
ro =
2VA
2VA
=
VOV
0.2
⇒ VA = 10 V
Since VA = 20 V/ μm, we have
L=
10
VA
= 0.5 μm
=
VA
20
1 W 2
k
V
2 n L OV
W
1
× 0.22
50 = × 200 ×
2
L
W
⇒
= 12.5
L
ID =
(b) If ID is increased to 100 μA (i.e.,
√ by a factor
of 10), VOV increases by a factor of 10 = 3.16 to
7.37 Refer to Fig. 7.15(a).
VOV = 0.25 × 3.16 = 0.79 V
VSG2 = |Vtp | + |VOV | = 0.5 + 0.3 = 0.8 V
√
and gm increases by a factor of 10 = 3.16 to
VG = 2.5 − VSG2 = 2.5 − 0.8 = 1.7 V
Chapter 7–13
1
W
V2
μn Cox
2
L 1 OV 1
W
1
100 = × 200 ×
× 0.32
2
L 1
W
⇒
= 11.1
L 1
1
W
|VOV 2 |2
ID2 = μp Cox
2
L 2
W
1
100 = × 100 ×
× 0.32
2
L 2
W
⇒
= 22.2
L 2
ID1 =
Av = −gm1 (ro1 ro2 )
gm1
2ID
2 × 0.1
=
= 0.67 mA/V
=
VOV
0.3
ro1 = ro2 =
|VA |L
20 × 0.5
= 100 k
=
ID
0.1
Av = −0.67 × (100 100) = −33.5 V/V
7.39 Refer to Fig. P7.39. The gain of the first
stage is
Av 1 = −gm1 (ro1 /2)
where (ro1 /2) is the equivalent resistance at the
output of Q1 and includes ro1 in parallel with the
output resistance of the current-source load,
which is equal to ro1 . Similarly, the gain of the
second stage is
Av 2 = −gm2 (ro2 /2)
Now because VAn = |VAp | = |VA | and both Q1 and
Q2 are operating at equal currents I , we have
ro1 = ro2 = ro
The overall voltage gain Av will be
Av = Av 1 Av 2
1
gm1 gm2 ro2
4
If the two transistors are operated at equal
overdrive voltages, |VOV |, both will have
equal gm ,
Av =
Av =
= |VAp
| and
7.38 Refer to Fig. 7.15. Since VAn
the channel lengths are equal, VAn = |VAp | and
ro1 = ro2 = ro . Thus
and
gm ro =
Av = −gm1 (ro1 ro2 ) = −gm1 (ro /2)
1
−40 = − gm1 ro
2
⇒ gm1 ro = 80
A0 =
2VAn
2VAn
L
=
VOV
VOV
1
(gm ro )2
4
2×5
10
2|VA |
=
=
|VOV |
|VOV |
|VOV |
Av = 400 =
10
1
×
4
|VOV |
2
⇒ |VOV | = 0.25 V
7.40
2×5×L
0.25
⇒ L = 2 μm
80 =
3 M
200 A
VSG2 = |Vtp | + |VOV | = 0.5 + 0.25 = 0.75 V
VG = VDD − VSG2 = 1.8 − 0.75 = 1.05 V
1
W
V2
ID1 = μn Cox
2
L 1 OV
1
W
100 = × 400 ×
× 0.252
2
L 1
W
⇒
=8
L 1
1
W
|VOV |2
ID2 = μp Cox
2
L 2
W
1
100 = × 100 ×
× 0.252
2
L 2
W
= 32
L 2
ID
IR
2 M
VGS
Figure 1
(a) Neglecting the dc current in the feedback
network and the Early effect, we see from Fig. 1
that ID = 200 μA. Now, using
1
W
2
VOV
ID = μn Cox
2
L
Chapter 7–14
The MOSFET will remain in saturation as long as
VDG ≥ −Vt . Thus at the limit VDG = −0.5 V,
we can determine VOV :
1
2
× 2 × VOV
2
⇒ VOV = 0.45 V
0.2 =
vGmax = 0.5 + vDmin
VGS + | v̂i | = 0.5 + VDS − | v̂o |
VGS = Vt + VOV = 0.5 + 0.45 = 0.95 V
The current in the feedback network can now be
found as
VGS
0.95
=
= 0.475 μA
IR =
2 M
2
which indeed is much smaller than the 200 μA
delivered by the current source. Thus, we were
justified in neglecting IR above.
(b) Replacing the MOSFET with its hybrid-π
model, we obtain the equivalent circuit shown in
Fig. 2.
ii
vi RG1
2 M
Rin
vgs
0.5 + 2.375 − 0.95
1
1+
|Av |
Substituting |Av | = 86.5, we obtain
| v̂o | = 1.9 V
An approximate value of | v̂o | could have been
obtained from
vOmin = VOV = 0.45 V
VDS − | v̂o | = VOV
vovi
RG2
gmvgs
ro vo
vgs vi
Figure 2
A node equation at the output node yields
vo − vi
vo
+ gm vgs +
=0
ro
RG2
where vgs = vi . Thus,
1
1
1
+
= −vi gm −
vo
ro
RG2
RG2
1
vo
= − gm −
(ro RG2 )
RG2
vi
gm =
| v̂o | =
| v̂o |
= 0.5 + 2.375 − | v̂o |
|Av |
Thus,
RG2 3 M
0.95 +
2ID
2 × 0.2
= 0.894 mA/V
=
VOV
0.45
VA
20
= 100 k
=
ID
0.2
1
vo
= − 0.89 −
× (100 3000)
vi
3000
ro =
= −86.5 V/V
To obtain the maximum allowable negative signal
swing at the output, we first determine the dc
voltage at the output by referring to Fig. 1,
RG2
VDS = VGS 1 +
RG1
3
= 0.95 × 1 +
= 2.375 V
2
⇒ | v̂o | = VDS − VOV = 2.375 − 0.45
= 1.925 V
|v̂ o |
= 22 mV
|v̂ i | =
86.5
(c) To determine Rin , refer to Fig. 2,
vi
vo − vi
−
ii =
RG1
RG2
vi
Av v i − v i
=
−
RG1
RG2
(1 − Av )
1
+
RG1
RG2
vi
1
(1 − Av )
=1
+
Rin =
ii
RG1
RG2
1 (1 + 86.5)
+
= 33.7 k
=1
2
3
= vi
7.41 From the results of Example 7.4, we see that
the almost linear region of the transfer
characteristic (i.e., region 3) is defined by
VIA = 0.89 V and VIB = 0.935 V. Maximum
output signal swing is achieved by biasing Q1 at
the middle of this range; thus
VI = 0.913 V
The peak-to-peak amplitude at the output will be
(VOA − VOB ) = 2.47 − 0.335 = 2.135 V. Thus the
1
peak amplitude will be (2.135) = 1.07 V.
2
7.42 Refer to Fig. 7.16(a).
Ro = 100 k = ro1 ro2
Chapter 7–15
thus
But
ro1
|VA |
5
= ro2 =
=
IREF
IREF
VOV 1 = 0.2 V
Since ID2 = ID3 = ID1 = 50 μA
Thus,
Av = −gm1 Ro
1
2
, we have
μ Cox (W/L) VOV
2 p
W
2ID2
W
=
= L 2
L 3
μp COX (VOV )2
−40 = −gm1 × 100
= 100 =
5
1
×
2 IREF
and ID =
⇒ IREF = 25 μA
2 (50 μA)
= 29.1
86 μA/V2 (0.2 V)2
⇒ gm1 = 0.4 mA/V
But
gm1 =
2μn Cox
W
L
ID1
1
W
0.4 = 2 × 0.4
× 0.025
L 1
W
⇒
=8
L 1
1
W
ID1 = μn Cox
V2
2
L 1 OV 1
1
2
× 400 × 8 × VOV
1
2
⇒ VOV 1 = 0.125 V
25 =
If Q2 and Q3 are operated at |VOV | = 0.125 V,
1
W
|VOV |2
ID2 = ID3 = μp Cox
2
L 2,3
1
W
25 = × 100 ×
× 0.1252
2
L 2,3
W
⇒
= 32
L 2,3
For Q1 ,
2 (50 μA)
W
= = 6.46
L 1
387 μA/V2 (0.2 V)2
Av must be at least −10 V/V
and Av = −gm (ro1
gm1 =
ro2 )
2ID
2 × 0.05
= 0.5 mA/V
=
VOV 1
0.2
ro1 ro2 =
10
= 20 k
0.5
But
ro1 =
VA1
V L
5L
= 100L
= An =
ID1
ID1
0.05
ro2 =
|VAp
|L
|VA2 |
6L
= 120L
=
=
ID2
ID2
0.05
Thus,
100L 120L = 20 k
⇒ L = 0.367 μm
If L is to be an integer multiple of 0.18 μm, then
L = 0.54 μm
7.43
To raise the gain to 20 V/V, ro1 ro2 has to be
raised to 40 k, which requires
L = 2 × 0.367 = 0.734
Again, to use a multiple of 0.18 μm we select
L = 0.9 μm. This represents an increase in L by a
5
0.90
= . Ws will have to increase by
factor of
0.54
3
the same factor. Thus, the area of each transistor
2
5
and the total
will increase by a factor of
3
area will increase as follows:
For an output of 1.6 V,
VSD2min = |VOV 2 | = 1.8 − 1.6 = 0.2 V,
Initial total area =
Area of Q1 + Area of Q2 + Area of Q3
For an output of 0.2 V,
= 6.46 × 0.542 + 29.1 × 0.542 + 29.1 × 0.542
VDS1min = 0.2 V,
= 18.85 μm2
Chapter 7–16
New total area =
6.46 × 0.92 + 29.1 × 0.92 + 29.1 × 0.92
Therefore the extreme values of vO for which Q1
and Q2 are in saturation 0.33 V ≤ vO ≤ 2.98 V
= 52.37 μm2
(c) From (b) we can find VIA and VIB :
Thus, the increase is by a factor of 2.78.
VIB = VOB + Vt = 0.33 + 0.8 = 1.13 V
If we solve (1) for VOA = 2.98 V, then
7.44 Refer to Fig. 7.16(a).
(VIA − 0.8)2 = 0.11 (1 − 0.03 × 2.98) ⇒ VIA
Note that Q2 , Q3 are not matched:
= 1.116 V
ID1 = 100 μA
Large-signal voltage gain
(a) ID2 = ID1 = 100 μA
W3
ID3
(W/L)3
=
=
ID2
W2
(W/L)2
=
(Note that VSG2 = VSG3 )
vO
2.98 − 0.33
=
vI
1.13 − 1.116
vO
= −189.3 V/V
vi
10
= 25 μA ⇒ IREF = 25 μA
40
(b) By referring to Fig. 7.16(d), you notice that in
Segment III, both Q1 and Q2 are in saturation and
the transfer characteristic is quite linear. The
output voltage in this segment is limited between
VOA and VOB : coordinates of point A:
v OA = VDD − |VOV 3 |
Differentiating both sides of (1) relative to vI :
ID3
25
=
|VOV 3 | =
10
1
1 W
× 50 ×
kp
2
1
2
L 3
For vO = 1.65 V, from 1 we have
⇒ ID3 = 100 μA
(d) vO =
VDD
3.3
=
= 1.65 V
2
2
2 (vI − 0.8) = 0.11 × (−0.03)
⇒
2
∂vO
∂vI
∂vO
= −606.1 (vI − 0.8)
∂vI
⇒ |VOV 3 | = 0.32 V
(vI − 0.8)2 = 0.11 (1 − 0.03 × 1.65) ⇒ vI
VOA = 3.3 − 0.32 = 2.98V
= 1.123 V
At point B: VOB = VIB − Vtn
∂vO
∂vI
Now we find the transfer equation for the linear
section: (Refer to Example 7.4)
iD1 = iD2 ⇒ (Note that |VOV 2 | = |VOV 3 |)
vO
1 W
kn
(vI − Vtn )2 1 +
2
L 1
VAn
W
VDD − vO
1
2
VOV
1
+
= k p
3
|VAP |
2
L 2
vO 20
1
× 100 × (v I − 0.8)2 1 +
2
1
100
40
3.3
− vO
1
× 0.322 1 +
= × 50 ×
2
1
50
vO vO 1+
(vI − 0.8)2 = 0.322 1.066 −
50
100
1
−
0.019v
O
(vI − 0.8)2 = 0.11
1 + 0.01vO
0.11(1 − 0.03vO )
(v I – 0.8)2 = 0.11(1 − 0.03vO )
v I = 1.123
= −195.8 V/V
(e) Rout = ro1
ro2
ro1 =
VAn
100 V
=
= 1 M
ID1
0.1 mA
ro2 =
VAp
50 V
= 500 k
=
ID2
0.1 mA
⇒ Rout = 500 k
Rout = 333 k
gm1 =
2kn
W
L
Now if we solve for VOB = VIB – 0.8
2
+ 0.0033VOB − 0.11 = 0 ⇒ VOB = 0.33 V
VOB
ID1
1
=
2 × 100 × 10−6 ×
20
× 100 × 10−6
1
= 0.632 mA/V
Av = −gm1 (ro1
(1)
1 M
ro2 ) = −210.6 V/V
Comment: The three estimates of voltage gain
obtained in (c), (d) and (e) are all reasonably
close; about −200 V/V.
Chapter 7–17
7.45 (a)
2ID
2 × 0.125
= 0.5 mA/V
=
VOV
1 − 0.5
gm =
1.0 V
Q2
ID2
R
VG
Av = 1 − 2 × 0.5 × 1000 = −999 V/V
(c)
VD
ii
ID1
0
R
Q1
vi
1.0 V
Figure 1
vgs
2gmvgs
ro/2 vo
vi
Rin i
i
vgs vi
From Fig. 1 we see that since the dc currents into
the gates are zero,
Figure 3
VD = VG
Also, since Q1 and Q2 are matched and carry
equal drain currents,
For the circuit in Fig. 3 we can write at the output
ID1 = ID2 = ID
vo
vo − vi
+ 2gm vgs +
=0
ro /2
R
VSG2 = VGS1 = 1 V
Substituting vgs = vi and rearranging, we obtain
and thus,
1
1−
vo
2gm R
= −2gm
2
1
vi
+
R ro
VG = 0
Thus,
ID =
1
× 1 × (1 − 0.5)2 = 0.125 mA
2
But 2gm R 1; thus
vo
ro −2gm R
Av =
vi
2
(b)
G
vgs
D
R
2gmvgs
vi vo
vgs
ro =
vgs vi
Figure 2
From Fig. 2 we see that
vo = vi − 2gm vgs R
But
vgs = vi
Thus,
vo
= 1 − 2gm R
vi
|VA |
20
= 160 k
=
ID
0.125
Av = −2 × 0.5(1000 80) = −74.1 V/V
Rin =
gmvgs
Av =
where
gmvgs
=
(d)
vi
vi
1
=
=R
vo
ii
(vi − vo )/R
1−
vi
R
1000
= 13.3 k
=
1 − Av
1 + 74.1
vi
Rin
13.3
= 0.4 V/V
=
=
vsig
Rin + Rsig
20 + 13.3
Gv =
vo
vi
vo
=
×
vsig
vsig
vi
= 0.4 × −74.1 = −29.6 V/V
(e) Both Q1 and Q2 remain in saturation for
output voltages that ensure that the minimum
voltage across each transistor is equal to
|VOV | = 0.5 V. Thus, the output voltage can range
from −0.5 V to +0.5 V.
Chapter 7–18
7.46 (a) IREF = IC3 =
3 − VBE3
46 k
7.48
io
3 − 0.7
46
= 0.05 mA
IREF =
⇒ IC2 = 5IC3
RL 20 k
IC2 = I = 0.25 mA ⇒ I = 0.25 mA
3V
io
3V
isig
IREF
Rs 20 k
Q1
vi
vo
46 k
Rin
I
Q3
Q2
Rin =
r o + RL
20 + 20
= 980 =
1 + gm ro
1 + 2 × 20
Since is = io ,
(b) |VA | = 50 V ⇒ ro1 =
|VA |
30
=
I
0.25
= 120 k
30
= 120 k
ro2 =
0.25
Total resistance at the collector of Q1 is
equal to ro1
ro2 , thus
rtot = 120 k 120 k = 60 k
(c) gm 1
rπ 1 =
IC1
0.25
=
=
= 10 mA/V
VT
0.025
β
50
=
= 5 k
gm
10
Rs
20
io
=
=
= 0.95 A/A
isig
Rs + Rin
20 + 0.98
If RL increases by a factor of 10, Rin becomes
Rin =
20 + 200
= 5.37 k
1 + 2 × 20
and the current gain becomes
20
io
=
= 0.79 A/A
isig
20 + 5.37
Thus an increase in RL by a factor of 10 resulted
in a decrease in the current gain from 0.95 A/A to
0.79 A/A, a change of only −17%. This indicates
that the CG amplifier functions as an effective
current buffer.
(d) Rin = rπ 1 = 5 k
Ro = ro1
ro2 = 120 k
120 k = 60 k
Av = −gm 1 Ro = −10 × 60 = −600 V/V
7.47 Refer to Fig. 7.18.
Rin =
ro + RL
1 + gm ro
20 + 20
=
= 980 1 + 2 × 20
7.49 Refer to Fig. P7.49.
ID = 0.2 mA VOV = 0.2 V
gm =
2ID
2 × 0.2
=
= 2 mA/V
VOV
0.2
ro =
VA
20
=
= 100 k
ID
0.2
Rout = ro + Rs + gm ro Rs
500 = 100 + Rs (1 + 2 × 100)
400
2 k
201
= ID RS + VGS
Rout = ro + Rs + gm ro Rs
⇒ Rs =
= 20 + 1 + 2 × 20 × 1 = 61 k
VBIAS
RL
vo
=
vsig
Rs + Rin
= ID RS + Vt + VOV
=
20
= 10.1 V/V
1 + 0.98
= 0.2 × 2 + 0.5 + 0.2
= 1.1 V
Chapter 7–19
7.50 Refer to Fig. P7.50. To obtain maximum
output resistance, we use the largest possible Rs
consistent with ID Rs ≤ 0.3 V. Thus
0.3 V
= 3 k
0.1 mA
Rs =
Now, for Q2 we have
gm = 1 mA/V
and
VA = 10 V
Thus,
ro =
VA
10 V
= 100 k
=
ID
0.1 mA
Rout = ro + Rs + gm ro Rs
(f) The value of vo can range from
VBIAS − Vt = 1.03 − 0.8 = 0.23 V to
(VDD − VOV 2 ). Since ID2 = ID1 and k n = k p , then
VOV 2 = VOV 1 . Thus the maximum value of vo is
3.3 − 0.224 = 3.076 V. Thus the peak-to-peak
value of vo is 3.076 − 0.23 = 2.85 V.
Correspondingly, the peak-to-peak value of vsig
will be
2.85
= 32 mV
vsig (peak to peak) =
89
7.52 Given Eq. (7.63):
Rin
re
= 100 + 3 + 1 × 100 × 3
ro + RL
RL
ro +
β +1
= 403 k
We can write
7.51 Refer to Fig. P7.51.
1 + (RL /ro )
1 + (RL /ro )
Rin
=
=
re
1 + [RL /(β + 1)ro ]
1 + (RL /101ro )
(a) ID1 = ID2 = ID3 = 100 μA
Using ID1
0.1 =
1
2
= k n (W/L)1 VOV
1 , we obtain
2
1
2
× 4 × VOV
1
2
RL /ro
0 1 10
100
1000
∞
Rin /re
1 2 10 50.8
91.8
101
Observe that the range of Rin is re to (β + 1)re .
⇒ VOV 1 = 0.224 V
7.53 Equation (7.66):
VGS1 = Vt + VOV 1 = 0.8 + 0.224 = 1.024 V
Rout = ro + (Re rπ ) + (Re rπ )gm ro
VBIAS = VGS + ID1 Rs
= ro + (re rπ )(1 + gm ro )
= 1.024 + 0.1 × 0.05 = 1.03 V
For gm ro 1,
(b) gm1
2ID1
2 × 0.1
= 0.9 mA/V
=
=
VOV 1
0.224
All transistors are operating at ID = 0.1 mA and
have |VA | = 20 V. Thus all have equal values
for ro :
ro =
|VA |
20
=
= 200 k
ID
0.1
(c) For Q2 , RL = ro2 = 200 k,
Rin =
=
r o + RL
1 + gm ro
200 + 200
= 2.2 k
1 + 0.9 × 200
(d) Rout = ro + Rs + gm ro Rs
= 200 + 0.05 + 0.9 × 200 × 0.05
Rout
ro + gm ro (Re rπ )
gm rπ Re
Rout
=1+
ro
rπ + Re
=1+
βRe
(β + 1)re + Re
Thus,
β(Re /re )
Rout
=1+
ro
β + 1 + (Re /re )
For β = 100,
100(Re /re )
Rout
=1+
ro
101 + (Re /re )
Re /re
0 1
Rout /ro
1 2 2.9 10
2
10 β/2
34
β
1000
51
92
= 209 k
Rin
2.2
vi
= 0.98 V/V
=
=
(e)
vsig
Rin + Rs
2.2 + 0.05
Observe that Rout ranges from ro to (β + 1)ro ,
with the maximum value obtained for Re = ∞.
RL
200
vo
=
= 90.9 V
=
vi
Rin
2.2
vo
= 90.9 × 0.98 = 89 V/V
vsig
7.54 Refer to Fig. P7.54. To obtain the
short-circuit current gain k, we replace the BJT
with its T model and short circuit the collector to
Chapter 7–20
io kisig
Thus,
Rout = 500 + (10 25) × 2001
ai
i
= 14.8 M
ro
Thus the CB amplifier has a current gain of nearly
unity and a very high output resistance: a
near-ideal current buffer!
re
E
A more exact value of k can be obtained using
Eq. (1); k = 0.975.
i1
isig
Rsig
7.55 Refer to Fig. P7.55.
I = IC = αIE = 0.99 ×
ro =
ground, resulting in the circuit shown in the
figure.
VA
100 V
= 100 k
=
IC
1 mA
where
gm =
Thus,
1/re
1
1
1
+ +
re
ro
Rsig
IC
1 mA
= 40 mA/V
=
VT
0.025 V
gm ro = 40 × 100 = 4000
rπ =
and
i1 = isig
β
100
= 2.5 k
=
gm
40
RE = 4.3 k
1/ro
1
1
1
+ +
re
ro
Rsig
Thus,
Rout = 100 + (4.3 2.5) × 4001 = 6.4 M
At the collector node, we can write
io ≡ kisig = i1 − αi
For
Thus,
VC = 10 V
kisig = isig
1/ro + (α/re )
1
1
1
+ +
re
ro
Rsig
1 mA
Rout = ro + (RE rπ )(1 + gm ro )
At the emitter node we see that there are three
parallel resistances to ground: re , ro , and Rsig .
i = −isig
5 − 0.7
4.3
(1)
10 V
= 1.6 μA
6.4 M
I =
A very small change indeed!
Now ro re and for the case Rsig re , we obtain
α/re
=α
1/re
For our case,
β
α=
β +1
β
100
k=α=
=
= 0.99
β +1
101
k
The output resistance Rout is given by
Rout = ro + (Rsig rπ )(1 + gm ro )
where
VA
50 V
ro =
=
= 500 k
IC
0.1 mA
IC
0.1 mA
=
gm =
= 4 mA/V
VT
0.025 V
gm ro = 4 × 500 = 2000
β
100
rπ =
= 25 k
=
gm
4
7.56 Refer to Fig. 7.27.
Rout = ro + (Re rπ )(1 + gm ro )
ro + (Re rπ )(gm ro )
Rout
= 1 + gm (Re rπ )
ro
=1+
gm rπ Re
rπ + Re
=1+
βRe
(β/gm ) + Re
For our case β = 100,
gm =
IC
0.5 mA
= 20 mA/V, thus
=
VT
0.025 V
100 Re
Rout
=1+
ro
5 + Re
where Re is in kilohms.
(1)
Chapter 7–21
(a) For Rout = 5 ro , Eq. (1) gives
Re = 0.208 k = 208 (b) For Rout = 10 ro , Eq. (1) gives
Re = 0.495 k 500 .
(c) For Rout = 50 ro , Eq. (1) gives Re = 4.8 k.
From Eq. (1) we see that the maximum value of
Rout /ro is obtained with Re = ∞ and its value is
101, which is (β + 1).
The minimum permitted output voltage is
VG − Vt = 1 − 0.5 = 0.5 V or 2VOV .
7.59 Refer to Fig. 7.32
Ro = gm3 ro3 ro4
For identical transistors,
Ro = (gm ro )ro
7.57 50 = gm2 ro2
= A02 =
=
2VA
VOV
Thus,
VA = 50 × VOV /2
= 25 × 0.2 = 5 V
5 = 5 × L ⇒ L = 1 μm
7.58 Refer to Fig. 7.33(a).
2ID
2I
=
VOV
VOV
2I
0.25
⇒ I = 0.25 mA
2=
For identical transistors,
Ro = (gm ro )ro =
2VA2
2VA VA
=
VOV I
VOV I
2VA2
200 =
0.25 × 0.25
⇒ VA = 2.5 V
VA = VA L
L=
IRo =
2|VA |2
VOV
Q.E.D.
(a) I = 0.1 mA
VA = VA L
gm1 =
2|VA |
|VA |
×
|VOV |
I
2.5
VA
=
= 0.5 μm
VA
5
To obtain W/L, we use
1
W
2
VOV
ID = I = μn Cox
2
L
W
1
× 0.252
250 = × 400 ×
2
L
W
= 20
⇒
L
To obtain maximum negative signal swing at the
output, we select VG so that the voltage at the
drain of Q1 is the minimum permitted, which is
equal to VOV (i.e., 0.25 V). Thus
VG = 0.25 + VGS2
= 0.25 + VOV 2 + Vt
= 0.25 + 0.25 + 0.5 = 1.0 V
2 × 42
= 160
0.2
Ro = 1.6 M
0.1 × Ro =
To obtain the W/L values,
1
W
|VOV |2
I = ID = μp Cox
2
L 3,4
1
W
100 = × 100 ×
× 0.22
2
L 3,4
W
⇒
= 50
L 3,4
(b) I = 0.5 mA
2 × 42
= 160
0.2
Ro = 320 k
W
1
|VOV |2
I = μp Cox
2
L 3,4
W
1
500 = × 100 ×
|VOV |2
2
L 3,4
W
⇒
= 250
L 3,4
0.5Ro =
7.60 Refer to Fig. 7.32.
Ro = (gm3 ro3 )ro4
For identical transistors,
Ro = (gm ro )ro
=
2|VA |
|VA |
×
|VOV |
I
Thus,
IRo =
2|VA |2
|VOV |
Chapter 7–22
This table belongs to Problem 7.60.
L = Lmin = 0.18 μm
IRo = 8.1 V
L = 2Lmin = 0.36 μm
IRo = 32.4 V
L = 3Lmin = 0.54 μm
IRo = 72.9 V
gm
Ro
Av
2WL
gm
Ro
Av
2WL
gm
Ro
Av o
2WL
(mA/V) (k) (V/V) (μm2 ) (mA/V) (k) (V/V) (μm2 ) (mA/V) (k) (V/V) (μm2 )
I = 0.01 mA
W/L = n
0.1
810 −40.5 0.065 n
I = 0.1 mA
W/L = 10 n
1.0
81
I = 1.0 mA
W/L = 100 n
10.0
8.1 −40.5
0.1
−40.5 0.65n
6.5n
|VA | =
0.1
7,290 −364.5 0.58n
1.0
324
−162
2.6n
1.0
729 −364.5 5.8n
10.0
32.4 −162
26n
10.0
72.9 −364.5
58n
Rop = (gm ro )ro = (2 × 20) × 20 = 800 k
Substituting
|VA |
3,240 −162 0.26n
Ro = Ron Rop = 400 k
L
2|VA |2 2
L
IRo =
|VOV |
Q.E.D.
Av = −gm1 Ro = −2 × 400 = −800 V/V
Now, for
L = 0.18 μm,
IRo =
2 × 52
× 0.182 = 8.1 V
0.2
L = 0.36 μm,
IRo =
2 × 52
×0.362 = 32.4 V
0.2
2 × 52
×0.542 = 72.9 V
0.2
To fill out the table above, we use
L = 0.54 μm,
gm =
IRo =
7.62
VDD 3.3 V
VG4
Q4
VD4
2ID
2I
2I
=
=
= 10I
|VOV |
|VOV |
0.2
Av = gm (Ro /2)
VG3
Q3
(a) The price paid is the increase in circuit area.
Ro
(b) As I is increased, gm increases and hence the
current-driving capability of the amplifier, and as
we will see later, its bandwidth.
(c) The circuit with the largest area (58n) as
compared to the circuit with the smallest area
(0.065n): Av is 364.5/40.5 = 9 times larger; gm is
100 times larger, but Ro is 11.1 times lower.
I 100 A
VSG4 = |Vtp | + |VOV |
= 0.8 + 0.2 = 1 V
Thus,
VG4 = VDD − VSG4 = 3.3 − 1 = 2.3 V
7.61 Refer to Fig. 7.33.
gm1
2ID1
2I
2 × 0.2
=
= 2 mA/V
=
=
VOV 1
VOV
0.2
Since all transistors are operating at the same ID
and |VOV |, all have equal values of gm . Also
because all have equal |VA | = 4 V, all ro ’s will be
equal:
To obtain the largest possible signal swing at the
output, we maximize the allowable positive signal
swing by setting VD4 at its highest possible value
of VDD − |VOV | = 3.3 − 0.2 = 3.1 V. This will be
obtained by selecting VGS as follows:
VG3 = VD4 − VSG3
4
|VA |
|VA |
=
= 20 k
=
ro =
ID
I
0.2
Since
Ron = (gm ro )ro = (2 × 20) × 20 = 800 k
VG3 = 3.1 − 1 = 2.1 V
VSG3 = VSG4 = 1 V
Chapter 7–23
the highest allowable voltage at the output will be
vD3max = VG3 + |Vtp |
= 2.1 + 0.8 = 2.9 V
Since both Q3 and Q4 carry the same current
I = 100 μA and are operated at the same
overdrive voltage, |VOV | = 0.2 V, their W/L ratios
will be the same and can be found from
1
W
|VOV |2
ID = μp Cox
2
L 3,4
W
1
100 = × 60 ×
× 0.22
2
L 3,4
W
⇒
= 83.3
L 3,4
⇒
W
L
= 10
1,2
For each of the PMOS transistors,
1
W
|VOV |2
ID = μp Cox
2
L 3,4
1
W
125 = × 100 ×
× 0.252
2
L 3,4
W
⇒
= 40
L 3,4
7.64
ix
Ro
To obtain Ro , we first find gm and ro of both
devices,
gm3,4 =
2 × 0.1
2ID
=
= 1 mA/V
|VOV |
0.2
ro3,4 =
|VA |
5
= 50 k
=
ID
0.1
Q2
ix
vx
vy
ro1
Ro = (gm3 ro3 )ro4
Q1
= 1 × 50 × 50 = 2.5 M
7.63 Refer to Fig. 7.33.
Av = −gm1 Ro
−280 = −1 × Ro ⇒ Ro = 280 k
gm1 =
2ID
2I
1
=
⇒ I = gm1 VOV
VOV
VOV
2
1
× 1 × 0.25 = 0.125 mA
2
All four transistors are operated at the same value
of ID and the same value of |VOV |. Also all have
the same channel length and |VA |; thus all ro
values are equal. Thus
=
Ron = Rop = 2Ro = 2 × 280 = 560 k
While vx appears across Ro , vy appears across ro1 ,
Thus,
vy
ro1
=
vx
Ro
ro1
=
ro1 + ro2 + gm2 ro2 ro1
For gm2 ro2 1 and gm2 ro1 1,
vy
vx
1
gm2 ro2
560 = (gm ro )ro
=
2|VA | |VA |
|VOV | I
2|VA |2
=
0.25 × 0.125
⇒ VA = 2.96 V
2.96
VA
= 0.6 μm
L= =
VA
5
For each of the NMOS devices,
1
W
V2
ID = μn Cox
2
L 1,2 OV
1
W
125 = × 400 ×
× 0.252
2
L 1,2
7.65 Refer to Fig. P7.65.
(a) For the circuit in (a),
1
W
2
I = μn Cox
VOVa
2
L
For the circuit in (b),
1
W
I = μn Cox
V2
2
4L OVb
Comparing Eqs. (1) and (2) we see that
VOVb = 2VOVa
Now,
gm =
2ID
VOV
Q.E.D.
(1)
(2)
Chapter 7–24
Thus for the circuit in (a),
gm1 = gm2 =
2I
VOVa
and for the circuit in (b),
gma =
gmb =
=
2I
2I
I
=
=
VOVb
2 VOVa
VOVa
2 × 0.4 ×
ro1 = ro2 =
Thus,
1
gma
Q.E.D.
2
Since the channel length in (b) is four times that
in (a),
gmb =
VAb = 4VAa
2μn Cox
5.4
× 0.2 = 1.55 mA/V
0.36
VA
VL
5 × 0.36
= A =
= 9 k
ID
ID
0.2
Ro = ro1 + ro2 + gm2 ro2 ro1 = 9 + 9 + 1.55 × 9 × 9
= 143.6 k
Av = −gm1 (Ro RL )
and
−100 = −1.55(Ro RL )
rob = 4roa
⇒ Ro RL = 64.5 k
Thus
1
1
1
+
=
Ro
RL
64.5
Ava = −gma roa
W
ID
L
1
1
1
1
=
−
=
RL
64.5 143.6
117
and
Avb = −gmb rob
⇒ RL = 117 k
1
= − gma × 4 roa
2
= 2Av a
Q.E.D.
Rin2 =
(b) For the cascode circuit in (c) to have the same
minimum voltage requirement at the drain as that
for circuit (b), which is equal to VOV b = 2VOV a ,
we must operate each of the two transistors in the
cascode amplifier at VOV = VOV a . Thus each of
the two transistors in the cascode circuit will have
gm = gma . Also, each will have ro = roa . Thus
=
ro2 + RL
1 + gm2 ro2
9 + 143.6
= 10.2 k
1 + 1.55 × 9
Rd 1 = ro1 Rin2 = 9 10.2 = 4.8 k
A1 = −gm1 Rd 1 = −1.55 × 4.8 = −7.41 V/V
Avc = −gm Ro
−gm [(gm ro )ro ]
7.67 Refer to Fig. P7.67.
= −A2va
Obviously, the cascode delivers a much greater
gain than that achieved by quadrupling the
channel length of the CS amplifier.
7.66
R2
(gm ro )ro
R3 =
R2 + ro
gm ro2 + ro
=
gm ro
gm ro
vo
Ro
Q2 5.4/0.36
Rin2
RL
i2 = i1
1
R3
ro
= gm vi
= gm v i
R3 + ro
ro + ro
2
i3 = i1 − i2 =
Q1 5.4/0.36
1
gm v i
2
i4 = i3 =
1
gm v i
2
i5 = i4 =
1
gm v i
2
ro1
vi
ro
(b) i1 = gm vi
I 0.2
mA
VG2
(a) R1 = ro1 = ro
i6 = 0 (because vsg4 = 0)
i7 = i5 =
1
gm v i
2
Chapter 7–25
1
(c) v1 = −i2 ro = − (gm ro )vi
2
1
v2 = −i4 R2 = − gm (gm ro )ro vi
2
1
= − (gm ro )2 vi
2
1
1
v3 = −i5 R1 = − gm vi ro = − (gm ro )vi
2
2
(d) vi is a 5-mV peak sine wave (see Fig. 1).
7.68
VDD 1.8 V
VG1
Q1
ro1
1.6 V
1
v̂ 1 = − × 20 × vi = −10 × 5 = −50 mV
2
Thus, v1 is a 50-mV peak sine wave that is 180◦
out of phase with vi .
1
v̂ 2 = − × 202 × 5 = −1 V
2
Thus, v2 is a 1-V peak sine wave, 180◦ out of
phase relative to vi .
Q2
VG2
(gm2ro2) ro1
1.4 V
VG3
Q3
Ro = (gm3ro3) (gm2ro2) ro1
I 0.2 mA
1
v̂ 3 = − × 20 × 5 = −50 mV
2
Thus, v3 is a 50-mV peak sine wave, 180◦ out of
phase relative to vi .
We design for a minimum voltage of |VOV | across
each of Q1 and Q2 .
vi
VG1 = VDD − VSG1 = VDD − |Vtp | − |VOV |
= 1.8 − 0.4 − 0.2 = 1.2 V
5 mV
0
t
VG2 = VS2 − VSG2
= 1.6 − 0.4 − 0.2 = 1.0 V
v1
VG3 = VS3 − VSG3
50 mV
= 1.4 − 0.4 − 0.2 = 0.8 V
0
t
v2
–1 V
All transistors carry the same ID = 0.2 mA and
operate at the same value of |VOV | = 0.2 V. Thus,
their W/L ratios will be equal,
0.2 =
⇒
0
t
1
W
× 0.1 ×
× 0.22
2
L
W
= 100
L
Ro = (gm ro )2 ro
where
v3
–50 mV
gm =
2 × 0.2
2ID
=
= 2 mA/V
|VOV |
0.2
ro =
|VA |L
6 × 0.4
= 12 k
=
ID
0.2
Ro = (2 × 12)2 × 12 = 6.91 M
0
t
7.69 Refer to Fig. P7.69.
(a) Ro1 = ro
Ro2 = ro
Figure 1
Chapter 7–26
Ro5 = ro
Ro = (gm3 ro3 )(ro4 rπ3 )
Ro4 = (gm ro )ro
I = 0.2 mA
I
0.2
gm3 =
= 8 mA/V
=
VT
0.025
VA
5
ro3 = ro4 =
=
= 25 k
I
0.2
β
50
=
rπ 3 =
= 6.25 k
gm3
8
Ro3 = ro3 + (gm3 ro3 )(Ro1 Ro2 )
1
= ro + gm ro × ro
2
1
1
ro (1 + gm ro )
(gm ro )ro
2
2
ro3 + Ro4
ro + gm ro ro
Rin3 =
1 + gm3 ro3
gm ro
=
1
+ ro
gm
Ro = (8 × 25)(25 6.25)
= 1 M
ro
(b) Ro = Ro3 Ro4
1
= (gm ro )ro (gm ro )ro
2
1
= (gm ro )ro
3
(c) When vo is short-circuited to ground, Rin2
becomes equal to 1/gm3 . This resistance will be
much smaller than the two other resistances
between the drain of Q1 and ground, namely,
Ro1 = ro and Ro2 = ro . Thus the signal current in
the drain of Q1 , gm1 vi will mostly flow into 1/gm3 ,
that is, into the source of Q3 and out of the drain
of Q3 to ground. Thus, the output short-circuit
current will be equal to gm1 vi ; thus the
short-circuit transconductance Gm will be
Gm = gm1
Q.E.D.
vo
= −gm1 Ro
(d)
vi
1
= −gm × (gm ro )ro
3
1
= − (gm ro )2
3
For
gm = 2 mA/V
and
7.71 When Eq. (7.88) is applied to the case of
identical pnp transistors, it becomes
Ro = (gm ro )(ro rπ )
Now,
I
|VA |
ro =
VT
I
gm ro = |VA |/VT
β
rπ =
gm
gm =
Thus,
=
=
=
=
A0 = 30
1
vo
= − (30)2 = −300 V/V
vi
3
|VA | Iro rπ
VT ro + rπ
|VA | |VA | rπ
VT ro + rπ
|VA | |VA |
VT 1 + ro
rπ
|VA |
|VA |
1
VT
1 + gm ro
β
|VA |
1
1 1
VT 1
+
|VA | β VT
|VA |
(VT /|VA |) + (1/β)
IRo =
=
For |VA | = 5 V and β = 50 we obtain
5
IRo =
= 200 V
(0.025/5) + (1/50)
7.70
VCC
I (mA)
VB4
Q4
VB3
Q3
Q.E.D.
0.1
0.5
1
Ro (k) 2000 400 200
7.72 The output resistance of the cascode
amplifier (excluding the load) is
Ro = gm ro (ro rπ )
Thus,
Ro
Av = −gm (Ro RL )
= −gm (Ro βro )
Chapter 7–27
For |VA | = 100 V, β = 50, and I = 0.2 mA we
obtain
I
0.2
gm =
=
= 8 mA/V
VT
0.025
β
50
= 6.25 k
rπ =
=
gm
8
100
|VA |
=
= 500 k
I
0.2
Ro = 8 × 500 × (500 6.25)
ro =
= 24, 691 k
Av = −8(24.7 25) × 103
= −99.4 × 103
−105 V/V
(b) Refer to the circuit in Fig. P7.74(b).
I
0.1
= 4 mA/V
=
VT
0.025
2ID2
2I
2 × 0.1
= 1 mA/V
gm2 =
=
=
VOV
VOV
0.2
β
100
rπ1 =
=
= 25 k
gm1
4
5
|VA |
=
ro1 =
= 50 k
I
0.1
|VA |
5
ro2 =
=
= 50 k
I
0.1
Rin = rπ1 = 25 k
gm1 =
Ro = gm2 ro2 ro1
= 1 × 50 × 50 = 2.5 M
7.73 Refer to Fig. 7.38. When all transistors have
equal β and ro , and, since they conduct equal
currents, they have equal gm , then
= −4 × 2.5 × 103 = −10, 000 V/V
Ron = Rop = gm ro (ro rπ )
(c) Refer to the circuit in Fig. P7.74(c).
Ro = Ron Rop =
1
(gm ro )(ro rπ )
2
Av o = −gm1 Ro
gm1 = gm2 =
Av = −gm Ro
1 mA/V
1
= − (gm ro )gm (ro rπ )
2
1
gm ro rπ
= − (gm ro )
2
rπ + ro
1
1
= − (gm ro )
1
1
2
+
gm ro
gm rπ
|VA |
Substituting gm ro =
and gm rπ = β,
VT
1
|VA |/VT
Av = −
2 (VT /|VA |) + (1/β)
ro1 = ro2 =
2ID
2I
2 × 0.1
=
=
=
|VOV |
|VOV |
0.2
|VA |
5
|VA |
=
= 50 k
=
ID
I
0.1
Rin = ∞
Ro = gm2 ro2 ro1
= 1 × 50 × 50 = 2.5 M
Av o = −gm1 Ro = −1 × 2.5 × 183 = −2500 V/V
(d) Refer to the circuit in Fig. P7.74(d).
gm1 =
2I
2ID
2 × 0.1
=
=
= 1 mA/V
|VOV |
|VOV |
0.2
I
0.1
=
gm2 =
= 4 mA/V
VT
0.025
5
|VA |
=
ro1 =
= 50 k
I
0.1
5
|VA |
=
= 50 k
ro2 =
I
0.1
β
100
rπ2 =
= 25 k
=
gm2
4
Rin = ∞
gm2
Ro = (gm2 ro2 )(ro1 rπ2 )
For |VA | = 5 V and β = 50 we obtain
5/0.025
1
Av = −
= −4000 V/V
2 (0.025/5) + (1/50)
7.74 (a) Refer to circuit in Fig. P7.74(a).
I
0.1
= 4 mA/V
=
VT
0.025
= gm1 = 4 mA/V
β
100
= 25 k
=
gm
4
|VA |
5
=
= 50 k
ro1 = ro2 =
I
0.1
Rin = rπ 1 = 25 k
rπ 1 = rπ 2 =
Ro = gm2 ro2 (ro1 rπ 2 )
= (4 × 50)(50 25) = 3.33 M
Av o = −gm Ro
= −4 × 3.33 × 103 = −13,320 V/V
gm1 =
= 4 × 50(50 25)
= 3.33 M
Av o = −gm1 Ro
= −1 × 3.33 × 106 = −3330 V/V
Comment: The highest voltage gain (13,320 V/V)
is obtained in circuit (a). However, the input
resistance is only 25 k. Of the two circuits with
infinite input resistance (c and d), the circuit in (d)
has the higher voltage gain. Observe that
combining MOSFETs with BJTs results in
Chapter 7–28
circuits superior to those with exclusively
MOSFETs or BJTs.
The lowest voltage at the output while Q3 remains
in saturation is
VOmin = VG3 − Vt3
7.75 (a) Refer to the circuit in Fig. P7.75(a).
W
gm1 = 2μn Cox
ID
L
√
= 2 × 0.4 × 25 × 0.1
= 1.41 mA/V
VA
1.8
ro1 =
=
= 18 k
ID
0.1
I
0.1
= 4 mA/V
gm2 =
=
VT
0.025
1.8
VA
=
= 18 k
ro2 =
I
0.1
β
125
rπ 2 =
= 31.25 k
=
gm2
4
= 1.7 − 0.6 = 1.1 V
2ID2,3
2 × 0.2
gm2 = gm3 =
=
= 1.6 mA/V
VOV 2,3
0.25
VA
10
=
= 50 k
ID
0.2
Ro = gm3 ro3 ro2
ro2 = ro3 =
= 1.6 × 50 × 50 = 4 M
7.77
(gm3ro3) (gm2ro2)ro1
IREF
Gm = gm1 = 1.41 mA/V
IO
Ro = gm2 ro2 (ro1 rπ 2 )
= 4 × 18 × (18 31.25) = 822.3 k
Av o = −Gm Ro = −1.41 × 822.3 = −1159 V/V
(b) Refer to circuit in Fig. P7.75(b).
√
gm1 = gm2 = 2 × 0.4 × 25 × 0.1
= 1.41 mA/V
1.8
VA
ro1 = ro2 =
=
= 18 k
I
0.1
Gm = gm1 = 1.41 mA/V
Q6
Q3
Q5
Q2
(gm2 ro2)ro1
ro1
Q4
Q1
Ro = gm2 ro2 ro1
= 1.41 × 18 × 18 = 457 k
Av o = −Gm Ro = −1.41 × 457 = −644 V/V
From the figure we see that
We observe that the circuit with a cascode
transistor provides higher gain.
Ro = (gm3 ro3 )(gm2 ro2 )ro1
7.76 Refer to Fig. 7.39.
7.78 Refer to Eq. (7.95),
(W/L)2
(W/L)1
40/1
= 200 μA
= 20
4/1
1
W
ID1 = μn Cox
V2
2
L 1 OV 1
Ro = β3 ro3 /2
IO = IREF
1
4
2
20 = × 160 × × VOV
1
2
1
⇒ VOV 1 = 0.25 V
VG2 = VGS1 = Vt + VOV 1 = 0.6 + 0.25 = 0.85 V
VOV 4 = VOV 1
where
ro3 =
100 V
VA
=
= 100 k
I
1 mA
Thus,
100 × 100
= 5 M
2
VO
10 V
=
IO =
= 2 μA
Ro
5 M
Ro =
2 μA
IO
= 0.002
=
IO
1 mA
or 0.2%
Thus,
VGS4 = VGS1 = 0.85 V
VG3 = 0.85 + 0.85 = 1.7 V
7.79 (a) IO1 = IO2 =
1 IREF
2
2
1+ 2
β
Chapter 7–29
(b)
1.1 + 2.5
= 36 k
0.1
VOmax is limited by Q3 saturating. Thus
R=
IO1
IO2
IO3
VOmax = VE3 − VECsat
IREF
0.7 mA
Q3
Q5
Q4
1
2
= 1.8 − 0.3 = 1.5 V
4
7.81 Replacing each of the transistors in the
Wilson mirror of Fig. 7.40 with its T model while
neglecting ro results in the circuit shown below.
Q1
ix
Q1
2
aie3
(1 a) ie3
ie3
aie2
VEE
vx
The figure shows the required circuit. Observe
that the output transistor is split into three
transistors having base–emitter junctions with
area ratio 1:2:4. Thus
0.1
0.1
IO1 =
=
= 0.0999 mA
2
2
1+ 2
1+ 2
β
50
1
Rin
ie2
re2
ie1
re1
Note that the diode-connected transistor Q1
reduces to a resistance re1 . To determine Rin , we
have applied a test voltage vx . In the following
we analyze the circuit to find ix and hence Rin , as
vx
Rin ≡
ix
0.2
= 0.1998 mA
2
1+ 2
50
0.4
=
= 0.3997 mA
2
1+ 2
50
IO2 =
IO4
re3
Note that all three transistors are operating at
equal emitter currents, approximately equal to
IREF . Thus
7.80
re1 = re2 = re3 =
2.5 V
VT
IREF
Analysis of the circuit proceeds as follows. Since
re1 = re2 , we obtain
1.8 V
Q2
ie2 = ie1
Q1
(1)
Node equation at node 1:
ie3 + αie2 = ie1 + ie2
Using Eq. (1) yields
1.1 V
ie3 = (2 − α)ie1
Q3
(2)
Node equation at node 2:
R
0.1 mA
ix = αie2 + (1 − α)ie3
IO
VO
Using Eqs. (1) and (2) yields
ix = ie1 [α + (1 − α)(2 − α)]
2.5 V
ix = ie1 [2 − 2α + α 2 ]
(3)
Chapter 7–30
Finally, vx can be expressed as the sum of the
voltages across re3 and re1 ,
Thus
vx = ie3 re + ie1 re
The voltage vx can be expressed as the sum of the
voltages across 1/gm3 and 1/gm1 :
ix = i2
Using Eq. (2) yields
vx = ie1 re (3 − α)
(4)
Substituting i3 = i2 and i1 = i2 , gm1 = gm3 = gm ,
and
Dividing Eq. (4) by Eq. (3) yields
Rin =
For α
vx
3−α
= re
ix
2 − 2α + α 2
vx = 2 i2 /gm
But i2 = ix ; thus
1,
Rin = 2re = 2
VT
IREF
vx = 2 ix /gm
Q.E.D.
and thus
2
Rin =
gm
Thus, for IREF = 0.2 mA,
Rin = 250 7.82 Replacing each of the three transistors in the
Wilson current mirror in Fig. 7.41(a) with its
T model results in the circuit in the figure.
i3
ix
i3
i2
vx
Q.E.D.
7.83 Refer to circuit in Fig. 7.41(a).
(a) Each of the three transistors is operating at
ID = IREF . Thus
1
W
2
VOV
IREF = μn Cox
2
L
1
2
× 400 × 10 × VOV
2
⇒ VOV = 0.3 V
180 =
2
vx = (i3 /gm3 ) + (i1 /gm1 )
1
gm3
1
i2
1
gm2
i1
1
gm1
VG3 = Vtn + VOV = 0.5 + 0.3 = 0.8 V
(b) Q1 is operating at VDS = VGS = 0.8 V
Q2 is operating at VDS = 2VGS = 1.6 V
Thus,
IREF − IO =
VDS
ro
where
Rin
Here, we have applied a test voltage vx to
determine Rin ,
vx
Rin ≡
ix
Since all three transistors are identical and are
operating at the same ID ,
gm1 = gm2 = gm3
Now from the figure we see that
i1 = i2
and
i2 + i3 = i2 + i1
Thus
i3 = i1 = i2
A node equation at node 2 gives
ix + i3 = i2 + i3
VA
18
= 100 k
=
IREF
0.18
0.8
= 0.008 mA = 8 μA
IREF − IO =
100
IO = 180 − 8 = 172 μA
ro =
(c) Refer to Fig. 7.41(c). Since Q1 and Q2 are
now operating at equal VDS , we estimate
IO = IREF = 180 μA.
(d) The minimum allowable VO is the value at
which Q3 leaves the saturation region:
VOmin = VG3 − Vt
= VGS3 + VGS1 − Vt
= 0.8 + 0.8 − 0.5 = 1.1 V
(e) Diode-connected transistor Q4 has an
incremental resistance 1/gm4 . Reference to Fig.
7.41(b) indicates that the incremental resistance
of Q4 would appear in series with the gate of Q3
and thus carries zero current. Thus including Q4
Chapter 7–31
has no effect on the value of Ro , which can be
found from Eq. (7.96):
Ro = gm3 ro3 ro2
where
2ID
2 × 0.18
= 1.2 mA/V
=
VOV
0.3
VA
18
ro2 = ro3 =
=
= 100 k
IREF
0.18
Thus,
Ro = 1.2 × 100 × 100 = 12 M
(f) For VO = 1 V, we obtain
VO
1V
IO =
=
= 0.08 μA
Ro
12 M
IO
= 0.04%
IO
gm3 =
7.85 Refer to Fig. 7.42.
(a) To obtain a current transfer ratio of 0.8 (i.e.,
IO /IREF = 0.8 and IO = 80 μA), we write
IREF
IO RE = VT ln
IO
100
0.08RE = 0.025 ln
80
⇒ RE = 69.7 0.08
= 3.2 mA
gm2 =
0.025
50
= 625 k
ro2 =
0.08
rπ2 = ∞ (because β = ∞)
Rout = RE + ro2 + gm2 ro2 RE
= 0.069 + 625 + 3.2 × 625 × 0.0697
7.84
= 764.5 k
IREF
200 A
Rout
IO 20 A
Q1
VBE2
VBE1
(b) To obtain IO /IREF = 0.1, that is, IO = 10 μA,
we write
100
0.01 RE = VT ln
10
Q2
RE
(a) Assuming β is high so that we can neglect
base currents,
IREF
IO RE = VT ln
IO
Substituting IO = 20 μA and IREF = 200 μA
results in
200
0.02 RE = 0.025 ln
20
⇒ RE = 2.88 k
(b) Rout = (RE rπ 2 ) + ro2 + gm2 ro2 (RE rπ 2 )
where
0.02
= 0.8 mA/V
0.025
VA
50
=
=
= 2500 k
IO
0.02
gm2 =
ro2
rπ 2 =
Relative to the value of ro2 ,
Rout
= 1.22
ro2
β
200
=
= 250 k
gm
0.8
⇒ RE = 5.76 k
0.01
= 0.4 mA/V
gm2 =
0.025
50
= 5000 k
ro2 =
0.01
rπ2 = ∞
Rout = RE + ro2 + gm2 ro2 RE
= 5.76 + 5000 + 0.4 × 5000 × 5.76
= 16.5 M
Compared to ro2 ,
16.5
Rout
= 3.3
=
ro2
5
(c) To obtain IO /IREF = 0.01, that is, IO = 1 μA,
we write
100
0.001 RE = 0.025 ln
1
⇒ RE = 115 k
0.001
= 0.04 mA/V
gm2 =
0.025
50
= 50 × 103 k
ro2 =
0.001
Rout = (2.9 250)+2500+0.8×2500×(2.9 250)
Rout = 115 + 50 × 103 + 0.04 × 50 × 103 × 115
= 8.2 M
= 280 M
A 5-V change in VO gives rise to
Relative to the value of ro2 ,
IO =
5
= 0.7 μA
7.1
280
Rout
=
= 5.6
ro2
50
Chapter 7–32
7.86 (a) Refer to the circuit in Fig. P7.86.
Neglecting the base currents, we see that all three
transistors are operating at IC = 10 μA, and thus
1 mA
VBE1 = VBE2 = VBE3 = 0.7 − 0.025 ln
10 μA
that we have set vi = 0 and applied a test
voltage vx . We note that
vgs = vbs = −vx
and
= 0.585 V
ix = −gmb vbs +
From the circuit we see that the voltage across R
is VBE = 0.585 V, thus
Thus,
IO R = VBE
0.585
= 58.5 k
R=
0.01
0.01
= 0.4 mA/V
(b) gm3 =
0.025
40
= 4000 k
ro3 =
0.01
β
100
=
= 250 k
rπ 3 =
gm3
0.4
(1)
ix = gmb vx +
vx
vx
− gm vgs +
ro1
ro3
vx
vx
+ gm vx +
ro1
ro3
from which we obtain
vx
1
= ro1 ro3
Ro ≡
ix
gm + gmb
Q.E.D.
Rout = (R rπ 3 ) + ro3 + gm3 ro3 (R rπ 3 )
7.89 The dc level shift provided by a source
follower is equal to its VGS . Thus, to obtain a dc
level shift of 0.9 V, we write
= (58.5 250) + 4000 + 0.4 × 4000 × (58.5 250)
VGS = 0.9 V = Vt + VOV
= 79.9 M
⇒ VOV = 0.9 − 0.6 = 0.3 V
7.87 Refer to the circuit in Fig. P7.87. Since Q1
and Q2 are matched and conducting equal
currents I , their VGS values will be equal. Thus
from the loop Q1 , Q6 , R, and Q2 , we see that
IR = VEB6
I
= VT ln
IS
Q.E.D.
ro =
G
vgs
ix
S
gmvgs
ro1
VA
VL
20 × 0.5
= 27.8 k
= A =
ID
ID
0.36
To determine Av o , we note [refer to Fig. 7.45(b)]
that the total effective resistance between the
MOSFET source terminal and ground is
1
ro1 ro3
. Denoting this resistance R, we
gmb
have
1
R = ro ro
gmb
7.88
ro3
2ID
2 × 0.36
=
= 2.4 mA/V
VOV
0.3
gmb = χgm = 0.2 × 2.4 = 0.48 mA/V
⇒ R = 3.3 k
vgs vbs
1
20
× 0.2 ×
× 0.32
2
0.5
I = 0.36 mA = 360 μA
=
gm =
Now to obtain I = 0.2 mA, we write
1 mA
0.2R = 0.7 − 0.025 ln
0.2 mA
To obtain the required bias current, we use
1
W
2
VOV
I = ID = μn Cox
2
L
v
x
gmbvbs
= 27.8 27.8
1
0.48
= 1.81 k
Thus, the open-circuit voltage gain is
B
v
x
Ro ix
The figure shows the equivalent circuit of the
source follower prepared for finding Ro . Observe
Av o =
=
R
R+
1
gm
1.81
1.81 +
1
2.4
= 0.81 V/V
Chapter 7–33
Ro = R//
1
gm
(b) Increasing the bias current by a factor of 10
(i.e., to 2 mA) results in
= 1.81 k//
1
2.4 mA/V
gm = 80 mA/V
re = 0.0125 k
= 0.339 k
When a load resistance of 2 k is connected to
the output, the total resistance between the output
node and ground become R RL = 1.81 2 =
0.95 k. Thus, the voltage gain becomes
Av =
0.95
0.95 +
1
2.4
rπ = 1.25 k
ro = 25 k
Rin2 = rπ2 = 1.25 k
Rin = 101[0.0125 + (1.25 25)] = 121.5 k
= 0.7 V/V
Thus, Rin has been reduced by a factor of 10.
121.5
vb1
=
vsig
121.5 + 500
7.90
= 0.2 V/V (considerably reduced)
5 V
200 A
Rsig 500 k
Q1
vo
vsig Q2
200 A
Rin
Rin2 r2
(1.25 25)
ve1
=
vb1
(1.25 25) + 0.0125
= 0.99 V/V (unchanged)
vo
= −gm2 ro = −80 × 25
vb1
= −2000 V/V (unchanged)
vo
= 0.2 × 0.99 × −2000 = −396 V/V
Gv =
vsig
which has been reduced by a factor of 3.5! All
this reduction in gain is a result of the reduction
in Rin .
7.91 From Fig. P7.91 we see that
Each of Q1 and Q2 is operating at an IC
approximately equal to 200 μA. Thus for both
devices,
gm =
re
0.2
= 8 mA/V
0.025
1
= 0.125 k
gm
rπ =
β
100
=
= 12.5 k
gm
8
ro =
VA
50
= 250 k
=
IC
0.2
IE2 = 10 mA
IE1 =
IE2
β2 + 1
re2 =
VT
25 mV
= 2.5 =
IE2
10 mA
re1 =
VT
25 mV
=
= 250 IE1
0.1 mA
10
= 0.1 mA
100
The Darlington follower circuit prepared for
small-signal analysis is shown in the figure.
(a) Rin2 = rπ 2 = 12.5 k
Rin = (β1 + 1)[re1 + (rπ 2 ro1 )]
Rsig 100 k
= 101[0.125 + (12.5 250)]
Q1
= 1.215 M
Rin
1.215
vb1
= 0.71 V/V
=
=
vsig
Rin + Rsig
1.215 + 0.5
rπ 2 ro1
ve1
=
= 0.99 V/V
vb1
(rπ 2 ro1 ) + re1
vo
= −gm2 ro2 = −8 × 250 = −2000 V/V
vb1
vo
= 0.71 × 0.99 × −2000 = −1405 V/V
Gv =
vsig
Q2
vsig
Rout
RL 1 k
Rin
Chapter 7–34
Rin = (β + 1)[re1 + (β2 + 1)(re2 + RL )]
(b) gm1 =
= 101[0.25 + (101)(0.0025 + 1)]
= 10.25 M
Rout = re2 +
re1 + Rsig /(β1 + 1)
β2 + 1
100 × 103
101
= 2.5 +
= 14.8 101
With RL removed,
vo
Gv o =
=1
vsig
250 +
vo
RL
= Gv o
vsig
RL + Rout
=1×
1
= 0.985
1 + 0.0148
gm2 =
IC2
1 mA
=
= 40 mA/V
VT
0.025
rπ 2 =
β
200
= 5 k
=
gm2
40
(c) Neglecting RG , we can write
vb2
=
vi
rπ2 6.8 k
(rπ2 6.8 k) +
1
gm1
= 0.65 V/V
vo
= −gm2 (3 1)
vb2
With RL connected,
Gv =
2ID1
2 × 0.1
= 0.632 mA/V
=
VOV
0.316
= −40 ×
3
= −30 V/V
4
vo
= 0.65 × −30 = −19.5 V/V
vi
(d)
7.92
RG
5 V
Avvi
ii
vi
RG 10 M
3 k
Figure 2
0.7 VGS
From Fig. 2 we can find ii as
0
VGS
Q1 0.1 mA
0.7 V
ii =
Q2
0
0.7
0.1
6.8
mA
6.8 k
=
vi − Av vi
RG
vi + 19.4 vi
RG
Thus,
Rin ≡
Figure 1
vi
10 M
RG
=
= 487 k
=
ii
20.5
20.5
Thus the overall voltage gain becomes
Rin
vo
=
× Av
vsig
Rin + Rsig
(a) From Fig. 1 we see that
ID1
But
ID1 =
0.1 mA/V
vo
487
× −19.5
=
vsig
487 + 500
1
W
2
μn Cox
VOV
2
L
= −9.6 V/V
(e) The suggested configuration, shown partially
in Fig. 3, will have
1
2
0.1 = × 2 × VOV
2
⇒ VOV = 0.316 V
10 M
10 M
vi
VGS = Vt + VOV = 1.316 V
vo
Thus,
VC2 = VG2 = 0.7 + VGS = 2.016 V
IC2 =
5 − 2.016
VCC − VC2
=
3 k
3
1 mA
Figure 3
Chapter 7–35
no effect on the dc bias of each transistor.
However, it will have a profound effect on Rin , as
Rin now is 10 M, and
10
vo
=
× −19.5 = −18.6 V/V
vsig
10 + 0.5
This is nearly double the value we had before!
From the figure we can determine the overall
voltage gain as
Gv =
=
vo
Total resistance in the drain
=
vsig
Total resistance in the sources
1
RL
= gm RL
1
1
2
+
gm1
gm2
where
7.93
gm = gm1 = gm2 = 5 mA/V
Gv =
1
× 5 × 10 = 25 V/V
2
RL 10 k
7.95 Refer to Fig. P7.95. All transistors are
operating at IE = 0.5 mA. Thus,
Rsig 10 k
Q1
Q2
re =
re1
v
sig
(a) Refer to Fig. P7.95(a).
re2
α × Total resistance in collector
vo
=−
vsig
Total resistance in emitter
=
The figure shows the circuit prepared for signal
analysis.
Gv =
=
vo
α × Total resistance in collectors
=
vsig
Total resistance in emitters
where
1
Gv =
For
α=
100
β
=
= 0.99
β +1
101
Gv =
Rsig
+ re1 + re2
β +1
re1 = re2 =
−α × 10 k
10 k
+ re
β +1
−0.99 × 10
= −66.4 V/V
10
+ 0.05
101
(b) Refer to Fig. P7.95(b).
vsig
vsig
=
ib1 =
10 + (β + 1)re1
10 + 101 × 0.05
αRL
α
VT
25 mV
=
= 50 IE
0.5 mA
VT
25 mV
=
= 50 IE
0.5 mA
10
= 50.2 V/V
10
+ 0.05 + 0.05
101
ic1 = βib1 =
100 vsig
10 + 101 × 0.05
ic2 = αic1 =
0.99 × 100 vsig
10 + 101 × 0.05
vo = −ic2 × 10
Gv ≡
7.94
vo
10 × 0.99 × 100
=−
= −65.8 V/V
vsig
10 + 101 × 0.05
(c) Refer to Fig. P7.95(c).
RL
=
Rsig
Q1
vs Gv =
1
gm1
Q2
1
gm2
vo
α × Total resistance in collector
=
vsig
Total resistance in emitters
0.99 × 10
0.99 × 10
=
10
10
+ 2 re
+ 2 × 0.05
β +1
101
= 49.7 V/V
(d) Refer to Fig. P7.95(d).
Rin (at the base of Q1 ) = (β1 + 1)[re1 + rπ2 ]
Chapter 7–36
(f)
where
re1 = 50 vo
ic2
rπ 2 = (β + 1)re2 = 101 × 50 = 5.05 k
Thus,
Q2
Rin = 101(0.05 + 5.05) = 515 k
Rin
515
vb1
= 0.98 V/V
=
=
vsig
Rin + Rsig
515 + 10
rπ 2
5.05
vb2
= 0.98 V/V
=
=
vb1
rπ 2 + re1
5.05 + 0.05
vo
= −gm2 × 10 k
vb2
Q1
vsig = −20 × 10 = −200 V/V
vo
= 0.98 × 0.98 × −200 = −194 V/V
Gv =
vsig
ie1 = ie2 =
(e) Refer to Fig. P7.95(e).
vsig
vsig
=
ib1 =
10 + (β + 1)re1
10 + 101 × 0.05
=
ic1 = β1 ib1 =
100 vsig
10 + 101 × 0.05
ie2 = ic1
ic2 = αie2 = αic1 =
vo = ic2 × 10 =
0.99 × 100 vsig
10 + 101 × 0.05
0.99 × 100 × 10 vsig
10 + 101 × 0.05
vsig
10
+ re1 + re2
β1 + 1
vsig
10
+ 0.05 + 0.05
101
ic2 = αie2 =
0.99 vsig
10
+ 0.05 + 0.05
101
vo = ic2 × 10 k =
0.99 × 10 vsig
10
+ 0.05 + 0.05
101
Thus,
Thus,
Gv =
ie1 ie2
10 k
vo
0.99 × 100 × 10
= 65.8 V/V
=
vsig
10 + 101 × 0.05
Gv =
vo
= 49.7 V/V
vsig
10 k
Exercise 8–1
VDD
Ex: 8.1 Referring to Fig. 8.3,
If RD is doubled to 5 k,
RD 5 k
I
VD1 = VD2 = VDD − RD
2
0.4 mA
= 1.5 −
(5 k) = 0.5 V
2
VCMmax = Vt + VD = 0.5 + 0.5 = +1.0 V
RD 5 k
ID
ID
I 0.8 mA
Since the currents ID1 , and ID2 are still 0.2 mA
each,
VSS
VGS = 0.82 V
So, VCMmin = VSS + VCS + VGS
= −1.5 V + 0.4 V + 0.82 V = −0.28 V
Thus,
VOV
So, the common-mode range is
−0.28 V to +1.0 V
=
2ID
=
W
kn
L
2 (0.4 mA)
0.2 mA/V2 (100)
= 0.2 V
Ex: 8.2 (a) The value of v id√that causes Q1 to
conduct the entire current is 2 VOV
√
→ 2 × 0.316 = 0.45 V
gm =
0.4 mA × 2
ID
=
= 4 mA/V
VOV /2
0.2 V
ro =
VA
20 V
=
= 50 k
ID
0.4 mA
then, VD1 = VDD − I × RD
Ad = gm (RD ro )
= 1.5 − 0.4 × 2.5 = 0.5 V
Ad = (4 mA/V) (5 k 50 k) = 18.2 V/V
VD2 = VDD = +1.5 V
(b) For Q2 to conduct the entire current:
√
v id = − 2 VOV = −0.45 V
then,
VD1 = VDD = +1.5 V
VD2 = 1.5 − 0.4 × 2.5 = 0.5 V
(c) Thus the differential output range is
VD2 − VD1 :from 1.5 − 0.5 = + 1 V
to 0.5 − 1.5 = −1 V
Ex: 8.3 Refer to answer table for Exercise 8.3
where values were obtained in the following way:
I
W
=
VOV = I /k n W/L ⇒
2
L
k n VOV
2(I /2)
I
=
VOV
VOV
√
v id /2 2
= 0.1 → v id = 2 VOV 0.1
VOV
gm =
Ex: 8.5 With I = 200 μA, for all transistors,
200 μA
I
=
= 100 μA
2
2
L = 2(0.18 μm) = 0.36 μm
ID =
ro1 = ro2 = ro3 = ro4 =
(10 V/ μm) (0.36 μm)
= 36 k
0.1 mA
1
W
2
,
VOV
Since ID1 = ID2 = μn Cox
2
L
W
2ID
W
=
=
2
L 1
L 2
μn Cox VOV
=
2(100 μA)
= 12.5
400 μA/V2 (0.2 V)2
W
W
2ID
=
=
L 3
L 4
μp Cox |VOV |2
2(100 μA)
= 50
100 μA/V2 (0.2)2
gm =
I
0.8 mA
=
= 0.4 mA
2
2
1
W
ID = k n
(VOV )2
2
L
Ex: 8.4 ID =
VA L
ID
ID
(100 μA) (2)
=
= 1 mA/V,
VOV /2
0.2 V
so
Ad = gm1 (ro1 ro3 ) = 1(mA/V) (36 k 36 k)
= 18 V/V
Exercise 8–2
Ex: 8.6 L = 2 (0.18 μm) = 0.36 μm
All ro =
VA
VCC
Ex: 8.8
2.5 V
·L
ID
RC
The drain current for all transistors is
200 μA
I
= 100 μA
ID = =
2
2
(10 V/ μm) (0.36 μm)
= 36 k
ro =
0.1 mA
Refering to Fig. 8.13(a),
1
W
2
for all NMOS
VOV
Since ID = μn Cox
2
L
transistors,
W
W
W
W
=
=
=
L 1
L 2
L 3
L 4
2ID
2(100 μA)
=
= 12.5
2
μn Cox VOV
400 μA/V2 (0.2 V)2
W
W
W
W
=
=
=
L 5
L 6
L 7
L 8
=
=
2ID
2(100 μA)
=
= 50
2
μp Cox VOV
100 μA/V2 (0.2 V)2
For all transistors,
gm =
|ID |
(0.1 mA) (2)
= 1 mA/V
=
|VOV | /2
(0.2 V)
From Fig. 8.13(b),
Ron = (gm3 ro3 ) ro1 = (1 × 36) × 36
= 1.296 M
Rop = (gm5 ro5 )ro7 = (1 × 36) × 36
= 1.296 M
Ad = gm1 Ron Rop
= (1 mA/V) (1.296 M 1.296 M)
= 648 V/V
IC1
IC2
RC 5 k
I 0.4 mA
2.5 V
VEE
IC1 = IC2 IE1 = IE2 =
I
0.4 mA
=
2
2
= 0.2 mA
VCM max VC + 0.4 V
= VCC − IC RC + 0.4 V
= 2.5 − 0.2 mA (5 k) + 0.4 V = +1.9 V
VCM min = −VEE + VCS + VBE
VCM min = −2.5 V + 0.3 V + 0.7 V = −1.5 V
Input common-mode range is −1.5 V to +1.9 V
Ex: 8.9 Substituting iE1 + iE2 = I in Eqn. (8.45)
yields
iE1 =
I
1 + e(v B2 −v B1 )/VT
I
1 + e(v B2 −v B1 )/VT
1
v B1 − v B2 = −VT ln
−1
0.99
0.99 I =
= −25ln (1/99)
Ex: 8.7
= 25ln (99) = 115 mV
Ex: 8.10 (a) The DC current in each transistor is
0.5 mA. Thus VBE for each will be
0.5
VBE = 0.7 + 0.025ln
1
= 0.683 V
⇒ v E = 5 − 0.683 = +4.317 V
(b) gm =
IC
0.5
mA
=
= 20
VT
0.025
V
(c) iC1 = 0.5 + gm1 v BE1
= 0.5 + 20 × 0.005 sin (2π × 1000t)
= 0.5 + 0.1 sin(2π × 1000t), mA
Exercise 8–3
iC2 = 0.5 − 0.1 sin(2π × 1000t), mA
(d) v C1 = (VCC − IC RC ) − 0.1
×RC sin(2π × 1000t)
= (15 − 0.5 × 10) − 0.1 × 10 sin(2π × 1000t)
= 10 − 1 sin(2π × 1000t) , V
v C2 = 10 + 1 sin(2π × 1000t) , V
(e) v C2 − v C1 = 2 · sin(2π × 1000t) , V
(f) Voltage gain ≡
v C2 − v C1
v B1 − v B2
2 V peak
= 200 V/V
=
0.01 V peak
Ex: 8.13 If the output of a MOS differential
amplifier is taken single-endedly, then
1
gm RD
2
(that is, half the gain obtained with the output
taken differentially), and from Fig. 8.25(d) we
have
RD
| Acm | 2RSS
| Ad | =
Thus,
CMRR ≡
| Ad |
= gm RSS
| Acm |
Q.E.D.
Ex: 8.14
Ex: 8.11 The transconductance for each
transistor is
gm = 2μn Cox (W/L)ID
ID =
Thus,
gm =
VCC
0.8 mA
I
=
= 0.4 mA
2
2
VB3
Q3
Q4
√
2 × 0.2 × 100 × 0.4 = 4 mA/V
vo1
vi1
The differential gain for matched
v O2 − v O1
= gm RD
RD values is Ad =
v id
= 86 dB
Ex: 8.12 From Exercise 8.11,
W/L = 100, μn Cox = 0.2 mA/V2 ,
0.8 mA
I
=
= 0.4 mA
2
2
W
ID
gm = 2μn Cox
L
ID =
=
2 0.2 mA/V2 (100) (0.4 mA)
gm = 4 mA/V
Using Eq. (8.88) and the fact that RSS = 25 k,
we obtain
2(4 mA/V) (25 k)
(2 gm RSS )
=
CMRR = gm
0.01
gm
= 20, 000
CMRR (dB) = 20 log10 (20, 000) = 86 dB
vo2
Q2
Q1
vi2
I 200 A
If we ignore the 1% here, then we obtain
Ad = gm RD = (4 mA/V) (5 k) = 20 V/V
RD
RD
| Acm | =
2RSS
RD
5
(0.01) = 0.001 V/V
=
2 × 25
20
| Ad |
= 20 log
CMRR (dB) = 20 log
| ACM |
0.001
VB4
Q5
VB5
VEE
I = 200 μA
Since β
1,
I
200 μA
=
= 100 μA
2
2
IC
100 μA
= 4 mA/V
= gm =
=
VT
25 mV
IC1 ≈ IC2 ≈
gm1 = gm2
RC1 = RC2 = RC = ro =
=
|VA |
IC
10 V
= 100 k
100 μA
ro1 = ro2 =
VA
10
=
= 100 k
I /2
0.1
re1 = re2 = re =
VT
25 mV
=
= 0.25 k
IE
0.1 mA
RC ro
100 k 100 k
=
re
0.25 k
= 200 V/V
| Ad | =
Rid = 2rπ ,
rπ =
β
100
= 25 k
=
gm
4 mA/V
Rid = 2(25 k) = 50 k
Exercise 8–4
REE =
10 V
VA
=
= 50 k
I
200 μA
=
=
RC RC
2REE RC
Ex: 8.16 From Eq. (8.120), we get
IS 2
RC 2
VOS = VT
+
RC
IS
100
× 0.01 = 0.01 V/V
2 × 50
CMRR (dB) = 20 log10
= 86 dB
Ad
200
= 20 log10
Acm
0.01
Using Eq. (8.96), we obtain
RC
βro
·
RC + 2REE
1+
ro
1+
Ricm = βREE
2
= 3.46 mV
If the total load resistance is assumed to be
mismatched by 1%, then we have
| Acm | =
3 × 2 × 10−3
= 25 (0.02)2 + (0.1)2
= 2.55 mV
100 ∼
100
=
IB =
= 0.5 μA
2(β + 1)
2 × 101
β
IOS = IB
β
= 0.5 × 0.1 μA = 50 nA
100
100
× 100
= 100 × 50 ×
100 + 2 × 50
1+
100
Ricm 1.68 M
1+
1
I = 0.4 mA
2
1
W
V2
ID = μn Cox
2
L n OV
Ex: 8.17 ID =
1
2
× 0.2 × 100 × VOV
2
⇒ VOV = 0.2 V
0.4 =
Ex: 8.15 From Exercise 8.4:
VOV = 0.2 V
Using Eq. (8.101) we obtain VOS due to RD /RD
as:
VOV
RD
·
VOS =
2
RD
0.2
× 0.02 = 0.002 V i.e 2 mV
2
(W/L)
,
To obtain VOS due to
W/L
=
gm1,2 =
2ID
2 × 0.4
= 4 mA/V
=
VOV
0.2
Gm = gm1,2 = 4 mA/V
ro2 =
VAn
20
= 50 k
=
ID
0.4
ro4 =
|VAp |
20
= 50 k
=
ID
0.4
Ro = ro2 ro4 = 50 50 = 25 k
Ad = Gm Ro = 4 × 25 = 100 V/V
use Eq. (8.106),
VOV
(W/L)
VOS =
2
W/L
0.2
× 0.02 = 0.002
⇒ VOS =
2
= 16 mA/V
⇒ 2 mV
ro2 = ro4 =
The offset voltage arising from Vt is obtained
from Eq. (8.109):
Ro = ro2 ro4 = 250 250 = 125 k
Ex: 8.18 Gm = gm1,2 VOS = Vt = 2 mV
I /2
0.4 mA
=
VT
0.025 V
100
VA
VA
=
= 250 k
=
IC
I /2
0.4
Ad = Gm Ro = 16 × 125 = 2000 V/V
β
160
=2×
= 20 k
gm1,2
16
Finally, from Eq. (8.110) the total input offset is
Rid = 2rπ = 2 ×
VOS =
1/2
VOV RD 2
VOV (W/L) 2
2
+
+ (Vt )
2 RD
2
W/L
Ex: 8.19
I /2
0.5 mA
= 20 mA/V
=
Gm = gm1 = gm2 VT
0.025 V
=
2 × 10−3
2
+ 2 × 10−3
2
+ 2 × 10−3
2
ro4 =
100 V
VA
=
= 200 k
I /2
0.5 mA
Exercise 8–5
Ro4 β4 ro4 = 50 × 200 = 10,000 k = 10 M
Ro5 =
1
β5 ro5
2
(a) Using Eq. (8.170), we obtain
I6 =
where
ro5 =
Ex: 8.22 Refer to Fig. (8.40).
VA
= 200 k
I /2
(W/L)6
(I /2)
(W/L)4
⇒ 100 =
(W/L)6
× 50
100
Thus,
thus, (W/L)6 = 200
1
Ro5 = × 100 × 200 = 10 M
2
Using Eq. (8.171), we get
Ro = Ro4 Ro5 = 10 10 = 5 M
I7 =
Ad = Gm Ro
= 20 mA/V × 5000 k = 105 V/V or 100 dB
(W/L)7
I
(W/L)5
⇒ 100 =
(W/L)7
× 100
200
thus, (W/L)7 = 200
Ex: 8.20 From Exercise 8.17, we get
ID = 0.4 mA
VOV = 0.2 V gm1,2 = 4 mA/V
Gm = 4 mA/V Ad = 100 V/V
Now,
RSS = 25 k
gm3 =
=
1
W
I
= μp Cox
V2
2
2
L 1 OV1
50
⇒ VOV 1 = = 0.129 V
1
× 30 × 200
2
Similarly for Q2 , VOV 2 = 0.129 V
2μp Cox
W
L
For Q6 ,
ID
p
√
2 × 0.1 × 200 × 0.4 = 4 mA/V
1
1
= 0.005 V/V
=
| Acm | =
2gm3 RSS
2 × 4 × 25
CMRR =
(b) For Q1 ,
100 =
⇒ VOV 6 = 0.105 V
(c) gm =
100
| Ad |
=
| Acm |
0.005
= 20,000 or 20 log 20,000 = 86 dB
Ex: 8.21 From Exercise 8.18, we get
1
2
× 90 × 200VOV
6
2
2ID
VOV
ID
Q1
Q2
Q6
VOV
50 μA 0.129 V 0.775 mA/V
50 μA 0.129 V 0.775 mA/V
100 μA 0.105 V 1.90 mA/V
I = 0.8 mA, IC 0.4 mA, VA = 100 V
(d) ro2 = 10/0.05 = 200 k
gm1,2 = 16 mA/V, Gm = 16 mA/V
ro4 = 10/0.05 = 200 k
ro2 = ro4 = 250 k, Ad = 2000 V/V
ro6 = 10/0.1 = 100 k
Now,
ro7 = 10/0.1 = 100 k
REE =
100 V
= 125 k
0.8 mA
Using Eq. (8.165),
| Acm | =
ro4
250
=
= 0.0125 V/V
β3 REE
160 × 125
CMRR =
2000
| Ad |
=
= 160, 000 V/V
| Acm |
0.0125
20 log CMRR = 104 dB
gm
(e) Eq. (8.168):
A1 = −gm1 (ro2 ro4 )
= −0.775 (200 200) = −77.5
Eq. (8.169):
A2 = −gm6 (ro6 ro7 )
= −95 V/V
V
V
Exercise 8–6
Overall voltage gain is
A1 × A2 = −77.5 × − 95 = 7363 V/V
Ex: 8.23 Rid = 20.2 k
Av o = 8513 V/V
Ro = 152 With RS = 10 k and RL = 1 k,
1
20.2
× 8513 ×
Gv =
20.2 + 10
(1 + 0.152)
= 4943 V/V
Ex: 8.24
ie8
= β 8 + 1 = 101
ib8
ib7
R3
3
= 0.0126
=
=
ic5
R3 + Ri3
3 + 234.8
ic5
= β 5 = 100
ib5
R1 + R2
40
ib5
=
= 0.888
=
ic2
R1 + R2 + Ri2
40 + 5.05
ic2
= β 2 = 100
i1
Thus the overall current gain is
ie8
= 101 × 0.0492 × 100 × 0.0126 × 100
i1
× 0.888 × 100
= 55,599 A/A
and the overall voltage gain is
R5
15.7
ib8
= 0.0492
=
=
ic7
R5 + Ri4
15.7 + 303.5
R6 ie8
vo
=
·
v id
Ri1 i1
ic7
= β 7 = 100
ib7
=
3
× 55599 = 8257 V/V
20.2
Chapter 8–1
8.1 Refer to Fig. 8.2.
1
W
I
= μn Cox
V2
(a)
2
2
L 1,2 OV
0.08 =
⇒ VOV
1
2
× 0.4 × 10 × VOV
2
= 0.2 V
ID1,2 =
1 W
kp
|VOV |2
2
L
1
× 4 × |VOV |2
2
⇒ |VOV | = 0.35 V
0.25 =
VSG = |Vtp | + |VOV |
VGS = Vtn + VOV = 0.4 + 0.2 = 0.6 V
= 0.8 + 0.35 = 1.15 V
(b) VCM = 0
VS = 0 + VSG = +1.15 V
VS = 0 − VGS = −0.6 V
VD1 = VD2 = −VSS + ID RD
I
= 0.08 mA
2
= VDD − ID1,2 RD
ID1 = ID2 =
VD1 = VD2
= 1 − 0.08 × 5 = +0.6 V
(c) VCM = +0.4 V
VS = 0.4 − VGS = 0.4 − 0.6 = −0.2 V
I
= 0.08 mA
2
= VDD − ID1,2 RD
ID1 = ID2 =
VD1 = VD2
= 1 − 0.08 × 5 = +0.6 V
Since VCM = 0.4 V and VD = 0.6 V,
VGD = −0.2 V, which is less than Vtn (0.4 V),
indicating that our implicit assumption of
saturation-mode operation is justified.
(d) VCM = −0.1 V
VS = −0.1 − VGS = −0.1 − 0.6 = −0.7 V
I
= 0.08 mA
2
= VDD − ID1,2 RD
ID1 = ID2 =
VD1 = VD2
= 1 − 0.08 × 5 = +0.6 V
(e) The highest value of VCM for which Q1 and
Q2 remain in saturation is
= −2.5 + 0.25 × 4
= −1.5 V
Since for each of Q1 and Q2 ,
VSD = 1.15 − (−1.5)
= 2.65 V
which is greater than |VOV |, Q1 and Q2 are
operating in saturation as implicitly assumed.
(b) The highest value of VCM is limited by the
need to keep a minimum of 0.4 V across the
current source, thus
VCM max = +2.5 − 0.4 − VSG
= +2.5 − 0.4 − 1.15 = +0.95 V
The lowest value of VCM is limited by the need to
keep Q1 and Q2 in saturation, thus
VCM min = VD1,2 − |Vtp |
= −1.5 − 0.8 = −2.3 V
Thus,
−2.3 V ≤ VICM ≤ +0.95 V
8.3
VDD 1 V
VCM max = VD1,2 + Vtn
= 0.6 + 0.4 = 1.0 V
5 k
vD1
G1
VSmin = −VSS + VCS = −1 + 0.2 = −0.8 V
VCM min = VSmin + VGS
RD
RD
(f) To maintain the current-source operating
properly, we need to keep a minimum voltage of
0.2 V across it, thus
vid = −0.8 + 0.6
vGS1
iD1 iD2
Q1
Q2
vS
= −0.2 V
ID1 = ID2
1
= × 0.5 = 0.25 mA
2
G2
vGS2
I 0.16 mA
VSS 1 V
8.2 Refer to Fig. P8.2.
(a) For v G1 = v G2 = 0 V,
5 k
vD2
(a) For iD1 = iD2 = 0.08 mA,
v G1 = v G2
Chapter 8–2
Thus,
0.16 =
v id = 0 V
iD1 = iD2
0.08 =
1
W
2
= μn Cox
VOV
2
L
1
2
× 0.4 × 10 × VOV
2
⇒ VOV = 0.2 V
v GS1 = v GS2 = 0.2 + 0.4 = 0.6 V
v S = −0.6 V
1
× 0.4 × 10 (v id + 0.4 − 0.4)2
2
⇒ v id = 0.283 V
√
which is 2VOV , as derived in the text.
v GS1 = 0.283 − (−0.4) = 0.683 V
v D1 = VDD − iD1 RD
= 1 − 0.16 × 5 = +0.2 V
Note that since v G1 = v id = 0.283 V, Q1 is still
operating in saturation, as implicitly assumed.
v D1 = v D2 = VDD − iD1,2 RD
v D2 = VDD − iD2 RD
= 1 − 0.08 × 5 = 0.6 V
=1−0×5=1V
v D2 − v D1 = 0 V
(b) For iD1 = 0.12 mA and iD2 = 0.04 mA,
1
W
(v GS2 − Vtn )2
iD2 = μn Cox
2
L
0.04 =
1
× 0.4 × 10 × (v GS2 − 0.4)2
2
⇒ v GS2 = 0.541 V
Thus,
v S = −0.541 V
1
W
(v GS1 − Vtn )2
iD1 = μn Cox
2
L
0.12 =
1
× 0.4 × 10 (v id − v S − Vtn )2
2
1
= × 0.4 × 10 (v id + 0.541 − 0.4)2
2
v D2 − v D1 = 1 − 0.2 = 0.8 V
(d) iD1 = 0.04 mA and iD2 = 0.12 mA. Since this
split of the current I is the complement of that in
case (b) above, the value of v id must be the
negative of that found in (b). Thus,
v id = −0.104 V
v GS1 = 0.541 V
v S = −0.645 V
v GS2 = 0.645 V
v D1 = VDD − iD1 RD
= 1 − 0.04 × 5 = 0.8 V
v D2 = 1 − 0.12 × 5 = 0.4 V
v D2 − v D1 = −0.4 V
⇒ v id = 0.104 V
(e) iD1 = 0 (Q1 just cuts off) and iD2 = 0.16 mA.
This case is the complement of that in (c) above,
thus
v GS1 = 0.104 − (−0.541) = 0.645 V
v GS1 = Vtn = 0.4 V
v D1 = VDD − iD1 RD
v GS2 = 0.683 V
= 1 − 0.12 × 5 = 0.4 V
v S = −0.683 V
v D2 = VDD − iD2 RD
= 1 − 0.04 × 5 = 0.8 V
v id = −0.683 + 0.4 = −0.283 V
√
which is − 2 VOV , as derived in the text.
v D2 − v D1 = 0.8 − 0.4 = 0.4 V
v D1 = VDD − iD1 RD = 1 − 0 × 5 = 1 V
(c) iD1 = 0.16 mA and iD2 = 0 with Q2 just
cutting off, thus
v D2 = VDD − iD2 RD = 1 − 0.16 × 5 = 0.2 V
v GS2 = Vtn = 0.4 V
⇒ v S2 = −0.4 V
iD1 =
1
× 0.4 × 10 (v GS1 − Vtn )2
2
v D2 − v D1 = −0.8 V
Summary
A summary of the results is shown in the
following table on the next page.
Chapter 8–3
Case i D1 (mA) i D2 (mA)
a
0.08
0.08
b
0.12
0.04
c
0.16
0
d
0.04
0.12
e
0
0.16
vid (V)
vS (V)
0
−0.6
vD1 (V) vD2 (V) vD2 − vD1 (V)
+0.6
+0.6
0
+0.104 −0.541
+0.4
+0.8
+0.4
+0.283
+0.2
+1.0
+0.8
−0.104 −0.645
+0.8
+0.4
−0.4
−0.283 −0.683
+1.0
+0.2
−0.8
−0.4
8.4
To obtain the complementary split in current, that
is, iD1 = 0.07 mA and iD2 = 0.09 mA,
VDD 1 V
v id = −0.025 V
RD
RD
5 k
vD1
G1
vid vGS1
5 k
vD2
iD1 iD2
Q2
Q1
vS
G2
vGS2
I 0.16 mA
VSS 1 V
8.5 Refer to Fig. P8.2.
To determine VOV ,
1
× 4 × |VOV |2
2
⇒ |VOV | = 0.354 V
0.25 =
With v G2 = 0 and v G1 = v id , to steer the current
from one side of the differential pair to the other,
v id must be the ends of the range
√
√
− 2 |VOV | ≤ v id ≤ 2 |VOV |
that is,
−0.5 V ≤ v id ≤ +0.5 V
For iD1 = 0.09 mA and iD2 = 0.07 mA,
1
W
(v GS2 − Vtn )2
iD2 = μn Cox
2
L
1
0.07 = × 0.4 × 10(v GS2 − 0.4)2
2
⇒ v GS2 = 0.587 V
and
v S = −0.587 V
1
W
iD1 = μn Cox
(v GS1 − Vtn )2
2
L
1
0.09 = × 0.4 × 10 (v GS1 − 0.4)2
2
⇒ v GS1 = 0.612 V
v id = v S + v GS1 = −0.587 + 0.612
At v id = −0.5 V, Q2 just cuts off, thus
v S = |Vtp | = 0.8 V
and
v SG1 = 0.8 − (−0.5) = 1.3 V
At this value of v SG1 ,
1
× 4 × (1.3 − 0.8)2
2
= 0.5 mA
iD1 =
which is the entire bias current.
v D1 = −2.5 + 0.5 × 4 = −0.5 V
Observe that since v G1 = v D1 , Q1 is still
operating in saturation, as implicitly assumed.
= 0.025 V
v D2 = −2.5 V
v D2 = VDD − iD2 RD
At v id = +0.5 V, Q1 just cuts off, thus
v SG1 = |Vtp | = 0.8 V and
= 1 − 0.07 × 5 = 0.65 V
v D1 = 1 − 0.09 × 5 = 0.55 V
v D2 − v D1 = 0.65 − 0.55 = 0.10 V
0.10
v D2 − v D1
=
= 4 V/V
Voltage gain =
v id
0.025
v S = +0.5 + 0.8 = +1.3 V
and thus
v SG2 = 1.3 V
which results in
Chapter 8–4
1
× 4 (1.3 − 0.8)2
2
= 0.5 mA
The upper limit on VCM is determined by the need
to keep Q1 and Q2 in saturation, thus
which is the entire bias current. Here,
= 0.1 + 0.4 = 0.5 V
iD1 =
v D2 = −2.5 + 0.5 × 4 = −0.5 V
which verifies that Q2 is operating in saturation,
as implicitly assumed.
8.6 Refer to the circuit in Fig. P8.6.
For v G1 = v G2 = 0 V,
ID1 = ID2 =
0.4
= 0.2 mA
2
To obtain
VD1 = VD2 = +0.1 V
VDD − ID1,2 RD = 0.1
0.9 − 0.2 RD = 0.1
Thus,
−0.2 V ≤ VICM ≤ +0.5 V
8.7 Refer to Eq. (8.23). For
v id /2 2
≤k
VOV
√
v id /2
≤ k
⇒
VOV
v id /2 2
v id /2
1−
I = I
VOV
VOV
√ √
Imax = I k 1 − k
(1)
Thus,
⇒ RD = 4 k
For Q1 and Q2 ,
VICM max = VD1,2 + Vtn
1
W
μn Cox
V2
2
L 1,2 OV
W
1
0.2 = × 0.4
× 0.152
2
L 1,2
W
⇒
= 44.4
L 1,2
ID1,2 =
√
Imax
= 2 k(1 − k)
I /2
Q.E.D.
(2)
and the corresponding value of v id is found from
Eq. (2) as
√
v id max = 2 kVOV
Q.E.D.
(3)
Equations (2) and (3) can be used to evaluate
Imax
v id max
and
for various values of k:
I /2
VOV
For Q3 ,
W
1
× 0.4 ×
× 0.152
2
L 3
W
⇒
= 88.8
L 3
0.4 =
k
v id max
VOV
Imax
I /2
0.01
0.1
0.2
0.2
0.632
0.894
0.2
0.6
0.8
Since Q3 and Q4 form a current mirror with
ID3 = 4ID4 ,
1 W
W
=
= 22.2
L 4
4 L 3
8.8 Switching occurs at
√
v id = 2VOV
VGS4 = VGS3 = Vtn + VOV = 0.4 + 0.15
Thus,
= 0.55 V
0.9 − (−0.9) − 0.55
R=
0.1
= 12.5 k
The lower limit on VCM is determined by the need
to keep Q3 operating in saturation. For this to
happen, the minimum value of VDS3 is
VOV = 0.15 V. Thus,
VICM min = −VSS + VOV 3 + VGS1,2
= −0.9 + 0.15 + 0.4 + 0.15
= −0.2 V
0.3 =
√
2VOV
⇒ VOV = 0.212 V
Now, to obtain full current switching at
v id = 0.5 V, VOV must be increased to
VOV = 0.212 ×
0.5
= 0.353 V
0.3
2
the current ID and
Since ID is proportional to VOV
hence the bias current I must be increased by the
ratio (0.353/0.212)2 , then I must be
0.353 2
I = 200 ×
= 554.5 μA
0.212
Chapter 8–5
8.9 Refer to Fig. 8.5.
gm =
1=
0.25 =
2(I /2)
I
=
VOV
VOV
⇒
1
1
× 0.25 = × 0.4 ×
2
2
8.12 Since the quiescent power dissipation is
P = (VDD + VSS ) × I
W
L
0.252
W
= 10
L
8.10 0.1 =
1
2
× 0.2 × 32VOV
2
⇒ VOV = 0.18 V
gm =
2 × (0.2/2)
= 1.11 mA/V
0.18
VA
10
= 100 k
=
ro =
ID
0.1
Ad = gm (RD ro )
= 1.11 × (10 100) = 10.1 V/V
8.11 For v id = 0.1 V
W
= 40
L
I
0.25
⇒ I = 0.25 mA
1
I
W
2
= μn Cox
VOV
2
2
L
⇒
W
1
× 0.2 ×
× 0.252
2
L
v id /2
VOV
2
= 0.04
v id /2
= 0.2
VOV
0.1/2
= 0.2
VOV
then the maximum allowable I is
1 mW
= 0.5 mA
I=
2V
We shall utilize this value. The value of VOV can
be found from
√
2 VOV = 0.25 V
0.25
⇒ VOV = √ = 0.18 V
2
The realized value of gm will be
gm =
2 × (I /2)
VOV
0.5
= 2.8 mA/V
0.18
To obtain a differential gain Ad of 10 V/V,
=
Ad = gm RD
10 = 2.8 × RD
⇒ RD = 3.6 k
Finally, the required value of W/L can be
determined from
I
W 2
1
ID = = μn Cox VOV
2
2
L
1
W
0.25 = × 0.4 ×
× 0.182
2
L
W
⇒
= 38.6
L
⇒ VOV = 0.25 V
gm =
2 × (I /2)
VOV
8.13 To limit the power dissipation to 1 mW,
P = (VDD + VSS )I
I
2=
0.25
Thus, the maximum value we can use for I is
⇒ I = 0.5 mA
I=
Ad =
1V
= 10
0.1 V
gm RD = 10
10
= 5 k
2
I
1
W
2
= μn Cox
VOV
2
2
L
⇒ RD =
1 mW
= 0.5 mA
2V
Using this value, we obtain
I
RD
2
0.2 = 1 − 0.25 × RD
VD = VDD −
⇒ RD = 3.2 k
Ad = gm RD
10 = gm × 3.2
Chapter 8–6
gm =
10
= 3.125 mA/V
3.2
8.15 Since both circuits use the same supply
voltages and dissipate equal powers, then their
currents must be equal, that is,
2 × (I /2)
I
=
VOV
VOV
ID = I
But
gm =
3.125 =
0.5
VOV
⇒ VOV = 0.16 V
To obtain W/L, we use
1
W
2
VOV
ID = μn Cox
2
L
W
1
× 0.162
0.25 = × 0.4 ×
2
L
W
⇒
= 48.8 50
L
where ID is the bias current of the CS amplifier
and I is the bias current of the differential pair.
The gain of the CS amplifier is
| A| = gm RD
where
gm =
Thus,
2μn Cox
| A| =
W
L
2μn Cox
ID
CS
W
L
ID RD
(1)
CS
The gain of the differential amplifier is
8.14 (a) Ad = gm RD
Ad = gm RD
20 = gm × 47
where
20
= 0.426 mA/V
⇒ gm =
47
2ID
2(I /2)
I
=
=
(b) gm =
VOV
VOV
VOV
I
0.426 =
0.2
⇒ I = 0.085 mA = 85 μA
(c) Across each RD the dc voltage is
0.085
I
RD =
× 47 = 2 V
2
2
(d) The peak sine-wave signal across each gate
source is 5 mV, thus at each drain the peak sine
wave is
Ad × 5 = 20 × 5 = 100 mV = 0.1 V
(e) The minimum voltage at each drain will be
v Dmin = VDD − RD ID − Vpeak
= VDD − 2 − 0.1
gm =
Thus,
2μn Cox
Ad =
2μn Cox
I
2
diff
I
RD
2
diff
(2)
If all transistors have the same channel length,
each of the differential pair transistors must be
twice as wide as the transistor in the CS amplifier.
8.16 For a CS amplifier biased at a current ID and
utilizing a drain resistance RD , the voltage gain is
|A| = gm RD
v Dmin ≥ v Gmax − Vtn
where
where
gm =
v Gmax = VCM + Vpeak (input)
Thus,
Thus,
W
L
Equating the gains in Eqs. (1) and (2) and
substituting ID = I gives
1
W
W
=
×
L CS
L diff 2
W
W
=2
⇒
L diff
L CS
For the transistor to remain in saturation
= 0.5 + 0.005 = 0.505 V
W
L
|A| =
2μn Cox
2μn Cox
W
ID
L
W√
ID RD
L
(1)
VDD ≥ 2.105 V
For a differential pair biased with a current I and
utilizing drain resistances RD , the differential
gain is
Thus, the lowest value of VDD is 2.21 V.
Ad = gm RD
VDD − 2.1 ≥ 0.505 − 0.5
Chapter 8–7
where
W I
2μn Cox
L 2
gm =
Thus
=
Ad =
2μn Cox
W √
I /2 RD
L
(2)
Equating the gains from Eqs. (1) and (2), we get
I = 2ID
That is, the differential pair must be biased at a
current twice that of the CS amplifier. Since both
circuits use equal power supplies, the power
dissipation of the differential pair will be twice
that of the CS amplifier.
μn (W/L)1,2
μp (W/L)3,4
(c) μn = 4μp and all channel lengths are equal,
W1,2
Ad = 2
W3,4
For Ad = 10,
W1,2
10 = 2
W3,4
⇒
W1,2
= 25
W3,4
8.18
8.17
Q3
RD
vod / 2
(vod / 2)
vid
2
vid
2
Q1
Rs / 2
(a) The figure shows the differential half-circuit.
Recalling that the incremental (small-signal)
resistance
of a diode-connected transistor is given
1
by
ro , the equivalent load resistance of
gm
Q1 will be
From symmetry, a virtual ground appears at the
mid point of Rs . Thus, the differential half circuit
will be as shown in the figure, and
v od
RD
=
Rs
1
v id
+
gm
2
1
ro3
RD =
gm3
Ad ≡
and the differential gain of the amplifier in
Fig. P8.17 will be
v od
1
= gm1
ro3 ro1
Ad ≡
v id
gm3
For Rs = 0,
Since both sides of the amplifier are matched, this
expression can be written in a more general way
as
1
ro3,4 ro1,2
Ad = gm1,2
gm3,4
(b) Neglecting ro1,2 and ro3,4 (much larger that
1/gm3,4 ),
gm1,2
Ad gm3,4
2μn Cox (W/L)1,2 (I /2)
= 2μp Cox (W/L)3,4 (I /2)
Ad =
RD
= gm RD ,
1/gm
as expected.
To reduce the gain to half this value, we use
1
Rs
=
2
gm
⇒ Rs =
2
gm
8.19 Refer to Fig. P8.19.
(a) With v G1 = v G2 = 0,
v GS1 = v GS2 = VOV 1,2 + Vtn
Chapter 8–8
Thus
8.20 Refer to Fig. P8.20.
VS1 = VS2 = −(VOV 1,2 + Vtn )
(a) With v G1 = v G2 = 0 V,
(b) For the situation in (a), VDS of Q3 is zero, thus
zero current flows in Q3 . Transistor Q3 will have
an overdrive voltage of
VS1 = VS2 = −VGS1,2 = −(Vt + VOV )
VOV 3 = VC − VS1,2 − Vtn
= VC + (VOV 1,2 + Vtn ) − Vtn
= VC + VOV 1,2
(c) With v G1 = v id /2 and v G2 = −v id /2 where
v id is a small signal, a small signal will appear
between drain and source of Q3 . Transistor Q3
will be operating in the triode region and its
drain-source resistance rDS will be given by
rDS =
μn Cox
1
W
VOV 3
L 3
Thus,
Rs =
μn Cox
1
W
VOV 3
L 3
Now,
W
VOV 1,2
L 1,2
W
gm3 = (μn Cox )
VOV 3
L 3
W
W
For
=
,
L 3
L 1,2
W
gm1,2
=
μn Cox
L
VOV 1,2
gm1,2 = (μn Cox )
The current through Q3 and Q4 will be zero
because the voltage across them (v DS3 + v DS4 ) is
zero.
Because the voltages at their gates are zero and at
their sources are −(Vt + VOV ), each of Q3 and Q4
will be operating at an overdrive voltage equal to
VOV . Thus each of Q3 and Q4 will have an rDS
given by
μn Cox
Since
(d) (i) Rs =
1
gm1,2
VOV 3 = VOV 1,2
rDS3,4 =
0.5
gm1,2
W
L
VOV
1
gm1,2
(W/L)1,2
(W/L)3,4
Rs = rDS3 + rDS4
then
2 (W/L)1,2
gm1,2 (W/L)3,4
Rs =
(3)
(b) With v G1 = v id /2 and v G2 = −v id /2 where
v id is a small signal,
Ad ≡
=
v od
v id
2 RD
1
1
+ Rs +
gm1
gm2
Using (3), we obtain
Ad =
1
gm1,2
=
RD
1 (W/L)1,2
+
gm1,2 (W/L)3,4
gm1,2 RD
(W/L)1,2
1+
(W/L)3,4
8.21 Refer to Fig. P8.21.
The value of R is found as follows:
But
R=
⇒ VC = VOV 1,2
(2)
1,2
⇒ VOV 3 = 2 VOV 1,2
VOV 3 = VC + VOV 1,2
(1)
and since
⇒ VC = 0
(ii) Rs =
1
W
VOV
L 3,4
substituting from (2) into (1) gives
But
VOV 3 = VC + VOV 1,2
gm1,2 = μn Cox
Thus,
1
1 VOV 1,2
=
Rs = g
m1,2
g
m1,2 VOV 3
× VOV 3
VOV 1,2
rDS3,4 =
=
VG6 − VG7
IREF
0.8 − (−0.8)
= 8 k
0.2
Chapter 8–9
Since I = IREF , Q3 and Q6 are matched and are
operating at
A summary of the results is provided in the table
below.
|VOV | = 1.5 − 0.8 − 0.5 = 0.2 V
Thus,
1
W
0.2 = × 0.1 ×
× 0.22
2
L 6,3
W
W
⇒
=
= 100
L 3
L 6
Transistor W/L I D (mA) |V GS |(V)
Each of Q4 and Q5 is conducting a dc current of
(I /2) while Q7 is conducting a dc current
IREF = I . Thus Q4 and Q5 are matched and their
W/L ratios are equal while Q7 has twice the
(W/L) ratio of Q4 and Q5 . Thus,
I
1
W
= μn Cox
V2
2
2
L 4,5 OV 4,5
Q1
50
0.1
0.7
Q2
50
0.1
0.7
Q3
100
0.2
0.7
Q4
20
0.1
0.7
Q5
20
0.1
0.7
Q6
100
0.2
0.7
Q7
40
0.2
0.7
where
VOV 4,5 = −0.8 − (−1.5) − 0.5 = 0.2 V
thus,
1
W
× 0.25 ×
× 0.04
2
L 4,5
W
W
⇒
=
= 20
L 4
L 5
0.1 =
and
W
= 40
L 7
ro4 = ro5 =
|VAp |
10
=
= 100 k
I /2
0.1
ro1 = ro2 =
10
VAn
=
= 100 k
I /2
0.1
Ad = gm1,2 (ro1,2 ro4,5 )
8.22 Refer to Fig. 8.13.
All transistors have the same channel length and
are carrying a dc current I /2. Thus all transistors
|VA |
have the same ro =
. Also, all transistors are
I /2
operating at the same |VOV | and have equal dc
currents, thus all have the same
2(I /2)
gm =
= I /|VOV |. Thus all transistors have
|VOV |
equal intrinsic gain gm ro = 2|VA |/|VOV |. Now, the
gain Ad is given by
Ad = gm (Ron Rop )
=
1
gm Ron
2
=
1
1
gm (gm ro )ro = (gm ro )2
2
2
Thus,
50 = gm1,2 (100 100)
⇒ gm1,2 = 1 mA/V
Ad =
1 2|VA | 2
2 VOV
= 2(|VA |/|VOV |)2
But
Q.E.D.
gm1,2
2(I /2)
=
|VOV 1,2 |
To obtain Ad = 500 V/V while operating all
transistors at |VOV | = 0.2 V, we use
1=
0.2
|VOV 1,2 |
500 = 2
|VA |2
0.04
⇒ |VOV 1,2 | = 0.2 V
⇒ |VA | = 3.16 V
The (W/L) ratio for Q1 and Q2 can now be
determined from
1
W
0.1 = × 0.1 ×
× 0.22
2
L 1,2
W
W
⇒
=
= 50
L 1
L 2
Since |VA | = 5 V/μm, the channel length L (for
all transistors) must be
3.16 = 5 × L
L = 0.632 μm
To obtain the highest possible gm , we operate at
the highest possible I consistent with limiting the
Chapter 8–10
power dissipation (in equilibrium) to 0.5 mW.
Thus,
I=
0.5 mW
= 0.28 mA
(0.9 + 0.9)V
= +0.52 V
VC2 = VCC − IC2 × RC
= 2.5 − 0 × 5 = 2.5 V
8.23 Refer to Fig. 8.15(a).
The current I will split equally between Q1 and
Q2 . Thus,
Observe that Q1 is operating in the active mode,
as implicitly assumed, and the current source has
a voltage of 2.323 V across it, more than
sufficient for its proper operation.
IE1 = IE2 = 0.2 mA
IC1 = IC2 = α × 0.2 = 0.99 × 0.2 = 0.198 mA
0.198
VBE1 = VBE2 = 0.7 + 0.025 ln
1
VCC 2.5 V
RC 5 k
RC 5 k
VC1
VC2
= 0.660 V
VE1 = VE2 = −1 − 0.66 = −1.66 V
0.5 V
VC1 = VC2 = VCC − IC1.2 RC
IC2
IC1
Q1
Q2
= 2.5 − 0.198 × 5 = +1.51 V
VE
8.24
0.4 mA
VCC 2.5 V
IC1
IC2
RC 5 k
RC 5 k
VC1
VC2
0.5 V
Q1
Q2
VEE 2.5 V
(b)
(b) With v B1 = −0.5 V, Q1 turns off and Q2
conducts all the bias current (0.4 mA) and thus
exhibits a VBE of 0.677 V, thus
VE = −0.677 V
VE
0.4 mA
VEE 2.5 V
(a)
(a) For v B1 = +0.5 V, Q1 conducts all the current
I (0.4 mA) while Q2 cuts off. Thus Q1 will have a
VBE obtained as follows:
0.99 × 0.4
VBE1 = 0.7 + 0.025 ln
1
which indicated that VBE1 = +0.177 V, which is
too small to turn Q1 on. Also, note that the current
source has a voltage of −0.677 + 2.5 = 1.823 V
across it, more than sufficient for its proper
operation.
VC1 = VCC − IC1 RC
= 2.5 − 0 × 5 = 2.5 V
VC2 = 2.5 − 0.99 × 0.4 × 5 = +0.52 V
VC1 = VCC − IC1 RC
8.25 Refer to Fig. 8.15(a) and assume the
current source I is implemented with a single
BJT that requires a minimum of 0.3 V for
proper operation. Thus, the minimum voltage
allowed at the emitters of Q1 and Q2 is
−2.5 V + 0.3 V = −2.2 V. Now, since each of
Q1 and Q2 is conducting a current of 0.2 mA,
their VBE voltages will be equal:
0.99 × 0.2
VBE1,2 = 0.7 + 0.025 ln
1
= 2.5 − 0.99 × 0.4 × 5
= 0.660 V
= 0.677 V
Thus,
VE = +0.5 − 0.677 = −0.177 V
which indicates that VBE2 = +0.177 V, too small
to turn Q2 on.
Chapter 8–11
Thus, the minimum allowable VCM is
VCM min = −2.2 + 0.660 = −1.54 V
The upper limit on VCM is dictated by the need to
keep Q1 and Q2 operating in the active mode, thus
VCM max = 0.4 + VC1,2
= 0.4 + (2.5 − 0.99 × 0.2 × 5)
= +1.91 V
iC1 = 10.78 μA,
v BE1
iC2 = 8.82 μA
10.78 × 10−3
= 0.69 + 0.025 ln
1
= 0.5767 V
v BE2
8.82 × 10−3
= 0.69 + 0.025 ln
1
= 0.5717 V
Thus,
Thus, the input common-mode range is
−1.54 V ≤ VICM ≤ 1.91 V
v B1 = v BE1 − v BE2
= 0.5767 − 0.5717 = 0.005 V
= 5 mV
8.26 (a) Refer to Fig. 8.15(a).
I
= 10 μA
2
IC1 = IC2 = α × 10 = 0.98 × 10 = 9.8 μA
9.8 × 10−3
VBE1 = VBE2 = 0.690 + 0.025 ln
1
IE1 = IE2 =
= 0.574 V
Thus,
VE = −0.574 V
VC1 = VC2 = VCC − IC RC
= 1.2 − 9.8 × 10−3 × 82
0.4 V
(b) Refer to Fig. 8.15(a).
The maximum value of VCM is limited by the
need to keep Q1 and Q2 in the active mode. This
is achieved by keeping v CE1,2 ≥ 0.3 V.
Since VC1,2 = 0.4 V,
VEmax = 0.4 − 0.3 = 0.1 V
and
8.27 Refer to Fig. 8.15(a) with VCC replaced by
(VCC + v r ).
I
v C1 = (VCC + v r ) − α RC
2
I
= (VCC − α RC ) + v r
2
I
v C2 = (VCC + v r ) − α RC
2
I
= (VCC − α RC ) + v r
2
v od ≡ v C2 − v C1 = 0
Thus, while v C1 and v C2 will include a ripple
component v r , the difference output voltage v od
will be ripple free. Thus, the differential amplifier
rejects the undesirable supply ripple.
8.28 Refer to Fig. 8.14.
I
(a) VCM max = VCC − RC
2
(b) For VCC = 2 V and VCM max = 1 V,
VCM max = VBE1,2 + VEmax
1
1 = 2 − (IRC )
2
VCM max = 0.574 + 0.1 = 0.674 V
⇒ IRC = 2 V
The minimum value of VCM is dictated by the
need to keep the current source operating
properly, i.e. to keep 0.3 V across it, thus
(c) IB =
I ≤ 2 × 101 × 2 = 404 μA
VEmin = −1.2 + 0.3 = −0.9 V
Select
and
I = 0.4 mA
VCM min = VEmin + VBE1,2
then
= −0.9 + 0.574 = −0.326 V
RC =
2
= 5 k
0.4
8.29
iE1
iE1 − (I /2)
=
I
I
Thus, the input common-mode range is
−0.326 V ≤ VICM ≤ +0.674 V
(c) Refer to Fig. 8.15(d).
iE1 = 11 μA,
iE2 = 9 μA
=
I /2
≤ 2 μA
β +1
iE1
− 0.5
I
Chapter 8–12
This table belongs to Problem 8.29.
v id (mV)
2
5
8
10
20
30
40
iE1
/v id (V−1 ) 9.99 9.97 9.92 9.87 9.50 8.95 8.30
I
This table belongs to Problem 8.30.
v id (mV)
2
v od (V)
0.2
0.498 0.987 1.457 1.90 2.311 2.685 3.022 3.320
v od
Gain =
v id
100
99.7
5
10
98.7
15
97.1
20
95.0
Using Eq. (8.48), we obtain
1
iE1
=
− 0.5
I
1 + e−v id /VT
Observe that for v id < 10 mV the proportional
transconductance gain is nearly constant at about
10. The gain decreases as v id further increases,
indicating nonlinear operation. This is especially
pronounced for v id > 20 mV.
8.30 Refer to Fig. 8.14.
v od = v C2 − v C1
= (VCC − iC2 RC ) − (VCC − iC1 RC )
25
92.4
30
89.5
35
86.3
40
83.0
The figure shows v od versus v id and the gain
versus v id . Observe that the transfer characteristic
is nearly linear and the gain is nearly constant for
v id ≤ 10 mV. As v id increases, the transfer
characteristic bends and the gain is reduced.
However, for v id even as large as 20 mV, the gain
is only 5% below its ideal value of 100.
8.31 Require v od = 1 V when v id = 10 mV and
I = 1 mA.
Using Eq. (8.48), we obtain
iE1 =
1 (mA)
= 0.599 mA
1 + e−10/25
= RC (iC1 − iC2 )
iE2 = I − iE1 = 1 − 0.599 = 0.401 mA
Using Eqs. (8.48) and (8.49) and assuming α 1,
so that iC1 iE1 and iC2 iE2 , we get
1
1
−
v od = IRC
1 + e−v id /VT
1 + ev id /VT
1
1
−
=5
1 + e−v id /VT
1 + ev id /VT
v od = v C2 − v C1
This relationship can be used to obtain the data in
the table above.
For v od = 1 V, we have
= (VCC − iC2 RC ) − (VCC − iC1 RC )
= (iC1 − iC2 )RC
(iE1 − iE2 )RC
= 0.198RC
1
= 5.05 k
0.198
I
VC1 = VC2 = VCC − RC
2
= 5 − 0.5 × 5.05 2.5 V
RC =
With a signal of 10 mV applied, the voltage at one
collector rises to 3 V and at the other falls to 2 V.
To ensure that the transistors remain in the active
region, the maximum common-mode input
voltage must be limited to (2 − 0.4) = +1.6 V.
8.32 (a) VBE = 0.69 + 0.025 ln
= 0.632 V
0.1
1
Chapter 8–13
(b) Using Eq. (8.48), we obtain
I
iC1 = αiE1 1 + e−v id /VT
⇒ I = 2VT gm
For v id = 20 mV,
8.35 v id = 10 mA/V
iC1
200 μA
=
= 138 μA
1 + e−20/25
iC2 = 200 − 138 = 62 μA
(c) For v id = 200 mV while iC1 = 138 μA and
iC2 = 62 μA: Since iC1 and iC2 have not changed,
v BE1 and v BE2 also would not change. Thus,
v B1 − v B2 = v BE1 + iE1 Re − iE2 Re − v BE2
= (v BE1 − v BE2 ) + Re (iE1 − iE2 )
200 = 20 + Re (iC1 − iC2 )
= 20 + Re (138 − 62)
⇒ Re =
180 mV
= 2.37 k
76 μA
(d) Without Re ,
v id = 20 mV → iC1 − iC2 = 76 μA
76 μA
= 3.8 mA/V
Gm =
20 mV
With Re ,
v id = 200 mV → iC1 − iC2 = 76 μA
76 μA
= 0.38 mA/V
Gm =
200 mV
Thus, the effective Gm has been reduced by a
factor of 10, which is the same factor by which
the allowable input signal has been increased
while maintaining the same linearity.
8.33 gm =
IC
α × 0.2
=
8 mA/V
VT
0.025
Rid = 2rπ = 2
β
160
= 40 k
=2×
gm
8
8.34 Rid = 2rπ = 20 k
= 2 × 0.025 × 10 = 0.5 mA
Input signal to half-circuit = 5 mV. For
I = 200 μA, the bias current of the half-circuit is
100 μA and,
25 mV
= 250 re =
0.1 mA
10
RC
=−
Gain of half-circuit = −
re
0.25
= −40 V/V
At each collector we expect a signal of
40 × 5 mV = 200 mV. Between the two
collectors, the signal will be 400 mV.
25 mV
= 100 0.25 mA
The 0.1-V differential input signal appears across
(2re + 2Re ), thus
8.36 (a) re =
ie =
100 mV
= 0.1 mA
200 + 2 × 400
v be = 0.1 × 100 = 10 mV
(b) The total emitter current in one transistor is
I
+ ie = 0.35 mA and in the other transistor
2
I
− ie = 0.15 mA.
2
(c) At one collector the signal voltage is
−αie RC −ie RC = −0.1 × 10 = −1 V and at
the other collector the signal voltage is +1 V.
(d) Voltage gain =
8.37
2V
= 20 V/V
0.1 V
VCC
RC
RC
rπ = 10 k
vod
β
= 10 k
gm
100
= 10
gm
Re
Re
⇒ gm = 10 mA/V
Ad = 100 = gm RC
RC =
100
100
= 10 k
=
gm
10
gm =
IC
I /2
VT
VT
I
VEE
Chapter 8–14
v id = 100 mV appears across (2 re + 2 Re ). Thus
the signal across (re + Re ) is 50 mV. Since the
signal across re is 5 mV, it follows that the signal
across Re must be 50 − 5 = 45 mV and thus
Re = 9re
We choose to operate at this value of I . Thus
gm =
IC
α(0.2/2)
4 mA/V
=
VT
0.025
Ad = gm RC
60 = 4 × RC
The input resistance Rid is
Rid = (β + 1) (2re + 2Re )
= 2(100 + 1) (re + Re )
⇒ RC = 15 k
I
VC1 = VC2 = VCC − RC
2
0.2
× 15
2
= 2 × 101 × (re + 9re )
= 2.5 −
= 2 × 101 × 10re
= +1 V
To obtain Rid = 100 k,
(b) Rid = 2rπ = 2
100 = 2 × 101 × 10 × re
⇒ re 50 = 60 × 10 = 600 mV = 0.6 V
VT
,
IE
25 mV
50 =
IE
⇒ IE = 0.5 mA
I = 1 mA
Re = 9re = 9 × 50 = 450 Gain =
100
= 50 k
4
(c) v od = Ad × v id
Since
re =
=2×
β
gm
α × 2RC
2re + 2Re
RC
re + Re
Thus, there will be ±0.3 V signal swing at each
collector. That is, the voltage at each collector
will range between 0.7 V and +1.3 V.
(d) To maintain the BJT in the active mode at all
times, the maximum allowable VCM is limited to
VCM max = 0.4 + v Cmin
= 0.4 + 0.7 = 1.1 V
8.39 Ad = gm RC
=
IC
RC
VT
(I /2)
RC
VT
=
IRC
2VT
⇒ RC = 10 k
=
4
= 80 V/V
2 × 0.025
The determination of a suitable value of VCC
requires information on the required input
common-mode range (which is not specified).
Suffice it to say that the dc voltage drop across RC
is 5 V and that each collector swings ±1 V. A
supply voltage VCC = 10 V will certainly be
sufficient.
I
VC1 = VC2 = VCC − RC
2
But the gain required is
Gain =
2V
v od
=
= 20 V/V
v id
0.1 V
Thus,
RC
20 =
0.05 + 0.45
=5−2=3V
v C1 = 3 − 80 × 0.005 sin(ωt)
= 3 − 0.4 sin(ωt)
v C2 = 3 + 0.4 sin(ωt)
8.38 (a) The maximum allowable value of the
bias current I is found as
I=
(VCC
P
1 mW
=
= 0.2 mA
+ VEE )
5V
v C2 − v C1 = 0.8 sin(ωt)
The waveforms are sketched in the figure on next
page.
Chapter 8–15
vˆid
⇒ VCM max = VCC + 0.4 −
−
2
vˆid
Ad VT +
Q.E.D.
2
(b) VCC = 2.5 V,
(4)
vˆid = 10 mV,
Ad = 50 V/V,
VCM max = 2.5 + 0.4 − 0.005 − 50(25 + 5) × 10−3
1.4 V
vˆod = Ad × vˆid = 50 × 10 = 500 mV
= 0.5 V
Using Eq. (2), we obtain
IRC = 2Ad VT = 2 × 50 × 0.025
= 2.5 V
To limit the power dissipation in the quiescent
state to 1 mV, the bias current must be limited to
I=
Pmax
1
= = 0.2 mA
VCC + VEE
5
Using this value for I , we get
RC =
2.5
= 12.5 k
0.2
(c) To obtain VCM max = 1 V, we use Eq. (4) to
determine the allowable value of Ad ,
8.40 (a) Consider transistor Q1 ,
I
vˆid
v C1min = (VCC − RC ) − Ad
2
2
1 = 2.5 + 0.4 − 0.005 − Ad (25 + 5) × 10−3
(1)
where
Ad = gm RC =
I /2
RC
VT
IRC
2VT
Since
vˆid
v B1 = VCM max +
2
to keep Q1 in the active mode,
v B1 ≤ 0.4 + v C1min
Thus,
VCM max +
vˆid
vˆid
= 0.4 + VCC − Ad VT +
2
2
Thus, by reducing VCM max from 1.4 V to 1 V, we
are able to increase the differential gain from
50 V/V to 63.2 V/V.
8.41 See figure on next page. The circuit together
with its equivalent half-circuit are shown in the
figure.
Thus,
IRC
= Ad VT
2
Substituting from (2) into (1), we obtain
vˆid
v C1min = VCC − Ad VT +
2
⇒ Ad = 63.2 V/V
(2)
Ad = gm1,2 (ro1,2 ro3,4 )
For
(3)
ro1,2 = ro3,4 =
VA
2VA
α(I /2)
I
IC1,2
I
VT
2VT
I
2VA 2VA
Ad =
2VT
I
I
gm1,2 =
=
VA
VA
I
×
=
2VT
I
2VT
=
20
= 400 V/V
2 × 0.025
Chapter 8–16
This figure belongs to Problem 8.41.
VCC
VBIAS
Q3
Q3
Q4
vod Q2
Q1
vid
VCM 2
vod /2
vid
VCM 2
vid
2
Q1
Biased
at I/2
Equivalent half-circuit
I
VEE
8.43
8.42
RC
RC
vod / 2
Q1
vid
2
1 R
2 id
Biased
at (I/2)
RC
RL
Q2
Re
Both circuits have the same differential
half-circuit shown in the figure. Thus, for both
Ad =
vod
αRC
re + Re
Rid = (β + 1)(2re + 2Re )
= 2(β + 1)(re + Re )
With v id = 0, the dc voltage appearing at the top
end of the bias current source will be
I
RC
(a) VCM − VBE −
2
(b) VCM − VBE
Since circuit (b) results in a larger voltage across
the current source and given that the minimum
value of VCM is limited by the need to keep a
certain specified minimum voltage across the
current source, we see that circuit (b) will allow a
larger negative VCM .
Total resistance between collectors
Total resistance in the emitter circuit
(2RC RL )
=α
2re
Ad = α
8.44 Refer to Fig. P8.42(a).
I
Re = 4VT
2
8VT
⇒ Re =
I
I
RC = 60VT
α
2
120VT
αI
Total resistance in collector circuit
Ad = α
Total resistance in emitter circuit
2RC
RC
=α
Ad = α
2re + 2Re
re + Re
RC =
(1)
(2)
Chapter 8–17
This figure belongs to Problem 8.45.
VCC
RC
RC
vod
Rsig/2
Rsig/2
Q1
vsig
2
Q2
Re
VCM
vsig
2
VEE
Substituting for RC from (2), for Re from (1), and
for re = VT /(I /2), we obtain
α(120VT /αI )
(2VT /I ) + (8VT /I )
Ad =
=
Rid
v id
=
v sig
Rid + Rsig
Rsig = 2(β + 1)(re + Re )
(1)
thus,
(2)
α × Total resistance between collectors
v od
=
v id
Total resistance in emitters
(3)
Gv ≡
β
, α(β + 1) = β, we have
β +1
2βRC
Gv =
2(β + 1)(re + Re ) + Rsig
α × Total resistance in collectors
vo
=
vi
Total resistance in emitters
0.99 × 25
2re + 2 × 0.25
where
VT
25 mV
= 250 =
re =
IE
0.1 mA
v od
2α(β + 1)RC
=
v sig
2(β + 1)(re + Re ) + Rsig
Since α =
2 RC
4RC
=
6(re + Re )
3 re + Re
Thus the gain increases from approximately
1
2
RC /(re + Re ) to RC /(re + Re ).
2
3
=
Using (2) and (3), we get
Thus,
(4)
(6)
4βRC
2(2β + 1)(re + Re ) + 2(β + 1)(re + Re )
8.46 Refer to Fig. P8.46.
2αRC
2re + 2Re
αRC
v od
=
v id
re + Re
(5)
then the new value of Gv is obtained by
replacing β by 2β in Eq. (4) and substituting for
Rsig from (5):
Gv =
Rid = (β + 1)(2re + 2Re )
2(β + 1)(re + Re )
v id
=
v sig
2(β + 1)(re + Re ) + Rsig
1 αRC
2βRC
=
4(β + 1)(re + Re )
2 re + Re
If β is doubled to 2β while Rsig remains at its old
value, we get
where
=
Substituting for Rsig = Rid = 2(β + 1)(re + Re )
into Eq. (4) gives
Gv =
120
= 12 V/V
2+8
8.45
Re
I
0.99 × 25
vo
25 V/V
=
vi
2 × 0.25 + 2 × 0.25
Rin = (β + 1)(2re + 2Re )
If v id = 0.5 v sig , then from (1) we obtain
= 2 × 101 × (0.25 + 0.25)
Rid = Rsig
= 101 k
Chapter 8–18
8.47 Refer to Fig. P8.47.
re =
8.49 gm =
VT
25 mV
=
= 250 IE
0.1 mA
=
α × Total resistance in collectors
vo
=
vi
Total resistance in emitters
=
2μn Cox
W
ID
L
√
2 × 3 × 0.1 = 0.77 mA/V
| Ad | = gm RD = 0.77 × 10 = 7.7 V/V
RD
RD
| Acm | =
2RSS
RD
0.99 × 25 k
2re + 500 =
0.99 × 25 k
25 V/V
=
500 + 500 10
× 0.01 = 5 × 10−4 V/V
2 × 100
| Ad |
= 1.54 × 104 or 83.8 dB
| Acm |
CMRR =
Rin = (β + 1)(2re + 500 )
= 101 × (2 × 250 + 500 )
8.50 Refer to Fig. P8.2.
= 101 k
ID = 0.25 mA =
8.48 (a) Refer to the circuit in Fig. P8.48. As a
differential amplifier, the voltage gain is found
from
α × Total resistance in collectors
vo
=
vi
Total resistance in emitters
α × RC
=
2re
1
W
μp Cox
|VOV |2
2
L
1
× 4 × |VOV |2
2
⇒ |VOV | = 0.353 V
0.25 =
gm =
2ID
2 × 0.25
=
= 1.416 mA/V
|VOV |
0.353
| Ad | = gm RD = 1.416 × 4 = 5.67 V/V
RD
RD
| Acm | =
2RSS
RD
αRC
=
2re
(b) The circuit in Fig. P8.48 can be considered as
the cascade connection of an emitter follower Q1
(biased at an emitter current I /2) and a
common-gate amplifier Q2 (also biased at an
emitter current of I /2). Referring to the figure
below:
=
4
× 0.02
2 × 30
= 1.33 × 10−3 V/V
CMRR = 4252.5 or 72.6 dB
8.51 Refer to Fig. P8.51.
(a) Assume v id = 0 and the two sides of the
differential amplifier are matched. Thus,
RC
vo
Q1
vi Q2
ID1 = ID2 = 0.5 mA
1
W
2
VOV
ID1,2 = μn Cox
2
L
1
2
× 2.5 × VOV
2
⇒ VOV = 0.632 V
0.5 =
re1
Rin2 re2
v e1,2
re2
1
=
=
vi
re1 + re2
2
αRC
vo
=
v e1,2
re2
VCM = VGS + 1 mA × RSS
= Vt + VOV + 1 × RSS
= 0.7 + 0.632 + 1
= 2.332 V
2ID
2 × 0.5
= 1.58 mA/V
=
VOV
0.632
Thus,
(b) gm =
1 αRC
αRC
vo
= ×
=
vi
2
re2
2re
Ad = gm RD
which is identical to the expression found in (a)
above.
8 = 1.38 × RD
⇒ RD = 5.06 k
Chapter 8–19
(c) VD1 = VD2 = VDD − ID RD
CMRR =
= 5 − 0.5 × 5.06 = 2.47 V
| Ad |
= 2gm RSS
| Acm |
(W/L)
W/L
where
(d)
gm =
2ID
2(0.1/2)
= 0.5 mA/V
=
VOV
0.2
For CMRR of 80 dB, the CMRR is 104 ; thus
RD
104 = 2 × 0.5 × RSS /0.02
ΔVD1
ΔVCM
Q1
1/gm
2RSS 2 k
The figure shows the common-mode half-circuit,
RD
VD1
=−
1
VCM
+ 2 RSS
gm
5.06
VD1
= −1.92 V/V
=−
1
VCM
+2
1.58
(e) For Q1 and Q2 to enter the triode region
VCM + VCM = Vt + VD1 + VD1
Substituting VCM = 2.332, Vt = 0.7 V,
VD1 = 2.47 V, and VD1 = −1.92VCM results in
2.332 + VCM = 0.7 + 2.47 − 1.92VCM
⇒ VCM = 0.287 V
With this change, VCM = 2.619 V and
VD1,2 = 1.919 V; thus VCM = Vt + VD1,2 .
8.52 The new deliberate mismatch RD /RD
cancels the two existing mismatch terms in the
expression for Acm given in the problem statement
so as to reduce Acm to zero. Thus,
RD
RD
×
= −0.002
RD
2RSS
RD
5
×
= −0.002
2 × 25
RD
RD
= −0.02 or − 2%
⇒
RD
(Note the sign of the change is usually determined
experimentally.)
8.53 | Acm | =
| Ad | = gm RD
RD
2RSS
(W/L)
W/L
RSS = 200 k
For the current source transistor to have
ro = 200 k,
VA × L
0.1 mA
200 × 0.1
= 4 μm
L=
5
200 =
8.54 It is required to raise the CMRR by 40 dB,
that is, by a factor of 100. Thus, the cascoding of
the bias current source must raise its output
resistance RSS by a factor of 100. Thus the
cascode transistor must have A0 = 100. Since
A0 = gm ro =
2VA
2I VA
=
VOV I
VOV
2VA
0.2
⇒ VA = 10 V
100 =
VA = VA × L
10 = 5 × L
⇒ L = 2 μm
8.55 Refer to Fig. P8.55,
vo
=
(a)
v id
Total resistance across which v o appears
α
Total resistance in the emitter
2 k
=α×
re1 + re2
VT
, where IE is
IE
the dc emitter current of each of Q1 and Q2 , we
use
To determine re1 = re2 = re =
VE = VB − VBE = 0 − 0.7
= −0.7 V
−0.7 − (−5)
= 1 mA
4.3
IE = 0.5 mA
2IE =
25 mV
= 50 0.5 mA
2 k
=α×
20 V/V
0.1 k
re1 = re2 =
vo
v id
Chapter 8–20
(b)
The common-mode half-circuit is shown in the
figure,
α × 2 k
vo
=−
v icm
(0.05 + 8.6) k
−0.23 V/V
vo
= 0.23 V/V
v icm
(c) CMRR =
20
|v o /v id |
=
= 86.5
|v o /v icm |
0.23
or 38.7 dB
(d) v o = −0.023 sin 2π × 60t
+ 0.2 sin 2π × 1000 t volts
8.56
RC
2RSS
RC
RC
10
× 0.02 = 0.001 V/V
200
To obtain Ricm , we use Eq. (8.96):
| Acm | =
Figure (a) shows the differential half-circuit.
IE = 0.5 mA,
| Acm | IC = αIE 0.5 mA
IC
0.5 mA
= 20 mA/V
=
gm =
VT
0.025 V
25 mV
= 50 0.5 mA
VA
100
= 200 k
=
ro =
IC
0.5
re =
α × Total resistance in collectors
Total resistance in emitters
10 k 10 k
(50 + 150) Ad =
Ricm βREE
1 + (RC /βro )
RC + 2REE
1+
ro
where 2REE = 200 k, thus REE = 100 k and
Ricm = 100 × 100
1 + (10/(100 × 200))
10 + 200
1+
200
= 4.88 M
8.57 (a) gm =
IC
0.1 mA
= 4 mA/V
VT
0.025 V
Ad = gm RC = 4 × 25 = 100 V/V
=
5
= 25 V/V
0.2
We have neglected ro because its equivalent value
at the output will be ro [1 + (Re /re )] =
200[1 + (150/50)] = 800 k which is much
greater than the effective load resistance of 5 k.
β
100
=2×
= 50 k
gm
4
RC
RC
(c) | Acm | =
2REE
RC
Rid = 2 × (β + 1)(50 + 150 )
=
= 2 × 101 × 0.2 (k) = 40.4 k
= 2.5 × 10−4 V/V
(b) Rid = 2rπ = 2
25
× 0.01
2 × 500
Chapter 8–21
(d) CMRR =
100
| Ad |
= 4 × 105
=
| Acm |
2.5 × 10−4
or 112 dB
VA
100
(e) ro =
= 1000 k
IC
0.1
Ricm βREE
1 + (RC /βro )
RC + 2REE
1+
ro
1 + (25/(100 × 1000))
= 100 × 500
25 + 1000
1+
1000
25 M
20
VA
=
= 100 k
I
0.2
For the transistors in the differential pair, we have
8.58 REE =
ro =
VA
20
=
= 200 k
I /2
0.1
Ricm βREE
For RC
Ricm βREE
=
1+
2REE
ro
REE = Ro | Wilson mirror
1
βro
2
where ro is that of the transistors in the Wilson
mirror, then
=
50
= 100 k
0.5
1
REE = × 100 × 100 = 5 M
2
5
| Acm | =
× 0.1
2 × 5, 000
ro =
= 5 × 10−5 V/V
50
CMRR =
= 106
5 × 10−5
or 120 dB
1 + (RC /βro )
RC + 2REE
1+
ro
ro ,
(c) If the bias current I is generated using a
Wilson mirror,
50 × 100
= 2.5 M
2 × 100
1+
200
8.60 See figure on next page.
v be1 = 2.5 sin(ωt), mV and
v be2 = −2.5 sin(ωt), mV
I
v C1 VCC −
RC −gm RC ×2.5×10−3 sin(ωt)
2
where
gm =
I /2
I mA
=
VT
0.05 V
Thus,
8.59 For the differential-pair transistors, we have
IC 0.25 mA
0.25
= 10 mA/V
0.025
VA
50
ro =
= 200 k
=
IC
0.25
gm =
I
I
v C1 = 5− ×10−
×10×2.5×10−3 sin(ωt)
2
0.05
= 5 − 5I − 0.5I sin(ωt)
Similarly,
v C2 = 5 − 5I + 0.5I sin(ωt)
(a) Ad = gm RC = 10 × 5 = 50 V/V
To ensure operation in the active mode at all times
with v CB = 0 V, we use
where we have neglected the effect of ro since
ro
RC .
v C1min = 0.005
(b) If the bias current is realized using a simple
current source,
50
VA
REE = ro | current source =
=
= 100 k
I
0.5
RC
RC
| Acm | =
2REE
RC
5
× 0.1
=
2 × 100
= 2.5 × 10−3 V/V
| Ad |
50
CMRR =
=
= 2 × 104
| Acm |
2.5 × 10−3
or 86 dB
5 − 5.5I = 0.005
⇒ I 0.9 mA
With this value of bias current, we obtain
0.9
= 18 mA/V
0.05
Ad = gm RC = 18 × 10 = 180 V/V
gm =
At each collector there will be a sine wave of
180 × 2.5 = 450 mV = 0.45 V amplitude
superimposed on the dc bias voltage of
5 − 0.45 × 10 = 0.5 V. Between the two
collectors there will be a sine wave with 0.9 V
peak amplitude. The second figure illustrates the
waveforms obtained.
Chapter 8–22
These figures belong to Problem 8.60.
8.61 If Q1 has twice the base-emitter junction
2
area of Q2 , the bias current I will split I in Q1
3
1
and I in Q2 . This is because with B1 and B2
3
grounded the two transistors will have equal
VBE ’s. Thus their currents must be related by the
ratio of their scale currents IS , which are
proportional to the junction areas.
RC
iC1
RC
iC2
vo2
vo1
vicm
Q1
2
Q2
ie1
vicm
ie2
ve vicm
vicm
REE
REE
With a common-mode input signal v icm applied,
as shown in the figure, the current (v icm /REE ) will
split between Q1 and Q2 in the same ratio as that
of their base-emitter junction areas, thus
ie1 =
2 v icm
3 REE
and
ie2 =
1 v icm
3 REE
Thus,
v o1 = −ic1 RC −ie1 RC = −
2 RC
v icm
3 REE
and
v o2 = −
1 RC
v icm
3 REE
With the output taken differentially, we have
v o2 − v o1 =
Acm =
1 RC
v icm
3 REE
1 RC
1
12
= ×
= 0.008 V/V
3 REE
3 500
8.62 If the output is taken single-endedly, then
| Acm | =
RC
2REE
| Ad | =
1
gm RC
2
Chapter 8–23
CMRRs =
| Acm |
= gm REE
| Ad |
VOS =
VOV
2
RD
RD
If the output is taken differentially, then
RC
RC
| Acm | =
2REE
RC
Thus,
| Ad | = gm RC
(b) For each value of VOS we use Eq. (2) to
determine I and then Eq. (1) to determine Ad . The
results are as follows:
CMRRd = 2gm REE /
RC
RC
VOS =
1√
I /k n
2
RD
RD
(2)
Thus,
VOS (mV)
2
CMRRd
=
CMRRs
RC /RC
I (mA)
2
20 log
= 34 dB
RC /RC
⇒
1
Ad = gm RD
VOS
8.65 VOV =
2 ID
I
=
=
gm
gm
VOV
RD
=
2
RD
5
4
8
12
16
20
I /2
1 k (W/L)
2 n
=
I
k n (W/L)
0.1
= 0.224 V
0.2 × 10
RD
RD
VOV
= 0.04 ⇒ VOS =
RD
2
RD
=
For I = 160 μA, we have
√
gm = 4 × 0.16 = 0.8 mA/V
Ad = 0.8 × 10 = 8 V/V
=
0.16
= 0.2 V
0.8
0.2
× 0.02 = 2 mV
VOS =
2
For I = 360 μA, we have
√
gm = 4 × 0.36 = 1.2 mA/V
VOV =
0.224
× 0.04 = 4.5 mV
2
(W/L)
= 0.04 ⇒ VOS =
(W/L)
VOV
2
(W/L)
(W/L)
0.224
× 0.04 = 4.5 mV
2
Vt = 5 mV ⇒ VOS = Vt = 5 mV
=
Worst-case VOS = 4.5 + 4.5 + 5 = 14 mV
Ad = 1.2 × 10 = 12 V/V
0.36
= 0.3 V
1.2
0.3
× 0.02 = 3 mV
VOS =
2
Thus by increasing the bias current, both the gain
and the offset voltage increase, and by the same
factor (1.5).
VOV =
√
√
8.64 (a) gm = 2k n ID = k n I
√
Ad = gm RD = k n I RD
I /2
I
VOV =
=
1
kn
kn
2
4
We observe that by accepting a larger offset we
are able to obtain a higher gain. Observe that the
gain realized is proportional to the offset voltage
one is willing to accept.
8.63 gm = 2 k n (W/L)ID
= k n (W/L)I
VOV
3
0.04 0.16 0.36 0.64 1.00
Ad (V/V)
RC
= 0.04 = 4%
RC
2
(1)
If the three components are independent,
√
VOS = 4.52 + 4.52 + 52 = 8.1 mV
8.66 The offset voltage due to Vt is
VOS = ±5 mV
The offset voltage due to RD is
RD
VOV
0.3
× 0.02 = 3 mV
=
VOS =
2
RD
2
The offset voltage due to (W/L) is
VOV (W/L)
0.3
=
× 0.02 = 3 mV
VOS =
2
(W/L)
2
Chapter 8–24
VCC
The worst-case offset voltage will be when all
three components add up,
VOS = 5 + 3 + 3 = 11 mV
RC
RC
The major contribution to the total is the
variability of Vt .
(a1I/2)
(a2I/2)
VO
Q1
To compensate for a total offset of 11 mV by
appropriately varying RD , we need to change RD
by RD obtained from
RD
VOV
×
11 mV =
2
RD
Q2
I
2
I
2
I
RD
11 × 2
⇒
=
= 0.0733
RD
300
or 7.33%
8.67 VOS = VT
RC
RC
and the collector voltages will be unequal,
VC1 = VCC − α1 (I /2)RC
= 25 × 0.1 = 2.5 mV
8.68 VOS = VT
IS
IS
VC2 = VCC − α2 (I /2)RC
Thus a differential output voltage VO develops:
VO = VC2 − VC1
1
IRC (α1 − α2 )
2
The input offset voltage VOS can be obtained by
dividing VO by the differential gain Ad :
= 25 × 0.1 = 2.5 mV
8.69 With both input terminals grounded, a
mismatch RC between the two collector
resistors gives rise to an output voltage
I
RC
VO = α
2
=
Ad = gm RC (1)
I /2
IRC
RC =
VT
2VT
Thus,
VOS = VT (α1 − α2 )
With a resistance RE connected in the emitter of
each transistor, the differential gain becomes
Substituting, we obtain
α × 2RC
αRC
| Ad | =
=
2(re + RE )
RE + re
α1 =
(2)
The input offset voltage VOS is obtained by
dividing VO in (1) by | Ad | in (2),
I
RC
VOS = (re + RE )
2
RC
Since re =
VOS
VT
,
I /2
1
RC
= (VT + IRE )
2
RC
8.70 See figure.
The current I splits equally between the two
emitters. However, the unequal β’s will mean
unequal α’s. Thus, the two collector currents will
be unequal,
IC1 = α1 I /2
IC2 = α2 I /2
β1
β1 + 1
and
β2
β2 + 1
β1
β2
= VT
−
β1 + 1 β2 + 1
α2 =
VOS
= VT
β1 β2 + β1 − β1 β2 − β2
(β1 + 1)(β2 + 1)
= VT
β1 − β2
(β1 + 1)(β2 + 1)
β1 − β2
β1 β2
1
1
= VT
−
β2
β1
VT
Q.E.D.
For β1 = 50 and β2 = 100, we have
1
1
−
= −0.25 mV
VOS = 25
100 50
Chapter 8–25
In terms of the emitter currents, this becomes
I
I
−
I
RS
2
2
−
re
RS +
2
2
(β + 1)
I
I
+
RS
I
2
2
re
RS −
=
+
2
2
(β + 1)
8.71 For the MOS amplifier:
RD
VOV
VOS =
2
RD
200
× 0.04
2
= 4 mV
=
For the BJT amplifier:
RC
VOS = VT
RC
I RS
IRS
and −
from
2 (β + 1)
4(β + 1)
each side, we obtain
Subtracting
= 25 × 0.04 = 1 mV
If in the MOS amplifier the width of each device
is increased by a factor of 4 while the bias current
is kept constant, VOV will be reduced by a factor
of 2. Thus VOS becomes
VOS = 2 mV
VCC
RS
2
=−
IRS
Ir e
I RS
+
+
4 (β + 1) 2 (β + 1)
2
Combining terms, we have
IRS
I RS
=
+ Ire
2 (β + 1)
(β + 1)
RS
I RS
so that
+ re =
I
2 (β + 1)
(β + 1)
8.72
RS IRS
I re
I RS
−
−
4 (β + 1) 2 (β + 1)
2
I =
RC
VC Q1
RC
RS RS
2
Q2
IB1
IB2
I
I
2
2
I
I RS
·
2 (β + 1)
I
I
2
2
VC = IC RC .
VC =
1
RS
+ re
(β + 1)
If
I RS RC
·
2 (β + 1)
VC
=
Ad
I RS
·
=
2 (β + 1)
I RS RC
·
2 (β + 1)
1
RS
+ re
(β + 1)
gm RC
VOS =
Assume the mismatch RS is split between the
two base (source) resistances. The emitter
currents will be different, as shown.
1
RS
+ re
(β + 1)
Now VOS can be obtained by dividing VC by Ad
= gm RC ,
VEE
Consider only the incremental currents involved.
β
≈ 1, we have
β +1
VOS =
gm
1
RS
+ re
(β + 1)
1
I RS
·
2
gm RS + (β + 1) re gm
Equating the voltage drop from each grounded
input to the common emitters, we have
I
I
RS
+
−
re
IB1 RS +
2
2
2
RS
I
I
= IB2 RS −
+
+
re
2
2
2
Since (β + 1) re = rπ and rπ gm = β, we have
I
· RS
2β
VOS =
Q.E.D.
g m RS
1+
β
I
Subtracting out the re terms, we have
2
I
RS
−
re
IB1 RS +
2
2
RS
I
= IB2 RS −
+
re
2
2
8.73 Since the only difference between the two
sides of the differential pair is the mismatch in VA ,
we can write
VCE1
IC1 = IC 1 +
VA1
Chapter 8–26
VCE2
IC2 = IC 1 +
VA2
(b) If the area of Q1 and hence IS1 is 5% larger
than nominal, then we have
IC1 + IC2 = αI
VCE2
VCE1
IC 2 +
+
= αI
VA1
VA2
VCE1
VCE2
⇒ IC = αI
2+
+
VA1
VA2
IC1
αI
=
2
For
VCE1
VA1
IC1
αI
2
IC2
IS1 = 1.05IS
and the area of Q2 and hence IS2 is 5% smaller
than nominal,
IS2 = 0.95IS
VCE1
VA1
VCE1
VCE2
1+
+
2VA1
2VA2
1+
1 and
VCE2
VA2
Thus,
IE1 = 0.5 × 1.05 = 0.525 mA
IE2 = 0.5 × 0.95 = 0.475 mA
1 we have
Assuming α 1, we obtain
1 VCE1
1 VCE2
1+
−
2 VA1
2 VA2
1 VCE2
αI
1 VCE1
1+
−
2
2 VA2
2 VA1
IC1 = 0.525 mA IC2 = 0.475 mA
To reduce the resulting offset to zero, we adjust
the potentiometer so that
The voltage VO between the two collectors will be
VC1 = VC2
VO = VC2 − VC1
⇒ VCC − (RC1 + x)IC1 = VCC − (RC2 + 1 − x)IC2
= IC1 RC − IC2 RC
αI
VCE1
VCE2
RC ×
=
−
2
VA1
VA2
IC1 (RC1 + x) = IC2 (RC2 + 1 − x)
(1)
I
Since we still have IC1 IC2 = α , the
2
differential gain is still given by
Ad = gm RC =
IC RC
αIRC
=
VT
2VT
0.525(5 + x) = 0.475(5 + 1 − x)
⇒ x = 0.225
(2)
Dividing (1) by (2) gives
VCE2
VCE1
VOS = VT
−
VA1
VA2
As a first-order approximation, we can assume
8.75 IBmax =
IBmin =
400
2.5 μA
2 × 81
400
= 1 μA
2 × 201
IOSmax =
200 200
−
1.5 μA
81
201
VCE1 VCE2 = 10 V
and substitute VA1 = 100 V and VA2 = 200 V to
determine VOS as
10
10
VOS = 25
−
100 200
= 25 × 0.05 = 1.25 mV
8.76 A 2-mV input offset voltage corresponds to
a difference RC between the two collector
resistances,
2 = VT
= 25 ×
8.74 Refer to Fig. P8.74.
(a) RC1 = 1.04 × 5 = 5.20 k
RC2 = 0.96 × 5 = 4.80 k
To equalize the total resistance in each collector,
we adjust the potentiometer so that
RC1 + x × 1 k = RC2 + (1 − x) × 1 k
5.2 + x = 4.8 + 1 − x
⇒ x = 0.3 k
RC
RC
RC
20
⇒ RC = 1.6 k
Thus a 2-mV offset can be nulled out by adjusting
one of the collector resistances by 1.6 k. If the
adjustment mechanism raises one RC and lowers
the other, then each need to be adjusted by only
(1.6 k/2) = 0.8 k.
If a potentiometer is used, the total resistance of
the potentiometer must be at least 1.6 k. If
specified to a single digit, we use 2 k.
Chapter 8–27
The gain Ad is found as follows:
8.77
VCC
a2I
3
RC
VC1
VO
RC
Q1
VC2
where
Q2
I
3
2I
3
2
α × Total resistance in collectors
Total resistance in emitters
α × 2RC
=
re1 + re2
Ad =
aI
3
re1 =
VT
3VT
1.5VT
VT
=
=
=
IE1
2I /3
2I
I
re2 =
VT
3VT
VT
=
=
IE2
I /3
I
thus,
I
Ad =
(a)
2αRC
2αIRC
=
4.5 VT /I
4.5 VT
(2)
Substituting in Eq. (1) gives
v id = 0.75 VT = 18.75 mV
Now, using large signal analysis:
RC
v id = VB2 − VB1 = (VB2 − VE ) − (VB1 − VE )
RC
Vod IC1 = IS1 e(VB1 −VE )/VT
(3)
(VB2 −VE )/VT
(4)
IC2 = IS2 e
Q1
vid
Q2
re1
where IS1 = 2 IS2 .
To make IC1 = IC2 ,
re2
IS1 e(VB1 −VE )/VT = IS2 e(VB2 −VE )/VT
e(VB2 −VB1 )/VT = 2
(b)
From Fig. (a) we see that the transistor with twice
the area (Q1 ) will carry twice the current in the
other transistor (Q2 ). Thus
2I
IE1 = ,
3
α2I
,
IC1 =
3
Thus,
IE2
I
=
3
IC2 =
Thus,
v id = 17.3 mV
which is reasonably close to the approximate
value obtained using small-signal analysis.
αI
2
8.78 Gm = 2 mA/V
α2I
RC
VC1 = VCC −
3
αI
VC2 = VCC −
RC
3
and the dc offset voltage at the output will be
With RL = ∞,
Ad = Gm Ro
and
v o = Gm Ro v id
VO = VC2 − VC1
With RL = 20 k,
1
VO = αIRC
3
To reduce this output voltage to zero, we apply a
dc input voltage v id in the direction shown in Fig.
(b). The voltage v id is required to produce v od in
the direction shown which is opposite in direction
to VO and of course |v od | = |VO |, thus
1
Ad v id = αIRC
3
VB2 − VB1 = VT ln 2
(1)
v o = Gm Ro v id
= Gm Ro
RL
RL + Ro
1
20
v id = Gm Ro v id
20 + Ro
2
Thus,
Ro = 20 k
Ad (with RL = ∞) = Gm Ro = 2 × 20 = 40 V/V
Chapter 8–28
8.79 Gm = gm1,2 =
2(I /2)
I
I
=
=
VOV
VOV
0.25
VDD
Ro = ro2 ro4
For
Q3
ro2 = ro4 =
|VA |
=
I /2
I /2
5
2 × 5 × 0.5
=
I
I
2.5
1 5
Ro = × =
2
I
I
Thus,
=
Q1
Q2
I
2.5
I
×
= 10 V/V
Ad = Gm Ro =
0.25
I
8.80
Q4
|VA |L
Q8
Q7
Q5
Q6
1
I
W
2
= μn Cox
VOV
2
2
L
1
2
× 0.2 × 50 × VOV
2
⇒ VOV = 0.14 V
0.1 =
gm1,2 =
2 × (I /2)
2 × 0.1
= 1.4 mA/V
=
VOV
0.14
VSS
|V | × L
|VA |
5 × 0.5
= A
=
ro2 = ro4 =
I /2
I /2
0.1
= 25 k
⇒ VOV = 0.2 V
Ad = gm1,2 (ro2 ro4 )
VGS = Vt + |VOV |
= 1.4 × (25 25)
= 0.5 + 0.2 = 0.7 V
= 17.5 V/V
For Q5 , Q6 , Q7 , and Q8 :
ID = 0.2 mA
8.81 Ad = gm1,2 (ro2 ro4 )
W
ID
gm1,2 = 2k n
L
√
√
= 4I = 2 I
ro2
|VA |
2|VA |
2×5
10
= ro4 =
=
=
=
I /2
I
I
I
√
10
1 10
= √
Ad = 2 I × ×
2
I
I
10
20 = √
I
⇒ I = 0.25 mA
1
2
× 5 × VOV
2
⇒ VOV = 0.28 V
0.2 =
VGS = 0.5 + 0.28 = 0.78 V
From the figure we see that for each transistor to
operate at VDS at least equal to VGS , the total
power supply is given by
VDD + VSS = VDS4 + VDS2 + VDS7 + VDS6
= VGS4 + VGS2 + VGS7 + VGS6
= 0.7 + 0.7 + 0.78 + 0.78
= 2.96 3.0 V
8.83
8.82 See figure.
(a) See figure on next page.
For Q1 , Q2 , Q3 and Q4 :
1
W
I
2
= μn Cox
VOV
2
2
L
0.1 =
1
2
× 5 × VOV
2
(b) Ad = gm1,2 (Ro4 Ro6 )
gm1,2 =
2(I /2)
I
=
VOV
VOV
Ro6 = gm6 ro6 ro8
Chapter 8–29
Q7
Q8
Q5
Q6
For |VOV | = 0.2 V and |VA | = 10 V, we have
10 2
Ad = 2
= 5000 V/V
0.2
Ro6
Ro4
Q3
vo
Q4
VBIAS
Q1
Q2
I
Since all transistors are operated at a bias current
(I /2) and have the same overdrive voltage |VOV |
and the same Early voltage, |VA |, all have the
same gm = I /|VOV | and the same
|VA |
ro =
= 2|VA |/I . Thus,
I /2
Ro6 = gm ro2
Ro4 = gm4 ro4 ro2 = gm ro2
Ad = gm (gm ro2 gm ro2 )
1
(gm ro )2
2
I
2|VA |
2|VA |
gm ro =
×
=
|VOV |
I
|VOV |
8.84 The currents i1 to i13 are shown on the circuit
diagram. Observe that i11 = i7 = i3 (the current
that enters a transistor exits at the other end!).
Also observe that the mirror Q3 and Q4 is indeed
functioning properly as the drain currents of Q3
1
and Q4 are equal (i12 = i2 = gm v id ). However,
4
the currents in their ro ’s are far from being equal!
There are some inconsistencies that result from
the approximations made to obtain the results
shown in Fig. P8.84, namely, gm ro
1. Note for
instance that although we find the current in ro of
1
Q2 to be gm v id , the voltages at the two ends of
2
1
ro are (gm ro )v id and v id /4; thus the current must
2
1
1
be v id
gm ro −
ro , which is approximately
2
4
1
gm v id .
2
The purpose of this problem is to show the huge
imbalance that exists in this circuit. In fact, Q1
1
3
has |v gs | = v id while Q2 has |v gs | = v id . This
4
4
imbalance results from the fact that the current
mirror is not a balanced load. Nevertheless, we
know that this circuit provides a reasonably high
common-mode rejection.
=
Ad = 2(|VA |/|VOV |)
2
Q.E.D.
This figure belongs to Problem 8.84.
8.85 Gm = gm1,2 =
ro2 =
2(I /2)
0.2
= 1 mA/V
=
VOV 1,2
0.2
20
VAn
=
= 200 k
I /2
0.1
Chapter 8–30
ro4 =
|VAp |
12
=
= 120 k
I /2
0.1
Thus,
IO = ID4 − ID2
Ro = ro2 ro4 = 200 120 = 75 k
= ID1 − ID2
Ad = Gm Ro = 1 × 75 = 75 V/V
The gain is reduced by a factor of 2 with
RL = Ro = 75 k.
=
I (W/L)A
2 (W/L)A
The input offset voltage is
VOS =
8.86
VDD
IO
Gm
where
Gm = gm1,2 =
2(I /2)
I
=
VOV
VOV
Thus,
Q3
Q4
IO
Q1
Q2
I
VSS
VOS = (VOV /2)
(W/L)A
(W/L)A
(b) ID1 = ID2 =
I
2
Q.E.D.
ID3 = ID1
If the (W/L) ratios of the mirror transistors have a
mismatch (WL)M , the current transfer ratio of
the mirror will have an error of
[(W/L)M /(W/L)M ]. Thus
(W/L)M
ID4 = ID3 1 +
(W/L)M
At the output node, we have
(a) Let
W
W
1
W
=
+ L 1
L A 2
L A
W
W
1
W
=
− L 2
L A 2
L A
Q1 and Q2 have equal values of VGS and thus of
VOV , thus
1
W
1
W
+ V2
ID1 = k n
2
L A 2
L A OV
1
W
1 (W/L)A 2
= k n
1+
VOV
2
L A
2 (W/L)A
Since, in the ideal case
1
I
W
ID1 = = k n
V2
2
2
L A OV
I
1 (W/L)A
ID1 =
1+
2
2 (W/L)A
Similarly, we can show that
1 (W/L)A
I
1−
ID2 =
2
2 (W/L)A
The current mirror causes
ID4 = ID3 = ID1
IO = ID4 − ID2
(W/L)M
= ID3 1 +
− ID2
(W/L)M
(W/L)M
= ID1 1 +
− ID2
(W/L)M
=
I (W/L)M
2 (W/L)M
and the corresponding VOS will be
IO
IO
=
Gm
I /VOV
VOV (W/L)M
=
2
(W/L)M
VOS =
Q.E.D.
0.2
× 0.02 = 2 mV
2
0.2
× 0.02 = 2 mV
=
2
(c) VOS |Q1 ,Q2 mismatch =
VOS |Q3 ,Q4 mismatch
Worst-case VOS = 2 + 2 = 4 mV
8.87 IE1 = IE2 = 0.25 mA
IC1 = IC2 0.25 mA
gm1,2 =
IC1,2
0.25 mA
=
= 10 mA/V
VT
0.025 V
Chapter 8–31
ro =
|VA |
10 V
= 40 k
=
IC
0.25 mA
Rid = 2 rπ = 2
two input terminals and determine the output
current i as follows:
β
100
=2×
= 20 k
gm
10
i = IC2 − IC4
I
I
1
−α
2
2 1 + (2/βp2 )
1
I
1−
=α
2
1 + (2/βp2 )
Ro = ro2 ro4 = 40 40 = 20 k
=α
Gm = gm1,2 = 10 mA/V
Ad = Gm Ro = 10 × 20 = 200 V/V
If RL = Rid = 20 k, then
Gv = 200 ×
= 200 ×
RL
RL + Ro
−α
20
= 100 V/V
20 + 20
Dividing i by Gm = gm1,2 =
VOS = −
8.88 Using Eq. (8.145), we obtain
αI
gives
2VT
2VT
βp2
2VT
βp
For βp = 50,
2 × 25
βp
VOS = −
VOS = −
−2 = −
I
I 2
= −α 2
2
2 βp
βp
2 × 25
= −20 μV
502
⇒ βp = 25
8.90
8.89
Q3
Q4
aI 2 (1
Q5
i
2
)
bP2
aI/2
aI/2
Q2
Q1
I/2
I/2
I
The figure shows a BJT differential amplifier
loaded in a base-current-compensated current
mirror. To determine the systematic input offset
voltage resulting from the error in the
current-transfer ratio of the mirror, we ground the
The figure shows a BJT differential amplifier
loaded with a Wilson current mirror. To determine
the systematic input offset voltage resulting from
the error in the current-transfer ratio of the mirror,
Chapter 8–32
we ground the two input terminals and determine
the output current i as follows:
i = α
α
I
1
I
−α
2
2 1 + (2/βp2 )
I 2
αI
= 2
2 βp2
βp
input offset voltage VOS :
αI /2
=
provides the
VT
= +3.6 V
(b) The dc bias voltage should be
VO = v Omax − 1.5
= 4 − 1.5 = +2.5 V
2VT
βp2
For βp = 50,
VOS = −
(a) VB7 = +5 − VEB6 − VEB7 = 5 − 0.7 − 0.7
v Omax = VB7 + 0.4 = +4 V
Dividing i by Gm = gm1,2
VOS = −
8.92 Refer to Fig. P8.91.
2 × 25
= −20 μV
502
(c) For v O to swing negatively (i.e., below the dc
bias value of 2.5 V) by 1.5 V, that is, to +1 V with
Q4 remaining in saturation, VBIAS should be
VBIAS = v Omin + 0.4
= 1.4 V
8.91 Refer to Fig. P8.91.
Ad = Gm Ro
(d) With VBIAS = 1.4 V, the bias voltage at the
collectors of Q1 and Q2 is
VC1,2 = VBIAS − VBE3,4
where
Gm = gm1,2
I /2
VT
= 1.4 − 0.7 = +0.7 V
and
The upper limit on VCM is 0.4 V above VC1,2 :
Ro = Ro4 Ro7
VCM max = 0.7 + 0.4 = +1.1 V
Here Ro4 is the output resistance of the cascode
amplifier (looking into the collector of Q4 ), thus
Ro4 = gm4 ro4 (ro2 rπ 4 )
Usually rπ 4
ro2 ,
Ro4 gm4 rπ 4 ro4 = β4 ro4
The resistance Ro7 is the output resistance of the
Wilson mirror and is given by
Ro7 =
1
β7 ro7
2
Thus
Ro = (β4 ro4 ) 1
β7 ro7
2
Since all β and ro are equal, we obtain
1
βro
Ro = (βro ) 2
1
βro
3
and
1
Q.E.D.
Ad = βgm ro
3
For β = 100 and VA = 20 V, we have
=
gm ro =
Ad =
IC VA
VA
20
=
=
= 800
VT IC
VT
0.025
1
× 100 × 800 = 2.67 × 104 V/V
3
8.93 To maximize the positive output voltage
swing, we select VBIAS as large as possible while
maintaining the pnp current sources in saturation.
For the latter to happen, we need a minimum of
0.3 V across each current source. Thus the
maximum allowable voltage at the emitters of Q3
and Q4 is VCC − 0.3 = 5 − 0.3 = +4.7 V. Then,
the maximum allowable value of
VBIAS = 4.7 − 0.7 = +4 V. To keep Q4 in
saturation,
v Omax = VBIAS + 0.4 = 4.4 V
If the dc voltage at the output is 0 V, then the
maximum positive voltage swing is 4.4 V. In the
negative direction,
v Omin = −VEE + VBE7 + VBE5 − 0.4
= −5 + 0.7 + 0.7 − 0.4
= −4 V
Thus,
−4 V ≤ v O ≤ +4.4 V
Gm = gm1,2 0.25 mA
= 10 mA/V
0.025 V
Ro4 = β4 ro4 = 50 ×
|VA |
I /2
Chapter 8–33
100 V
= 20 M
0.25 mA
1
100
1
Ro5 = β5 ro5 = × 100 ×
2
2
0.25
= 20 M
= 50 ×
Ro = Ro4 Ro5 = 20 M 20 M = 10 M
Ad = Gm Ro = 10 × 10,000 = 105 V/V
8.94 The overdrive voltage, |VOV |, at which Q1
and Q2 are operating is found from
1
I
= k p (W/L)|VOV |2
2
2
1
0.1 = × 6.4 × |VOV |2
2
⇒ |VOV | = 0.18 V
Gm = gm1,2
2(I /2)
=
|VOV |
0.2
= 1.13 mA/V
=
0.18
|VAp |
10
=
= 100 k
ro2 =
I /2
0.1
ro4 =
|VAnpn |
30
=
= 300 k
I /2
0.1
Ro = ro2 ro4 = 100 k 300 k = 75 k
But
Ro = ro2 ro4
and ro2 = ro4 (Q2 and Q4 have the same ID =
and the same VA ). Thus
ro2 = ro4 = 100 k =
|VA | =
I
2
|VA |
I /2
I
× 100 k = 10 V
2
10 = |VA |L = 20 L
⇒ L = 0.5 μm
(c) v Omin = VCM − Vtn
= 0 − 0.5 = −0.5 V
v Omax = VDD − |VOV | = 1 − 0.2 = 0.8 V
Thus,
−0.5 V ≤ v O ≤ 0.8 V
|VA |
10
=
= 50 k
I
0.2
The CMRR can be obtained using Eq. (8.159):
(d) RSS =
CMRR = (gm ro )(gm RSS )
= (1 × 100)(1 × 50)
= 5000 or 74 dB
Ad = Gm Ro = 1.13 × 75 = 85 V/V
8.96 The CMRR is given by Eq. (8.158):
8.95 (a) For Q1 and Q2 ,
1
W
I
= μn Cox
V2
2
2
L 1,2 OV
W
1
0.1 = × 0.4 ×
× 0.04
2
L 1,2
W
W
=
= 12.5
⇒
L 1
L 2
For Q3 and Q4 ,
1
W
I
|VOV |2
= μn Cox
2
2
L 3,4
1
W
0.1 = × 0.1 ×
× 0.04
2
L 3,4
W
W
=
= 50
⇒
L 3
L 4
(b) Gm = gm1,2
1 mA/V
Ad = Gm Ro
50 = 1 × Ro
⇒ Ro = 50 k
2 (I /2)
I
0.2
=
=
=
=
VOV
VOV
0.2
CMRR = [gm1,2 (ro2 ro4 )] [2 gm3 RSS ]
(a) Current source is implemented with a simple
current mirror:
|VA |
RSS = ro | QS =
I
2(I /2)
I
=
gm1,2 = gm3 =
VOV
VOV
ro2 = ro4 =
2|VA |
|VA |
=
I /2
I
Thus,
I
1 2|VA |
|VA |
I
×2×
× ×
×
VOV
2
I
VOV
I
2
VA
=2
Q.E.D.
VOV
CMRR =
(b) Current source is implemented with the
modified Wilson mirror in Fig. P8.82:
RSS = gm7 ro7 ro9
Transistor Q7 has the same k (W/L) as Q1 and Q2 ,
but Q7 carries a current I twice that of Q1 and Q2 .
Thus
√
√
VOV 7 = 2VOV 1,2 = 2VOV
Chapter 8–34
and
gm7
√
2I
2I
2I
=
= √
=
VOV 7
V
2VOV
OV
VA
ro7 = ro9 =
I
Thus,
√ 2
√ 2
2I VA
2VA
RSS =
=
VOV
I
VOV I
and
√ 2
1 2|VA |
I
I
2VA
× ×
×2×
×
CMRR =
VOV
2
I
VOV
VOV I
√
VA 3
=2 2
Q.E.D.
VOV
For k (W/L) = 4 mA/V and I = 160 μA,
1+
1
gm ro3
1
= 0.98 A/A
1+
1 × 50
Am = 1
=1
Rom = ro4 = 50 k
Ro2 = ro2 + 2RSS + 2gm2 ro2 RSS
= 50 + 50 + 2 × 1 × 50 × 25
= 2600 k
Acm = −(1 − Am )Gmcm (Rom Ro2 )
Acm = −(1 − 0.98) × 0.02 × (50 2600)
= −0.0196 V/V
CMRR =
2
25
Ad
= 1274
=
Acm
0.0196
or 62.1 dB
1
× 4 × |VOV |2
2
⇒ |VOV | = 0.2 V
Alternatively, using the approximate expression
in Eq. (8.157), we obtain
For |VA | = 5 V:
Acm −
0.080 =
For case (a),
CMRR = 2 ×
5
0.2
and
2
= 1250 or 62 dB
CMRR =
25
= 1250
0.02
or 61.9 dB
For case (b),
√
CMRR = 2 2
1
1
= −0.02 V/V
=−
2gm3 RSS
2 × 1 × 25
5
0.2
3
= 4.42 × 104
8.98 CMRR =
or 93 dB
Ad
Acm
CMRR = 60 dB or equivalently 1000. Thus,
8.97 Gm = gm1,2
ro2
2(I /2)
0.2
= 1 mA/V
=
=
VOV
0.2
5
|VA |
= ro4 =
=
= 50 k
I /2
0.1
1000 =
50
| Acm |
⇒ | Acm | = 0.05 V/V
But from Eq. (8.153), we obtain
Ro = ro2 ro4 = 50 k 50 k
| Acm | = (1 − Am )Gmcm (Rom Ro2 )
= 25 k
Since Rom
Ad = Gm Ro = 1 × 25 = 25 V/V
| Acm | = (1 − Am )
5
|VA |
=
= 25 k
I
0.2
1
1
= 0.02 mA/V
=
=
2RSS
2 × 25
RSS =
Gmcm
Rim =
Ro2 and Gmcm = 1/2RSS , we have
Rom
2RSS
0.05 = (1 − Am ) ×
20
2 × 20
⇒ (1 − Am ) = 0.1
1
ro3
gm3
where
gm3 = gm1 = gm2 = 1 mA/V
8.99 From Eq. (8.153), we have
Acm = −(1 − Am )Gmcm (Rom Ro2 )
ro3 = ro2 = ro4 = 50 k
where
Rim = 1 k 50 k = 0.98 k
Gmcm =
1
1
=
= 0.011 mA/V
2RSS
2 × 45
Chapter 8–35
Using the fact that Ro2
Rom , we obtain
IB =
Acm −(1 − 0.98) × 0.011 × 45
The lower limit on VICM is determined by the
lowest voltage allowed at the collector of Q5
while Q5 is in the active mode. This voltage is
−5 + 0.3 = −4.7 V. Thus
= −0.01 V/V
CMRR =
0.125 mA
I /2
= 1.25 μA
β +1
100
30
Ad
= 3000
=
Acm
0.01
VICM min = −4.7 + VBE1,2 = −4.7 + 0.7
or 69.5 dB
= −4 V
8.100
The upper limit on VICM is determined by the
need to keep Q1 in the active mode. Thus
VCC 5 V
VICM max = VC1 + 0.4
= 4.3 + 0.4 = 4.7 V
Q3
Q4
Thus the input common-mode range is
vO
Q2
Q1
−4 V ≤ VICM ≤ +4.7 V
The common-mode gain can be found using Eq.
(8.165):
Acm = −
R
I
I
Q6
Q5
ro4
β3 REE
Here,
ro4 =
|VA |
100
=
= 800 k
I /2
0.125
β3 = 100
REE = ro5 =
5 V
Gm = gm1,2
I /2
VT
I /2
5=
VT
Thus
Acm = −
800
= −0.02 V/V
100 × 400
The CMRR can be found as
CMRR =
⇒ I = 0.25 mA
Utilizing two matched transistors, Q5 and Q6 , the
value of R can be found from
0 − (−5) − 0.7
= 0.25 mA
I=
R
⇒ R = 17.2 k
β
100
= 40 k
=2×
Rid = 2rπ = 2
gm
5
Ro = ro2 ro4
|VA |
100
=
= 400 k
I
0.25
| Ad |
2000
=
= 100,000
| Acm |
0.02
or 100 dB
8.101 See figure on next page.
From the solution to Problem 8.100, we know
that I = 0.25 mA. For the Widlar current source,
use R = 2 k. Thus
IREF =
5 − 0.7
= 2.15 mA
2
Ro = 800 k 800 k = 400 k
The value of RE can be found from
IREF
IRE = VBE6 − VBE5 = VT ln
I
2.15
0.25 × RE = 0.025 ln
0.25
Ad = Gm Ro = 5 × 400 = 2000 V/V
RE = 215 where
|VA |
100
=
= 800 k
ro2 = ro4 =
I /2
0.125
thus
Chapter 8–36
5 V
Ro = 200 k 200 k = 100 k
Ad = Gm Ro = 8 × 100 = 800 V/V
Rid = 2rπ = 2β/gm
Q3
Q4
vO
Q2
Q1
R
300
= 37.5 k
8
|VA |
40
=
= 100 k
REE =
I
0.4
The common-mode gain can be found
=
I
IREF
using Eq. (8.165):
ro4
Acm = −
β3 REE
=−
Q6
Q5
RE
5 V
200
= −0.013 V/V
150 × 100
The CMRR can be obtained from
800
| Ad |
=
= 60,000
CMRR =
| Acm |
0.013
or 96 dB
Gv =
The output resistance of the Widlar current source
is given by Eq. (7.102). Thus
=
REE = [1 + gm5 (RE rπ 5 )]ro5
where
gm5
I
0.25 mA
= 10 mA/V
=
=
VT
0.025 V
rπ 5 =
β
100
= 10 k
=
gm5
10
100
VA
=
= 400 k
I
0.25
= [1 + 10(0.215 10)] × 400
Rid
× Ad
Rid + Rsig
37.5
× 800 = 444.4 V/V
37.5 + 30
8.103 Refer to Fig. P8.103. To determine the bias
current I , which is the drain current of Q7 , we
analyze the Wilson mirror circuit as follows: All
four transistors, Q5 – Q8 , are conducting equal
currents (I ) and have the same VGS ,
VGS = Vt + VOV
ro5 =
Thus
REE
IR = 15 − (−5) − 2 VGS
= 1.24 M
144I = 20 − 2 Vt − 2 VOV
Rid , Ro , Ad , IB , and the range of VICM will be the
same as in Problem 8.100. The common-mode
gain, however, will be lower:
ro4
Acm = −
β3 REE
But
=−
800
= 6.45 × 10−3 V/V
100 × 1240
and the CMRR will be
2000
| Ad |
= 3.1 × 105
=
CMRR =
| Acm |
6.45 × 10−3
or 110 dB
8.102 Gm = gm1,2 I=
1 2
k (W/L)VOV
2 n
1
2
2
× 2 × VOV
= VOV
2
Thus
=
2
= 20 − 2 × 0.7 − 2VOV
144 VOV
2
144 VOV
+ 2VOV − 18.6 = 0
⇒ VOV = 0.35 V
and
I /2
0.2
= 8 mA/V
=
VT
0.025
I = 0.352 = 0.12 mA
(a) Rid = 2rπ = 2β/gm
Ro = ro2 ro4
where
|VA |
40
ro2 = ro4 =
=
= 200 k
I /2
0.2
gm = gm1,2 I /2
0.06
=
= 2.4 mA
VT
0.025
Chapter 8–37
2 × 100
= 83.3 k
2.4
(b) Ad = gm1,2 Ro
Rid =
ro2 = ro4 =
60
|VA |
=
= 60 k
I /2
1
Ro = 60 k 60 k = 30 k
where
Ad = 40 × 30 = 1200 V/V
Ro = ro2 ro4
(c) Acm can be found using Eq. (8.165),
ro4
Acm = −
β3 REE
But
ro2 = ro4 =
|VA |
60
=
= 1 M
I /2
0.06
Ro = 500 k
where
|VA |
60
=
= 30 k
I
2
60
= −0.02 V/V
=−
100 × 30
REE = ro5 =
Ad = 2.4 × 500 = 1200 V/V
(c) Acm can be found from Eq. (8.165):
ro4
Acm = −
β3 REE
Acm
where REE is the output resistance of the Wilson
mirror,
or 95.6 dB
REE = gm7 ro7 ro5
1200
| Ad |
=
= 60, 000
| Acm |
0.02
CMRR =
8.105 Refer to Fig. 8.40.
where
gm7 =
2I
2 × 0.12
=
VOV
0.35
= 0.7 mA/V
60
|VA |
=
= 500 k
ro7 = ro5 =
I
0.12
REE = 0.7 × 5002 = 175 M
Acm = −
1
= 5.7 × 10−5 V/V
100 × 175
1200
| Ad |
= 21 × 106
=
CMRR =
| Acm |
5.7 × 10−5
or 146 dB
8.104 Refer to Fig. P8.104. To determine the bias
current I , which is the current in the collector of
Q5 , we first find the reference current through the
6.65-k resistor:
9 − (−5) − 0.7
= 2 mA
IREF =
6.65
Assuming Q5 and Q6 are matched, we have
I = 2 mA
(a) gm1,2
I /2
1 mA
= 40 mA/V
=
VT
0.025 V
Rid = 2rπ = 2β/gm1,2
2 × 100
= 5 k
40
(b) Ad = Gm Ro
=
W6 can be determined using Eq. (8.172):
(W/L)7
(W/L)6
=2
(W/L)4
(W/L)5
(60/0.5)
(W /0.5)6
=2
(10/0.5)
(60/0.5)
⇒ W6 = 20 μm
For all devices we can evaluate ID as follows:
ID8 = IREF = 225 μA
ID5 = IREF
(W/L)5
= IREF = 225 μA
(W/L)8
I = ID5 = 225 μA
1
ID5 = 112.5 μA
2
= ID1 = 112.5 μA
ID1 = ID2 =
ID3 = ID4
ID6 = ID7 = IREF = 225 μA
With ID in each device known, we can use
1
W
|VOVi |2
IDi = μCox
2
L i
to determine |VOVi | and then
|VGSi | = |VOVi | + |Vt |
The values of gmi and roi can then be determined
from
2IDi
gmi =
|VOVi |
|VA |
IDi
where
roi =
Gm = gm1,2 = 40 mA/V
A1 = −gm1 (ro2 ro4 )
Ro = ro2 ro4
= −0.9 × (80 80) = −36 V/V
Chapter 8–38
The results for Problem 8.105 are summarized in the following table.
Q1
Q5
Q6
Q7
Q8
112.5 112.5 112.5 112.5
225
225
225
225
|VOV | (V)
0.25
0.25
0.25
0.25
0.25 0.25 0.25 0.25
|VGS | (V)
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
gm (mA/V)
0.9
0.9
0.9
0.9
1.8
1.8
1.8
1.8
ro (k)
80
80
80
80
40
40
40
40
ID (μA)
Q2
Q3
Q4
A2 = −gm6 (ro6 ro7 )
Thus
= −1.8 × (40 40) = −36 V/V
200 =
= −1.5 + 1 − 0.75 = −1.25 V
1
W
μn Cox
V2
2
L 5,7,8 OV
W
1
= × 400 ×
× 0.04
2
L 5,7,8
W
W
W
=
=
= 25
L 5
L 7
L 8
1
W
|VOV |2
ID6 = 200 = μp Cox
2
L 6
W
1
200 = × 100 ×
× 0.04
2
L 6
W
= 100
L 6
Thus
The results are summarized in the following table:
A0 = A1 A2 = −36 × −36 = 1296 V/V
The upper limit of VICM is determined by the need
to keep Q5 in saturation, thus
VICM max = VDD − |VOV 5 | − |VSG1 |
= 1.5 − 0.25 − 1 = +0.25 V
The lower limit of VICM is determined by the need
to keep Q1 and Q2 in saturation, thus
VICM min = VG3 − |Vt |
= −VSS + |VGS3 | − |Vt |
−1.25 V ≤ VICM ≤ +0.25 V
The output voltage range is
−VSS + VOV 6 ≤ v O ≤ VDD − |VOV 7 |
Transistor Q1
W/L
Q2 Q3 Q4 Q5 Q6 Q7 Q8
12.5 12.5 50 50 25 100 25 25
that is,
−1.25 V ≤ v O ≤ +1.25 V
Ideally, the dc voltage at the output is zero.
(b) The upper limit of VICM is determined by the
need to keep Q1 and Q2 in saturation, thus
1
W
μn Cox
V2
2
L 1,2 OV
W
1
100 = × 400 ×
× 0.04
2
L 1,2
W
W
=
= 12.5
⇒
L 1
L 2
1
W
|VOV |2
ID3 = ID4 = 100 = μp Cox
2
L 3,4
1
W
100 = × 100 ×
× 0.04
2
L 3,4
W
W
=
= 50
⇒
L 3
L 4
8.106
(a) ID1 = ID2 = 100 =
ID5 = ID7 = ID8 = 200 μA
VICM max = VD1 + Vt
= VDD − |VSG4 | + Vt
= 0.9 − |Vt | − |VOV 4 | + Vt
= 0.9 − 0.2 = +0.7 V
The lower limit of VICM is determined by the need
to keep Q5 in saturation,
VICM min = −0.9 + |VOV 5 | + |VGS1 |
= −0.9 + 0.2 + 0.2 + 0.4 = −0.1 V
Thus
−0.1 V ≤ VICM ≤ +0.7 V
(c) v Omax = VDD − |VOV 6 |
= 0.9 − 0.2 = +0.7 V
Chapter 8–39
v Omin = −VSS + |VOV 7 |
= IREF
= −0.9 + 0.2 = −0.7 V
(48/0.8)
(40/0.8)
= 90 × 1.2 = 108 μA
Thus
−0.7 V ≤ v O ≤ +0.7 V
Thus ID7 will exceed ID6 by 18 μA, which will
result in a systematic offset voltage,
(d) A1 = −gm1,2 (ro2 ro4 )
VO = 18 μA(ro6 ro7 )
where
where
2 × 0.1
gm1,2 =
= 1 mA/V
0.2
6
|VA |
ro2 = ro4 =
=
= 60 k
0.1 mA
0.1
ro6 = 111 k
and ro7 now becomes
10
= 92.6 k
0.108
A1 = −1 × (60 60) = −30 V/V
ro7 =
A2 = −gm6 (ro6 ro7 )
Thus
where
VO = 18 × 10−3 × (111 92.6)
2 × 0.2
= 2 mA/V
0.2
6
|VA |
=
= 30 k
ro6 = ro7 =
0.2
0.2
= 909 mV
gm6 =
The corresponding input offset voltage will be
VOS =
A2 = −2 × (30 30) = −30 V/V
A0 = A1 A2 = 30 × 30 = 900 V/V
=
8.107 (a) Increasing (W/L)1 and (W/L)2 by a
factor of 4 reduces |VOV 1,2 | by a factor of 2. Thus
gm1,2 = 2ID /|VOV 1,2 | increase by a factor of 2.
909
= 0.82 mV
1109
8.109
(a) With the two input terminals connected to a
dc voltage of VDD /2 = +0.6 V and for Q1 − Q4 to
conduct a current of 200 μA, we have
1
W
ID1,2 = k n
V2
2
L 1,2 OV
1
W
200 = × 540 ×
× 0.152
2
L 1,2
W
⇒
= 32.9
L 1,2
(b) A1 is proportional to gm1,2 , thus A1 increases
by a factor of 2 and the overall voltage gain
increases by a factor of 2.
(c) Since the input offset voltage is proportional
to |VOV 1,2 |, it will decrease by a factor of 2. This,
however, does not apply to VOS due to Vt .
8.108 If (W/L)7 becomes 48/0.8, ID7 will become
ID7 = ID8
VO
A0
(W/L)7
(W/L)8
This figure belongs to Problem 8.109.
VDD 1.2 V
Q3
Q4
Q6
Q1
Q2
vo
IREF 200 A
Q8
Q5
Q7
Chapter 8–40
1 W
|VOV |2
kp
2
L 3,4
1
W
200 = × 100 ×
× 0.152
2
L 3,4
W
⇒
= 178
L 3,4
Thus
ID3,4 =
0.65 V ≤ VICM ≤ 1.05 V
Note that the input dc voltage in part (a) falls
outside the allowable range of VICM ! Thus, part (a)
should have specified a VICM greater than 0.65 V.
The results of part (a), however, will not change.
Transistor Q5 must carry a current of 400 μA, thus
1
W
400 = k n
V2
2
L 5 OV
W
1
= × 540 ×
× 0.152
2
L 5
W
⇒
= 65.8
L 5
(c) 0.15 V ≤ v O ≤ (1.2 − 0.15)
that is,
0.15 V ≤ v O ≤ 1.05 V
Similarly, Q7 is required to conduct a current of
400 μA, thus
W
W
=
= 65.8
L 7
L 5
Q4
Q5
Q6
Q7
|VA |
1.8
=
= 9 k
0.2 mA
0.2
gm6 =
2 × 0.4
= 5.33 mA/V
0.15
ro6 = ro7 =
1.8
|VA |
=
= 4.5 k
0.4 mA
0.4
A2 = −gm6 (ro6 ro7 )
= −5.33(4.5 4.5) = 12 V/V
A0 = A1 A2 = −12 × −12 = 144 V/V
8.110 Refer to Fig. P8.110.
The results are summarized in the following table:
Q3
ro2 = ro4 =
= −12 V/V
Finally, Q6 must conduct a current equal to that of
Q7 , that is, 400 μA, thus
1
W
400 = × 100 ×
× 0.152
2
L 6
W
⇒
= 356
L 6
Q2
2 × 0.2
= 2.67 mA/V
0.15
A1 = −gm1,2 (ro2 ro4 ) = 2.67(9 9)
Transistor Q8 conducts a current of 200 μA, thus
W
1 W
=
= 32.9
L 8
2 L 5
Transistor Q1
(d) gm1,2 =
(a) With the inputs grounded and the output
at 0 V dc, we have
Q8
IE1 = IE2 =
1
× 0.4 = 0.2 mA
2
ID (μA)
200 200 200 200 400 400 400 200
IE3 = IE4 0.2 mA
W/L
32.9 32.9 178 178 65.8 356 65.8 32.9
IE5 0.5 mA
IE6 = 1 mA
(b) The upper limit on VICM is determined by the
need to keep Q1 and Q2 in saturation, thus
(b) The short-circuit transconductance of the first
stage is
VICM max = VD1,2 + |Vt |
Gm = gm1,2 =
= VDD − |Vt | − |VOV | + |Vt |
= 1.2 − 0.15 = 1.05 V
The lower limit on VICM is determined by the
need to keep Q5 in saturation, thus
VICM = |VOV 5 | + VGS1,2
= 0.15 + 0.15 + 0.35 = 0.65 V
IC1,2
0.2 mA
= 8 mA/V
VT
0.025 V
The voltage gain of the first stage can be obtained
by multiplying Gm by the total resistance at the
output node of the stage, i.e., the common
collectors of Q2 and Q4 and the base of Q5 . Since
ro2 = ro4 = ∞, the resistance at this node is equal
to the input resistance of Q5 which is Rπ5 ,
rπ5 =
β
gm5
Chapter 8–41
where
gm5 =
IC5
0.5
=
= 20 mA/V
VT
0.025
ic3
5 k
thus
rπ 5
ib3
Q3
100
=
= 5 k
20
v b5
= −Gm rπ 5
v id
= −8 × 5 = −40 V/V
The voltage gain of the second stage is
A2 ≡
v c5
= −gm5 RC
v b5
where RC5 is the total resistance in the collector of
Q5 . Since ro5 = ∞, RC5 is simply the input
resistance of the emitter follower Q6 , we have
RC5 = Ri6 = (β + 1)(re6 + RL )
where
re6 =
VT
25 mV
= 25 =
IE6
1 mA
Ri6 = (100 + 1)(0.025 + 1)
= 103.5 k
Q4
ic1
Thus the voltage gain of the first stage is given by
A1 ≡
5 k
25 ib1
vid
25 Q2
Q1
50 50 50 Rin
Rin = (β + 1)(4 × 50 )
= 101 × 200 20 k
ic1
= β1 = 100
ib1
ib3
(5 + 5)
10
=
=
= 0.5
ic1
(5 + 5) + Rin2
10 + 10
ic3
= β3 = 100
ib3
Thus
Thus
A2 = −20 × 103.5 = −2070 V/V
ic3
ic3
ib3
ic1
=
×
×
= 100 × 0.5 × 100
ib1
ib3
ic1
ib1
The gain of the third stage is given by
= 5000 A/A
A3 =
vo
RL
1
= 0.976 V/V
=
=
v5
RL + re6
1 + 0.025
The overall voltage gain can now be obtained as
A0 ≡
50 vo
= A1 A2 A3
v id
= −40 × −2070 × 0.976 = 8.07 × 104 V/V
8.112 Refer to Fig. 8.41. From Example 8.7, we
obtain
IC1 = IC2 = 0.25 mA
IC4 = IC5 = 1 mA
IC7 = 1 mA
8.111 See figure.
Rin2 = 2(β + 1)(25 + 25)
= 2 × 101 × 50 10 k
Effective load of first stage = Rin2 (5 + 5)
= 10 10 = 5 k
A1 =
α
Total resistance between collectors of Q1 and Q2
Total resistance in emitters of Q1 and Q2
5 k
= 25 V/V
4 × 50 IC8 = 5 mA
Thus
re1 = re2 25 mV
= 100 0.25 mA
re4 = re5 =
25 mV
= 25 1 mA
With 100- resistance in the emitter of each of
Q1 and Q2 , we have
Rid = (β + 1)(2re1,2 + 2Re1,2 )
= 101 × (2 × 0.1 + 2 × 0.1)
= 40.4 k
Chapter 8–42
Thus, Rid increases by a factor of 2. With 25-
resistance in the emitter of each of Q4 and Q5 , the
input resistance of the second stage becomes
Thus the gain of the third stage now becomes
Ri2 = (β + 1)(2re4,5 + 2Re4,5 )
−130.5 V/V
= 101 (2 × 0.025 + 2 × 0.025)
and the overall voltage gain increases to
= 10.1 k
vo
130.5
= 1.73 × 105 V/V
= 8513 ×
v id
6.42
Thus, Ri2 is increased by a factor of 2. The gain of
the first stage will be
v o1
=
v id
α × Total resistance between the collectors of Q1 and Q2
Total resistance in emitters of Q1 and Q2
40 k 10 k
= 20 V/V
2 × 0.1 + 2 × 0.1
Thus the gain of the first stage decreases but only
slightly. Of course, the two 100- resistances in
the emitters reduce the gain but some of the
reduction is mitigated by the increase in Ri2 ,
which increases the effective load resistance of
the first stage.
A3 = −α
(b) The output resistance now becomes
very large resistance
Ro = 3 k re8 +
β +1
3 k
When the amplifier is loaded with RL = 100 ,
RL
=
RL + Ro
100
1.73 × 105 ×
3000 + 100
Gv = 1.73 × 105
Gv = 5581 V/V
If the original amplifier is loaded in RL = 100 ,
Gv = 8513 ×
The gain of the second stage will now be
A2 =
v o2
3 k Ri3
= −α
v o1
2 × 0.025 + 2 × 0.025
From Example 8.8, Ri3 = 234.8 k, thus
A2 −
3 234.8
= −29.6 V/V
0.1
which is about half the value without the two
25- emitter resistances. The gain of the third
stage remains unchanged at −6.42 V/V, and the
gain of the fourth stage remains unchanged at
1 V/V. Thus the overall voltage gain becomes
303.5
2.3 + 0.025
100
= 3378 V/V
152 + 100
Thus, although the output resistance of the
original amplifier is much lower than that of the
modified one, the overall voltage gain realized
when the original amplifier is loaded in 100-
resistance is much lower than that obtained with
the modified design. Thus, replacing the 15.7-k
resistance with a constant-current source is an
excellent modification to make!
8.114 (a)
vo
= A1 A2 A3 A4
v id
= 20 × −29.6 × −6.42 × 1
= 3800.6 V/V
which is less than half the gain obtained without
the emitter resistances. This is the price paid for
doubling Rid .
8.113 Refer to Fig. 8.41. With R5 replaced with a
1-mA constant-current source with a high output
resistance, the total resistance in the collector of
Q7 now becomes the input resistance of Q8 ,
which is
Ri4 = (β + 1)(re8 + R6 )
= 101 × (0.005 + 3) = 303.5 k
Refer to Fig. (a) for the dc analysis. Replacing the
68 k-33 k divider network by its Thévenin
Chapter 8–43
equivalent, we obtain
VBB = −5 V +
IE3 =
33
× 10 V
33 + 68
= 2.1 mA
= −1.73 V
VO = −5 + 2.1 × 2.4 = 0 V
RBB = 68 k 33 k = 22.2 k
(b) Rin = 68 k 33 k rπ1
Now, we can determine IE1 from
IE1 =
=
0.824 − 0.7 − (−5)
5.6
2.4 +
101
where
VBB − (−5) − 0.7
RBB
4.7 +
β +1
−1.73 + 5 − 0.7
= 0.52 mA
22.2
4.7 +
101
IC1 = α1 × 0.52 = 0.99 × 0.52 0.52 mA
The collector current IC1 and the 8.2-k resistor it
feeds can be replaced by a Thévenin equivalent as
shown in Fig. (b). Thus
rπ1 =
β
gm1
gm1 =
IC1
0.52
=
= 20.8 mA/V
VT
0.025
rπ1 =
100
= 4.81 k
20.8
Rin = 68 k 33 4.81 4 k
5.6 k
Rout = 2.4 k re3 +
β +1
where
5V
0.74 V
8.2 k
VT
25 mV
=
= 11.9 IE3
2.1 mA
5.6
= 2.4 0.0119 +
101
re3 =
3.3 k
Rout
IE2
= 65.5 (c) Refer to Fig. (d)
Q2
IC2
(b)
IE2 =
5 − 0.74 − 0.7
8.2
3.3 +
101
= 1.05 mA
IC2 1.04 mA
The collector current IC2 and the 5.6-k
resistance it feeds can be replaced by a Thévenin
equivalent as shown in Fig. (c). Thus
ic1 = gm1 v i = 20.8v i
Ri2 = rπ2 =
β
gm2
where
gm2 =
IC2
1.04 mA
= 41.6 mA
=
VT
0.025 V
rπ2 =
100
= 2.4 k
41.6
ib2 = gm1 v i
8.2
= 16.1v i
8.2 + 2.4
Chapter 8–44
ic2 = β2 ib2 = 100 × 16.1v i = 1610v i
=
Ri3 = (β + 1)(re3 + 2.4 k)
= 101(0.0119 + 2.4) = 243.6 k
gm2
gm1
1
1
gm1 ro1
1+
Since gm1 ro
1,
gm2
1
1−
Ais gm1
gm1 ro1
1
= Ais |ideal 1 −
gm1 ro1
5.6
= 0.0225ic2
5.6 + 243.6
= 0.0225 × 1610v i = 36.18v i
ib3 = ic2 ×
ie3 = (β + 1)ib3
= 101 × 36.18 = 3654v i
v o = ie3 × 2.4 k
where
= 3654 × 2.4v i = 8770v i
Ais |ideal =
Thus
vo
= 8770 V/V
vi
Finally, from inspection,
Ro = ro2
8.115 From the figure we observe that the
controlled source gm1 v gs1 can be replaced by a
resistance 1/gm1 , thus
1
v gs1 = ii ro1 gm1
Ri ≡
gm2
gm1
v gs1
1
=
ro1
ii
gm1
iosc = gm2 v gs2 = gm2 v gs1 = gm2
8.116 (a) Refer to Fig. P8.116. The current ID in
each of the eight transistors can be found by
inspection. Then, gm of each transistor can be
determined as 2ID /|VOV | and ro as |VA |/ID . The
results are given in the table below:
(b) See figure on next page. Observe that at the
output node the total signal current is 4id where
1
ro1 ii
gm1
id = gm1,2
1
ro1
iosc
gm1
Ais ≡
= gm2
1
ii
+ ro1
gm1
=
v id
2
I
v id
2|VOV |
This figure belongs to Problem 8.115.
d2, g1, g2
iosc
ro1
ii
vgs1 vgs2
gm1vgs1
gm2vgs2
ro2
Ri
Ro
This table belongs to Problem 8.116.
Transistor
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
ID
I
2
I
2
I
2
I
2
I
2
I
I
2
I
gm
I
|VOV |
I
|VOV |
I
|VOV |
I
|VOV |
I
|VOV |
2I
|VOV |
I
|VOV |
2I
|VOV |
ro
2|VA |
I
2|VA |
I
2|VA |
I
2|VA |
I
2|VA |
I
|VA |
I
2|VA |
I
|VA |
I
Chapter 8–45
This figure belongs to Problem 8.116, part (b).
Q5
Q3
id
Q4
id
vid
2
Q1
id
Q6
2id
id
Q2
vid
2
vo
4vid
2id
0V
Q7
Q8
This figure belongs to Problem 8.116, part (c).
Q5
Q3
Q6
Q4
io6
io5
ro6
vo
ro8
ro5
Ro1
vicm
2RSS
vicm
2RSS
Ro2
1
( gm7 // ro7 (
io8
Q7
Q8
and since the output resistance is
Ro = ro6 ro8 =
1 |VA |
2 I
then
v o = 4 id Ro = 4 ×
I
1 |VA |
×
× v id
2|VOV | 2 I
Thus
Ad ≡
vo
|VA |
=
v id
|VOV |
Q.E.D.
(c) See figure. With v icm applied to both input
terminals, we can replace each of Q1 and Q2 with
an equivalent circuit composed of a controlled
current, v icm /2RSS in parallel with a very large
output resistance (Ro1 and Ro2 which are equal).
The resistances Ro1 and Ro2 will be much larger
than the input resistance of each of the mirrors
Q3 − Q5 and Q4 − Q6 and thus
we can neglect Ro1 and Ro2 altogether. The
short-circuit output current of the Q4 − Q6 mirror
will be
gm6
1
v icm
io6 =
1−
gm4
gm4 ro4 2RSS
v icm
|VOV |
= 1−
2|VA |
RSS
Chapter 8–46
and the output resistance will be ro6 . The
short-circuit output current of the Q3 − Q5 mirror
will be
gm5
1
v icm
io5 =
1−
gm3
gm3 ro3 2RSS
|VOV |
v icm
= 1−
2|VA |
2RSS
and the output resistance will be ro5 . Since ro5 is
much larger than the input resistance of the
Q7 − Q8 mirror ( 1/gm7 ), most of io5 will flow
into Q7 , resulting in an output short-circuit
current io8 :
gm8
1
1−
io8 =
io5
gm7
gm7 ro7
1
=2 1−
io5
gm7 ro7
|VOV |
v icm
1
= 1−
1−
2|VA |
gm7 ro7 RSS
and the output resistance is ro8 . Thus, at the
output node we have a net current
1
|VOV |
v icm
io6 − io8 = 1 −
2|VA |
gm7 ro7
RSS
v icm
1
gm7 ro7
RSS
This current flows into the output resistance
(ro6 ro8 ) and thus produces an output voltage
vo =
ro6 ro8
1
v icm
RSS
gm7 ro7
ro6 ro8 1
RSS gm7 ro7
Ad = |
|VA |
I
VA
|
VOV
1
|VA |/I
1
2
| Acm | =
|VA |/I [I /|VOV | ] [2|VA |/I ]
| Acm | =
1 1 |VOV |
1
×
=
2 2 |VA |
4
CMRR = 4
VA
VOV
VOV
VA
2
Q.E.D.
(e) The upper limit on VICM is determined by Q1
and Q2 remaining in saturation, thus
VICMmax = VDD − |VSG | + |Vt |
= VDD − |VOV |
The lower limit on VICM is determined by the
need to keep the bias current source in saturation,
i.e. maintaining a minimum voltage across it of
|VOV |, thus
VICMmin = −VSS + |VOV | + |VGS |
= −VSS + 2|VOV | + |Vt |
Thus
−VSS + |Vt | + 2|VOV | ≤ VICM ≤ VDD − |VOV |
and the common-mode gain becomes
| Acm | =
(d) RSS =
Q.E.D.
The output linear range is
VDD − |VOV | ≤ v O ≤ −VSS + |VOV |
Exercise 9–1
Ex: 9.1 AM = −
=−
RG
gm (RD RL )
RG + Rsig
10
× 2(10 10)
10 + 0.1
= −9.9 V/V
1
fP 1 =
2πCC 1 (Rsig + RG )
=
1
2π × 1 × 10−6 (0.1 + 10) × 106
= 0.016 Hz
fP 2 =
gm + 1/RS
2π CS
(2 + 0.1) × 10−3
=
= 334.2 Hz
2π × 1 × 10−6
1
fP 3 =
2πCC 2 (RD + RL )
=
1
2π × 1 × 10−6 (10 + 10) × 103
= 8 Hz
fZ =
=
1
2π CS RS
1
2π × 1 × 10−6 × 10 × 103
fL =
=
1
2π
1
2π
1
τC 1
+
1
τCE
+
1
τC 2
1
1
1
+
+
× 103
7.44 0.071 13
= 2.28 kHz
1
fZ =
2πCE RE
=
1
= 31.8 Hz
2π × 1 × 10−6 × 5 × 103
Since fZ is much lower than fL it will have a
negligible effect on fL .
Ex: 9.3 Cox =
ox
3.45 × 10−11 F/m
=
tox
10 × 10−9 m
= 3.45 × 10−3 F/m2
= 3.45 f F/μm2
Cov = WLov Cox
= 10 × 0.05 × 3.45 = 1.72 f F
Cgs =
2
WLCox + Cov
3
2
× 10 × 1 × 3.45 + 1.72
3
= 24.72 fF
=
= 15.9 Hz
Cgd = Cov = 1.72 f F
Since the highest-frequency pole is fP 2 = 334.2
and the next highest-frequency singularity is fZ at
15.9 Hz, the lower 3-dB frequency fL will be
Csb 0
10
Csb = = = 6.1 f F
VSB
1
1+
1+
V0
0.6
fL fP 2 = 334.2 Hz
Cdb 0
10
= = 4.1 f F
Cdb = VDB
2+1
1+
1+
V0
0.6
Ex: 9.2 Refer to Fig. 9.10.
τC 1 = CC 1 [Rsig + (RB rπ )]
= 1 × 10−6 [5 + (100 2.5)] × 103
= 7.44 ms
RB Rsig
τCE = CE RE re +
β +1
β = gm rπ = 40 × 2.5 = 100
re 1/gm = 25 100 5
−6
× 103
5 0.025 +
τCE = 1 × 10
101
τCE = 0.071 ms
τC 2 = CC 2 (RC + RL )
= 1 × 10−6 (8 + 5) × 103
= 13 ms
Ex: 9.4 gm = 2k n (W/L)ID
= 2 × 0.16 × (10/1) × 0.1 = 0.566 mA/V
gm
fT =
2π(Cgs + Cgd )
=
0.566 × 10−3
2π(24.72 + 1.72) × 10−15
fT = 3.4 GHz
Ex: 9.5 Cde = τF gm
where
τF = 20 ps
gm =
IC
1 mA
=
= 40 mA/V
VT
0.025 V
Exercise 9–2
Thus,
fH =
Cde = 20 × 10−12 × 40 × 10−3 = 0.8 pF
1
2πCin (Rsig RG )
1
2π × 4.26 × 10−12 (0.01 4.7) × 106
Cje 2Cje 0
=
= 2 × 20 = 40 f F
= 3.7 MHz
Cπ = Cde + Cje
= 0.8 + 0.04 = 0.84 pF
1 × 106 =
20
⇒ Cin = 1.625 pF
= 0.33 = 12 f F
2
0.5
gm
fT =
2π(Cπ + Cμ )
1+
40 × 10−3
= 7.47 GHz
2π(0.84 + 0.012) × 10−12
Ex: 9.6 | hfe | = 10 at f = 50 MHz
Thus,
fT = 10 × 50 = 500 MHz
gm
Cπ + Cμ =
2πfT
=
40 × 10−3
2π × 500 × 106
= 12.7 pF
Cπ = 12.7 − 2 = 10.7 pF
Cin = Cgs + Cgd (1 + gm RL )
1.625 = 1 + Cgd (1 + 7.14)
⇒ Cgd = 0.08 pF
Ex: 9.10 To reduce the midband gain to half the
value found, we reduce RL by the same factor,
thus
RL = 1.5 k
But,
RL = ro RC RL
1.5 = 100 8 RL
⇒ RL = 1.9 k
Cin = Cπ + Cμ (1 + gm RL )
= 7 + 1(1 + 40 × 1.5)
= 68 pF
10.7 = Cde + 2
fH =
⇒ Cde = 8.7 pF
Since Cde is proportional to gm and hence IC , at
IC = 0.1 mA,
Cde = 0.87 pF
and
Cπ = 0.87 + 2 = 2.87 pF
4 × 10−3
= 130.7 MHz
2π(2.87 + 2) × 10−12
Ex: 9.8 AM = −
=−
RG
gm RL
RG + Rsig
4.7
× 7.14 = −7.12 V/V
4.7 + 0.01
1
2πCin (0.1 4.7) × 106
But,
Ex: 9.7 Cπ = Cde + Cje
fT =
1
2πCin (Rsig RG )
Cμ0
VCB m
1+
V0c
Cμ = =
Ex: 9.9 fH =
=
1
2πCin Rsig
1
2π × 68 × 10−12 × 1.65 × 103
= 1.42 MHz
Thus, by accepting a reduction in gain by a factor
of 2, the bandwidth is increased by a factor of
1.42/0.754 = 1.9, approximately the same factor
as the reduction in gain.
Ex: 9.11 ft = | AM | fH
2 × 109 =
12.5
2π(CL + Cgd ) × 10 × 103
⇒ CL + Cgd = 99.5 f F
CL = 99.5 − 5 = 94.5 f F
Exercise 9–3
1000
s
1+
2π × 105
Ex: 9.12 T (s ) =
ω
1+j
ωP 1
|T | =
1+
|T | =
1+
2= 1+
ωH
ωP 1
ω
ωP 1
AM
ω
1+j
ωP 2
1+
ω
ωP 2
2
| AM |
2
ω
ω 2
1+
ωP 1
k ωP 1
−4=0
The approximate value of ωH is obtained from
Eq. (9.77),
1
1
+
ωH 1
ωP2 1
4ωP2 1
1+
ωH
k ωP 1
17 ωH 2
1 ωH 4
+
16 ωP 1
16 ωP 1
4
2
ωH
ωH
+ 17
− 16 = 0
ωP 1
ωP 1
2
⇒ ωH = 0.95ωP 1
The approximate value of ωH is found from
Eq. (9.77):
1
1
ωH 1
+
ωP2 1
16ωP2 1
For ωH = 0.99ωP 1,
0.992
2 = (1 + 0.992 ) 1 +
k2
= 0.97ωP 1
⇒ k = 9.88
Ex: 9.15 Cin = Cgs + Cgd (1 + gm RL )
Ex: 9.14 2 = 1 +
For k = 1,
ωH 2
2= 1+
ωP 1
= 1+
2
=1+
⇒ k = 2.78
ωH
ωP 1
ωH
ωP 1
For k = 4, the exact value of ωH is obtained from
ωH 2
ωH 2
1+
2= 1+
ωP 1
4ωP 1
For ωH = 0.9ωP 1,
0.81
2 = (1 + 0.81) 1 + 2
k
+5
⇒ ωH = 0.89ωP 1
| AM |
2
2
4
⇒ ωH = 0.84ωP 1
GB = 1000 × 100 × 103 = 108 Hz
Ex: 9.13 T ( j ω) = ωH
ωP 1
2
ωH
ωP 1
2
1+
1+
ωH
ωP 1
ωH
k ωP 1
2
2
2
= 20 + 5(1 + 1.25 × 10)
= 87.5 f F
fH =
=
1
2πCin Rsig
1
2π × 87.5 × 10−15 × 10 × 103
= 181.9 MHz
This is greater than the value obtained in
Example 9.8, fH = 135.5 MHz, by 34%. The
value obtained in Example 9.8 is a better estimate
of fH as it takes into account the effect of CL .
⇒ ωH = 0.64ωP 1
The approximate value using Eq. (9.77) is
2
ωP 1
ωH 1
= √
ωP2 1
2
Ex: 9.16 | AM | = gm RL = 1.25 × 10 = 12.5 V/V
= 0.71ωP 1
GB = | AM | fH
For k = 2, the exact value of ωH is obtained from
ωH 2
ωH 2
1+
2= 1+
ωP 1
2ωP 1
= 12.5 × 135.5 = 1.69 GHz
=1+
5 ωH
4 ωP 1
2
+
1 ωH
4 ωP 1
4
Ex: 9.17 | AM | =
Rgs = 10 k
1
× 12.5 = 6.25 V/V
2
Exercise 9–4
(1 + gm RL ) + RL
Rgd = Rsig
= 10(1 + 6.25) + 5 = 77.5 k
RCL = RL = 5 k
τgs = Cgs Rgs = 20 × 10−15 × 10 × 103 = 200 ps
τgd = Cgd Rgd = 5×10−15 ×77.5×103 = 387.5 ps
τCL = CL RCL = 25 × 10−15 × 5 × 103 = 125 ps
τH = τgs + τgd + τCL
Ex: 9.19 (a) gm = 40 mA/V
rπ =
200
= 5 k
40
ron =
VAn
130
=
= 130 k
I
1
rop =
|VAp |
50
=
= 50 k
I
1
RL = ron rop = 130 50 = 36.1 k
AM = −
= 200 + 387.5 + 125
= 712.5 ps
=−
1
fH =
2πτH
rπ
gm RL
rπ + rx + Rsig
5
× 40 × 36.1
5 + 0.2 + 36
= −175 V/V
1
=
= 223.4 MHz
2π × 712.5 × 10−12
(b) Cin = Cπ + Cμ (1 + gm RL )
GB = 6.25 × 223.4 = 1.4 GHz
= 16 + 0.3(1 + 40 × 36.1)
Ex: 9.18 gm =
2μn Cox
= 450 pF
W
ID
L
Rsig
= rπ (rx + Rsig )
Since ID is increased by a factor of 4, gm doubles:
= 5 (0.2 + 36) = 4.39 k
gm = 2 × 1.25 = 2.5 mA/V
fH =
Since RL is ro /2, increasing ID by a factor of four
results in ro and hence RL decreasing by a factor
of 4, thus
RL =
1
× 10 = 2.5 k
4
| AM | = gm RL = 2.5 × 2.5 = 6.25 V/V
= 10 k
Rgs = Rsig
Rgd = Rsig
(1 + gm RL ) + RL
= 10(1 + 6.25) + 2.5
=
1
2πCin Rsig
1
2π × 450 × 10−12 × 4.39 × 103
= 80.6 kHz
(c) Rπ = Rsig
= 4.39 k
Rμ = Rsig
(1 + gm RL ) + RL
= 4.39(1 + 40 × 36.1) + 36.1
= 6.38 M
= 75 k
RCL = RL = 36.1 k
RCL = RL = 2.5 k
τH = Cπ + Cμ Rμ + CL RCL
τH = τgs + τgd + τCL
= 16 × 4.39 + 0.3 × 6.38 × 103 + 5 × 36.1
= Cgs Rsig
+ Cgd Rgd + CL RCL
= 70.2 + 1914 + 180.5
= 20 × 10−15 × 10 × 103 + 5 × 10−15 × 75
= 2164.7 ns
× 103 + 25 × 10−15 × 2.5 × 103
= 200 + 375 + 62.5
= 637.5 ps
fH =
1
= 250 MHz
2π × 637.5 × 10−12
GB = | AM | fH
= 6.25 × 250 = 1.56 GHz
fH =
1
2π × 2164.7 × 10−9
= 73.5 kHz
gm
(d) fZ =
2πCμ
=
40 × 10−3
= 21.2 GHz
2π × 0.3 × 10−12
(e) GB = 175 × 73.5 = 12.9 MHz
Exercise 9–5
Ex: 9.20 Rin =
R L + ro
1 + gm ro
500 + 20
=
= 20 k
1 + 25
Gv =
RL
500
= 16.7 V/V
=
Rsig + Rin
10 + 20
τH = Cgs Rsig + Cgd × 21Rsig
= Cgs Rsig + 0.25Cgs × 21Rsig
= 6.25Cgs Rsig
1
2π × 6.25Cgs Rsig
fH =
Rgs = Rsig Rin = 10 20 = 6.7 k
For the cascode amplifier,
Rgd = RL Ro
τH Rsig [Cgs 1 + Cgd 1 (1 + gm1 Rd 1 )]
= 500 280 = 179.5 k
where
τH = Cgs Rgs + (Cgd + CL )Rgd
Rd 1 = ro 1 Rin2 = ro = 20 × 10−15 × 6.7 × 103 + (5 + 25) × 10−15
× 179.5 × 103
= 134 + 5385
= 5519 ps
1
= 28.8 MHz
fH =
2π × 5519 × 10−12
2
ro
2
gm
= ro =
2
gm
+ ro
gm
ro
2ro
2ro
=
=
2 + gm ro
2 + 40
21
gm ro τH = Cgs Rsig 1 + 0.25 1 +
21
40
= Cgs Rsig 1 + 0.25 1 +
21
=
Thus, while the midband gain has been increased
substantially (by a factor of 9.7), the bandwidth
has been substantially lowered (by a factor of
9.4). Thus, the high-frequency advantage of the
CG amplifier is completely lost!
= 1.73Cgs Rsig
Ex: 9.21 (a) ACS = −gm (RL ro )
fH =
1
= −gm (ro ro ) = − gm ro
2
Thus,
1
= − × 40 = −20 V/V
2
Acascode = −gm (RL Ro )
ro + ro
gm ro
1
2π × 1.73 Cgs Rsig
6.25
fH (cascode)
=
= 3.6
fH (CS)
1.73
(c)
ft (cascode)
= 2 × 3.6 = 7.2
ft (CS)
= −gm (ro gm ro ro )
−gm ro = −40 V/V
Thus,
Acascode
=2
ACS
(b) For the CS amplifier,
τH = Cgs Rgs + Cgd Rgd
where
Rgs = Rsig
Rgd = Rsig (1 + gm RL ) + RL
Rsig (1 + gm RL )
1
= Rsig 1 + gm ro
2
1
= Rsig 1 + × 40 = 21Rsig
2
Ex: 9.22 gm = 40 mA/V
rπ =
β
200
= 5 k
=
gm
40
Rin = rπ + rx = 5 + 0.2 = 5.2 k
A0 = gm ro
= 40 × 130 = 5200 V/V
Ro 1 = ro 1 = 130 k
Rin2 = re 2
= 25
ro 2 + RL
ro 2 + RL /(β2 + 1)
130 + 50
50
130 +
201
= 35 Ro β2 ro 2 = 200 × 130 = 26 M
Exercise 9–6
AM = −
=−
rπ
gm (Ro RL )
rπ + rx + Rsig
5
40(26,000 50)
5 + 0.2 + 36
AM = −242 V/V
= rπ 1 (rx 1 + Rsig )
Rsig
= 5 (0.2 + 36) = 4.39 k
Rπ 1 = Rsig
= 4.39 k
Rc 1 = ro 1 Rin2
Ex: 9.24 From Example 9.11, we get
τH = b1 = 104 ps
fH =
=
1
2πτH
1
= 1.53 GHz
2π × 104 × 10−12
This is lower than the exact value found in
Example 9.11 (i.e., 1.86 GHz) by about 18%, still
not a bad estimate!
= 130 k 35 35 Rμ1 = Rsig
(1 + gm1 Rc 1 ) + Rc 1
= 4.39(1 + 40 × 0.035) + 0.035
= 10.6 k
τH = Cπ 1 Rπ 1 + Cμ1 Rμ1 + Cπ 2 Rc 1
+ (CL + Cμ2 )(RL Ro )
= 16 × 4.39 + 0.3 × 10.6 + 16 × 0.035
+ (5 + 0.3)(50 26,000)
Ex: 9.25 gm = 40 mA/V
re = 25 rπ =
= Rsig + rx = Rsig = 1 k
Rsig
RL = RL ro = 1 100 = 0.99 k
fH =
1
= 470 kHz
2π × 338.5 × 10−9
RL + re +
=
To have fH equal to 1 MHz,
1
1
=
= 159.2 ns
τH =
2π fH
2π × 1 × 106
Thus,
159.2 = 70.24 + 3.18 + 0.56
+ (CL + Cμ )(50 26000)
⇒ CL + Cμ = 1.71 pF
Thus, CL must be reduced to 1.41 pF.
Ex: 9.23 From Eq. (9.120), we obtain
Rgs =
Rsig
Rsig + RL
RL
+
=
gm RL + 1
gm RL + 1
gm RL + 1
Rgd = Rsig
RCL =
RL
gm RL + 1
=
Rsig
β +1
0.99
= 0.97 V/V
0.99 + 0.025 + (1/101)
Cπ + Cμ =
ft = | AM | fH = 242 × 470 = 113.8 MHz
Thus, in comparison to the CE amplifier of
Exercise 9.19, we see that | AM | has increased
from 175 V/V to 242 V/V, fH has increased from
73.5 kHz to 470 kHz, and ft has increased from
12.9 MHz to 113.8 MHz.
RL
AM =
= 70.24 + 3.18 + 0.56 + 264.5
= 338.5 ns
β
100
= 2.5 k
=
gm
40
gm
2πfT
40 × 10−3
2π × 400 × 106
= 15.9 pF
Cμ = 2 pF
Cπ = 13.9 pF
fZ =
1
1
=
2πCπ re
2π × 13.9 × 10−12 × 25
= 458 MHz
b1 =
Rsig
R
+ C +C
Rsig
1
+
RL
Cπ + Cμ 1 + L
π
L
re
rπ
Rsig
R
1+ L +
re
rπ
0.99
13.9 + 2 1 +
× 1 + (13.9 + 0)0.99
0.025
=
1
0.99
+
1+
0.025 2.5
= 2.66 × 10−9 s
b2 =
Cπ Cμ RL Rsig
13.9 × 2 × 0.99 × 1
=
0.99
1
Rsig
RL
1+
+
1+
+
0.025 2.5
rπ
re
= 0.671 × 10−18
Exercise 9–7
ωP 1 and ωP 2 are the roots of the equation
Ex: 9.28 Ad = gm1,2 (ro 2 ro 4 )
1 + b1 s + b 2 s = 0
where
Solving we obtain,
0.5
= 20 mA/V
0.025
100
= 200 k
ro 2 = ro 4 =
0.5
Ad = 20(200 200) = 2000 V/V
2
gm1,2 =
fP 1 = 67 MHz
fP 2 = 563 MHz
Since fP 1 fP 2,
The dominant high-frequency pole is that
introduced at the output node,
fH fP 1 = 67 MHz
Ex: 9.26 (a) ID 1,2 =
1
W
μn Cox
V2
2
L 1,2 OV
1
2
× 0.2 × 100VOV
2
⇒ VOV = 0.2 V
0.4 =
gm =
2ID
2 × 0.4
=
= 4 mA/V
VOV
0.2
(b) Ad = gm (RD ro )
where
VA
20
= 50 k
=
ro =
ID
0.4
Ad = 4(5 50) = 4 × 4.545
= 18.2 V/V
(c) fH =
=
2π(CL + Cgd
1
+ Cdb )(RD ro )
1
2π(100 + 10 + 10) × 10−15 × 4.545 × 103
= 292 MHz
(d) τgs = Cgs Rsig = 50 × 10 = 500 ps
τgd = Cgd Rgd = Cgd [Rsig (1 + gm RL ) + RL ]
= 10[10(1 + 18.2) + 4.545]
= 1965.5 ps
τCL = (CL + Cdb )RL = 110 × 4.545 = 500 ps
τH = τgs + τgd + τCL
= 500 + 1965.5 + 500 = 2965.5 ps
1
fH =
2π × 2965.5 × 10−12
= 53.7 MHz
Ex: 9.27 fZ =
=
fH =
=
1
2πCL (ro 2 ro 4 )
1
2π × 2 × 10−12 × 100 × 103
= 0.8 MHz
Ex: 9.29 (a) AM = −gm RL
where
RL = RL ro = 20 20 = 10 k
AM = −2 × 10 = −20 V/V
τH = Cgs Rgs + Cgd Rgd + CL RL
= Cgs Rsig + Cgd [Rsig (1 + gm RL ) + RL ] + CL RL
= 20 × 20 + 5[20(1 + 20) + 10] + 5 × 10
= 400 + 2150 + 50
= 2600 ps
fH =
=
1
2πτH
1
2π × 2600 × 10−12
= 61.2 MHz
GB = | AM | fH
= 20 × 61.2
= 1.22 GHz
(b) Gm =
gm
2
= 0.67 mA/V
=
1 + gm Rs
1+2
Ro ro (1 + gm Rs )
= 20 × 3 = 60 k
1
2π RSS CSS
1
2π × 75 × 103 × 0.4 × 10−12
= 5.3 MHz
Thus, the 3-dB frequency of the CMRR is
5.3 MHz.
RL = RL Ro = 20 60 = 15 k
AM = −Gm RL
= −0.67 × 15 = −10 V/V
Rgd = Rsig (1 + Gm RL ) + RL
= 20(1 + 10) + 15
= 235 k
Exercise 9–8
RCL = RL = 15 k
fP 2 =
Rsig + Rs + Rsig Rs /(ro + RL )
ro
1 + gm Rs
ro + RL
Rgs =
=
1
2πCμ RL
1
2π × 2 × 10−12 × 10 × 103
where
= 8 MHz
2
= 1 k
Rs =
gm
T (s ) = 20 × 1
20 + 1 +
20
+ 20
Rgs =
20
1+2×
20 + 20
s
1+
ωP 1
|T ( j ω)| =
1+
τH = Cgs Rgs + Cgd Rgd + CL RCL
= 20 × 10.75 + 5 × 235 + 5 × 15
= 215 + 1175 + 75 = 1465 ps
1
= 109 MHz
2π × 1465 × 10−12
GB = 10 × 109 = 1.1 GHz
Ex: 9.30 Refer to Fig. 9.42(b).
AM =
2rπ
1
× × gm RL
2rπ + Rsig
2
where
gm = 20 mA/V
100
= 5 k
rπ =
20
10
1
× × 20 × 10 = 50 V/V
AM =
10 + 10
2
fP 1 =
2π
=
1
Cπ
+ Cμ (2rπ Rsig )
2
1
6
2π
+ 2 × 10−12 (10 10) × 103
2
= 6.4 MHz
s
ωP 2
1+
= 10.75 k
fH =
50
ω
ωP 1
50
2
1+
ω
ωP 2
2
√
At ω = ωH , |T | = 50/ 2, thus
2= 1+
=1+
ωH
ωP 1
ωH
ωP 1
+ fH2
+
1+
2
ωH4
+ ωH2
2
ωP 1ωP2 2
fH4
2 2
fP 1fP 2
2
ωH
ωP 2
2
+
1
1
+ 2
ωP2 1
ωP 2
1
fP21
+
1
fP22
ωH
ωP 2
2
ωH
ωP 1
2 ωH
ωP 2
2
−1=0
−1=0
1
fH4
1
2
+
f
+
−1=0
H
6.42 × 82
6.42
82
⇒ fH = 4.6 MHz (Exact value)
Using Eq. (9.164), an approximate value for fH
can be obtained:
1
1
fH 1/
+ 2
fP21
fP 2
= 1/
1
1
+ 2 = 5 MHz
6.42
8
Chapter 9–1
9.1 Refer to Fig. 9.3(b).
Vg
=
Vsig
RG
RG + Rsig +
gm Vg YS
YS + gm
1
gm
+ sCS
Is
RS
=
1
Vg
gm +
+ sCS
RS
Is =
1
sCC1
where
RG = RG1 RG2 = 2 M 1 M = 667 k
and
= gm
Rsig = 200 k
Vg
RG
=
Vsig
RG + Rsig
Thus,
s
s+
1
CC1 (RG + Rsig )
1
2πCC1 (RG + Rsig )
gm + 1/RS
2πCS
fP2 =
fZ =
Thus,
fP1 =
s + 1/CS RS
gm + 1/RS
s+
CS
1
2πCS RS
where
We required
gm = 5 mA/V and RS = 1.8 k
fP1 ≤ 10 Hz
To make fP2 ≤ 100 Hz,
gm + 1/RS
≤ 100
2πCS
thus we select CC1 so that
1
≤ 10
2πCC1 (RG + Rsig )
CC1 ≥
5 × 10−3 + (1/1.8 × 103 )
= 8.8 μF
2π × 100
⇒ CS ≥
1
= 18.4 nF
2π × 10 × (667 + 200) × 103
Select CS = 10 μF.
Thus,
⇒ CC1 = 20 nF
5 × 10−3 + (1/1.8 × 103 )
= 88.4 Hz
2π × 10 × 10−6
fP2 =
9.2 Refer to Fig. 9.3(b).
and
RD
× RL
Vo = −Id
1
RD +
+ RL
sCC2
fZ =
RD RL
Vo
=−
Id
RD + RL
9.4 Refer to Fig. 9.3.
s
s+
1
CC2 (RD + RL )
1
2πCC2 (RD + RL )
fP3 =
1
= 8.84 Hz
2π × 10 × 10−6 × 1.8 × 103
AM = −
RG
× gm (RD RL )
RG + Rsig
where
where
RG = RG1 RG2 = 47 M 10 M
RD = 10 k and RL = 10 k
= 8.246 M
To make fP3 ≤ 10 Hz,
Rsig = 100 k, gm = 5 mA/V, RD = 4.7 k and
RL = 10 k.
1
≤ 10
2πCC2 (RD + RL )
⇒ CC2
1
≥
= 0.8 μF
2π × 10 × (10 + 10) × 103
Select, CC2 = 0.8 μF.
Thus,
AM = −
= −15.8 V/V
fP1 =
9.3 Refer to Fig. 9.3(b).
Is =
Vg
1
+ ZS
gm
8.426
× 5(4.7 10)
8.426 + 0.1
=
1
2πCC1 (RG + Rsig )
1
2π × 0.01 × 10−6 (8.426 + 0.1) × 106
= 1.9 Hz
Chapter 9–2
gm + 1/RS
2πCS
fP2 =
=
5 × 10−3 + 0.5 × 10−3
= 87.5 Hz
2π × 10 × 10−6
20 dB/decade
26 dB
20 log 20 26 dB
1
= 8 Hz
2π × 10 × 10−6 × 2 × 103
fP3 =
=
Gain, dB
1
2πCS RS
fZ =
=
(e) The Bode plot for the gain is shown in Fig. 2.
6 dB
1
2πCC2 (RD + RL )
f 10 Hz f 100 Hz
1
= 10.8 Hz
2π × 1 × 10−6 (4.7 + 10) × 103
Since
fP2 fP1 , fP3 , fZ ,
fL fP2 = 87.5 Hz
Figure 2
Observe that the dc gain is 6 dB, i.e. 2 V/V. This
makes perfect sense since from Fig. 1 we see that
at dc, capacitor CS behaves as open circuit and the
gain becomes
DC gain = −
9.5
Vo
f (log scale)
10 k
RD
= −
1
1
+ RS
+ 4.5
gm
2
= −2 V/V
Id I s
RD
1
gm
Is
Vi
RS
9.6 See figure on next page. Replacing the
MOSFET with its T model results in the circuit
shown in the figure.
AM = −
CS
=−
RG
× gm (RD RL )
RG + Rsig
2
× 3(20 10)
2 + 0.5
= −16 V/V
Figure 1
Replacing the MOSFET with its T model results
in the circuit shown in Fig. 1.
(a) AM ≡
Vo
= −gm RD
Vi
−20 = −2 × RD
⇒ RD = 10 k
(b) fP =
100 =
gm + 1/RS
2πCS
2 × 10−3 + (1/4.5 × 103 )
2πCS
⇒ CS = 3.53 μF
(c) fZ =
1
=
2πCS RS
To minimize the total capacitance we select CS so
as to place fP2 (usually the highest-frequency
low-frequency pole) at 100 Hz. Thus,
gm
100 =
2πCS
=
3 × 10−3
2πCS
⇒ CS = 4.8 μF
Select CS = 5 μF.
Of the two remaining poles, the one caused by
CC2 has associated relatively low-valued
resistances (RD and RL are much lower than RG ),
thus to minimize the total capacitance we place
fP3 at 10 Hz and fP1 at 1 Hz. Thus,
10 =
1
2πCC2 (RD + RL )
1
2πCC2 (20 + 10) × 103
1
= 10 Hz
2π × 3.53 × 10−6 × 4.5 × 103
≡
(d) Since fP fZ ,
⇒ CC2 = 0.53 μF
fL fP = 100 Hz
Select CC2 = 1 μF.
Chapter 9–3
This figure belongs to Problem 9.6.
CC2
Vo
Id Is
Rsig
Vsig
1=
0
CC1
Is
1
1=
2πCC1 (2 + 0.5) × 106
⇒ CC1 = 63.7 nF
Select CC1 = 100 nF = 0.1 μF.
With the selected capacitor values, we obtain
fP2
1
= 0.64 Hz
2π × 0.1 × 10−6 × 2.5 × 106
3 × 10−3
=
= 95.5 Hz
2π × 5 × 10−6
fZ = 0 (dc)
fP3
1
=
= 5.3 Hz
2π × 1 × 10−6 (20 + 10) × 103
Since fP2 fP1 and fP3 , we have
fL fP2 = 95.5 Hz
9.7 The amplifier in Fig. P9.7 will have the
equivalent circuit in Fig. 9.9 except with RE = ∞
(i.e. omitted). Also, the equivalent circuits in
Fig. 9.10 can be used to determine the three
short-circuit time constants, again with RE = ∞.
Since the amplifier is operating at
IC IE = 100 μA = 0.1 mA and β = 100,
25 mV
= 250 0.1 mA
gm =
0.1 mA
= 4 mA/V
0.025 V
rπ =
β
100
=
= 25 k
gm
4
RL
1/gm
CS
To make CE responsible for 80% of fL , we use
1
= 0.8 ωL = 0.8 × 2πfL
τCE
⇒ τCE =
Using the equivalent circuit in Fig. 9.10(b), we get
RB Rsig
τCE = CE re +
β +1
1
2 ms
0.8 × 2π × 100
Thus,
(200 20) × 103
= 2 × 10−3
CE 250 +
101
⇒ CE = 4.65 μF
Select, CE = 5 μF.
Using the information in Fig. 9.10(a), we
determine τC1 as
τC1 = CC1 [(RB rπ ) + Rsig ]
To make the contribution of CC1 to the
determination of fL equal to 10%, we use
1
= 0.1ωL = 0.1 × 2πfL
τC1
⇒ τC1 =
re =
Io
RG
1
2πCC1 (RG + Rsig )
fP1 =
RD
1
= 15.92 ms
0.1 × 2π × 100
Thus,
CC1 [(200 25) × 103 + 20 × 103 ] = 15.92 × 10−3
⇒ CC1 = 0.38 μF
Select CC1 = 0.5 μF.
For CC2 we use the information in Fig. 9.10(c) to
determine τC2 :
τC2 = CC2 (RC + RL )
To make the contribution of CC2 to the
determination of fL equal to 10%, we use
1
= 0.1ωL = 0.1 × 2πfL
τC2
⇒ τC2 =
1
= 15.92 ms
0.1 × 2π × 100
Chapter 9–4
Thus,
−3
CC2 (20 + 10) × 10 = 15.92 × 10
3
⇒ CC2 = 0.53 μF
Although, to be conservative we should select
CC2 = 1 μF; in this case we can select
CC2 = 0.5 μF
because the required value is very close to 0.5 μF
and because we have selected CC1 and CE larger
than the required values. The resulting fL will be
1
1
1
1
fL =
+
+
2π τCE
τC1
τC2
(200 20) × 103
τCE = 5 × 10−6 × 250 +
101
= 2.15 ms
τC1 = 0.5 × 10−6 [(200 25) × 103 + 20 × 103 ]
= 21.1 ms
τC2 = 0.5 × 10−6 (20 + 10) × 103 = 15 ms
3
10
103
103
1
fL =
+
+
2π 2.15 21.1
15
= 92.2 Hz
which is lower (hence more conservative) than
the required value of 100 Hz.
Ctotal = 5 + 0.5 + 0.5 = 6.0 μF
Using the method of short-circuit time constants
and the information in Fig. 9.10, we obtain
τC1 = CC1 [(RB rπ ) + Rsig ]
= CC1 (Rin + Rsig )
= 1 × 10−6 (5.7 + 5) × 103 = 10.7 ms
RB Rsig
τCE = CE RE re +
β +1
= 20×
10
−6
Rin = RB1 RB2 rπ
where
RB1 = 33 k, RB2 = 22 k
IC
0.3 mA
= 12 mA/V
=
VT
0.025 V
gm =
VT
25 mV
re =
= 83.3 =
IE
0.3 mA
rπ =
β
120
= 10 k
=
gm
12
Thus,
Rin = 33 22 10 = 5.7 k
Rin
AM = −
gm (RC RL )
Rin + Rsig
3.9 × 10 (33 22 5) × 103
83.3 +
121
τC2 = CC2 (RC + RL )
= 1 × 10−6 (4.7 + 5.6) × 103 = 10 ms
1
1
1
1
fL +
+
2π τC1
τCE
τC2
1
1
1
1
=
+
+
2π 10.7 × 10−3
2.2 × 10−3
10.3 × 10−3
= 102.7 Hz
9.9 Refer to the data given in the statement for
Problem 9.8.
RB = RB1 RB2 = 33 k 22 k = 13.2 k
IC IE 0.3 mA
gm =
IC
0.3 mA
=
= 12 mA/V
VT
0.025 V
re =
VT
25 mV
= 83.3 =
IE
0.3 mA
rπ =
β
120
= 10 k
=
gm
12
From Fig. 9.10, we have
τC1 = CC1 [(RB rπ ) + Rsig ]
For CC1 to contribute 10% of fL , we use
1
= 0.1ωL = 0.1 × 2πfL
τC1
= 0.1 × 2π × 50
⇒ τC1 = 31.8 ms
Thus,
CC1 [(13.2 10) + 5] × 103 = 31.8 × 10−3
⇒ CC1 = 3 μF
where
τC2 = CC2 (RC + RL )
Rsig = 5 k, RC = 4.7 k, and RL = 5.6 k
For CC2 to contribute 10% of fL , we use
Thus,
1
= 0.1ωL = 0.1 × 2πfL
τC2
AM = −
5.7
× 12(4.7 5.6)
5.7 + 5
= −16.3 V/V
= 2.2 ms
9.8 Refer to Fig. 9.9.
In the midband,
3
= 0.1 × 2π × 50
⇒ τC2 = 31.8 ms
Chapter 9–5
and
Thus,
−3
CC2 (4.7 + 5.6) × 10 = 31.8 × 10
3
fL = fP =
⇒ CC2 = 3.09 μF 3 μF
RB Rsig
= CE RE re +
β +1
| AM | =
For CE to contribute 80% of fL , we use
1
τCE
αRC
re
1
1+
Re
re
Thus, including
Re reduces the gain magnitude by
Re
the factor 1 +
.
re
= 0.8ωL = 0.8 × 2πfL
= 0.8 × 2π × 50
(c) From Eq. (3), we obtain
⇒ τCE = 3.98 ms
fL =
Thus,
(13.2 5) × 1000
CE 3900 83.3 +
121
1
2πCE re
1
1+
Re
re
Thus,
including
Re reduces fL by the factor
Re
1+
. This is the same factor by which the
re
magnitude of the gain is reduced. Thus, Re can be
used to tradeoff gain for decreasing fL (that is,
increasing the amplifier bandwidth).
= 3.98 × 10−3
⇒ CE = 36.2 μF
(d) I = 0.25 mA, RC = 10 k, CE = 10 μF
9.10
Vo
aIe
Vsig
(3)
(b) From Eq. (2) we see that
Finally,
τCE
1
2πCE (re + Re )
Ie
25 mV
VT
=
= 100 I
0.25 mA
re =
For Re = 0:
RC
| AM | =
1
= 159.2 Hz
2π × 10 × 10−6 × 100
fL =
re
αRC
10 k
= 100 V/V
re
100 To lower fL by a factor of 10, we use
Re
1+
CE
Re
= 10
re
⇒ Re = 900 The gain now becomes
Figure 1
| AM | =
Replacing the BJT with its T model results in the
circuit shown in Fig. 1.
(a) Ie =
See Fig. 2 for the Bode plot.
Vsig
re + Re +
1
sCE
Gain (dB)
Re 0
Vo = −αIe RC
40 dB
Re 900 Thus,
αRC
Vo
=−
Vsig
re + Re
s
1
s+
CE (re + Re )
(1)
αRC
re + Re
20 dB
15.9 Hz 159 Hz
From this expression we obtain
AM = −
100
100
=
= 10 V/V
Re
10
1+
re
(2)
Figure 2
f (Hz)
(log scale)
Chapter 9–6
This figure belongs to Problem 9.11, part (a).
CC
Vo
aIe
Rsig
RC
RL
Vsig
V b Ie
re
CE
Zin
Figure 1
9.11 Replacing the BJT with its T model results
in the equivalent circuit shown in Fig. 1 above.
(a) At midband, CE and CC act as short circuits.
Thus
(e) To minimize the total capacitance we choose
to make the pole caused by CE the dominant one
and make its frequency equal to fL = 100 Hz,
Rin = (β + 1)re
(β + 1)re
Vo
=−
gm (RC RL )
Vsig
(β + 1)re + Rsig
=−
β(RC RL )
(β + 1)re + Rsig
(b) Because the controlled current source αIe is
ideal, it effectively separates the input circuit
from the output circuit. The result is that the poles
caused by CE and CC do not interact. The pole
due to CE will have frequency ωPE :
ωPE =
1
10, 000
25 +
101
2π × 100 =
CE
⇒ CE = 12.83 μF
Placing the pole due to CC at 10 Hz, we obtain
2π × 10 =
1
CC (10 + 10) × 103
⇒ CC = 0.8 μF
(f) A Bode plot for the gain magnitude is shown
in Fig. 2.
1
Rsig
CE re +
β +1
and the pole due to CC will have a frequency ωPC
ωPC =
1
CC (RC + RL )
(c) The overall voltage transfer function can be
expressed as
Vo
s
s
= AM
Vsig
s + ωPE s + ωPC
VT
25 mV
= 25 (d) re =
=
IE
1 mA
100(10 k 10 k)
AM = −
101 × 25 × 10−3 k + 10 k
= −40 V/V
Figure 2
The gain at fP2 (10 Hz) is 12 dB. Since the gain
decreases by 40 dB/decade or equivalently
12 dB/octave, it reaches 0 dB (unity magnitude)
at f = fPC /2 = 5 Hz.
Chapter 9–7
9.12 Cox =
=
ox
tox
3.45 × 10−11 F/m
= 0.43 × 10−2 F/m2
8 × 10−9 m
= 0.43 × 10−2 × 10−12 F/μm2
= 4.3 fF/μm2
2ID
2 × 0.2
= 1.33 mA/V
=
VOV
0.3
gm
fT =
2π(Cgs + Cgd )
9.13 gm =
=
1.33 × 10−3
= 7.1 GHz
2π × (25 + 5) × 10−15
k n = μn Cox
= 450 × 108 (μm2 /V·s)
× 4.3 × 10−15 F/μm2
= 193.5 μA/V
1
W
2
ID = k n
VOV
(1 + λVDS )
2
L
2
1
2
× 193.5 × 20 × VOV
(1 + 0.05 × 1.5)
2
⇒ VOV = 0.31 V
200 =
2ID
2 × 0.2
= 1.3 mA/V
=
VOV
0.31
γ
χ= 2 2φf + VSB
gm =
0.5
= √
= 0.19
2 0.65 + 1
gmb = χ gm = 0.25 mA/V
ro =
| VA |
1
1
= 100 k
=
=
ID
| λ|ID
0.05 × 0.2
Cgs =
2
WLCox + WLov Cox
3
2
× 20 × 1 × 4.3 + 20 × 0.05 × 4.3
3
= 57.3 + 4.3 = 61.6 fF
=
9.14 fT =
gm
2π(Cgs + Cgd )
For Cgs Cgd
gm
fT 2πCgs
2
WLCox + WLov Cox
3
If the overlap component is small, we get
Cgs =
2
WLCox
(2)
3
The transconductance gm can be expressed as
W
gm = μn Cox
VOV
(3)
L
Cgs Substituting from (2) and (3) into (1), we obtain
W
μn Cox
VOV
L
fT =
2
2π × WLCox
3
3μn VOV
=
4πL2
We note that for a given channel length, fT can
be increased by operating the MOSFET at a
higher VOV .
For L = 0.5 μm and μn = 450 cm2 /V·s,
Cgd = WLov Cox = 20 × 0.05 × 4.3
we have
= 4.3 fF
VOV = 0.2 V ⇒ fT =
Csb0
Csb = | VSB |
1+
V0
= 20
1
1+
0.7
= 12.8 fF
Cdb0
Cdb = | VDB |
1+
V0
= 20
= 9.4 fF
2.5
1+
0.7
gm
fT =
2π(Cgs + Cgd )
=
1.3 × 10−3
= 3.1 GHz
2π(61.6 + 4.3) × 10−15
(1)
3 × 450 × 108 × 0.2
4π × 0.52
= 5.73 GHz
VOV = 0.4 V ⇒ fT =
3 × 450 × 108 × 0.4
4π × 0.52
= 11.46 GHz
9.15 fT =
gm
2π(Cgs + Cgd )
For Cgs Cgd
gm
fT 2πCgs
(1)
2
WLCox + WLov Cox
3
If the overlap component (WLov Cox ) is small,
we get
Cgs =
Cgs 2
WLCox
3
(2)
Chapter 9–8
9.17 fT =
The transconductance gm is given by
W
ID
gm = 2μn Cox
L
(3)
where
IC
0.5 mA
=
= 20 mA/V
VT
0.025 V
gm =
Substituting from (2) and (3) into (1), we get
W
ID
2μn Cox
L
fT =
2
2π × WLCox
3
1.5
μn ID
=
Q.E.D.
πL 2Cox WL
gm
2π(Cπ + Cμ )
Cπ = 8 pF
Cμ = 1 pF
Thus,
We observe thatfor a given device, fT is
proportional to ID ; thus to obtain faster
operation the MOSFET is operated at a higher ID .
Also,√we observe that fT is inversely proportional
to L WL; thus faster operation is obtained from
smaller devices.
fT =
20 × 10−3
= 353.7 MHz
2π × (8 + 1) × 10−12
fβ =
353.7
fT
=
= 3.54 MHz
β
100
9.18 See figure below. Cπ = Cde + Cje
where Cde is proportional to IC .
At IC = 0.5 mA,
8 = Cde + 2 ⇒ Cde = 6 pF
2VA
2VA L
9.16 A0 =
=
VOV
VOV
A0 =
2×5×L
= 50L, V/V (L in μm)
0.2
fT 3μn VOV
3 × 400 × 108 × 0.2
=
2
4πL
4πL2
fT =
1.91
, GHz (L in μm)
L2
1
At IC = 0.25 mA, Cde = × 6 = 3 pF, and
2
Cπ = 3 + 2 = 5 pF.
Also, at IC = 0.25 mA, gm = 10 mA/V. Thus fT at
IC = 0.25 mA is
fT =
9.19 rx = 100 The expressions for A0 and fT can be used to
obtain their values for different values of L. The
results are given in the following table.
L
10 × 10−3
= 265.3 MHz
2π(5 + 1) × 10−12
Lmin
2Lmin
3Lmin
4Lmin
5Lmin
0.13 μm 0.26 μm 0.39 μm 0.52 μm 0.65 μm
gm =
IC
1 mA
= 40 mA/V
=
VT
0.025 V
rπ =
β
100
=
= 2.5 k
gm
40
ro =
VA
50
= 50 k
=
IC
1
A0 (V/V)
6.5
13
19.5
26
32.5
Cde = τF gm = 30 × 10−12 × 40 × 10−3 = 1.2 pF
fT (GHz)
113
28.3
12.6
7.1
4.5
Cje0 = 20 pF
This figure belongs to Problem 9.18.
rx
B
Cm
B'
C
Vp
rp
Cp
gm Vp
E
ro
Chapter 9–9
Cπ = Cde + 2Cje0 = 1.2 + 2 × 0.02 = 1.24 pF
Cje0
VCB m
1+
V0c
Cμ = Cμ = |hfe | 40 =
20
= 10.4 fF
2 0.5
1+
0.75
gm
fT =
2π(Cπ + Cμ )
=
9.21 For f fβ ,
fT
f
2000 MHz
f
⇒ f = 50 MHz
fβ =
40 × 10−3
2π(1.24 + 0.01) × 10−12
fT
2000 MHz
= 10 MHz
=
β0
200
9.22
rx
= 5.1 GHz
rp
9.20 For f fβ ,
|hfe | =
B'
B
Cp
fT
f
Cm
C, E
At f = 50 MHz and IC = 0.2 mA,
Zin
fT
50
⇒ fT = 500 MHz
|hfe | = 10 =
With the emitter and the collector grounded, the
equivalent circuit takes the form shown in the
figure, and the input impedance becomes
At f = 50 MHz and IC = 1.0 mA,
fT
50
⇒ fT = 600 MHz
1
1
+ jω(Cπ + Cμ )
rπ
rπ
= rx +
1 + jω(Cπ + Cμ )rπ
|hfe | = 12 =
Zin = rx +
Now,
fT =
gm
2π(Cπ + Cμ )
Since ωβ =
where
rπ
ω
1+j
ωβ
ω
1−j
ωβ
= rx + rπ
2
ω
1+
ωβ
Cπ = Cde + Cje
Zin = rx +
= τF gm + Cje
Cμ = 0.1 pF
At IC = 0.2 mA, gm =
500 × 106 =
0.2
= 8 mA/V, thus
0.025
8 × 10−3
2π(Cπ + 0.1) × 10−12
τF × 8 × 10−3 + Cje = 2.45 × 10−12
40 × 10−3
2π(Cπ + 0.1) × 10−12
⇒ Cπ = 10.51 pF
Solving (1) together with (2) yields
τF = 252 ps
Cje = 0.43 pF
1+
(1)
1
= 40 mA/V, thus
At IC = 1 mA, gm =
0.025
τF × 40 × 10−3 + Cje = 10.51 × 10−12
rπ
Re (Zin ) = rx +
⇒ Cπ = 2.45 pF
600 × 106 =
1
, then
(Cπ + Cμ )rπ
(2)
ω
ωβ
2
For the real part to be an estimate of rx accurate to
within 10%, we require
rπ
2 ≤ 0.1rx
ω
1+
ωβ
1
rx
2 ≤ 0.1
rπ
ω
1+
ωβ
But rx ≤
rx
rπ
, thus
≤ 0.1,
10
rπ
Chapter 9–10
1
ω
ωβ
1+
9.25 (a) Vo = −AVi
2 ≤ 0.1 × 0.1
If the current flowing through Rsig is denoted Ii ,
we obtain
Ii
sC(Vi − Vo )
=
Yin =
Vi
Vi
Vo
= sC 1 −
Vi
= sC(1 + A)
or, equivalently,
2
ω
1+
≥ 100
ωβ
⇒ ω ≥ 10ωβ
Thus,
Cin = C(1 + A)
1/sCin
Vi (s)
=
(b)
1
Vsig (s)
Rsig +
sCin
1
=
1 + sCin Rsig
9.23 To complete the table below we use the
following relationships:
re =
VT
25 mV
=
IE
IE (mA)
gm =
IC
αIE
IE
IE (mA)
=
=
VT
VT
VT
0.025 V
A
Vo (s)
=−
Vsig (s)
1 + sCin Rsig
β0
, k
gm (mA/V)
gm
fT =
2π(Cπ + Cμ )
rπ =
fβ =
(c) DC gain = 40 dB = 100 V/V,
⇒ A = 100 V/V
1
f3dB =
2πCin Rsig
1
2π(Cπ + Cμ )rπ
1
2πCin × 1 × 103
⇒ Cin = 1591.5 pF
Cin
1591.5
C=
=
= 15.8 pF
A+1
101
(d) The Bode plot is shown in the figure below.
100 × 103 =
fT
fβ =
β0
9.24 Cin = Cgs + Cgd (1 + gm RL )
= 1 + 0.1(1 + 39)
= 5 pF
fsdB =
=
1
2πCin Rsig
1
2π × 5 × 10−12 Rsig
For fsdB > 1 MHz,
Rsig <
1
= 31.8 k
2π × 5 × 10−12 × 1 × 106
This table belongs to Problem 9.23.
Transistor IE (mA) re () gm (mA/V) rπ (k)
β0
fT (MHz) Cμ (pF) Cπ (pF) fβ (MHz)
(a)
2
12.5
80
12.5
100
500
2
23.5
5
(b)
1
25
40
3.13
125
500
2
10.7
4
(c)
1
25
40
2.5
100
500
2
10.7
5
(d)
10
2.5
400
0.25
100
500
2
125.3
5
(e)
0.1
250
4
25
100
150
2
2.2
1.5
(f)
1
25
40
0.25
10
500
2
10.7
50
(g)
1.25
20
50
0.2
10
800
1
9
80
Chapter 9–11
From the figure we see that the gain reduces to
unity two decades higher than f3dB , that is at
10 MHz.
9.26 Refer to Example 9.3. If the transistor is
replaced with another whose W is half that of the
original transistor, we obtain
1
W 2 = W1
2
Since
2
Cgs = WLCox + WLov Cox
3
then
1
Cgs2 = Cgs1 = 0.5 pF
2
Also,
in comparison to fH 1 = 398 MHz
4.7
× gm2 RL2
4.7 + 0.1
| AM 2 | =
4.7
× 0.71 × 7.14
4.8
= 5 V/V
=
in comparison to | AM 1 | = 7 V/V.
GB2 = 5 × 952 = 4.73 GHz
in comparison to GB1 = 7 × 398 = 2.79 GHz.
9.27 fH =
1
2πCin Rsig
For fH ≥ 6 MHz
Cin ≤
1
1
=
2πfH Rsig
2π × 6 × 106 × 1 × 103
Cgd = WLov Cox
Cin ≤ 26.5 pF
thus,
But,
1
Cgd 1 = 0.2 pF
2
Cgd 2 =
Since
= 5 + (1 + gm RL ) × 1, pF
= 6 + gm RL , pF
W
2μn Cox ID
L
gm =
Cin = Cgs + (1 + gm RL )Cgd
For Cin ≤ 26.5 pF we have
then
gm RL ≤ 20.5
1
gm2 = √ gm1 = 0.71 mA/V
2
RL ≤
Since
W
1
2
μn Cox
VOV
2
L
ID =
then
VOV 2
20.5
= 4.1 k
5
Corresponding to RL = 4.1 k, we have
| AM | = gm RL = 20.5 V/V
GB = | AM | fH
= 20.5 × 6 = 123 MHz
√
= 2VOV 1
If fH = 2 MHz, we obtain
Finally,
Cin = 26.5 × 3 = 79.5 pF
ro2 = ro1 = 150 k
gm RL = 79.5 − 6 = 73.5
Thus,
Thus,
RL2 = RL1 = 7.14 k
| AM | = 73.5 V/V
Thus,
GB = 73.5 × 2 = 147 MHz
Cin2 = Cgs2 + (gm2 RL2 + 1)Cgd 2
= 0.5 + (0.71 × 7.14 + 1) × 0.2
9.28 AM = −
Rin
gm RL
Rin + Rsig
= 1.71 pF
where
This should be compared to Cin1 = 4.26 pF. Thus,
RL = RD RL ro
fH 2 =
=
1
2πCin2 (Rsig RG )
1
2π × 1.71 × 10−12 (0.1 4.7) × 106
= 952 MHz
= 8 k 10 k 50 k
= 4.1 k
AM = −
100
× 3 × 4.1
100 + 100
= −6.1 V/V
Chapter 9–12
Cin = Cgs + Cgd (1 + gm RL )
(1)
= 1 + 0.2(1 + 3 × 4.1)
RL = RD RL ro
(2)
where
Rsig = Rsig Rin
= 100 k 100 k = 50 k
fH =
RG
gm RL
RG + Rsig
where
= 3.66 pF
1
fH =
2πCin Rsig
9.29 (a) AM = −
1
2π × 3.66 × 10−12 × 50 × 103
= 870 kHz
To double fH by changing Rin , Eq. (2) indicates
that Rsig must be halved:
= 20 k 20 k 100 k
= 9.1 k
AM = −
2 M
× 5 × 9.1
2 M + 0.5 M
= −36.4 V/V
(b) fH =
1
2πCin Rsig
where
Cin = Cgs + Cgd (1 + gm RL )
= 3 + 0.5(1 + 5 × 9.1)
Rsig = 25 k
= 26.25 pF
which requires Rin to be changed to Rin2 ,
and
25 k = 100 Rin2
Rsig = Rsig RG
⇒ Rin2 = 33.3 k
= 500 k 2000 k
This change will cause | AM | to become
| AM 2 | =
33.3
× 3 × 4.1
33.3 + 100
= 3.1 V/V
which is about half the original value.
To double fH by changing RL , Eq. (2) indicates
that Cin must be halved:
Cin2 =
1
× 3.66 = 1.83 pF
2
Using Eq. (1), we obtain
1.83 = 1 + 0.2(1 + gm RL2 )
⇒ gm RL2 = 3.15
Thus,
RL2 = 1.05 k
and RL2 can be found from
1.05 = RL 8 k 50 k
= 400 k
Thus,
fH =
1
2π × 26.25 × 10−12 × 400 × 103
= 15.2 kHz
gm
(c) fZ =
2πCgd
=
5 × 10−3
2π × 0.5 × 10−12
= 1.6 GHz
9.30 gm = 2μn Cox (W/L)1 ID1
√
= 2 × 0.09 × 100 × 0.1
= 1.34 mA/V
| VA1 |
12.8
= 128 k
=
ro1 =
ID1
0.1
ro2 =
| VA2 |
19.2
=
= 192 k
ID2
0.1
⇒ RL = 1.24 k
The total resistance at the output node, RL , is
given by
and the midband gain becomes
RL = ro1 ro2 = 128 k 192 k
| AM 2 | =
100
× 3.15 = 1.6 V/V
100 + 100
which is about a quarter of the original gain.
Clearly, changing Rin is the preferred course of
action!
= 76.8 k
AM = −gm1 RL
= −1.34 × 76.8 = −103 V/V
fH =
1
2πCin Rsig
Chapter 9–13
where
fH =
Cin = Cgs + Cgd (1 + gm1 RL )
= 0.2 + 0.015(1 + 103)
= 1.76 pF
Thus,
1
2π × 1.76 × 10−12 × 200 × 103
= 452 kHz
gm
1.34 × 10−3
=
fZ =
2πCgd
2π × 0.015 × 10−12
fH =
= 14.2 GHz
9.31 gm RL = 50
Cin = Cπ + Cμ (1 + gm RL )
= 10 + 1(1 + 50)
fH =
= 395 kHz
9.33 (a) AM =
RB
rπ
−
gm RL
RB + Rsig rπ + rx + (Rsig RB )
For RB Rsig , rx
AM −
1
2πCin Rsig
1
2π × 61 × 10−12 × 5 × 103
= 522 kHz
=
Rsig , Rsig rπ ,
rπ
gm RL = −βRL /Rsig
Rsig
Q.E.D.
(b) Cin = Cπ + (gm RL + 1)Cμ
For gm RL 1 and gm RL Cμ Cπ ,
Cin gm RL Cμ
fH =
= 61 pF
1
2π × 201.4 × 10−12 × 2 × 103
1
2πCin Rsig
where
Rsig = rπ [rx + (RB Rsig )]
rπ Rsig rπ
Thus,
9.32
AM = −
RB
rπ
gm RL
RB + Rsig rπ + rx + (Rsig RB )
fH 1
2πgm RL Cμ rπ
fH =
1
2πCμ βRL
where
RL = ro RC RL
= 100 k 10 k 10 k
= 4.76 k
(c) GB = | AM | fH
=β
and
rπ = β/gm = 100/40 = 2.5 k
AM = −
2.5
100
×
100 + 10 2.5 + 0.1 + (10 100)
× 40 × 4.76
Q.E.D.
RL
1
1
=
Rsig 2πCμ βRL
2πCμ Rsig
For Rsig = 25 k and Cμ = 1 pF,
GB =
1
2π × 1 ×
10−12
× 25 × 103
= −37 V/V
1
fH =
2πCin Rsig
For IC = 1 mA and β = 100,
where
AM = −100 ×
= 201.4 pF
and
Rsig = rπ [rx + (RB Rsig )]
fH =
25
= −100 V/V
25
6.37 MHz
GB
=
= 63.7 kHz
| AM |
100 V/V
(ii) RL = 2.5 k:
AM = −100 ×
= 2.5 [0.1 + (100 10)]
= 2 k
= 6.37 MHz
(i) RL = 25 k:
Cin = Cπ + Cμ (1 + gm RL )
= 10 + 1 × (1 + 40 × 4.76)
Q.E.D.
fH =
2.5
= −10 V/V
25
6.37 MHz
GB
=
= 637 kHz
| AM |
10 V/V
Chapter 9–14
1.25
50
×
× 170
50 + 5 1.25 + 0.05 + (50 5)
= −33 V/V
AM = −
and
20 log| AM | = 30.4 dB
This should be compared to the previous value of
39 V/V (32 dB). To determine fH , we first find Cin ,
Cin = Cπ + Cμ (1 + gm RL )
= 15 + 1(1 + 170)
The Bode plots are shown in the figure.
= 186 pF
If the midband gain is unity,
and the effective source resistance Rsig ,
fH = GB = 6.37 MHz
This is obtained when RL is
R
1 = 100 × L
25
⇒ RL = 0.25 k = 250 Rsig = rπ [rx + (RB Rsig )]
= 1.25 [0.05 + (50 5)]
= 0.98 k
Thus
fH =
1
2πCin Rsig
1
2π × 186 × 10−12 × 0.98 × 103
= 873 kHz
=
9.34 Refer to Example 9.4. Since IE is doubled to
2 mA, we have
IC
2 mA
= 80 mA/V
gm =
=
VT
25 mV
rπ =
β
100
= 1.25 k
=
gm
80 mA/V
ro =
VA
100 V
= 50 k
=
IC
2 mA
Cπ + Cμ =
gm
80 × 10−3
=
= 16 pF
ωT
2π × 800 × 106
Cμ = 1 pF
Cπ = 15 pF
This should be compared to the previous value of
754 kHz. The gain-bandwidth product becomes
GB = | AM | fH = 33 × 873 = 28.8 MHz
This should be compared to the previous value of
39 × 754 = 29.4 MHz. Thus, increasing the bias
current by a factor of 2 results in an increase in fH
by a factor of 1.16—that is, by about 16%.
However, because of the attendant reduction in
input resistance, the overall gain decreased by
about the same factor and GB remained nearly
constant. The price paid for the slight increase in
fH is an increase in power dissipation by a factor
of about two.
rx = 50 Also, now
9.35 Rin =
RB = 50 k
=
RC = 4 k
The new value of AM is
AM = −
RB
rπ
(gm RL )
RB + Rsig rπ + rx + (RB Rsig )
where
RL = ro RC RL
= 50 4 5 = 2.13 k
Thus,
gm RL = 80 × 2.13 = 170 V/V
and
R
1−K
100 k
= 1000 k = 1 M
1 − 0.9
9.36 Using Miller’s theorem, we obtain
Z
Z
, Zout =
Zin =
1
1−A
1−
A
For
1
Z=
jωC
1
⇒ Cin = C(1 − A)
Zin =
jωC(1 − A)
1
1
⇒ Cout = C 1 −
Zout =
1
A
jωC 1 −
A
Chapter 9–15
(a) A = −1000 V/V, C = 1 pF
The first figure below (left) shows that
Cin = 1(1 + 1000) = 1001 pF
1
= 1.001 pF
Cout = 1 1 +
1000
Vo = AVi
(1)
From Miller’s theorem, we have
Rin =
(b) A = −10 V/V, C = 10 pF
Cin = 10(1 + 10) = 110 pF
1
= 11 pF
Cout = 10 1 +
10
R2
R2
R2
=
=
Vo
Vo
1+A
1+
1−
Vi
−Vi
(2)
Using the voltage divider rule at the input, we get
−Vi = Vsig
(c) A = −1 V/V, C = 10 pF
Cin = 10(1 + 1) = 20 pF
Rin
Rin + R1
⇒ Vi = −Vsig
Cout = 10(1 + 1) = 20 pF
Rin
Rin + R1
(3)
For each value of A we use Eq. (2) to determine
Rin , Eq. (3) to determine Vi (for Vsig = 1 V),
Eq. (1) to determine Vo , and finally we calculate
the value of Vo /Vsig . The results are given in the
table below.
(d) A = +1 V/V, C = 10 pF
Cin = C(1 − 1) = 0
Cout = C(1 − 1) = 0
(e) A = +10 V/V, C = 10 pF
Cin = 10(1 − 10) = −90 pF
1
= 9 pF
Cout = 10 1 −
10
The −90 pF input capacitance can be used to
cancel an equal (+90 pF) capacitance between the
input node and ground.
Vo
(V)
Vo /Vsig
(V/V)
A
(V/V)
Rin
(k)
Vi
(V)
10
9.091 × 10−1
−0.476
−4.76 −4.76
100
9.901 × 10−2
−0.0901
−9.01 −9.01
1000 9.990 × 10−3 −9.89 × 10−3 −9.89 −9.89
10,000 9.999 × 10−4 −9.989 × 10−4 −9.99 −9.99
9.37
Ii R 10 k
2
R1 1 k Ii
Vi
Vsig Rin 9.38
0
(a) Refer to Fig. 1.
A
Vi − 2Vi
Vi
Vi − Vo
=
=−
R
R
R
Ii =
Thus,
Vo
Vi
Ii
Rin ≡
Vi
= −R
Ii
This figure belongs to Problem 9.38.
Ii
Rsig
IL
Vsig 0
ZL
2
Vo
Vi
Rin
Figure 1
(ViVo)/R
R
Chapter 9–16
(b) Replacing the signal source with its
equivalent Norton’s form results in the circuit in
Fig. 2. Observe that Req = ∞ when Rsig = R. In
this case,
IL =
Vsig
Vsig
=
Rsig
R
(a) For the dc analysis, refer to the figure.
VCC = IE RC + IB RB + VBE
1.5 = IE × 1 +
⇒ IE =
IE
× 47 + 0.7
β +1
1.5 − 0.7
= 0.546 mA
47
1+
101
IC = αIE = 0.99 × 0.546 = 0.54 mA
(b) gm =
rπ =
(c)
IC
0.54 mA
=
= 21.6 mA/V
VT
0.025 V
β
200
= 4.63 k
=
gm
21.6
Vo
= −gm (RC RL )
Vb
= −21.6(1 1) = −10.8 V/V
Figure 2
(c) If ZL =
(d) Using Miller’s theorem, the component of Rin
due to RB can be found as
1
,
sC
Rin1 =
Vi = IL ZL
RB
1 − (Vo /Vb )
47 k
= 4 k
1 − (−10.8)
Vsig
1
×
R
sC
1
Vsig
=
sCR
and
=
2
Vsig
Vo = 2Vi =
sCR
Thus,
(e) Gv =
=
Rin = Rin1 rπ
= 4 4.63 = 2.14 k
Rin
Vo
×
Rin + Rsig
Vb
2.14
× −10.8 = −7.4 V/V
2.14 + 1
Vo
Cμ
(f) Cin = Cπ + 1 +
Vb
=
2
Vo
=
Vsig
sCR
which is the transfer function of an ideal
noninverting integrator.
where
Cπ + Cμ =
9.39
gm
21.6 × 10−3
=
2πfT
2π × 600 × 106
Cπ + Cμ = 5.73 pF
VCC 1.5 V
Cπ = 5.73 − 0.8 = 4.93 pF
Cin = 4.93 + (1 + 10.8) × 0.8
IE
RC
(g) Rsig = Rin Rsig
RB
IB
IC
= 2.14 k 1 k = 0.68 k
fH =
VBE
= 14.37 pF
IE
=
1
2πCin Rsig
1
2π × 14.37 × 10−12 × 0.68 × 103
= 16.3 MHz
Chapter 9–17
9.40
B
Vp
B
C
Cm
rp
Cp
gm Vp
re
Cp
E
E
Zi (s)
Zi (s)
From the figure we see that the controlled
current-source gm Vπ appears across its control
voltage Vπ , thus we can replace the current source
with a resistance 1/gm . Now, the parallel
equivalent of rπ and 1/gm is
rπ
rπ
rπ (1/gm )
= re
=
=
1
gm rπ + 1
β +1
rπ +
gm
Thus, the equivalent circuit simplifies to that of re
in parallel with Cπ ,
1
Zi (s) =
re
=
1 + sCπ re
1
+ sCπ
re
re
Zi (jω) =
1 + jωCπ re
Again, gm fT 1
4πCπ re
It follows that in this case,
f45◦ =
1
fT = 200 MHz
2
9.41 AM = −gm RL
= −4 × 20 = −80 V/V
1
fsdB = fH =
2π(CL + Cgd )RL
=
1
2π(2 + 0.1) × 10−12 × 20 × 103
Zi (jω) will have a 45◦ phase at
= 3.8 MHz
ω45 Cπ re = 1
fZ =
⇒ ω45 =
1
Cπ re
Now,
fT =
gm
2π(Cπ + Cμ )
At high bias currents,
Cπ Cμ
and
fT gm
2πCπ
Since gm 1/re , we have
fT 1
2πCπ re
Thus,
f45◦ fT = 400 MHz
If the bias current is reduced to the value that
results in Cπ Cμ ,
fT =
gm
gm
=
2π × 2Cπ
4πCπ
1
, thus
re
gm
4 × 10−3
=
= 6.4 GHz
2πCgd
2π × 0.1 × 10−12
ft = | AM | fH
= 80 × 3.8 = 304 MHz
9.42 ft =
CL + Cgd
gm
2π(CL + Cgd )
gm
=
2πft
2 × 10−3
= 0.159 pF
2π × 2 × 109
To reduce ft to 1 GHz, an additional capacitance
of 0.159 pF must be connected to the output node.
(Doubling the effective capacitance at the output
node reduces ft by a factor of 2.)
=
9.43 Refer to Fig. P9.43. To determine gm1 we use
W
gm1 = 2μn Cox
ID1
L 1
100
× 0.1
= 2 × 0.090 ×
1.6
= 1.06 mA/V
Chapter 9–18
ro1 =
VA1
12.8
= 128 k
=
ID1
0.1
| VA2 |
19.2
=
= 192 k
ro2 =
ID2
0.1
RL = ro1 ro2 = 128 192 = 76.8 k
AM = −gm1 RL
= −1.06 × 76.8 = −81.4 V/V
CL = Cdb1 + Cdb2 + Cgd 2
= 20 + 36 + 15 = 71 fF
fH =
fH =
1
2π(CL + Cgd 1 )RL
1
2π(71 + 15) × 10−15 × 76.8 × 103
Cin = 5.37 + (10.7 + 1) × 1
= 17.07 pF
Rsig = rπ rx = 1.5 k 0.1 k
= 0.094 k
1
fH =
2πCin Rsig
=
1
2π × 17.07 × 10−12 × 0.094 × 103
= 99.2 MHz
(b) If | AM | is reduced to 1, we obtain
1=
1.5
× gm RL
1.6
⇒ gm RL = 1.07
= 24.1 MHz
Cin = Cπ + (gm RL + 1)Cμ
gm1
1.06 × 10−3
=
fZ =
2πCgd 1
2π × 0.015 × 10−12
= 5.37 + (1.07 + 1) × 1
= 11.2 GHz
= 7.44 pF
fH =
9.44 The equivalent circuit is shown in the figure.
IC
2 mA
gm =
= 80 mA/V
=
VT
0.025 V
β
120
=
= 1.5 k
rπ =
gm
80
(a) AM = −
−10 = −
rπ
gm RL
rπ + rx
1.5
× gm RL
1.5 + 0.1
⇒ gm RL = 10.7 V/V
RL = 0.133 k
gm
Cπ + Cμ =
2πfT
=
−3
80 × 10
= 6.37 pF
2π × 2 × 109
Cπ = 6.37 − 1 = 5.37 pF
Cin = Cπ + (gm RL + 1)Cμ
This figure belongs to Problem 9.44.
1
2π × 7.44 × 10−12 × 0.094 × 103
= 227.6 MHz
9.45 Figure 1 (next page) shows the amplifier
high-frequency equivalent circuit. A node
equation at the output provides
1
+ sCL Vo + gm Vπ + sCμ (Vo − Vπ ) = 0
ro
Replacing Vπ by Vi and collecting terms results in
1
+ s(CL + Cμ ) = −Vi (gm − sCμ )
Vo
ro
⇒
1 − s(Cμ /gm )
Vo
= −gm ro
Vi
1 + s(CL + Cμ )ro
Q.E.D.
For IC = 200 μA = 0.2 mA and VA = 100 V,
gm =
IC
0.2 mA
= 8 mA/V
=
VT
0.025 V
ro =
VA
100
=
= 500 k
IC
0.2
Chapter 9–19
This figure belongs to Problem 9.45.
Cm
Vi
rp
Vp
Cp
gmVp
ro
Vo
CL
Figure 1
DC gain = −gm ro = 8 × 500 = −4000 V/V
f3dB =
=
1
2π(CL + Cμ )ro
1
2π(1 + 0.2) × 10−12 × 500 × 103
Gain (dB)
50
40
20 dB/decade
30
= 265.3 kHz
gm
fZ =
2πCμ
=
The Bode plot is shown in the figure.
20
40 dB/decade
10
8 × 10−3
= 6.37 GHz
2π × 0.2 × 10−12
ft = | Adc | f3dB
0
2
10
20
200
f (MHz)
20 dB/decade
20
30
= 4000 × 265.3 = 1.06 GHz
The Bode plot is shown in Figure 2.
9.47 (a) A(s) = 1000
1
1 + s/(2π × 105 )
(b)
|A|, dB
60
3 dB
40
20 dB/decade
20
f
0
10 kHz 100 kHz 1 MHz 10 MHz 100 MHz
Figure 2
0
5.7°
10 kHz 100 kHz 1 MHz
45°
9.46 AM = 40 dB ⇒ 100 V/V
90°
5.7°
A(s) =
100 1 + s/(2π × 200 × 106 )
s
s
1+
1
+
2π × 2 × 106
2π × 20 × 106
Since fP1
fP2
fZ , we have
f3dB fP1 = 2 MHz
Figure 1
Figure 1 shows the Bode plot for the gain
magnitude and phase.
f
Chapter 9–20
(c) GB = 1000 × 100 kHz = 100 MHz
(d) The unity-gain frequency ft is
ft = 100 MHz
s
1+ 4
10
s
s
1+ 3 1+ 5
10
10
9.49 A(s) = −10
3
(a) ωH 103 rad/s
(e)
(b) ωH = 1
1
1
+ 10
106
10
−
2
108
= 1010 Hz
If the frequency of the finite zero is lowered to
103 rad/s the zero will cancel the pole at 103 rad/s
and the transfer function becomes
1
A(s) = −103
s
1+ 5
10
The 3-dB frequency now becomes
ω3dB = 105 rad/s
Figure 2
Figure 2 shows the magnitude response when a
second pole at 1 MHz appears in the transfer
function. The unity-gain frequency ft now is
ft = 10 MHz
9.50 If at ω = 107 rad/s the excess phase due to
the 3 coincident poles (at frequency ωP ) is 30◦ ,
then each pole is contributing 10◦ . Thus,
107
= 10◦
ωP
tan−1
107
= 5.67 × 107 rad/s
tan 10◦
ωP =
which is different from the gain-bandwidth
product,
9.51 τH = Cgs Rgs + Cgd Rgd + CL RCL
GB = 100 MHz
where
9.48 Using the dominant-pole approximation,
ωH ωP1
1
1
1
+ 2
2
ωP1
ωP2
ωP1
= ωP1 2
1+
ωP2
(a) For a difference of 10%,
ωP1
= 0.9ωP1
ωP1 2
1+
ωP2
⇒
ωP2
= 4.26
ωP1
(b) For a difference of 1%,
ωP1
= 0.99ωP1
ωP1 2
1+
ωP2
⇒
Rgs = Rsig = 10 k
Cgd = 5 fF
Using the root-sum-of-squares formula, we get
ωH Cgs = 30 fF
ωP2
= 49.3
ωP1
Rgd = Rsig (1 + gm RL ) + RL
= 10(1 + 2 × 20) + 20
= 430 k
CL = 30 fF
RCL = RL = 20 k
Thus,
τH = 30 × 10 + 5 × 430 + 30 × 20
= 3050 ps
fH =
=
1
2πτH
1
2π × 3050 × 10−12
= 52.2 MHz
fZ =
gm
2 × 10−3
=
= 63.7 GHz
2πCgd
2π × 5 × 10−15
Chapter 9–21
9.52 AM = −gm RL
Thus,
= −4 × 20 = −80 V/V
fP1 =
Cin = Cgs + Cgd (gm RL + 1)
1
2πCeq1 Req1
= 10.1 pF
1
2π × 20 × 10−12 × 5 × 103
= 1.59 MHz
Using the Miller approximation, we obtain
At node 2:
1
fH 2πCin Rsig
Req2 = Ro1 Rin2 = 2 k 10 k
fP1 =
= 2 + 0.1(80 + 1)
=
= 1.67 k
1
2π × 10.1 × 10−12 × 20 × 103
Ceq2 = Co1 + Cin2
= 788 kHz
= 2 + 10 = 12 pF
Using the open-circuit time constants, we get
fP2 =
τgs = Cgs Rgs = Cgs Rsig
= 2 × 20 = 40 ns
=
Rgd = Rsig (1 + gm RL ) + RL
1
2πCeq2 Req2
1
2π × 12 × 10−12 × 1.67 × 103
= 7.94 MHz
= 20(1 + 80) + 20 = 1640 k
τgd = Cgd Rgd = 0.1 × 1640 = 164 ns
At node 3:
τCL = CL RL
Req3 = Ro2 RL = 2 k 1 k = 0.67 k
= 2 × 20 = 40 ns
Ceq3 = Co2 + CL = 2 + 7 = 9 pF
τH = τgs + τgd + τCL
(1)
= 40 + 164 + 40 = 244 ns
1
fH =
2πτH
=
1
= 652 kHz
2π × 244 × 10−9
The estimate obtained using the open-circuit time
constants is more appropriate as it takes into
account the effect of CL . We note from Eq. (1)
that τCL is 16.4% of τH , thus CL has a significant
effect on the determination of fH .
9.53 The figure shows the equivalent circuit of
the two-stage amplifier where we have modeled
each stage as a transconductance amplifier. At
node 1:
Req1 = Rsig Rin1
= 10 k 10 k = 5 k
Ceq1 = Cin1 + Csig = 10 + 10 = 20 pF
This figure belongs to Problem 9.53.
fP3 =
1
2πCeq3 Req3
1
2π × 9 × 10−12 × 0.67 × 103
= 26.4 MHz
fP3 =
Thus, the three poles have frequencies 1.59 MHz,
7.94 MHz, and 26.4 MHz. Since the frequency of
the second pole is more than two octaves higher
than that of the first pole, the 3-dB frequency will
be mostly determined by fP1 ,
f3dB fP1 = 1.59 MHz
A slightly better estimate of f3dB can be determined
using the root-sum-of-squares formula,
2 2 2
1
1
1
+
+
f3dB = 1/
fP1
fP2
fP3
1
1
1
= 1/
+
+
1.592
7.942
26.42
= 1.56 MHz
Chapter 9–22
9.54 τgs = Cgs Rgs = Cgs Rsig
Thus, the original CL of 25 fF must be
increased by
= 5 × 10 = 50 ns
66.6 − 25 = 41.6 fF
Rgd = Rsig (1 + gm RL ) + RL
= 10(1 + 5 × 10) + 10
= 520 k
9.56 We will assume that the value given in the
problem statement is for Rsig (not Rsig ):
τgd = Cgd Rgd = 1 × 520 = 520 ns
Rsig = 5 k
RCL = CL RL
rπ =
= 5 × 10 = 50 ns
Rsig = rπ Rsig = 5 k 5 k
τH = τgs + τgd + τCL
= 50 + 520 + 50 = 620 ns
1
fH =
2πτH
=
β
100
=
= 5 k
gm
20
= 2.5 k
(1)
1
= 257 kHz
2π × 620 × 10−9
τH = Cπ Rπ = Cπ Rsig
= 10 × 2.5 = 25 ns
τμ = Cμ Rμ
= Cμ [Rsig (1 + gm RL ) + RL ]
The interaction of Rsig with the input capacitance
contributes all of τgs (50 ns) and a significant part
of τgd , namely
= 1 × [2.5(1 + 20 × 5) + 5]
Cgd [Rsig (1 + gm RL )] = 1 × 10(1 + 50) = 510 ns
τCL = CL RL
Thus, the total contribution of Rsig is
= 10 × 5 = 50 ns
50 + 510 = 560 ns
560
which is
= 90.3% of τH . To double fH , we
620
must reduce τH to half of its value:
τH = τπ + τμ + τCL
τH =
1
× 620 = 310 ns
2
Now,
τH = Rsig [Cgs + Cgd (1 + gm RL )]
+ Cgd RL + CL RL
= 257.5 ns
= 25 + 257.5 + 50 = 332.5 ns
1
1
=
= 479 kHz
fH =
2πτH
2π × 332.5 × 10−9
rπ
gm RL
AM = −
rπ + Rsig
5
× 20 × 5
5+5
= −50 V/V
=−
310 = Rsig [5 + 1(1 + 50)] + 1 × 10 + 5 × 10
⇒ Rsig = 4.46 k
9.55 To lower fH from 135.5 MHz (see Example
9.8) to 100 MHz, τH must be increased to
τH =
1
1
=
2πfH
2π × 100 × 106
9.57 Refer to Fig. 9.19(a). Since RB is not
specified, we assume that its value is very large.
rπ
AM = −
gm RL
rπ + rx + Rsig
where
rπ =
β
100
= 2.5 k
=
gm
40
= 1591.5 ps
Thus,
Now,
AM = −
τH = τgs + τgd + τCL
2.5
× 40 × 5
2.5 + 0.1 + 1
= −138.9 V/V
1591.5 = 200 + 725 + τCL
Using the Miller approximation, we obtain
⇒ τCL = 666.5
Cin = Cπ + Cμ (1 + gm RL )
But,
= 10 + 0.3(1 + 40 × 5)
τCL = CL RL
= 70.3 pF
665.5 = CL × 10
Rsig = rπ (rx + Rsig )
⇒ CL = 66.6 fF
= 2.5 (0.1 + 1) = 0.76 k
Chapter 9–23
fH =
1
2πCin Rsig
1
=
2π × 70.3 × 10−12 × 0.76 × 103
= 2.98 MHz
(c) CL = 50 pF
τCL = CL RL = 50 × 7.5 = 375 ns
τH = τgs + τgd + τCL
= 20 + 246.5 + 375
τπ = Cπ Rπ = Cπ Rsig
= 641.5 ns
1
fH =
2πτH
= 10 × 0.76 = 7.6 ns
=
Using the open-circuit time constants, we get
τμ = Cμ [Rsig (gm RL + 1) + RL ]
= 0.3[0.76(40 × 5 + 1) + 5]
= 47.3 ns
τCL = CL RL = 3 × 5 = 15 ns
τH = τπ + τμ + τCL
= 7.6 + 47.3 + 15 = 69.9 ns
1
fH =
2πτH
1
=
= 2.28 MHz
2π × 69.9 × 10−9
This is a more realistic estimate of fH as it takes
into account the effect of CL .
9.58 RL = ro RL = 20 k 12 k
= 7.5 k
1
= 248 kHz
2π × 641.5 × 10−9
Using the Miller approximation, since CL is not
taken into account, then for all three cases we
obtain
Cin = Cgs + Cgd (gm RL + 1)
= 0.2 + 0.2(1.5 × 7.5 + 1)
= 2.65 pF
fH =
=
1
2πCin Rsig
1
2π × 2.65 × 10−12 × 100 × 103
= 600 kHz
which is very close to the estimate obtained using
the method of open-circuit time constants for the
case CL = 0. However, as CL is increased, the
estimate obtained using the Miller approximation
becomes less and less realistic, which is due to
the fact that it does not take CL into account.
τgs = Cgs Rgs = Cgs Rsig
= 0.2 × 100 = 20 ns
9.59 Refer to Fig. 9.26(c).
= 0.2[100(1.5 × 7.5 + 1) + 7.5]
Vo
1/gm
=
gm RL
1
Vsig
+ Rsig
gm
= 246.5 ns
=
τgd = Cgd [Rsig (gm RL + 1) + RL ]
(a) CL = 0
1/5
× 5 × 10
1
+1
5
τCL = 0
= 8.3 V/V
τH = τgs + τgd = 20 + 246.5 = 266.5 ns
fP1 =
fH =
= 239 MHz
= 20 + 246.5 + 75 = 341.5 ns
fP2 =
=
1
= 466 kHz
2π × 341.5 × 10−9
2π × 4 × 10−12 1 τH = τgs + τgd + τCL
1
2πτH
1
gm
1
fP1 =
τCL = CL RL = 10 × 7.5 = 75 ns
fH =
1
2πCgs Rsig 1
= 597 kHz
2π × 266.5 × 10−9
(b) CL = 10 pF
=
1
5
× 103
1
2π(CL + Cgd )RL
1
2π(2 + 0.2) × 10−12 × 10 × 103
= 7.23 MHz
Chapter 9–24
This figure belongs to Problem 9.60.
Rsig
E
Vo
C
Vsig re
RL
Cp Vp
(CLCm)
gmVp
B
Since fP1 fP2 , fP2 will be dominant and
τgs = Cgs (Rin Rsig )
fH fP2 = 7.23 MHz
τgs = 0.2(1.32 50)
= 0.26 ns
9.60 See figure above. Replacing the BJT with its
high-frequency T model while neglecting ro and
rx results in the equivalent circuit shown in the
figure.
(a) There are two separate poles, one at the input
given by
fP1
1
=
2πCπ (Rsig re )
1
2π(CL + Cμ )RL
= 100 7650 = 98.7 k
τgd = (Cgd + CL + Cdb )Rgd
= (0.015 + 0.03 + 0.02) × 98.7
= 6.42 ns
and the other at the output, given by
fP2 =
Rgd = RL Ro
τH = τgs + τgd = 0.26 + 6.42
= 6.68 ns
Q.E.D.
fH =
(b) IC = 1 mA,
gm =
IC
1 mA
= 40 mA/V
=
VT
0.025 V
re 1
= 25 gm
fP1
1
=
−12
2π × 10 × 10 (1 0.025) × 103
= 652.5 MHz
fP2 =
1
2π(1 + 1) × 10−12 × 10 × 103
= 7.96 MHz
Since fP2
fP1 , fP2 will be dominant and
fH fP2 = 7.96 MHz
9.61 ro =
VA
10
=
= 100 k
ID
0.1
Rsig = ro /2 = 50 k
RL = ro = 100 k
gm ro = 1.5 × 100 = 150
Rin =
ro + RL
100 + 100
= 1.32 k
=
1 + gm ro
1 + 150
=
1
2πτH
1
= 23.8 MHz
2π × 6.68 × 10−9
9.62 Refer to Example 9.9. To reduce fH to
200 MHz, τH must become
τH =
1
1
=
2πfH
2π × 200 × 106
= 795.8 ps
Since τgs remains constant at 26.6 ps, τCL must be
increased to
τCL = 795.8 − 26.6 = 769.2 ps
But,
τCL = (Cgd + CL )Rgd
thus,
769.2 = (5 + CL ) × 18.7
⇒ CL + 5 = 41.1 fF
CL = 36.1 fF
Ro = Rsig + ro + gm ro Rsig
Thus, the amount of additional capacitance to be
connected at the output is
= 50 + 100 + 150 × 50 = 7650 k
36.1 − 25 = 11.1 fF
Chapter 9–25
9.63 Ro = ro2 + ro1 + (gm2 ro2 )ro1
fH =
= 2ro + gm ro2
1
2πτH
1
= 737 kHz
2π × 216 × 10−9
= 2 × 20 + 2 × 20 × 20 = 840 k
=
Av = −gm1 (Ro RL )
GB ≡ | AM | fH = 40 × 737 = 29.5 MHz
= −2(840 1000)
(b) AM = −gm1 (Ro RL )
= −913 V/V
where
Using Eq. (9.109), we obtain
Ro = ro1 + ro2 + gm2 ro2 ro1
τH = Rsig [Cgs1 + Cgd 1 (1 + gm1 Rd 1 )]
= 2ro + gm ro2
+ Rd 1 (Cgd 1 + Cdb1 + Cgs2 )
= 2 × 20 + 4 × 20 × 20 = 1640 k
+ (RL Ro )(CL + Cgd 2 )
AM = −4(1640 20) = −79 V/V
where
Rin2 =
Rd 1 = ro1 Rin2
Rin2
ro2 + RL
=
1 + gm2 ro2
=
ro2 + RL
1 + gm2 ro2
20 + 20
0.49 k
1 + 4 × 20
Rd 1 = ro1 Rin2 = 20 0.49 = 0.48 k
20 + 1000
= 24.9 k
=
1 + 2 × 20
Using Eq. (9.109), we obtain
Rd 1 = 20 24.9 = 11.1 k
τH = Rsig [Cgs1 + Cgd 1 (1 + gm1 Rd 1 )]
+ Rd 1 (Cgd 1 + Cdb1 + Cgs2 )
Thus,
+ (RL Ro )(CL + Cgd 2 )
τH = 100[20 + 5(1 + 2 × 11.1)]
+ 11.1(5 + 5 + 20)
= 20[2 + 0.2(1 + 4 × 0.48)]
+ 0.48(0.2 + 0.2 + 2)
+ (1000 840)(20 + 5)
+ (20 1640)(1 + 0.2)
= 13587 + 333 + 11413
= 25, 333 ps = 25.33 ns
fH =
1
= 6.28 MHz
2π × 25.33 × 10−9
9.64 (a) AM = −gm RL
τH = 51.7 + 1.15 + 23.7 = 76.6 ns
fH =
1
= 2.08 MHz
2π × 76.6 × 10−9
GB ≡ | AM | fH = 79 × 2.08 = 164 MHz
Note the increase in bandwidth and in GB.
where
RL = RL ro = 20 20 = 10 k
9.65 20 log | AM | = 74 dB
Thus,
⇒ | AM | = 5000
AM = −4 × 10 = −40 V/V
Ro (gm ro )ro
τgs = Cgs Rgs
RL = Ro
= Cgs Rsig = 2 × 20 = 40 ns
| AM | = gm (RL Ro )
Rgd = Rsig (1 + gm RL ) + RL
5000 =
= 20(1 + 4 × 10) + 10
= 830 k
τgd = Cgd Rgd = 0.2 × 830 = 166 ns
τCL = CL RL = 1 × 10 = 10 ns
τH = τgs + τgd + τCL
= 40 + 166 + 10 = 216 ns
1
gm Ro
2
1
(gm ro )2
2
⇒ gm ro = 100
=
2VA
= 100
VOV
⇒ VOV =
2 × 10
= 0.2 V
100
Chapter 9–26
1
W
2
μn Cox
VOV
2
L
ID =
Cgd = 5 fF and VA = 10 V in Eqs. (1)–(6), we
obtain the following results in the table below.
1
× 0.2 × 50 × 0.22
2
= 0.2 mA
gm
ft =
2π(CL + Cgd )
=
9.67 (a) For the CS amplifier,
| AM | = gm (ro ro ) =
fH =
where
gm =
2ID
2 × 0.2
= 2 mA/V
=
VOV
0.2
=
2 × 10−3
2π(1 + 0.1) × 10−12
ft =
1
2πCin Rsig
1
1
2π Cgs + Cgd
gm ro + 1 Rsig
2
(1)
For the cascode amplifier,
= 289.4 MHz
f3dB
1
gm ro
2
| AM | = gm (Ro ro )
289.4
ft
=
= 57.9 kHz
=
| AM |
5000
= gm [(gm ro )ro ro ]
gm ro
If the cascode transistor is removed,
Thus, the gain increases by a factor of 2.
AM = −gm (ro RL )
fH =
−gm ro = −100 V/V
1
2πCin Rsig
where
9.66 (a) From Fig. 9.29, we have
gm
ft =
2π(CL + Cgd )
√
2μn Cox (W/L) =
ID
Q.E.D.
2π(CL + Cgd )
(b) gm = 2μn Cox (W/L) ID
(2)
Rd 1 = ro VOV = (3)
= ro Cin = Cgs + Cgd (1 + gm Rd 1 )
Rd 1 = ro Rin2
ID
1
μn Cox (W/L)
2
VA
ID
(4)
Ro = (gm ro )ro
(5)
ro =
= ro (1)
RL + ro
gm ro
ro + ro
gm ro
2
2
gm
gm
2
Cin = Cgs + Cgd 1 + gm ×
gm
= Cgs + 3Cgd
1
2π(Cgs + 3Cgd )Rsig
AM = −gm (Ro RL )
fH =
= −gm (Ro Ro )
From (1) and (2), the ratio N of fH of the cascode
amplifier to fH of the CS amplifier is
1
gm ro + 1
Cgs + Cgd
2
N=
Cgs + 3Cgd
1
= − gm Ro
2
Substituting
(6)
μn Cox = 0.4 mA/V2 , W/L = 20, CL = 20 fF,
(2)
This table belongs to Problem 9.66, part (b).
ID (mA) ft (GHz) VOV (V) gm (mA/V) ro (k) Ro (M) AM (V/V) fH (MHz)
0.1
8
0.16
1.26
100
12.6
−7938
1
0.2
11.5
0.22
1.80
50
4.5
−4050
2.8
0.5
18
0.35
2.83
20
1.13
−1600
11.3
Chapter 9–27
Thus,
Ro = β2 ro2 = 100 × 100 = 10,000 k
1
Cgs + (gm ro )Cgd
2
N
Cgs + 3Cgd
τH = Cπ1 Rπ1 + Cμ1 Rμ1 + (Ccs1 + Cπ2 )Rc1
Q.E.D.
1
gm ro
2
⇒ gm ro = 100
(b) 50 =
1
Cgs + × 100 × 0.1Cgs
2
N=
Cgs + 3 × 0.1Cgs
1+5
=
= 4.6
1 + 0.3
(c) gm ro =
100 =
2VA
VOV
2 × 10
VOV
⇒ VOV = 0.2 V
1
W
2
VOV
ID = μn Cox
2
L
1
× 0.4 × 10 × 0.22
2
= 0.08 mA = 80 μA
=
9.68 Refer to Fig. 9.30.
gm =
IC
1 mA
= 40 mA/V
=
VT
0.025 V
β
100
=
= 2.5 k
rπ =
gm
40
rπ
gm (βro RL )
AM = −
rπ + rx + Rsig
=−
2.5
40(100 × 100 2)
2.5 + 0.05 + 5
+ (CL + Ccs2 + Cμ2 )(RL Ro )
= 10 × 1.67 + 2 × 3.4 + (0 + 10) × 0.0255
+ (0 + 0 + 2)(2 10,000)
= 16.7 + 6.8 + 0.255 + 4 = 27.8 ns
fH =
1
1
=
2πτH
2π × 27.8 × 10−9
= 5.7 MHz
9.69 (a) Gain from base to collector of Q1 = −1.
Thus,
Cin = Cπ1 + Cμ1 (1 + 1)
= Cπ1 + 2Cμ1
fP1 =
=
1
2πRsig Cin
1
2πRsig (Cπ1 + 2Cμ )
Q.E.D.
At the output node, the total capacitance is
(CL + Cc2 + Cμ2 ) and since ro is large, Ro will be
very large, thus the total resistance will be RL .
Thus the pole introduced at the output node will
have a frequency fP2 ,
fP2 =
1
2π(CL + Cc2 + Cμ2 )RL
Q.E.D.
(b) I = 1 mA
1 mA
= 40 mA/V
0.025 V
β
100
= 2.5 k
=
rπ =
gm
40
gm =
−26.5 (V/V)
(i) Rsig = 1 k
Rsig = rπ (rx + Rsig )
Rsig = rπ Rsig = 2.5 1 = 0.71 k
= 2.5 (0.05 + 5) = 1.67 k
fP1 =
Rπ 1 = Rsig = 1.67 k
ro2 + RL
Rc1 = ro1 re2
ro2 + RL /(β2 + 1)
⎤
⎡
100 + 2 ⎥
⎢
= 100 ⎣0.025
2 ⎦
100 +
101
= 25.5 Rμ1 = Rsig (1 + gm1 Rc1 ) + Rc1
1
2π × 0.71 × 103 (10 + 2 × 2) × 10−12
= 16 MHz
fP2 =
1
2π(0 + 0 + 2) × 10−12 × 2 × 103
40 MHz
fH = 1
=1
1
1
+ 2
fp12
fp2
1
1
+ 2 = 14.9 MHz
2
16
40
= 1.67(1 + 40 × 0.0255) + 0.0255
(ii) Rsig = 10 k
= 3.4 k
Rsig = rπ Rsig = 2.5 10 = 2 k
Chapter 9–28
fP1 =
1
2π × 2 × 103 (10 + 4) × 10−12
To determine Cπ , we use
gm
2π(Cπ + Cμ )
= 5.7 MHz
fT =
fP2 = 40 MHz
1
1
+ 2 = 5.6 MHz
fH = 1
5.72
40
1 × 109 =
τH = 0.54 × 12.5 + 0.1 × 639.8 + 0.54 × 12.3
IC = 0.1 mA
0.1 mA
= 4 mA/V
gm =
0.025 V
β
100
= 25 k
=
rπ =
gm
4
+ 0.1 ×
VA
100 V
=
= 1000 k
ID
0.1 mA
1
= 0.25 k
re gm
rπ
gm (βro RL )
AM = −
rπ + rx + Rsig
rπ
gm (βro βro )
=−
rπ + rπ
Obviously the last term, which is due to the pole
at the output node, is dominant. The frequency of
the output pole is
fP =
1
= 31.8 kHz
2π × 5000 × 10−9
fH fP = 31.8 MHz
Because the other poles are at much higher
frequencies, an estimate of the unity-gain
frequency can be found as
1
= − βgm ro
4
1
= − × 100 × 4 × 1000
4
= −100,000 V/V
ft = | AM | fP = 105 × 31.8 × 103 = 3.18 GHz
Rsig = rπ Rsig = rπ rπ =
1
rπ = 12.5 k
2
⎞
⎜ ro + RL ⎟
⎟
Rc1 = ro re ⎜
⎝
RL ⎠
ro +
β +1
⎞
⎛
ro + βro ⎟
⎟
⎠
β
ro
ro +
β +1
1000 0.25 ×
1
× 100 × 1000
2
= 6.8 + 64 + 6.6 + 5000 ns
ro =
⎜
= 1000 0.25⎜
⎝
⇒ Cπ + Cμ = 0.64 pF
Cπ = 0.64 − 0.1 = 0.54 pF
9.70 Refer to Fig. 9.30.
Rπ 1 = Rsig = 12.5 k
⎛
4 × 10−3
2π(Cπ + Cμ )
β +1
2
= 1000 12.5 = 12.3 k
This estimate of ft is not very good (too high!).
The other three poles have frequencies much
lower than 3.18 GHz and will cause the gain to
decrease faster, reaching the 0 dB value at a
frequency lower than 3.18 GHz. Also note that fT
of the BJTs is 1 GHz and the models we use for
the BJT do not hold at frequencies approaching fT .
9.71 AM =
Ro = βro = 100 × 1000 = 100 M
RL = RL ro 1
gm
1
gmb
= 2 20 = 1.82 k
AM =
1.82
1.82 +
Ro = ro fZ =
τH = Cπ 1 Rπ 1 + Cμ1 Rμ1 + (Ccs1 + Cπ 2 )Rc1
+ (CL + Cc2 + Cμ2 )(RL Ro )
RL +
where
Rμ1 = Rsig (1 + gm1 Rc1 ) + Rc1
= 12.5(1 + 4 × 12.3) + 12.3 = 639.8 k
RL
=
1
5
= 0.91 V/V
1
1
= 20 0.2 k = 200 gm
5
gm
2πCgs
5 × 10−3
= 398 MHz
2π × 2 × 10−12
Chapter 9–29
Next, we evaluate b1 and b2 :
Cgs
Cgs + CL
Rsig +
R
b1 = Cgd +
gm RL + 1
gm RL + 1 L
= 0.1 +
2+1
2
20 +
× 1.82
5 × 1.82 + 1
5 × 1.82 + 1
(Cgs + Cgd )CL + Cgs Cgd
Rsig RL
b2 =
gm RL + 1
(2 + 0.1) × 1 + 2 × 0.1
× 20 × 1.82
5 × 1.82 + 1
= 8.3 × 10−18
√
√
b2
8.3
Q=
=
= 0.44
b1
6.5
Thus, the poles are real and their frequencies can
be obtained by finding the roots of the polynomial
(1 + b1 s + b2 s2 )
−9
−18 2
= 1 + 6.5 × 10 s + 8.3 × 10
1
fH =
2πRsig Cgd +
Cgs
gm RL + 1
s
which are
Q.E.D.
For the given numerical values,
fH =
= 5.96 + 0.54 = 6.50 × 10−9 s
=
and
1
2π × 100 × 103 10 +
2
× 10−12
5 × (2 20) + 1
= 156 kHz
(Note: An error was made in the first printing of
the book and the values of Cgs and Cgd were
exchanged. The above value of fH corresponds to
the numbers in the first printing.)
For Cgs = 10 pF and Cgd = 2 pF,
fH =
1
10
× 10−12
2+
5 × (2 20) + 1
2π × 100 ×
103
= 532 kHz
ωP1 = 0.21 × 109 rad/s
and
ωP2 = 0.57 × 109 rad/s
9.73 Refer to Fig. 9.31(c). Replacing Cgs with an
input capacitance between G and ground, we get
Thus,
Ceq = Cgs (1 − K)
ωP1
= 33.4 MHz
fP1 =
2π
ωP2
fP2 =
= 90.7 MHz
2π
Since the two poles are relatively close to each
other, an estimate of fH can be obtained using
1
1
+ 2
fH = 1
2
fP1
fP2
= 31.6 MHz
where
K=
gm RL
1 + gm RL
then
Ceq = Cgs /(1 + gm RL )
and the total input capacitance becomes
Cin = Cgd + Ceq
= Cgd +
9.72 fH fP1 where
b1 = Cgd +
1
2πb1
Cgs
Cgs + CL
Rsig +
R
gm RL + 1
gm RL + 1 L
For CL = 0,
b1 = Cgd Rsig +
= Cgd
The frequency of the input pole is
fP1 =
1
2πRsig Cgd +
Cgs
1 + gm RL
fH fP1
Cgs
(Rsig + RL )
gm RL + 1
For Rsig RL ,
Cgs
Rsig
gm RL + 1
Cgs
+
Rsig
gm RL + 1
b1 Cgd Rsig +
Cgs
1 + gm RL
9.74 With gmb = 0 and ro large, we obtain
RL RL
and
AM =
gm RL
gm RL + 1
Chapter 9–30
For AM = 0.9,
0.9 =
gm RL
gm RL + 1
⇒ gm RL = 9
√
Now, for a maximally-flat response, Q = 1/ 2.
Using the expression for Q in Eq. (9.129), we get
Q=
√
gm RL + 1 [(Cgs + Cgd )CL + Cgs Cgd ]Rsig RL
√ √
1
3 RL
√ = RL
2
10 1 +
100
⇒
Vo (s)
dc gain
=
ω0
Vi (s)
2
+ ω02
s +s
Q
=
=
s2
+ s 2 × 2π × 106 + (2π × 106 )2
0.8
s2 + s 8.886 × 106 s + 39.48 × 1012
RL
100
2
RL
−4
+1=0
100
9.76 Refer to Fig. 9.33.
IC = 1 mA
gm = 40 mA/V,
rπ =
RL = 27 k and RL = 373 k
The second answer is not very practical as it
implies the transistor is operating at
gm = 9/373 = 0.024 mA/V, a very small
transconductance!. We will pursue only the first
answer. Thus,
RL = 27 k
VA
20
= 20 k
=
IC
1
gm
fT =
2π(Cπ + Cμ )
ro =
2 × 109 =
f3dB = f0 =
ω3dB =
=
1
√
2π b2
gm RL + 1
Rsig RL [(Cgs + Cgd )CL + Cgs Cgd ]
9+1
100 × 27[(10 + 1) × 10 + 10 × 1] × 106 × 10−24
= 5.55 Mrad/s
f3dB = 884 kHz
40 × 10−3
2π(Cπ + Cμ )
⇒ Cπ + Cμ = 3.2 pF
Cπ = 3.2 − 0.1 = 3.1 pF
RL = RL ro = 1 20 = 0.95 k
Rsig = Rsig + rx = 1 + 0.1 = 1.1 k
RL
AM =
RL + re +
gm = 0.33 mA/V
and the 3-dB frequency is found using
Eq. (9.127):
re = 25 100
= 2.5 k
40
This equation results in two solutions,
0.8
√
[Cgs + Cgd (gm RL + 1)]Rsig + (Cgs + CL )RL
√
√
1
9 + 1 [(10 + 1)10 + 10 × 1] × 100 × RL
√ =
[10 + 1(9 + 1)] × 100 + (10 + 10)RL
2
Thus, the transfer function will be
AM =
Rsig
β +1
0.95
0.95 + 0.025 +
1.1
101
= 0.96 V/V
fZ =
=
1
2πCπ re
1
2π × 3.1 × 10−12 × 25
2 GHz
b1 =
Rsig
R
Cπ + Cμ 1 + L
Rsig + Cμ + CL 1 +
RL
re
rπ
1
Q= √
2
Rsig
R
1+ L +
rπ
re
0.95
3.1 + 0.1 1 +
× 1.1 + (3.1 + 0) × 0.95
0.025
=
0.95
1.1
1+
+
0.025
2.5
ω0 = ω3dB = 2π × 106 rad/s
= 0.27 × 10−9
9.75 For a maximally flat response we have
Chapter 9–31
b2 =
[(Cπ + Cμ )CL + Cπ Cμ ]RL Rsig
Rsig
R
1+ L +
re
rπ
(0 + 3.1 × 0.1) × 0.95 × 1.1
=
1.1
0.95
+
1+
0.025 2.5
= 8.2 × 10−21
√
√
b2
8.2 × 10−21
Q=
=
= 0.335
b1
0.27 × 10−9
Thus, the poles are real and their frequencies can
be found as the roots of the polynomial
(1 + b1 s + b2 se )
= 1 + 0.27 × 10−9 s + 8.2 × 10−21 s2
s
s
= 1+
1+
ωP1
ωP2
(c) Rsig small and the frequency response is
determined by the output pole:
fP2 =
=
1
2π(CL + Cgd + Cdb )(RD ro )
1
2π(100 + 5 + 5) × 10−15 × 9.1 × 103
= 159 MHz
fH 159 MHz
(d) Rsig = 40 k
τgs = Cgs Rgs
= Cgs Rsig
= 40 × 10−15 × 40 × 103
⇒ ωP1 = 4.25 × 109 rad/s
= 1.6 ns
ωP2 = 28.6 × 109 rad/s
Rgd = Rsig (gm RL + 1) + RL
Thus,
= 40(1.6 × 9.1 + 1) + 9.1
fP1 = 676 MHz
fP2 = 4.6 GHz
Thus,
9.77 I = 0.4 mA
1
W
2
VOV
(a) ID = μn Cox
2
L
1
2
× 0.4 × 16VOV
2
⇒ VOV = 0.25 V
gm =
τgd = Cgd Rgd = 5 × 631.5 = 3.16 ns
τCL = (CL + Cdb )RL
f3dB fP1 = 676 MHz
0.2 =
= 631.5 k
2ID
2 × 0.2
=
VOV
0.25
= (100 + 5) × 9.1
= 955.5 ps = 0.96 ns
τH = τgs + τgd + τCL
= 1.6 + 3.16 + 0.96 = 5.72 ns
fH =
=
1
2πτH
1
2π × 5.72 × 10−9
= 27.8 MHz
= 1.6 mA/V
(b) ro =
VA
20
=
ID
0.2
= 100 k
RD ro = 10 100
= 9.1 k
Ad = gm (RD ro )
= 1.6 × 9.1 = 14.5 V/V
9.78 The common-mode gain will have a zero at
fZ =
=
1
2πRSS CSS
1
2π × 100 × 103 × 1 × 10−12
= 1.59 MHz
Thus, the CMRR will have two poles, one at fZ ,
i.e. at 1.59 MHz, and the other at the dominant
Chapter 9–32
pole of Ad , 20 MHz. Thus, the 3-dB frequency of
CMRR will be approximately equal to fZ ,
Since CSS is proportional to W , its value will be
quadrupled:
f3dB = 1.59 MHz
CSS = 400 fF
The output resistance RSS will remain unchanged.
Thus, fZ will decrease by a factor of 4 to become
9.79 At low frequencies,
fZ = 1 MHz
Ad = 100 V/V
Acm = 0.1 V/V
9.81 gm =
Ad
= 1000 or 60 dB
Acm
IC
0.25 mA
= 10 mA/V
=
VT
0.025 V
rπ =
β
100
= 10 k
=
gm
10
The first pole of CMRR is coincident with the
zero of the common-mode gain,
fT =
gm
2π(Cπ + Cμ )
fP1 = 1 MHz
Cπ + Cμ =
The second pole is coincident with the dominant
pole of the differential gain,
=
fP2 = 10 MHz
= 3.2 pF
A sketch for the Bode plot for the gain magnitude
is shown in the figure.
Cπ = 3.2 − 0.5 = 2.7 pF
CMRR =
gm
2πfT
10 × 10−3
2π × 500 × 106
(a)
CMRR (dB)
RC
60
20 dB/decade
Vo /2
Rsig
Vid
2
40
40 dB/decade
20
0
0.1
9.80 RSS =
1
fP1
10
fP2
100
1000 f, MHz
40
VA
=
I
0.1
= 400 k
CSS = 100 fF
fZ =
=
1
2πCSS RSS
1
= 4 MHz
2π × 100 × 10−15 × 400 × 103
If VOV of the current source is reduced by a factor
of 2 while I remains unchanged, (W/L) must be
increased by a factor of 4. Assume L remains
unchanged, W must be increased by a factor of 4.
The figure on the next page shows the differential
half-circuit and its high-frequency equivalent
circuit.
(b) Ad ≡
=−
Vo
rπ
=−
gm RC
Vid
rπ + rx + Rsig
10
× 10 × 10
10 + 0.1 + 10
= −49.8 V/V
(c) Cin = Cπ + Cμ (1 + gm RC )
= 2.7 + 0.5(1 + 10 × 10)
= 53.2 pF
fH =
1
2πCin Rsig
Chapter 9–33
This figure belongs to Problem 9.81.
Rsig
Cm
rx
Vo/2
Vid 2 Vp
rp
Cp
RC
gmVp
where
Rsig = rπ (Rsig + rx )
= 10 10.1 5 k
fH =
1
= 598 kHz
2π × 53.2 × 10−12 × 5 × 103
GB = | Ad | fH = 49.8 × 598 = 29.8 MHz
9.82 gm1,2 =
2ID1,2
I
=
VOV 1,2
VOV 1,2
0.2 mA
=
= 1 mA/V
0.2 V
2| VA |
| VA |
=
I /2
I
I
2| VA | 2| VA |
Ad =
| VOV |
I
I
ro2 = ro4 =
Ad =
| VA |
| VOV |
fP1 =
1
2πCL Ro
where
Ro = ro2 ro4 =
fP1 =
I
2πCL | VA |
Ad = gm1,2 (ro2 ro4 )
fP2 =
gm3
2πCm
= 1(100 100) = 50 V/V
where
ro2 = ro4 =
| VA |
10 V
=
= 100 k
ID
0.1 mA
| VA |
I
fP1
1
=
2πCL Ro
gm3 =
I
2ID
=
| VOV |
| VOV |
=
1
2πCL (ro2 ro4 )
Cm =
CL
4
=
1
2π × 0.2 × 10−12 (100 100) × 103
fP2 =
4I
2πCL | VOV |
1
= 15.9 MHz
2π × 0.2 × 50 × 10−9
gm3
fP2 =
2πCm
=
where
gm3
2ID
I
=
=
= 1 mA/V
| VOV |
| VOV |
fP2 =
fZ =
−3
1 × 10
= 1.59 GHz
2π × 0.1 × 10−12
2gm3
= 2fP2 = 2 × 1.59 = 3.18 GHz
2πCm
9.83 Ad = gm1,2 (ro2 ro4 )
gm1,2 =
2ID
I
=
| VOV |
| VOV |
fZ =
(1)
(2)
2gm3
8I
= 2fP2 =
2πCm
2πCL | VOV |
(3)
Dividing (2) by (1), we obtain
| VA |
fP2
= 4 Ad
=4
fP1
| VOV |
Q.E.D.
Since fP2 = 4 Ad fP1 , the unity-gain frequency ft
is equal to GB, thus
ft = Ad fP1
=
I
| VA |
| VOV | 2πCL | VA |
ft =
=
I /| VOV |
2πCL
gm
2πCL
Q.E.D.
Chapter 9–34
the short-circuit at the output causes Cμ2 to
appear in parallel with Cπ1 and Cπ2 . Thus,
For the numerical values given, we have
20
= 100 V/V
0.2
I
0.2
= 1 mA/V
=
gm =
VOV
0.2
Ad =
fP1 =
=
Vπ =
Ii (s) I
2πCL | VA |
1
1
+
re1
rπ2
1
(1)
+ s(Cπ1 + Cπ2 + Cμ2 )
At the output node we have
−3
0.2 × 10
2π × 100 × 10−15 × 20
Io (s) = gm2 Vπ − sCμ2 Vπ
(2)
Combining Eqs. (1) and (2) gives
= 15.9 MHz
gm2 − sCμ2
Io (s)
= 1
1
Ii (s)
+
+ s(Cπ1 + Cπ2 + Cμ2 )
re1
rπ2
ft = 15.9 × 100 = 1.59 GHz
fP2 = 4Ad fP1 = 4 × 100 × 15.9
Since the two transistors are operating at
approximately equal dc bias currents, their
small-signal parameters will be equal, thus
= 6.37 GHz
fZ = 2fP2 = 12.7 GHz
A sketch of the Bode plot for | Ad | is shown in the
figure.
gm − sCμ
Io (s)
= 1
1
Ii (s)
1+
+ s(2Cπ + Cμ )
re
β +1
=
1 − s(Cμ /gm )
gm re
1
1
1+
1 + s (2Cπ + Cμ )re / 1 +
β +1
β +1
=
1 − s(Cμ /gm )
1
1
1+
1 + s (2Cπ + Cμ )re / 1 +
β +1
β +1
=
1 − s(Cμ /gm )
1
1
1 + 2/β
1 + s (2Cπ + Cμ )re / 1 +
β +1
α
Thus we see that the low-frequency transmission
is
9.84 See figure below. The mirror
high-frequency equivalent circuit is shown in the
figure. Note that we have neglected rx and ro . The
model of the diode-connected transistor Q1
reduces to re1 in parallel with Cπ1 .
Io
(0) =
Ii
1+
2
β
as expected. The pole is at fP ,
fP To obtain the current-transfer function Io (s)/Ii (s),
we first determine Vπ in terms of Ii . Observe that
1
1
1
2π (2Cπ + Cμ )re / 1 +
β
This figure belongs to Problem 9.84.
Cm2
C1, B1, B2
Ii (s)
Vp re1
sCm2Vp
Cp1
Cp2
rp2
gm2Vp
Io (s)
Chapter 9–35
(b) Rs = 100 and the zero is at
gm
fZ =
2πCμ
Gm =
For the numerical values given,
AM = −3.33 × 5 = −16.7 V/V
IC
1 mA
=
= 40 mA/V
gm =
VT
0.025 V
Rgd = 100(1 + 3.33 × 5) + 5
= 1771.7 k
100 + 0.1
= 66.7 k
Rgs =
1 + 5 × 0.1
re 25 Cπ + Cμ =
=
gm
2πfT
τH = 10 × 66.7 + 2 × 1771.7 = 4.21 ns
40 × 10−3
2π × 500 × 1006
fH =
= 12.7 pF
(c) Rs = 200 1
fP =
2π[(2 × 10.7 + 2) × 10−12 × 25/1.01]
Gm =
1.01 × 1012
2π × 23.4 × 25
5
= 2.5 mA/V
1 + 5 × 0.2
AM = −2.5 × 5 = −12.5 V/V
Rgd = 100(1 + 2.5 × 5) + 5 = 1355 k
= 274.8 MHz
gm
fZ =
2πCμ
=
1
= 37.8 MHz
2π × 4.21 × 10−9
GB = 631 MHz
Cπ = 12.7 − 2 = 10.7 pF
=
5
= 3.33 mA/V
1 + 5 × 0.1
Rgs =
100 + 0.2
= 50.1 k
1 + 5 × 0.2
τH = 10 × 50.1 + 2 × 1355 ns
40 × 10−3
= 3.18 GHz
2π × 2 × 10−12
fH =
9.85 Refer to Eqs. (9.146)–(9.153). For our case,
gm
(1)
Gm =
1 + gm Rs
1
= 49.6 MHz
2π × 3.21 × 10−9
GB = 49.6 × 12.5 = 620 MHz
A summary of the results is provided in the
following table:
Ro = very large
Rs = 0 Rs = 100 Rs = 200 RL = RL Ro = RL
Am = −Gm RL =
−gm RL
1 + gm Rs
Rgd = Rsig (1 + Gm RL ) + RL
Rgs =
Rsig + Rs
1 + gm Rs
τH = Cgs Rgs + Cgd Rgd
fH =
1
2πτH
(2)
(3)
| AM | (V/V)
25
16.7
12.5
fH | (MHz)
26.6
37.8
49.6
GB (MHz)
641
631
620
(4)
Observe that increasing Rs trades off gain for
bandwidth while GB remains approximately
constant.
For the numerical values given:
(a) Rs = 0
9.86 (a) GB = | AM | fH
Gm = gm = 5 mA/V
=
1
2πCgd Rsig
Rgd = 100(1 + 5 × 5) + 5 = 2605 k
=
1
2π × 0.2 × 10−12 × 100 × 103
τH = 10 × 100 + 2 × 2605 = 6.21 ns
= 7.96 MHz
1
= 26.6 MHz
fH =
2π × 6.21 × 10−9
(b) | AM | = 20 V/V
GB = 26.6 × 25 = 641 MHz
fH =
AM = −gm RL = −5 × 5 = −25 V/V
7.96
= 398 kHz
20
Chapter 9–36
(c) A0 = gm ro
RL = RL Ro = 40 120 = 30 k
100 = 5 × ro
AM = −Gm RL
⇒ ro = 20 k
= −1.67 × 30 = −50 V/V
gm
5
=
Gm =
1 + gm Rs
1 + gm Rs
Rgd = Rsig (1 + Gm RL ) + RL
Ro = ro (1 + gm Rs ) = 20(1 + gm Rs )
= 20(1 + 1.67 × 30) + 30
RL = RL Ro = 20 20(1 + gm Rs )
= 1050 k
AM = −Gm RL
τgd = Cgd Rgd = 0.1 × 1050 = 105 ns
5
20 =
[20 20(1 + gm Rs )]
1 + gm Rs
τCL = CL RCL
4(1 + gm Rs ) =
20 × 20(1 + gm Rs )
20 + 20(1 + gm Rs )
⇒ 1 + gm Rs = 4
3
= 0.6 k = 600 ⇒ Rs =
gm
9.87 (a) AM = −gm RL
= CL RL
= 1 × 30 = 30 ns
Rsig + Rs + Rsig Rs /(ro + RL )
ro
1 + gm Rs
ro + RL
Rgs =
=
where
20 + 0.4 + 20 × 0.4/(40 + 40)
40
1 + 5 × 0.4
40 + 40
RL = RL ro
= 10.25 k
= 40 40 = 20 k
τgs = Cgs Rgs = 2 × 10.25 = 20.5 ns
AM = −5 × 20 = −100 V/V
τH = τgs + τgd + τCL
τgs = Cgs Rgs = Cgs Rsig
= 20.5 + 105 + 30 = 155.5 ns
= 2 × 20 = 40 ns
Rgd = Rsig (1 + gm RL ) + RL
= 20(1 + 5 × 20) + 20
= 2040 k
τgd = Cgd Rgd = 0.1 × 2040
1
2πτH
fH =
=
1
= 1.02 MHz
2π × 155.5 × 10−9
GB = 51.2 MHz
= 204 ns
τCL = CL RL
= 1 × 20 = 20 ns
τH = τgs + τgd + τCL
= 40 + 204 + 20 = 264 ns
fH =
1
= 603 kHz
2π × 264 × 10−9
9.88 Gm =
RL = RL Ro
= ro ro (1 + gm Rs )
= ro ro (1 + k)
ro × ro (1 + k)
ro + ro (1 + k)
GB = 100 × 603 = 60.3 MHz
=
(b) With Rs = 400 ,
gm
Gm =
1 + gm Rs
= ro
5
= 1.67 mA/V
=
1 + 5 × 0.4
Ro = ro (1 + gm Rs )
= 40(1 + 5 × 0.4) = 120 k
gm
gm
=
1 + gm Rs
1+k
1+k
2+k
AM = −Gm RL = −
gm ro
2+k
Thus,
AM =
−A0
2+k
Q.E.D.
Chapter 9–37
Rgs =
Rsig + Rs + Rsig Rs /(ro + RL )
ro
1 + gm Rs
ro + RL
The results we obtain appear in the following
table.
k
Rsig + Rs + Rsig Rs /2ro
=
1
1 + gm Rs
2
| AM |, V/V τH ns fH (MHz) GB (MHz)
0
100
264
0.603
60.3
1
66.7
191.3
0.832
55.6
2
50
155
1.03
51.5
3
40
133.2
1.19
47.6
4
33.3
118.7
1.34
44.6
5
28.6
108.3
1.47
42.0
6
25
100.5
1.58
39.5
7
22.2
94.4
1.69
37.5
8
20
89.6
1.78
35.6
9
18.2
85.7
1.86
33.9
Utilizing the expressions for RL and Gm RL
derived earlier, we obtain
A0
1+k
Rgd = Rsig 1 +
+ ro
2+k
2+k
10
16.7
82.3
1.93
32.2
11
15.4
79.6
2.00
30.8
12
14.3
77.2
2.06
29.5
τgd = Cgs Rgd = A0
1+k
+ Cgd ro
Cgd Rsig 1 +
2+k
2+k
13
13.3
75.1
2.12
28.2
14
12.5
73.3
2.17
27.1
15
11.8
71.6
2.22
26.2
For Rsig Rs ,
Rsig (1 + Rs /2ro )
Rgs 1 + (k/2)
For ro Rs ,
Rgs Rsig
1 + (k/2)
τgs = Cgs Rgs =
Cgs Rsig
1 + (k/2)
Rgd = Rsig (1 + Gm RL ) + RL
τCL = CL RL
= CL ro
To obtain fH = 2 MHz, we see from the table that
1+k
2+k
k = 11
Thus,
Thus,
1 + gm Rs = 11
τH = τgs + τgd + τCL
Cgs Rsig
A0
+ Cgd Rsig 1 +
1 + (k/2)
2+k
1+k
1+k
+ CL ro
+Cgd ro
2+k
2+k
Cgs Rsig
A0
=
+ Cgd Rsig 1 +
2+k
1 + (k/2)
1+k
+(CL + Cgd )ro
Q.E.D.
2+k
=
10
= 5 k
2
The gain achieved is
⇒ Rs =
| AM | = 15.4 V/V
9.90 (a) Refer to Fig. P9.90(a). Since the total
resistance at the drain is ro , we have
AM = −gm ro
Q.E.D.
τgs = Cgs Rgs = Cgs Rsig
Rgd = Rsig (1 + gm RL ) + RL
9.89 Substituting the given numerical values in
the expressions for AM and τH given in the
statement for Problem 9.88 and noting that
A0 = gm ro = 5 × 40 = 200, we obtain
fH =
1
2πτH
and
GB = | AM |fH
= Rsig (1 + gm ro ) + ro
τgd = Cgd Rgd = Cgd [Rsig (1 + gm ro ) + ro ]
τCL = CL RL = CL ro
Thus,
τH = τgs + τgd + τCL
= Cgs Rsig + Cgd [Rsig (1 + gm ro ) + ro ]
+ CL ro
Q.E.D.
Chapter 9–38
This figure belongs to Problem 9.90, part (b).
Rsig
Vg1 1
gm1
Vsig
Q1
Vo
ro1
ro2
Q2
Vg2
Figure 1
Cgd 1 : Capacitor Cgd 1 is between G1 and ground
and thus sees the resistance Rsig ,
For the given numerical values,
AM = −1 × 20 = −20 V/V
τH = 20 × 20 + 5[20(1 + 1 × 20) + 20] + 10 × 20
Rgd 1 = Rsig
= 400 + 2200 + 200 = 2800 ps = 2.8 ns
1
1
=
fH =
2πτH
2π × 2.8 × 10−9
= 56.8 MHz
τgd 1 = Cgd 1 Rsig
Cgs1 : To find the resistance Rgs1 seen by capacitor
Cgs1 , we replace Q1 with its hybrid-π equivalent
circuit with Vsig set to zero, Cgd 1 = 0, and Cgs1
replaced by a test voltage Vx . The resulting
equivalent circuit is shown in Fig. 3.
GB = 20 × 56.8 = 1.14 GHz
(b) From Fig. 1 we see that
Vg1
=1
Vsig
Rsig
D1
Vg1 G1
Ix
Vg2
ro1
=
1
Vg1
+ ro1
gm1
Vx Vo
= −gm2 ro2
Vg2
S1
Thus,
AM = 1 ×
ro1
× −gm2 ro2
1
+ ro1
gm1
ro1
=−
(gm2 ro2 )
1/gm1 + ro1
Ix
Analysis of the circuit in Fig. 3 proceeds as
follows:
Q.E.D.
Vg1 = Ix Rsig
Vs1 = Vg1 − Vx = Ix Rsig − Vx
Node equation at S1 ,
Ix = gm1 Vx −
Vs1
ro1
Ix Rsig − Vx
ro1
Rsig
1
Ix 1 +
= Vx gm1 +
ro1
ro1
Cgd1
= gm1 Vx −
Q1
Cgs1
Cgd2
G2
Cgs2
Q2
CL
Thus,
Rgs1 ≡
Rsig + ro1
Vx
=
1 + gm1 ro1
Ix
τgs1 = Cgs1 Rgs1
Figure 2
Vs1
Figure 3
Next we evaluate the open-circuit time constants.
Refer to Fig. 2.
Rsig G
1
ro1
gm1Vx
= Cgs1
Rsig + ro1
1 + gm1 ro1
Chapter 9–39
Cgs2 : Capacitor Cgs2 sees the resistance between
G2 and ground, which is the output resistance of
source follower Q1 ,
Rgs2 =
1
ro1
gm1
Thus,
τgs2 = Cgs2
1
ro1
gm1
Cgd 2 : Transistor Q2 operates as a CS amplifier
with an equivalent signal-source resistance equal
to the output
resistance
of the source follower Q2 ,
1
that is,
ro1 and with a gain from gate to
gm1
drain of gm2 ro2 . Thus, the formula for Rgd in a CS
amplifier can be adapted as follows:
1
Rgd 2 =
ro1 (1 + gm2 ro2 ) + ro2
gm1
and thus,
τgd 2 = Cgd 2
1
ro1 (1 + gm2 ro2 ) + ro2
gm1
CL : Capacitor CL sees the resistance between D2 ,
and ground which is ro2 ,
τCL = CL ro2
Summing τgd 1 , τgs1 , τgs2 , τgd 2 and τCL gives τH in
the problem statement. Q.E.D.
GB = 19 × 286 = 5.43 GHz
Thus, while the dc gain remained approximately
the same both fH and GB increased by a factor of
about 5!
9.91 At an emitter bias current of 0.1 mA, Q1 and
Q2 have
gm = 4 mA/V
re = 250 rπ =
β
100
= 25 k
=
gm
4
VA
100
= 1000 k
=
IC
0.1
gm
Cπ + Cμ =
2πfT
ro =
=
4 × 10−3
= 3.2 pF
2π × 200 × 106
Cμ = 0.2 pF
Cπ = 3 pF
To determine Rin and the voltage gain AM , refer to
the circuit in Fig. 9.40(a). Here, however,
RL is ro2 .
Rin2 = rπ2 = 25 k
For the given numerical values:
Rin = (β1 + 1)[re1 + (ro1 Rin2 )]
20
AM = −
(1 × 20)
1 + 20
= 101[0.25 + (1000 25)]
= −19 V/V
τgd 1 = Cgd 1 Rsig = 5 × 20 = 100 ps
τgs1 = Cgs1
Rsig + ro1
1 + gm ro1
20 + 20
= 38 ps
1 + 1 × 20
1
= Cgs2
ro1
gm1
2.5 M
Vb1
Rin
2.5 M
=
1 V/V
=
Vsig
Rin + Rsig
2.5 M + 10 k
(Rin2 ro1 )
Vb2
=
Vb1
(Rin2 ro1 ) + re1
25 1000
= 0.99 1 V/V
(25 1000) + 0.25
= 20
=
τgs2
Vo
= −gm2 ro2 = −4 × 1000 = −4000 V/V
Vb2
= 20 × (1 20) = 19 ps
1
τgd 2 = Cgd 2
ro1 (1 + gm ro2 ) + ro2
gm1
= 5[(1 20)(1 + 20) + 20]
= 200 ps
τCL = CL ro2 = 10 × 20 = 200 ps
τH = 100 + 38 + 19 + 200 + 200 = 557 ps
fH =
1
2πτH
1
=
2π × 557 × 10−12
= 286 MHz
Thus,
AM =
Vo
= −4000 V/V
Vsig
To determine fH we use the method of
open-circuit time constants. Figure 9.40(b) shows
the circuit with Vsig = 0 and the four capacitances
indicated. Again, recall that here RL = ro2 . Also,
in our present circuit there is a capacitance CL at
the output.
Capacitance Cμ1 sees a resistance Rμ1 ,
Rμ1 = Rsig Rin
= 10 k 2.5 M 10 k
Chapter 9–40
To find the resistance Rπ 1 we refer to the circuit
in Fig. 9.40(c) where Rin2 is considered to
include ro2 ,
Rin2 = 25 k 1000 k = 24.4 k
We use the formula for Rπ 1 given in
Example 9.13:
Rπ 1 =
Rsig + Rin2
Rsig
Rin2
1+
+
rπ 1
re1
10 + 24.4
= 347 10 24.4
+
1+
25 0.25
Capacitance Cπ 2 sees a resistance Rπ 2 :
Rπ 1 =
Rπ 2 = Rin2 Rout1
Rsig
= rπ 2 ro1 re1 +
β1 + 1
10
= 25 1000 0.25 +
101
= 344 The high-frequency analysis can be performed in
an analogous manner to that used in the text for
the bipolar circuit. Refer to Fig. 9.42(b) and adapt
the circuit for the MOS case. Thus,
fP1 =
2πRsig
=
1
Cgs
+ Cgd
2
1
4
2π × 100 × 103
+ 0.5 × 10−12
2
= 637 kHz
and
fP2 =
1
2πRD Cμ
1
2π × 50 × 103 × 0.5 × 10−12
= 6.37 MHz
=
Since fP2 10fP1 , the pole at fP1 will dominate
and
fH fP1 = 637 kHz
Capacitance Cμ2 sees a resistance Rμ2 :
Rμ2 = (1 + gm2 ro2 )(Rin2 Rout1 ) + ro2
= 2376 k
9.93 Using an approach analogous to that utilized
for the BJT circuit (Fig. 9.42), we see that there is
a pole at the input with frequency fP1 :
We can determine τH from
fP1 =
= (1 + 4 × 1000) × 0.344 + 1000
2πRsig
τH = Cμ1 Rμ1 + Cπ 1 Rπ 1 + Cμ2 Rμ2
+ Cπ 2 Rπ 2 + CL ro
= 0.2 × 10 + 3 × 0.347 + 0.2 × 2376
+ 3 × 0.344 + 1 × 1000
τH = 2 + 1 + 475.2 + 1 + 1000
= 1479.2 ns
Observe that there are two dominant
capacitances: the most significant is CL and the
second most significant is Cμ2 .
fH =
=
1
2πτH
1
= 107.6 kHz
2π × 1479.2 × 10−9
2ID
2(I /2)
=
9.92 gm =
VOV
VOV
=
I
0.2 mA
=
= 1 mA/V
VOV
0.2 V
RD
Vo
=
Vsig
2/gm
=
1
1
gm RD = × 1 × 50 = 25 V/V
2
2
1
Cgs
+ Cgd
2
fP1 =
2π × 20 × 103
1
2
+ 0.1 × 10−12
2
= 7.2 MHz,
and a pole at the output with frequency fP2 ,
fP2 =
=
1
2π(Cgd + CL )RL
1
2π × (0.1 + 1) × 10−12 × 20 × 103
= 7.2 MHz
Thus,
fP1 = fP2 = 7.2 MHz
The midband gain AM is obtained as
AM =
RL
1
= gm RL
2/gm
2
1
× 5 × 20 = 50 V/V
2
Thus, the amplifier transfer function is
=
Vo (s)
= Vsig (s)
50
1+
s
2π × 7.2 × 106
2
Chapter 9–41
Vo
=
Vsig
1+
50
ω
2π × 7.2 × 106
2
Vo
= (gm ro )2 = 10,000 V/V
Vsig
(b) τgs1 = Cgs Rsig
Vo
50
= √ , thus
Vi
2
2
√
ω3dB
2=1+
2π × 7.2 × 106
√
f3dB =
2 − 1 × 7.2 MHz
= 20 × 10 = 200 ps
= 4.6 MHz
At the drain of Q1 we have (Cdb1 + Cgs2 ) and the
resistance seen is ro :
At ω = ω3dB ,
9.94 gm =
Rgd 1 = Rsig (1 + gm1 ro1 ) + ro1
= 10(1 + 100) + 100
= 1110 k
τgd 1 = Cgd 1 Rgd 1 = 5 × 1110 = 5550 ps
IC
1 mA
= 40 mA/V
VT
0.025 V
re 25 rπ =
τd 1 = (Cdb1 + Cgs2 )ro
= (5 + 20) × 100 = 2500 ps
Rgd 2 = ro1 (1 + gm2 ro2 ) + ro2
β
120
= 3 k
=
gm
40
= 100(1 + 100) + 100 = 1110 k
Rin = 2rπ = 6 k
τgd 2 = Cgd 2 Rgd 2 = 5 × 1110 = 5550 ps
Vo
Rin
αRL
=
Vsig
Rin + Rsig 2re
τd 2 = Cdb2 ro2
= 5 × 100 = 500 ps
10
6
×
= 66.7 V/V
6 + 12 2 × 0.025
gm
Cπ + Cμ =
2πfT
40 × 10−3
=
= 12.7 pF
2π × 500 × 106
Cμ = 0.5 pF
2πRsig
2π × 12 ×
103
= 14,300 ps = 14.3 ns
=
1
Cπ
+ Cμ
2
=
= 200 + 5550 + 2500 + 5550 + 500
fH =
Cπ = 12.2 pF
fP1 =
τH = τgs1 + τgd 1 + τd 1 + τgd 2 + τd 2
1
2πτH
1
= 11.1 MHz
2π × 14.3 × 10−9
9.96 (a)
1
12.2
+ 0.5 × 10−12
2
5 V
52
1 mA
3
3 k
= 2 MHz
fP2 =
=
1
2πRL Cμ
RG 10 M 0
1
2π × 10 × 103 × 0.5 × 10−12
2 V
= 31.8 MHz
Thus, fP1 is the dominant pole and
fH fP1 = 2 MHz
VG1 2 V
VGS 1.3 V
0.7 V
1 mA
Q1
0.1 mA
0
Q2
9.95 (a) For each of Q1 and Q2 ,
gm =
2 × 0.1
2ID
=
= 1 mA/V
| VOV |
0.2
ro =
| VA |
10
=
= 100 k
ID
0.1
gm ro = 100
0.1 mA
6.8 k
Figure 1
Chapter 9–42
Thus,
The dc analysis is shown in Fig. 1. It is based on
VS1 = VBE2 = 0.7 V. Neglecting IB2 , we obtain
0.7 V
ID1 =
0.1 mA
Q.E.D.
6.8 k
1
2
ID1 = k n (W/L)VOV
2
1
2
0.1 = × 2 × VOV
2
⇒ VOV 0.3 V
Vo
= 0.66 × −30
Vi
−20 V/V
Using Miller’s theorem, the input resistance Rin is
found as
RG
10 M
Rin =
=
Vo
1 − (−20)
1−
Vi
VGS = Vt + VOV = 1 + 0.3 = 1.3 V
= 476 k
Rin
Vi
=
Vsig
Rin + Rsig
VG1 = 0.7 + 1.3 = 2 V
VC1 = VG1 = 2 V
5−2
IC2 =
= 1 mA
Q.E.D.
3
2ID1
2 × 0.1
=
= 0.67 mA/V
(b) gm1 =
VOV
0.3
Cgs = Cgd = 1 pF
=
476
= 0.83 V/V
476 + 100
Vo
= 0.83 × 20 = 16.5 V/V
Vsig
(c) The pole due to C1 has a frequency f1 :
IC
1 mA
= 40 mA/V
=
VT
0.025 V
β
200
rπ 2 =
=
= 5 k
gm2
40
gm2
Cπ 2 + Cμ2 =
2πfT 2
gm2 =
f1 =
=
1
2πC1 (Rsig + Rin )
1
2π × 0.1 ×
10−6 (100
+ 476) × 103
= 2.8 Hz
40 × 10−3
=
= 10.6 pF
2π × 600 × 106
Cμ2 = 0.8 pF
The pole due to C2 has a frequency f2 :
f2 =
Cπ 2 = 9.8 pF
1
2πC2 (3 + 1) × 103
1
= 40 Hz
2π × 1 × 10−6 × 4 × 103
Since f2 f1 , the lower 3-dB frequency fL will be
=
(c) Q1 acts as a source follower, thus
6.8 k rπ 2
Vb2
=
1
Vi
+ (6.8 k rπ 2 )
gm1
(6.8 5)
= 0.66 V/V
=
1.5 + (6.8 5)
Neglecting RG , we obtain
Vo
= −gm2 (3 k 1 k)
Vb2
= −40(3 1) = −30 V/V
fL f2 = 40 Hz
(d) τgd 1 = Cgd 1 (Rin Rsig )
= 1 × 10−12 (476 100) × 103
= 82.6 ns
To determine the resistance Rgs seen by Cgs , refer
to Fig. 2.
This figure belongs to Problem 9.96, part (d).
Rsig
Rsig 100 k
⬅
Ix
Vx
gmVx
Cgs
Ix
Rs 6.8 k // rp2
Figure 2
Rs
Chapter 9–43
Since CL = 0, we can obtain a good estimate of
fH using the Miller approximation:
We can show that
Rsig + Rs
Vx
=
Rgs ≡
Ix
1 + gm1 Rs
Cin = Cπ + Cμ (gm RL + 1)
where
= 6 + 2(20 × 10 + 1)
Rs = 6.8 k rπ 2
= 408 pF
= 6.8 5 = 2.88 k
1
2πRsig Cin
100 + 2.88
= 35.1 k
Rgs =
1 + 0.67 × 2.88
fH =
τgs = Cgs Rgs = 1 × 10−12 × 35.1 × 103 = 35.1 ns
=
τπ 2 = Cπ 2 (rπ 1 6.8 k)
= 39 kHz
−12
= 9.8 × 10
× 2.88 × 10
1
2π × 10 × 103 × 408 × 10−12
3
= 28.2 ns
1
6.8 k [1 + gm2 (3 1)] + (3 1)
Rμ2 =
gm1
3
+ 0.75
= (1.5 6.8) 1 + 40 ×
4
(b) This is a cascode amplifier. Refer to Fig. 9.30
for the analysis equations.
AM = −
−
rπ
gm (βro RL )
rπ + Rsig
rπ
gm RL
rπ + Rsig
= 38.8 k
= −66.7 V(V) (same as the CE in (a))
τμ2 = Cμ2 Rμ2 = 0.8 × 38.8 = 31.1 ns
Rsig = rπ Rsig = 5 10 = 3.33 k
τH = τgd + τgs + τπ 2 + τμ2
Rπ1 = Rsig
= 82.6 + 35.1 + 38.8 + 31.1
τπ1 = Cπ1 Rπ1 = 6 × 3.33 = 20 ns
= 187.6 ns
1
fH =
2πτH
Rc1 = re2 = 50 =
Rμ1 = Rsig (1 + gm1 Rc1 ) + Rc1
1
= 848 kHz
2π × 187.6 × 10−9
9.97 All transistors are operating at
IE = 0.5 mA. Thus,
gm 20 mA/V
re 50 β
100
= 5 k
=
rπ =
gm
20
ro = very high (neglect)
rx = very small (neglect)
Cπ + Cμ =
gm
20 × 10−3
=
2πfT
2π × 400 × 106
= 8 pF
Cμ = 2 pF
= 3.33(1 + 40 × 0.05) + 0.05
= 3.33(1 + 2) + 0.05 = 10.05 k
τμ1 = Cμ1 Rμ1 = 2 × 10.05 = 20.1 ns
τc1 = Cπ2 Rc1 = 6 × 0.05 = 0.3 ns
τμ2 = Cμ2 RL = 2 × 10 = 20 ns
τH = 20 + 20.1 + 0.3 + 20 = 60.4 ns
fH =
1
1
=
2πτH
2π × 60.4 × 10−9
= 2.6 MHz
(c) This is a CC-CB cascade similar to the circuit
analyzed in Fig. 9.42. There are two poles: one at
the input,
1
fP1 =
2π(Rsig 2rπ )
Cπ = 6 pF
(a) CE amplifier
rπ
gm RL
AM = −
rπ + Rsig
=−
5
× 20 × 10 = −66.7 V/V
5 + 10
fP1 =
=
Cπ
+ Cμ
2
1
2π(10 10) × 103 (3 + 2) × 10−12
1
2π × 5 × 5 × 10−9
= 6.4 MHz
Chapter 9–44
and one at the output,
fP2 =
=
1
2πRL Cμ
1
2π × 10 × 103 × 2 × 10−12
= 8 MHz
Since the two poles are relatively close to each
other, we use the root-sum-of-the-squares formula
to obtain an estimate for fH :
1
1
fH = 1/ 2 + 2
fP1
fP2
1
1
= 1/
+ 2 = 5 MHz
8
6.42
AM =
RL
Rsig
2re +
β +1
10
50 V/V
10
2 × 0.05 +
101
(d) This is a CC-CE cascade similar to the circuit
analyzed in Example 9.13.
=
Rin = (β1 + 1)(re1 + rπ 2 )
τπ 1 = Cπ1 Rπ1 = 6 × 0.15 = 0.9 ns
Rπ2 = Rin2 Rout1
Rsig
+ re1
= rπ2 β1 + 1
10
+ 0.05 = 0.15 k
=5
101
τπ 2 = Cπ2 Rπ2 = 6 × 0.15 = 0.9 ns
Rμ2 = (1 + gm2 RL )(Rin2 Rout1 ) + RL
10
= (1 + 20 × 10) 5 + 0.05 + 10
101
= 39.1 k
τμ2 = Cμ2 Rμ2 = 2 × 39.1 = 78.2 ns
τH = 19.6 + 0.9 + 0.9 + 78.2 = 99.6 ns
fH =
1
= 1.6 MHz
2π × 99.6 × 10−9
(e) This is a folded cascode amplifier. The
analysis is identified to that for (b) above.
AM = −66.7 V/V
= 101(0.05 + 5) = 510 k
fH = 2.6 MHz
Rin
510
Vb1
=
=
Vsig
Rin + Rsig
510 + 10
(f) This is a CE-CB cascade. The analysis is
identical to that for case (c) above.
= 0.98 V/V
rπ 2
5
Vb2
=
=
= 0.99 V/V
Vb1
rπ 2 + re1
5 + 0.05
AM = 50 V/V
fH = 5 MHz
Vo
= −gm2 RL = −20 × 10 = −200 V/V
Vb2
AM =
Vo
= −0.98 × 0.99 × 200 = −194 V/V
Vsig
Rμ1 = Rsig Rin
Summary of Results
Case Configuration AM (V/V) fH (MHz)
= 10 510 = 9.81 k
a
CE
−66.7
0.039
τμ1 = Cμ1 Rμ1 = 2 × 9.81 = 19.6 ns
b
Cascode
−66.7
2.6
c
CC-CB
50
5
d
CC-CE
−194
1.6
e
Folded Cascode
−66.7
2.6
f
CC-CB
50
5
Rπ 1
=
Rsig + Rin2
=
Rsig
Rin2
1+
+
rπ 1
re1
10 + 5
= 0.15 k
5
10
+
1+
5
0.05
Exercise 10–1
10
Vo
= 4 = 0.001 V
A
10
Ex: 10.1 (c) A = 100 V/V and Af = 10 V/V
Vi =
Since A is not much greater than Af , we shall use
the exact expression to determine β and hence
R2 /R1 ,
(f) A ⇒ 0.8 × 104 V/V
Af =
A
1 + Aβ
100
10 =
1 + 100β
⇒ β = 0.09 V/V
Af =
0.8 × 104
1 + 0.8 × 104 × 9 × 10−4
= 975.6 V/V
975.6 − 1000
× 100
1000
= −2.44% or a reduction of 2.44%.
which is a change of
Now,
R1
= 0.09
R1 + R2
1
R2
=
− 1 = 10.11
R1
0.09
(d) Aβ = 100 × 0.09 = 9
1 + Aβ = 10
⇒ 20 dB
(e) Vo = Af Vs = 10 × 1 = 10 V
Vf = βVo = 0.09 × 10 = 0.9 V
10
Vo
=
= 0.1 V
A
100
(f) A → 80 V/V
Vi =
80
= 9.756
Af =
1 + 80 × 0.09
9.756 − 10
× 100 = −2.44% or a
a change of
10
reduction of 2.44%.
Ex. 10.2 (c) A = 104 V/V and Af = 103 V/V
A
Af =
1 + Aβ
104
103 =
1 + 104 β
⇒ β = 9 × 10−4 V/V
R1
= 9 × 10−4
R1 + R2
R2
1
=
− 1 = 1110.1
R1
9 × 10−4
(d) Aβ = 104 × 9 × 10−4 = 9
1 + Aβ = 10
⇒ 20 dB
(e) Vs = 0.01 V
Vo = Af Vs = 103 × 0.01 = 10 V
Vf = βVo = 9 × 10−4 × 10 = 0.009 V
Ex. 10.3 To constrain the corresponding change
in Af to 0.1%, we need an amount-of-feedback of
at least
10%
= 100
1 + Aβ =
0.1%
Thus the largest obtainable closed-loop gain will
be
1000
A
=
= 10 V/V
Af =
1 + Aβ
100
Each amplifier in the cascade will have a nominal
gain of 10 V/V and a maximum variability of
0.1%; thus the overall voltage gain will be
(10)3 = 1000 V/V and the maximum variability
will be 0.3%.
Ex. 10.4 β =
R1
1
= 0.1
=
R1 + R2
1+9
Aβ = 104 × 0.1 = 1000
1 + Aβ = 1001
Af =
A
1 + Aβ
Af =
104
= 9.99 V/V
1 + 104 × 0.1
fHf = fH (1 + Aβ)
= 100 × 1001 = 100.1 kHz
Ex. 10.5 Signal at output = Vs
=1×
100
1 × 100
=1×
1V
1 + 1 × 100 × 1
101
Interference at output = Vn
=1×
A1 A2
1 + A1 A2 β
A1
1 + A1 A2 β
1
0.01 V
1 + 1 × 100 × 1
Thus S/I at the output becomes 1/0.01
= 100 or 40 dB
Since S/I at the input is 1/1=1 or 0 dB, the
improvement is 40 dB.
Exercise 10–2
Ex. 10.6 (a) Refer to Fig. 10.8(c).
R1
R1 + R2
β=
A
36.36
=
= 4.4 V/V
1 + Aβ
1 + 36.36 × 0.2
Af =
If Aβ were 1, then
(b)
1
1
=
= 5 V/V
β
0.2
Af Ex. 10.7 From the solution of Example 10.4,
Aβ = 6
RD
1 + Aβ = 7
Vd
fHf = (1 + Aβ)fH
R2
Q
V
t
Vr
=7×1
= 7 kHz
R1
Ex. 10.8 Refer to Fig. E10.8. The 1-mA bias
current will split equally between the emitters of
Q1 and Q2 , thus
Figure 1
Figure 1 shows the circuit prepared for
determining the loop gain Aβ. Observe that we
have eliminated the input signal Vs , and opened
the loop at the gate of Q where the input
impedance is infinite obviating the need for a
termination resistance at the right-hand side of the
break. Now we need to analyze the circuit to
determine
Vr
Aβ ≡ −
Vt
First, we write for the gain of the CS amplifier Q,
Vd
= −gm [RD (R1 + R2 )]
Vt
(1)
then we use the voltage-divider rule to find Vr ,
R1
Vr
=
Vd
R1 + R2
Combining Eqs. (1) and (2) gives
Aβ ≡ −
Thus,
R1
Vr
= gm [RD (R1 + R2 )]
Vt
R1 + R2
IE1 = IE2 = 0.5 mA
Transistor Q3 will be operating at an emitter
current
IE3 = 5 mA
determined by the 5-mA current source. Since the
dc component of Vs = 0, the negative feedback
will force the dc voltage at the output to be
approximately zero. See Fig. 1 on next page.
The β circuit is shown in Fig. 1 together with the
determination of β and of the loading effects of
the β circuit on the A circuit,
β=
R1
1
= 0.1 V/V
=
R1 + R2
1+9
R11 = R1 R2 = 1 9 = 0.9 k
(2)
R22 = R1 + R2 = 1 + 9 = 10 k
The A circuit is shown in Fig. 2. See figure on
next page.
re1 = re2 =
which can be simplified to
Aβ = gm
RD R1
RD + R1 + R2
re3 =
(c) A =
Aβ
β
ie =
= gm
RD (R1 + R2 )
RD + R1 + R2
20
R1
=
= 0.2 V/V
(d) β =
R1 + R2
20 + 80
10 × 20
= 7.27
Aβ = 4
10 + 20 + 80
A=
7.27
= 36.36 V/V
0.2
ie =
VT
25 mV
= 50 =
IE1,2
0.5 mA
VT
25 mV
=5
=
IE3
5 mA
Vi
re1 + re2 +
Rs + R11
β +1
Vi
0.05 + 0.05 +
10 + 0.9
101
⇒ ie = 4.81Vi
Rb3 = (β + 1)[re3 + (R22 RL )]
= 101[0.005 + (10 2)]
= 168.84 k
(1)
Exercise 10–3
These figures belong to Exercise 10.8.
R2
R2
1
2
R1
Vf 1
Vo
2
R1
b
0
R2
1
Vf
R1
Vo R1 R2
2
R1
R2
1
2
R1
R22 R1 R2
R11 R1 R2
Figure 1
RC
20 k
Q3
aie
Rs 10 k
Q1
Vi
ib3
ie3
Q2
Vo
Rb3
ie
R22
R11
RL 2 k
Ro
Ri
Figure 2
Vo
= 85 V/V
Vi
ib3 = αie
RC
RC + Rb3
A≡
= 0.99 ie
20
20 + 168.84
β = 0.1 V/V
⇒ ib3 = 0.105ie
Aβ = 8.5
(2)
Vo = ie3 (R22 RL )
85
= 8.95 V/V
9.5
From the A circuit, we have
Af =
= (β + 1)ib3 (R22 RL )
= ib3 × 101(10 2)
⇒ Vo = 168.33ib3
Combining (1)–(3), we obtain
1 + Aβ = 9.5
Ri = Rs + R11 + (β + 1)(re1 + re2 )
(3)
= 10 + 0.9 + 101 × 0.1
= 21 k
Exercise 10–4
Rif = Ri (1 + Aβ)
= 21 × 9.5 = 199.5 k
RD
Rin = Rif − Rs = 199.5 − 10 = 189.5 k
From the A circuit, we have
RC
Ro = RL R22 re5 +
β +1
20
= 2 10 0.005 +
101
Vo
R22
Q
= 181 Rof
R11
Ro
=
1 + Aβ
Vi 181
= 19.1 9.5
Rof = RL Rout
=
Ri
Figure 2
19.1 = 2 k Rout
R1
β=
R1 + R2
A
Af =
1 + Aβ
⇒ Rout = 19.2 Ex. 10.9 Figure 1 shows the β circuit together
with the determination of β, R11 and R22 .
β=
From A circuit, we have
Ri =
R1
R1 + R2
1
gm
Ro = RD R22
R11 = R1 R2
Rin = Rif = Ri (1 + Aβ)
R22 = R1 + R2
1
(1 + Aβ)
gm
Rin =
Figure 2 shows the A circuit. We can write
Vo = gm (RD R22 )Vi
Rout = Rof =
Thus,
A≡
Rout =
Vo
= gm [RD (R1 + R2 )]
Vi
Ro
1 + Aβ
RD (R1 + R2 )
1 + Aβ
This figure belongs to Exercise 10.9.
R2
R2
1
2
R1
Vf 1
Vo
2
R1
b
0
R2
1
R1
Vf
R1
Vo R1 R2
2
1
R2
R1
2
R22 R1 R2
R11 R1 R2
Figure 1
Ro
Exercise 10–5
Comparison with the results of Exercise 10.6
shows that the expressions for A and β are
identical. However, Rin and Rout cannot be
determined using the method of Exercise 10.6.
Using Eq. (10.36), we obtain
Af =
Ex. 10.10 From the solution to Example 10.6, we
have
Aβ = 653.6
1 + Aβ = 654.6
A decrease in the op amp gain by 10% results in a
decrease in A by 10% and a corresponding
decrease in Af by
A1 gm2
1 + A1 gm2 RF
200 × 2
= 4.94 mA/V
1 + 200 × 2 × 0.2
From Eq. (10.32), we have
Ri = Rs + Rid + RF
Rid + RF
= 100 + 0.2 = 100.2 k
From Eq. (10.35), we get
Aβ A1 gm2 RF = 200 × 2 × 0.2 = 80
10%
10%
=
= 0.015%
1 + Aβ
654.6
1 + Aβ = 81
A more exact solution (not using differential) is as
follows:
= 81 × 100.2 8.1 M
The open-loop gain A becomes
From Eq. (10.33), we have
A = 0.9 × 653.6 = 588.24 mA/V
Ro = ro2 + RL + RF
β = RF = 1 k
ro2 + RF
Af =
588.24
1 + 588.24 × 1
= 0.9983 mA/V
Change in Af = 0.9983 − 0.9985
= −0.0002
−0.0002
× 100
Percentage change in Af =
0.9983
= −0.02%
Rif = (1 + Aβ)Ri
= 20 + 0.2 = 20.2 k
Rof = Ro (1 + Aβ) = 20.2 × 81 = 1.64 M
If gm2 drops by 50%, A drops by 50% to
A = A1 gm2 = 200 × 1 = 200 mA/V
and Af becomes
Af =
200
= 4.878 mA/V
1 + 200 × 0.2
Thus,
Ex. 10.11 For a nominal closed-loop
transconductance of 2 mA/V, we have
1
= 0.5 k
RF = β =
2 mA/V
From the solution to Example 10.6, we obtain
gm (RF Rid ro2 )
μ
A=
RF 1 + gm (RF Rid ro2 )
A=
1000 2(0.5 100 20)
0.5 1 + 2(0.5 100 20)
A = 985.2 mA/V
Io
985.2
=
= 1.996 mA/V
Af ≡
Vs
1 + 985.2 × 0.5
Ex. 10.12 Af 5 mA/V
β
1
= 0.2 k = 200 Af
RF = 200 Af = 4.94 − 4.878 = −0.062
Af
0.062
× 100 = −1.25%
× 100 = −
Af
4.94
Ex. 10.13 See figure on next page. Figure 1
shows the circuit for determining the loop gain.
The figure also shows the analysis. We start by
finding the current in the drain of Q2 as gm2 Vg2
(this excludes the current in ro2 ). Since
ro2 RL + RF , most of gm2 Vg2 will flow through
RL and RF (Rid + Rs ). Since RF Rid + Rs , the
voltage across RF will be approximately
−gm2 Vg2 RF . This voltage is amplified by A1
which provides at its output
Vr = −A1 gm2 RF Vg2
Thus, we find Aβ as
Aβ ≡ −
Vr
= A1 gm2 RF
Vg2
Exercise 10–6
This figure belongs to Exercise 10.13.
Rs
G2
A1
Vr
Rid
Vg2
ro2 RL RF
Q2
gm2Vg2
0
Rid Rs RF
gm2Vg2
RL
gm2Vg2 RF
RF
Figure 1
Rout = Rof − RL
Ex. 10.14 From Eq. (10.34), we obtain
Aβ =
(A1 gm2 RF )
Rid
Rid + Rs + RF
ro2
ro2 + RL + RF
Rout ro2 (1 + A1 gm2 RF )
Ri = Rs + Rid + RF
Rif = Ri (1 + Aβ)
= Rs + Rid + RF + (A1 gm2 RF )Rid
Rin = Rif − Rs
Rin = Rid + RF + (Agm2 RF )Rid
ro2
ro2 + RL + RF
ro2
ro2 + RL + RF
For RF Rid and ro2 RL + RF , we have
Af ≡
when the loop gain is large, we use
β
Ex. 10.15 From Eq. (10.34), we obtain
Rid
Rid + Rs + RF
ro2
ro2 + RL + RF
RE2
RE2 + RF + RE1
For RE1 = RE2 = 100 ,
Q.E.D.
1
= 10 Af
But,
10 =
(A1 gm2 RF )
Q.E.D.
Io
100 mA/V
Vs
β = RE1 ×
Rin Rid + Agm2 RF Rid
ro2
Ex. 10.16 To obtain
= Ri + AβRi
Aβ =
For RF ro2 and Rid Rs + RF , we have
From Eq. (10.32), we obtain
= Rid (1 + Agm2 RF )
Rid
= ro2 + RF + (A1 gm2 RF )
Rid + Rs + RF
From Eq. (10.33), we get
100 × 100
200 + RF
⇒ RF = 800 −Io RC1
Vo
=
Vs
Vs
= −Af RC1 = −100 × 0.6 = −60 V/V
Ro = ro2 + RL + RF
Rof = Ro (1 + Aβ)
= Ro + AβRo
= ro2 +RL +RF +(A1 gm2 RF )
Rid
ro2
Rid + Rs + RF
Ex. 10.17 See figure on next page. Figure 1
shows the circuit prepared for the determination
of the loop gain,
Aβ ≡ −
Vr
Vt
Exercise 10–7
This figure belongs to Exercise 10.17.
RC3
RC2
RC1
Ic1
rp2
Q1
re1
Vr
Q3
Ic2
Q2
Vt Ib3
Ri3
Ie3
Ie1
RF
If
RE2
RE1
Figure 1
We shall trace the signal around the loop as
follows:
Ic2 = gm2 Vt
(1)
RC2
Ib3 = Ic2
RC2 + Ri3
(2)
where
Ri3 = (β + 1) re3 + [RE2 (RF + (RE1 re1 ))]
(3)
Ie3 = (β + 1)Ib3
(4)
Ie3 = 101Ib3
(11)
If = 0.13Ie3
(12)
Ie1 = 0.706If
(13)
Ic1 = 0.99Ie1
(14)
Vr = −1.957Ic1
(15)
Combining (9)–(15), we obtain
If = Ie3
RE2
RE2 + RF + (RE1 re1 )
(5)
Ie1 = If
RE1
RE1 + re1
(6)
Ic1 = αIe1
(7)
Vr = −Ic1 (RC1 rπ 2 )
(8)
Aβ = −
Ex. 10.18
RF
ro
Rs
Combining (1)–(7) gives Vr in terms of Vt and
hence Aβ ≡ −Vr /Vt . We shall do this
numerically using the values in Example 10.8:
Vr
= 249.3
Vt
V Vr t Rid
gm2 = 40 mA/V, RC2 = 5 k, β = 100,
Rid mV
t
RL
Figure 1
re3 = 6.25 , RE1 = RE2 = 100 , RF = 640 ,
Figure 1 shows the circuit prepared for
determining the loop gain
re1 = 41.7 , α1 = 0.99, RC1 =
9 k, and rπ 2 = 2.5 k
Ri3 = 101 0.00625 + [0.1
(0.64
+ (0.1 0.0417))]
Aβ ≡ −
Using the voltage-divider rule, we can write by
inspection
= 9.42 k
Ic2 = 40Vt
Ib3 = 0.347Ic2
Vr
Vt
(9)
Vr =
(10)
−μVt
RL [RF + (Rs Rid )]
(Rs Rid )
ro + RL [RF + (Rs Rid )] RF + (Rs Rid )
Exercise 10–8
Vr =
RL (Rs Rid )
−μVt
ro [RL + RF + (Rs Rid )] + RL [RF + (Rs Rid )]
Thus,
Aβ = −
Q.E.D.
Using the numerical values in Example 10.9, we
get
104 × 1 × 1
Aβ =
0.1(1 + 10 + 1) + 1(10 + 1)
RF
1 + gm (ro RF )
(d) Rout = Rof =
=
Ex. 10.19 See figure on next page. Figure 1(a)
shows the feedback amplifier circuit. The β
circuit is shown in Fig. 1(b), and the
determination of β is shown in Fig. 1(c),
1
RF
Q.E.D.
Ro
1 + Aβ
ro RF
1 + gm (Rs RF )(ro RF )/RF
1
1
1
gm (Rs RF )
=
+
+
Rout
ro
RF
RF
⇒ Rout = ro = 819.7
RF
1 + gm (Rs RF )
(e) A = −5(1 10)(20 10)
A = −30.3 k
β=−
1
1
= −0.1 mA/V
=−
RF
10
1 + Aβ = 4.03
Af =
1
= −RF
β
(b) The determination of R11 and R22 is illustrated
in Figs. 1(d) and (e), respectively:
30.3
A
=−
= −7.52 k
1 + Aβ
4.03
(Compare to the ideal value of −10 k).
Ri = Rs RF = 1 10 = 909 R11 = R22 = RF
Ro = ro RF = 20 10 = 6.67 k
Finally, the A circuit is shown in Fig. 1(f). We can
write by inspection
909
Ri
=
= 226 1 + Aβ
4.03
1
1
−
= 291 Rin = 1
Rif
Rs
Ri = Rs R11 = Rs RF
Ro = ro R22 = ro RF
Vgs = Ii Ri
Ex. 10.20 From Eq. (10.54), we obtain
Vo
A
=
Is
1 + Aβ
A = −μ
Af =
gm (Rs RF )(ro RF )
1 + gm (Rs RF )(ro RF )/RF
(c) Rif =
Ri
1 + Aβ
Rs RF
Rif =
1 + gm (Rs RF )(ro RF )/RF
1
1
gm (ro RF )
1
=
+
+
Rif
Rs
RF
RF
Ro
6.67
=
= 1.66 k
1 + Aβ
4.03
Rout = Rof = 1.66 k
Thus,
Vo
= −gm (Rs RF )(ro RF )
A≡
Ii
−
Rif =
Rof =
Vo = −gm Vgs (ro R22 )
Af =
Q.E.D.
Aβ = 3.03
(a) For large loop gain, we have
Af 1
1
=
[1 + gm (ro RF )]
Rin
RF
⇒ Rin =
Vr
=
Vt
μRL (Rid Rs )
ro [RL + RF + (Rid Rs )] + RL [RF + (Rid Rs )]
β=−
thus,
Q.E.D.
R1 R2 ro2
Ri
R1 R2 1/gm + (R1 R2 ro2 )
For μ = 100, R1 = 10 k, R2 = 90 k,
gm = 5 mA/V, ro2 = 20 k, we have
Ri = Rs Rid (R1 + R2 )
= ∞ ∞ 100 = 100 k
A = −100
10 90 20
100
10 90 0.2 + (10 90 20)
= −1076.4 A/A
10
R1
= −0.1 A/A
=−
R1 + R2
10 + 90
But,
β=−
1
1
1
=
+
Rif
Rs
Rin
Af = −
1076.4
= −9.91 A/A
1 + 107.64
Exercise 10–9
This figure belongs to Exercise 10.19.
RF
Vo
Is
Vgs
Rs
gmVgs
ro
Rif
Rout Rof
Rin
(a)
If
RF
1
RF
1
2
Vo
2
b
(b)
1
If
RF
Vo
(c)
RF
RF
1
1
2
R11 RF
2
R22 RF
(e)
(d)
Vo
Ii
Rs
R11 Vgs
R22
gmVgs
ro
Ro
Ri
(f)
Figure 1
Rif =
Ri
100 k
=
= 920 1 + Aβ
108.64
Rin = Rif = 920 Rout = Rof = Ro (1 + Aβ)
Ro = ro2 + (R1 R2 ) + gm ro2 (R1 R2 )
= 929 k
Rout = 929 × 108.64 = 101 M
Substituting R2 = 0 and Rs = Rid = ∞ in Eq.
(10.50), we obtain
Ri = R1
and in Eq. (10.55), we obtain
Ro = ro2
and in Eq. (10.53), we obtain
A = −μ
Ex. 10.21 With R2 = 0, Eq. (10.48) gives
β = −1
Af = −1 A/A
R1
= −μgm R1
1/gm
Now,
Af =
A
1 + Aβ
Exercise 10–10
Af = −
μgm R1
1 + μgm R1
1 + A0 β = 1 + 105 × 0.01 = 1001
Rin = Rif = Ri /(1 + Aβ)
=
R1
1 + μgm R1
Rin 1/μgm
Rout = Rof = (1 + Aβ)Ro
= (1 + μgm R1 )ro2
β1
and
then the pole will be shifted to a frequency
Ex. 10.22 Total phase shift will be 180◦ at the
frequency ω180 at which the phase shift of each
amplifier stage is 60◦ . Thus,
◦
= 60
◦
ω180 = tan 60 × 10
√
= 3 × 104 rad/s
4
At ω180 , we have
| A| =
If β is changed to a value that results in a nominal
closed-loop gain of 1, then we obtain
1 + A0 β = 1 + 105 × 1 105
μ(gm ro2 )R1
fPf = fP (1 + A0 β)
= 100 × 1001 = 100.1 kHz
For μgm R1 1, we have
ω180
tan−1 4
10
The pole will be shifted to a frequency
10
√
1+3
3
= 125
Thus, the loop gain magnitude will be
fPf = 105 × 100 = 10 MHz
Ex. 10.24 From Eq. (10.68), we see that the
poles coincide when
(ωP1 + ωP2 )2 = 4(1 + A0 β)ωP1 ωP2
(104 + 106 )2 = 4(1 + 100β) × 104 × 106
⇒ 1 + 100β = 25.5
⇒ β = 0.245
The corresponding value of Q = 0.5. This can
also be verified by substituting in Eq. (10.70).
A maximally
√ flat response is obtained when
Q = 1/ 2. Substituting in Eq. (10.70), we obtain
(1 + 100β) × 104 × 106
104 + 106
| Aβ| = 125β
1
√ =
2
For stable operation, we require
⇒ β = 0.5
125βcr < 1
In this case, the low-frequency closed-loop gain is
1
⇒ βcr =
= 0.008
125
Af (0) =
β ≥ βcr will result in oscillations.
Correspondingly, the minimum closed-loop gain
for stable operation will be
=
Af =
=
103
1 + 103 βcr
1000
103
=
= 111.1
1 + 1000 × 0.008
9
Ex. 10.23 The feedback shifts the pole by a
factor equal to the amount of feedback:
A0
1 + A0 β
100
= 1.96 V/V
1 + 100 × 0.5
Ex. 10.25 The closed-loop poles are the roots of
the characteristic equation
1 + A(s)β = 0
⎛
⎞3
⎜
1+⎝
⎟
s ⎠β = 0
1+ 4
10
10
Exercise 10–11
To simplify matters, we normalize s by the factor
104 , thus obtaining the normalized
complex-frequency variable S = s/104 , and the
characteristic equation becomes
(S + 1)3 + 103 β = 0
(1)
From Fig. 1, we can easily obtain the loop gain as
Aβ = A(s) × 0.01
=
105
1+
× 0.01
s
2π × 10
1000
s
1+
2π × 10
This equation has three roots, a real one and a pair
that can be complex conjugate. The real pole can
be found from
=
(S + 1)3 = −103 β
From this single-pole response (low-pass STC
response) we can find the unity-gain frequency by
inspection as
⇒ S = −1 − 10β 1/3 = − 1 + 10β 1/3
(2)
f1 = fP × 1000
Dividing
the characteristic
polynomial in (1) by
S + 1 + 10β 1/3 gives a quadratic whose two
roots are the remaining poles of the feedback
amplifier. After some straightforward but
somewhat tedious algebra, we obtain
The phase angle at f1 will be −90◦ and thus the
phase margin is 90◦ .
S 2 + 10β 1/3 − 2 S + 1 + 100β 2/3 − 10β 1/3
Ex. 10.27 From Eq. (10.82), we obtain
=0
(3)
The pair of poles can now be obtained as
√
S = −1 + 5β 1/3 ± j5 3 β 1/3
= 104 Hz
| Af (jω1 )|
= 1/|1 + e−jθ |
1/β
= 1/|1 + cos θ − j sin θ|
(4)
(a) For PM = 30◦ , θ = 180 − 30 = 150◦ , thus
Equations (1) and (3) describe the three poles
shown in Fig. E10.25.
| Af (jω1 )|
= 1/|1 + cos 150◦ − j sin 150◦ |
1/β
From Eq. (2) we see that the pair of complex
poles lie on the jω axis for the value of β that
makes the coefficient of S equal to zero, thus
= 1.93
βcr =
2
10
3
(b) For PM = 60◦ , θ = 180 − 60 = 120◦ , thus
| Af (jω1 )|
= 1/|1 + cos 120◦ − j sin 120◦ |
1/β
= 0.008
Note that this is the same value found in the
solution of Exercise 10.22.
=1
(c) For PM = 90◦ , θ = 180 − 90 = 90◦ , thus
| Af (jω1 )|
= 1/|1 + cos 90◦ − j sin 90◦ |
1/β
Ex. 10.26
99R
√
= 1/ 2 = 0.707
R
Figure 1
A (s)
Ex. 10.28 See figure on next page. To obtain
guaranteed stable performance, the maximum rate
of closure must not exceed 20 dB/decade. Thus
we utilize the graphical construction in Fig. 1 to
obtain the
Exercise 10–12
This figure belongs to Exercise 10.28.
dB
“rate of closure” 20 dB/decade
|A|
20 dB/decade
100
40 dB/decade
80
de
eca
B/d
d
0
60
2
40
20
102
101
1
20 log b
100
forntiat
e
e
fr
dif
or
101
vdifferentiator 10 2
10 3
10 4
10 5
10 6 f (Hz)
1
τ
Figure 1
maximum value of the differentiator frequency as
1 Hz. Thus,
Ex. 10.30 The frequency of the first pole must be
lowered from 1 MHz to a new frequency
1
≤ 2π × 1 Hz
τ
1
s = 159 ms
τ≥
2π
10 MHz
= 1000 Hz
104
that is, by a factor of 1000. Thus, the capacitance
at the controlling node must be increased by a
factor of 1000.
Ex. 10.29 To obtain stable performance for
closed-loop gains as low as 20 dB (which is 80
dB below A0 , or equivalently 104 below A0 ),
we must place the new dominant pole at
1 MHz/104 = 100 Hz.
fD =
Chapter 10–1
10.1 Af =
200 =
R2 = 10
A
1 + Aβ
= 290 k
104
1 + 104 β
(c) (i) A = 1000(1 − 0.2) = 800 V/V
⇒ β = 4.9 × 10−3
3
If A changes to 10 , then we get
Af =
1+
103
1
−1
0.033
800
1 + 800 × 0.099
= 9.975 V/V
1000
× 4.9 × 10−3
Thus, Af changes by
1000
= 169.5
=
5.9
Percentage change in Af =
Af =
9.975 − 10
× 100 = −0.25%
10
(ii) A = 200(1 − 0.2) = 160 V/V
=
169.5 − 200
× 100
200
= −15.3%
Af =
160
= 9.877 V/V
1 + 160 × 0.095
Thus, Af changes by
10.2 (a) Because of the infinite input resistance
of the op amp, the fraction of the output voltage
Vo that is fed back and subtracted from Vs is
determined by the voltage divider (R1 , R2 ), thus
R1
β=
R1 + R2
(b) (i) A = 1000 V/V
A
Af =
1 + Aβ
10 =
1000
1 + 1000β
⇒ β = 0.099 V/V
R1
= 0.099
R1 + R2
1
R2
=
R1
0.099
1
−1
R2 = R1
0.099
1
− 1 = 91 k
= 10
0.099
1+
(ii) A = 200 V/V
200
10 =
1 + 200β
⇒ β = 0.095 V/V
1
−1
R2 = R1
0.095
1
− 1 = 95.3 k
= 10
0.095
(iii) A = 15 V/V
10 =
15
1 + 15β
⇒ β = 0.033 V/V
9.877 − 10
× 100 = −1.23%
10
(iii) A = 15(1 − 0.2) = 12 V/V
=
Af =
12
= 8.574
1 + 12 × 0.033
Thus, Af changes by
8.575 − 10
× 100 = −14.3%
10
We conclude that as A becomes smaller and hence
the amount of feedback (1 + Aβ) is lower, the
desensitivity of the feedback amplifier to changes
in A decreases. In other words, the negative
feedback becomes less effective as (1 + Aβ)
decreases.
=
10.3 The direct connection of the output terminal
to the inverting input terminal results in Vf = Vo
and thus
β=1
If A = 1000, then the closed-loop gain will be
Af =
=
A
1 + Aβ
1000
= 0.999 V/V
1 + 1000 × 1
Amount of feedback = 1 + Aβ
= 1 + 1000 × 1 = 1001
or 60 dB
For Vs = 1 V, we obtain
Vo = Af Vs = 0.999 × 1 = 0.999 V
Vi = Vs − Vo = 1 − 0.999
= 0.001 V
Chapter 10–2
If A becomes 1000(1 − 0.1) = 900 V/V, then we
get
900
= 0.99889
Af =
1 + 900 × 1
Thus, Af changes by
=
0.99889 − 0.999
× 100 = −0.011%
0.999
10.4 A =
Vo
5V
=
= 500 V/V
Vi
10 mV
Vf = Vs − Vi = 1 − 0.01 = 0.99 V
β=
Vf
0.99
= 0.198 V/V
=
Vo
5
Ahigh = 1500
If we apply negative feedback with a feedback
factor β, then
Af , nominal =
1000
1 + 1000β
Af , low =
500
1 + 500β
Af , high =
1500
1 + 1500β
It is required that
Af , low ≥ 0.99Af , nominal
and
Af , high ≤ 1.01Af , nominal
10.5 (a) Af =
A
1 + Aβ
Ideally,
Af =
1
β
1
A
Af ideal − Af = −
β
1 + Aβ
1
1 + Aβ − Aβ
=
=
(1 + Aβ)β
(1 + Aβ)β
Expressed as a percentage of the ideal gain 1/β,
we have
1
Difference
=
× 100%
Ideal
1 + Aβ
For Aβ 1,
100
Difference
%
Ideal
Aβ
(b) For Af to be within:
(i) 0.1% of ideal value, then
100
≤ 0.1
Aβ
(1)
(2)
If we satisfy condition (1) with equality, we can
determine the required value of β. We must then
clock that condition (2) is satisfied. Thus,
500
1000
= 0.99 ×
1 + 500β
1 + 1000β
⇒ β = 0.098
For this value of β, we obtain
Af , nominal =
1000
1 + 1000 × 0.098
= 10.101
Af , low =
500
= 10
1 + 500 × 0.098
Af , high =
1500
= 10.135
1 + 1500 × 0.098
Thus, the low value of the closed-loop gain is
0.101 below nominal or −1%, and the high value
is 0.034 above nominal or 0.34%. Thus, our
amplifier meets specification and the nominal
value of closed-loop gain is 10.1. This is the
highest possible closed-loop gain that can be
obtained while meeting specification.
⇒ Aβ ≥ 1000
Now, if three closed-loop amplifiers are placed in
cascade, the overall gain obtained will be
(ii) 1% of ideal value, then
Nominal Gain = (10.1)3 = 1030
100
≤1
Aβ
Lowest Gain = 103 = 1000
⇒ Aβ ≥ 100
Highest Gain = (10.135)3 = 1041
(iii) 5% of ideal value, then
Thus, the lowest gain will be approximately 3%
below nominal, and the highest gain will be 1%
above nominal.
100
≤5
Aβ
⇒ Aβ ≥ 20
10.6 Anominal = 1000
Alow = 500
5V
= 2500 V/V
2 mV
5V
= 50 V/V
Af =
100 mV
10.7 A =
Chapter 10–3
Amount of feedback ≡ 1 + Aβ
=
we get
2500
A
= 50
=
Af
50
A=μ
or 34 dB
=μ
Rid /(R1 + Rid )
(R1 + R2 )
R1 Rid /(R1 + Rid ) + R2
=μ
Rid (R1 + R2 )
R1 Rid + R2 Rid + R1 R2
Aβ = 49
β=
49
= 0.0196 V/V
2500
R1 + R2
R1 Rid
(R1 Rid ) + R2
R1
Thus,
10.8
A=μ
X
Rid
Vs X'
V1 mV1
Vo
R2
Rid
Rid + (R1 R2 )
Q.E.D.
10.9 From Eq. (10.10), we have
dAf /Af
1
=
dA/A
1 + Aβ
Since −40 dB is 0.01, we have
0.01 =
R1
1
1 + Aβ
⇒ Aβ = 99
For
dAf /Af
1
=
dA/A
5
Figure 1
Rid
Vr Vt
Rid
V1
mV1 R2
R1
we have
1 + Aβ = 5
⇒ Aβ = 4
10.10 Af = 10 V/V
1 + Aβ =
Figure 2
Figure 1 shows the given circuit with the op amp
replaced with its equivalent circuit model. To
determine the loop gain Aβ, we short circuit Vs
and break the loop at the input terminals of the op
amp. To keep the circuit unchanged, we must
place a resistance equal to Rid at the left-hand side
of the break. This is shown in Fig. 2, where a test
signal Vt is applied at the right-hand side of the
break. To determine the returned voltage Vr , we
use the voltage-divider rule as follows:
R1 Rid
Vr = −μV1
(R1 Rid ) + R2
Substituting V1 = Vt and rearranging, we obtain
Aβ ≡ −
R1 Rid
Vr
=μ
Vt
(R1 Rid ) + R2
±10%
= 100
±0.1%
A
100
⇒ A = 1000 V/V
100 − 1
= 0.099 V/V
β=
1000
10 =
10.11 For A = 1000 V/V, we have
Af = 10 =
1000
1 + Aβ
⇒ Densensitivity factor ≡ 1 + Aβ = 100
Aβ = 99
99
= 0.099 V/V
1000
For A = 500 V/V, we have
β=
Af = 10 =
500
1 + Aβ
Since
⇒ Densensitivity factor ≡ 1 + Aβ = 50
R1
β=
R1 + R2
β=
49
= 0.098 V/V
500
Chapter 10–4
If the A = 1000 amplifiers have a gain
uncertainty of ±10%, the gain uncertainty of the
closed-loop amplifiers will be
=
±10%
= ±0.1%
100
Gain uncertainty of A = 500 amplifiers
50
⇒ Gain uncertainty = ±5%
2μ
1 + 2μβ
105 =
12μ
1 + 12μβ
(1)
(2)
Dividing Eq. (2) by Eq. (1) yields
1.105 =
6(1 + 2μβ)
1 + 12μβ
3.885
= 9.33 × 10−3 V/V
416.6
(6)
Dividing (6) by (5) yields
1.105 =
6(1 + 2μβ)
1 + 12μβ
⇒ μβ = 3.885
which is identical to the first case considered, and
μ=
9.5(1 + 2 × 3.885)
= 41.66 V/V
1 + 12μβ
which is a factor of 10 lower than the value
required when the gain required was 100. The
feedback factor β is
3.885
= 9.33 × 10−2 V/V
41.66
(b) Finally, for the case Af = 10 ± 0.5% we can
write by analogy
Substituting in Eq. (1) yields
β=
12μ
1 + 12μβ
(5)
which is a factor of 10 higher than the case with
Af = 10.
⇒ μβ = 3.885
95(1 + 2 × 3.885)
= 416.6 V/V
2
2μ
1 + 2μβ
10.5 =
β=
1.105 + 1.105 × 12μβ = 6 + 12μβ
μ=
(a) For ±5% maximum variability, Eqs. (1) and
(2) become
9.5 =
10.12 Let the gain of the ideal (nonvarying)
driver amplifier be denoted μ. Then, the
open-loop gain A will vary from 2μ to 12μ.
Correspondingly, the closed-loop gain will vary
from 95 V/V to 105 V/V. Substituting these
quantities into the closed-loop gain expression,
we obtain
95 =
49.92
= 9.95 × 10−3 V/V
5016.8
Repeating for Af = 10 V/V (a factor of 10 lower
than the original case):
β=
If we require a gain uncertainty of ±0.1% using
the A = 500 amplifiers, then
±0.1% =
which is more than a factor of 10 higher than the
gain required in the less constrained case. The
value of β required is
μβ = 49.92
μ = 501.68 V/V
β = 9.95 × 10−2 V/V
If Af is to be held to within ±0.5%, Eqs. (1) and
(2) are modified to
99.5 =
2μ
1 + 2μβ
100.5 =
12μ
1 + 12μβ
Dividing (4) by (3) yields
6(1 + 2μβ)
1.01 =
1 + 12μβ
⇒ μβ = 49.92
Substituting into (3) provides
μ=
99.5(1 + 2 × 49.92)
2
= 5016.8 V/V
(3)
(4)
10.13 If the nominal open-loop gain is A, then we
require that as A drops to (A/2) the closed-loop
gain drops from 10 to a minimum of 9.8.
Substituting these values in the expression for the
closed-loop gain, we obtain
10 =
A
1 + Aβ
A/2
1
1 + Aβ
2
Dividing Eq. (1) by Eq. (2) yields
1
2 1 + Aβ
2
1.02 =
1 + Aβ
9.8 =
(1)
(2)
Chapter 10–5
1.02 =
=1+
2 + Aβ
1 + Aβ
1
1 + Aβ
Af , low =
700
= 9.957 V/V
1 + 700 × 0.099
and a high value of
Af , high =
1300
= 10.023 V/V
1 + 1300 × 0.099
1
= 50
0.02
Substituting in Eq. (1) gives
Thus, the cascade of two stages will have a
range of
A = 10 × 50 = 500 V/V
Lowest gain = 9.9572 = 99.14 V/V
and
Highest gain = 10.0232 = 100.46 V/V
50 − 1
= 0.098 V/V
500
If β is accurate to within ±1%, to ensure that the
minimum closed-loop gain realized is 9.8 V/V,
we have
A/2
9.8 =
1
1 + A × 0.098 × 1.01
2
⇒ A = 653.4 V/V
which is −0.86% to +0.46% of the nominal
100 V/V gain, well within the required ±1%.
⇒ 1 + Aβ =
β=
10.15 Af =
10.14 If we use one stage, the amount of
feedback required is
1 + Aβ =
1000
A
= 10
=
Af
100
A
1 + Aβ
(1)
0.1A
1 + 0.1Aβ
(2)
100 =
99 =
A
1 + Aβ
Dividing Eq. (1) by Eq. (2) gives
1.01 =
10(1 + 0.1Aβ)
1 + Aβ
10 + Aβ
1 + Aβ
Thus the closed-loop amplifier will have a
variability of
=
±30%
= ±3%
10
which does not meet specifications. Next, we try
using two stages. For a nominal gain of 100, each
stage will be required to have a nominal gain of
10. Thus, for each stage the amount of feedback
required will be
=1+
1000
= 100
10
Thus, the closed-loop gain of each stage will have
a variability of
Substituting (1 + Aβ) = 900 into Eq. (1) yields
Variability of Af =
1 + Aβ =
±30%
= ±0.3%
100
and the cascade of two stages will thus show a
variability of ±0.6%, well within the required
±1%. Thus two stages will suffice.
=
We next investigate the design in more detail.
Each stage will have a nominal gain of 10 and thus
1000
= 100
10
⇒ Aβ = 99
1 + Aβ =
⇒ β = 0.099
Since A ranges from 700 V/V to 1300 V/V, the
gain of each stage will range from
⇒
9
1 + Aβ
9
= 0.01
1 + Aβ
1 + Aβ = 900
Aβ = 899
A = 100 × 900 = 90, 000 V/V
The value of β is
β=
899
= 9.989 × 10−3 V/V
90, 000
If A were increased tenfold, i.e, A = 900, 000, we
obtain
900, 000
= 100.1 V/V
Af =
1 + 8990
If A becomes infinite, we get
Af =
A
1 + Aβ
1
1
=
1
β
+β
A
1
= 100.11 V/V
=
9.989 × 10−3
=
Chapter 10–6
10.16 A = AM
s
s + ωL
A
1 + Aβ
Af =
C=
=
AM s/(s + ωL )
1 + AM βs/(s + ωL )
=
AM s
s + ωL + sAM β
=
AM s
s(1 + AM β) + ωL
AM
s
=
1 + AM β s + ωL /(1 + AM β)
Thus,
AM
1 + AM β
ωL
=
1 + AM β
AMf =
ωLf
10.19 Let’s first try N = 2. The closed-loop gain
of each stage must be
√
Af = 1000 = 31.6 V/V
Thus, the amount-of-feedback in each stage
must be
1 + Aβ =
A
1000
= 31.6
=
Af
31.6
f3dB |stage = (1 + Aβ)fH
1000
= 100
10
Thus,
fH f = (1 + AM β)fH
= 100 × 10 = 1000 kHz = 1 MHz
fL
fLf =
1 + AM β
=
1
4 μF
2π × 5000 × 8
The 3-dB frequency of each stage is
Thus, both the midband gain and the 3-dB
frequency are lowered by the amount of feedback,
(1 + AM β).
10.17 1 + AM β =
and the coupling capacitor C will have a value of
100
= 1 Hz
100
= 31.6 × 20 = 632 kHz
Thus, the 3-dB frequency of the cascade
amplifier is
f3dB |cascade = 632 21/2 − 1 = 406.8 kHz
which is less than the required 1 MHz.
Next, we try N = 3. The closed-loop gain of each
stage is
Af = (1000)1/3 = 10 V/V
and thus each stage will have an
amount-of-feedback
1 + Aβ =
1000
= 100
10
which results in a stage 3-dB frequency of
10.18 To capacitively couple the output signal to
an 8- loudspeaker and obtain fL = 100 Hz, we
need a coupling capacitor C,
C=
1
2πfL × 8
f3dB |stage = (1 + Aβ)fH
= 100 × 20 = 2000 kHz
= 2 MHz
1
= 198.9 μF 200 μF
2π × 100 × 8
If closed-loop gain AM f of 10 V/V is obtained
from an amplifier whose open-loop gain
AM = 1000 V/V, then
The 3-dB frequency of the cascade amplifier
will be
f3dB |cascade = 2 21/3 − 1
1000
= 100
1 + AM β =
10
and
100
fL
=
= 1 Hz
fLf =
100
100
If the required fLf is 50 Hz, then
which exceeds the required value of 1 MHz.
Thus, we need three identical stages, each with a
closed-loop gain of 10 V/V, an
amount-of-feedback of 100, and a loop gain
fL = 50 × (1 + AM β)
Thus,
= 50 × 100 = 5000 Hz,
β = 0.099 V/V
=
= 1.02 MHz
Aβ = 99
Chapter 10–7
A1 A2
1 + A1 A2 β
10.20 Af =
100 =
10A2
1 + A1 A2 β
0.9A2
900
⇒ A2 = 10, 000 V/V
10 =
(1)
β=
(1 + A1 A2 β) × 8 = 40 kHz
⇒ 1 + A1 A2 β = 5
899
= 0.0999 V/V
0.9 × 10, 000
10.22
V
Substituting in (1) gives
A2 =
100 × 5
= 50 V/V
10
1 + 10 × 50 × β = 5
vS
ve
⇒ β = 0.008 V/V
fLf =
=
m 100
vO
vI
80
1 + A1 A2 β
80
= 16 Hz
5
10.21 Vo ripple = Vn
V
Figure 1
A1
1 + A1 A2 β
vO
To reduce Vo ripple to 100 mV,
0.1 = 1 ×
0.9
1 + A1 A2 β
Slope 0.99 V/V
⇒ 1 + A1 A2 β = 9
Af =
A1 A2
1 + A1 A2 β
10 =
0.9A2
9
0
0.01 = 1 ×
0.9
1 + A1 A2 β
⇒ 1 + A1 A2 β = 90
Af =
A1 A2
1 + A1 A2 β
10 =
0.9A2
90
A2 = 1000 V/V
β=
Slope 0.99 V/V
8
= 0.089 V/V
0.9 × 100
To reduce Vo ripple to 10 mV,
89
= 0.099 V/V
0.9 × 1000
To reduce Vo ripple to 1 mV,
0.001 = 1 ×
0.9
1 + A1 A2 β
⇒ 1 + A1 A2 β = 900
vS
7 mV
⇒ A2 = 100 V/V
β=
7 mV
Figure 2
Refer to Fig. 1. For v I = +0.7 V, we have v O = 0
and
+0.7
vI
=
= +7 mV
ve =
μ
100
Similarly, for v I = −0.7 V, we obtain v O = 0 and
ve =
vI
−0.7
=
= −7 mV
μ
100
Thus, the limits of the deadband are now ±7 mV.
Outside the deadband, the gain of the feedback
amplifier, that is, v O /v S , can be determined by
noting that the open-loop gain A ≡ v O /v e =
100 V/V and the feedback factor β = 1, thus
Af ≡
vO
A
=
vS
1 + Aβ
100
= 0.99 V/V
1 + 100 × 1
The transfer characteristic is depicted in Fig. 2.
=
Chapter 10–8
This figure belongs to Problem 10.23.
10.23 The closed-loop gain for the first
(high-gain) segment is
Af 1 =
1000
1 + 1000β
v S = 0.9 +
(1)
and that for the second segment is
Af 2 =
100
1 + 100β
We require
Af 1
= 1.1
Af 2
Thus, dividing Eq. (1) by Eq. (2) yields
1.1 = 10
1 + 100β
1 + 1000β
1.1 + 1100β = 10 + 1000β
⇒ β = 0.089
Af 1 =
1000
= 11.1 V/V
1 + 1000 × 0.089
Af 2 =
100
= 10.1 V/V
1 + 100 × 0.089
The first segment ends at
|v O | = 10 mV × 1000 = 10 V. This
corresponds to
vS =
10 V
10
= 0.9 V
=
Af 1
11.1
The second segment ends at
|v O | = 10 + 0.05 × 100 = 15 V. This
corresponds to
(2)
15 − 10
Af 2
5
= 1.4 V
10.1
Thus, the transfer characteristic of the feedback
amplifier can be described as follows:
= 0.9 +
For |v S | ≤ 0.9 V, v O /v S = 11.1 V/V
For 0.9 V ≤ |v S | ≤ 1.4 V, v O /v S = 10.1 V/V
For |v S | ≥ 1.4 V, v O = ±15 V
The transfer characteristic is shown in the above
figure.
10.24 Because the op amp has an infinite input
resistance and a zero output resistance, this circuit
is a direct implementation of the ideal feedback
structure and thus
A = 1000 V/V
and
β=
R1
R1 + R2
The ideal closed-loop gain is
Af =
1
R2
=1+
β
R1
Thus,
R2
10
⇒ R2 = 90 k
10 = 1 +
Chapter 10–9
β=
10
= 0.1 V/V
10 + 90
Aβ = 1000 × 0.1 = 100
Af =
=
A
1 + Aβ
1000
= 9.9 V/V
1 + 100
=
A
1 + A × 0.1
⇒ A = 1010 V/V
Thus μ must be increased by the factor
1010
= 2.343 to become
431.1
μ = 2343 V/V
To obtain Af that is exactly 10, we use
10 =
1000
1 + Aβ
⇒ Aβ = 99
10.26 Refer to Fig. 10.10.
(a) β =
β = 0.099
0.099 =
R1
R1 + R2
0.099 =
10
10 + R2
⇒ R2 = 91 k
R1
R1 + R2
R2
1
Af ideal = = 1 +
β
R1
5=1+
R2
1
⇒ R2 = 4 k
(b) From Example 10.2, we have
10.25 Refer to Fig. 10.11.
(a) The ideal closed-loop gain is given by
Af =
1
R1 + R2
R2
=
=1+
β
R1
R1
R2
10
10 = 1 +
Aβ = (gm1 RD1 )(gm2 RD2 )
R1
1
RD2 + R2 + R1 gm1
⇒ R2 = 90 k
=
(4 × 10)(4 × 10)
(b) From Example 10.3, we obtain
= 22.54
RL [R2 + R1 (Rid + Rs )]
RL [R2 + R1 (Rid + Rs )] + ro
A=
R1 (Rid + Rs )
Rid
×
[R1 (Rid + Rs )] + R2
Rid + Rs
Af =
Aβ = μ ×
10 [90 + 10 (100 + 100)]
10 [90 + 10 (100 + 100)] + 1
Aβ = 1000 ×
100
10 (100 + 100)
×
[10 (100 + 100)] + 90 100 + 100
= 1000 × 0.9009 × 0.0957 × 0.5
= 43.11
43.11
Aβ
=
= 431.1 V/V
A=
β
0.1
A
431.1
=
= 9.77 V/V
Af =
1 + Aβ
1 + 43.11
(c) To obtain Af = 9.9 V/V, we use
9.9 =
A
1 + Aβ
1
×
1 + gm1 R1
=
1
1
×
1 + 4 × 1 10 + 4 + (1 0.25)
Aβ
22.54
=
= 112.7 V/V
β
0.2
A
1 + Aβ
112.7
= 4.79 V/V
1 + 22.54
10.27 (a) The feedback network consists of the
voltage divider (R1 R2 ), thus
β=
R1
R1 + R2
If the loop gain is large, the closed-loop gain
approaches the ideal value
Af =
R2
1
=1+
β
R1
=1+
10
= 11 V/V
1
Chapter 10–10
results in the circuit in Fig. 3 which we can use to
determine the loop gain Aβ as follows:
(b)
0.1 mA
8.4 V
0.1 mA
Q1
Q2
0.003 mA
0.7 V R2
0
0.3 mA
7.7 V
10 k 0.7
mA
Rs
100 k
1 mA
R1
1 k
Figure 3
Figure 1
Vt
re1 + Rs
Ie1 =
(1)
Ic1 = α1 Ie1
(2)
The dc analysis is shown in Fig. 1 from which we
see that
Ve2 = −(β2 + 1)Ic1 RL [R2 + (R1 Rib )]
IE1 0.1 mA
Vr = Ve2
IE2 0.3 mA
Combining (1) to (4), we can determine Aβ as
VE2 = +7.7 V
Aβ ≡ −
(c) Setting Vs = 0 and eliminating dc sources,
the feedback amplifier circuit simplifies to that
shown in Fig. 2.
= α1
×
R1 Rib
(R1 Rib ) + R2
Vr
Vt
(β2 + 1) RL [R2 + (R1 Rib )]
re1 + Rs
R1 Rib
(R1 Rib ) + R2
Substituting
α1 (β2 + 1) = α(β + 1) = β = 100
Q2
B1
Q1
re1 =
R2
VT
25 mV
= 250 =
IE1
0.1 mA
Rs = 100 RL = 1 k
Rs
R1
RL
Rib
Figure 2
R1 = 1 k
R2 = 10 k
Rib = 101(0.25 + 0.1) = 35.35 k
we obtain
Now, breaking the feedback loop at the base of Q1
while terminating the right-hand side of the
circuit (behind the break) in the resistance Rib ,
Rib = (β1 + 1)(re1 + Rs )
100 1 [10 + (1 35.35)]
Aβ =
0.25 + 0.1
×
= 23.2
1 35.35
(1 35.35) + 10
(3)
(4)
Chapter 10–11
(d) A =
23.2
Aβ
=
= 255.2 V/V
β
(1/11)
RF + RS1
A
1 + Aβ
Af =
RS2
If = Id 3
Id 1 = If
255.2
= 10.5 V/V
=
1 + 23.2
1
gm1
(3)
+ RS2
RS1
(4)
1
gm1
RS1 +
Vr = Id 1 RD1
10.28 (a) The feedback network consists of the
voltage divider (RF , RS1 ). Thus,
β=
RS1
RS1 + RF
Substituting the numerical values in (1)–(5), we
obtain
Vd 2 = −4 × 10Vt = −40Vt
and the ideal value of the closed-loop gain is
Af =
(5)
Id 3 =
RF
1
=1+
β
RS1
(6)
Vd 2
1
1
+ 0.1 0.9 + 0.1 4
4
Id 3 = 2.935Vd 2
RF
0.1
⇒ RF = 0.9 k
10 = 1 +
(7)
If = Id 3
0.1
0.9 + 0.1 (b)
1
4
+ 0.1
If = 0.0933Id 3
Id 1 = If
RD2
RD1
Vd2
Id1
Vr Vt
Q3
Id3
0.1 +
1
4
= 0.286If
(9)
(10)
Combining (6)–(10) gives
Vr = −31.33Vt
RF
1/gm1
⇒ Aβ = 31.33
If
RS1
RS2
A=
Af =
Figure 1
=
Figure 1 shows the circuit for determining the
loop gain. Observe that we have broken the loop
at the gate of Q2 where the input resistance is
infinite, obviating the need for adding a
termination resistance. Also, observe that as usual
we have set Vs = 0. To determine the loop gain
Aβ ≡ −
Vd 2 = −gm2 RD2 Vt
1
1
+ RS2 RF + RS1 gm3
gm1
A
1 + Aβ
Thus, Af is 0.3 V/V lower than the ideal value of
10 V/V, a difference of −3%. The circuit could be
adjusted to make Af exactly 10 by changing β
through varying RF . Specifically,
313.3
1 + 313.3β
⇒ β = 0.0968
(1)
Vd 2
Aβ
31.33
=
= 313.3 V/V
β
0.1
313.3
= 9.7 V/V
1 + 31.33
10 =
Vr
Vt
we write the following equations:
Id 3 =
0.1
Vr = 10Id 1
Q2
Q1
Id1
Id3
(8)
(2)
But,
β=
RS1
RS1 + RF
Chapter 10–12
0.0968 =
0.1
0.1 + RF
Ie3 = (β3 + 1)Ib2
(3)
RE
RE + re1
(4)
⇒ RF = 933 Ie1 = Ie3
(an increase of 33 ).
Vr = −α1 Ie1 (RC1 rπ2 )
Substituting
10.29 (a) The feedback circuit consists of the
voltage divider (RF , RE ). Thus,
β=
(5)
α1 = 0.99
RE
RE + RF
RC1 = 2 k
and,
gm2 =
RF
1
Af ideal = = 1 +
β
RE
IC2
2 mA
= 80 mA/V
=
VT
0.025 V
rπ 2 =
β2
100
= 1.25 k
=
gm2
80
Thus,
RE = 0.05 k
RF
25 = 1 +
0.05
re1 =
⇒ RF = 1.2 k
β3 = 100
(b) Figure 1 below shows the feedback amplifier
circuit prepared for determining the loop gain Aβ.
Observe that we have eliminated all dc sources,
set Vs = 0, and broken the loop at the base of Q2 .
We have terminated the broken loop in a
resistance rπ 2 . To determine the loop gain
Aβ ≡
RC2 = 1 k
RF = 1.2 k
we obtain
Ic2 = 80Vt
Vr
Vt
Ib3 = Ic2
we write the following equations:
Ic2 = gm2 Vt
Ib3 = Ic2
VT
25 mV
= 25 = 0.025 k
IE1
1 mA
(1)
RC2
RC2 + (β3 + 1) [RF + (RE re1 )]
(2)
(6)
1
1 + 101[1.2 + (0.05 0.025)]
= 8.072 × 10−3 Ic2
(7)
Ie3 = 101Ib3
(8)
This figure belongs to Problem 10.29, part (b).
RC2
Ib3
RC1
Ic1
Q1
Vr
rp2
Vt
Ie1
re1
RE
RF
Ie3
Figure 1
Q2
Ic2
Q3
Ie3
Chapter 10–13
Ie1 = Ie3
50
= 0.667Ie3
50 + 25
(9)
A = 47.62 V/V
Vr = −0.99(2 1.25)Ie1
Vr = −0.7615Ie1
(10)
Combining (6)–(10) results in
A
1 + Aβ
⇒ R2 = 179 k
R1 = 821 k
10.30 All MOSFETs are operating at
ID = 100 μA = 0.1 mA and |VOV | = 0.2 V, thus
2 × 0.1
= 1 mA/V
=
0.2
10.31 Ri = 2 k
Ro = 2 k
A = 1000 V/V
β = 0.1 V/V
All devices have
ro =
47.62
1 + 47.62β
R2
= 0.179
R1 + R2
828.2
= 24.3 V/V
1 + 33.13
gm1,2
A
1 + Aβ
⇒ β = 0.179 V/V
Aβ
33.13
A=
=
= 828.2 V/V
β
1/25
=
(b) Af =
5=
Aβ = 33.13
Af =
Thus,
|VA |
10
=
= 100 k
ID
0.1
Loop Gain ≡ Aβ = 1000 × 0.1 = 100
1 + Aβ = 101
(a)
Af =
Q3
Q4
Vo
=
Rs
Q1
Q2
R1
Vt Vr
A
1 + Aβ
1000
= 9.9 V/V
101
Rif = Ri (1 + Aβ)
= 2 × 101 = 202 k
R2
Rof =
=
Figure 1
Ro
1 + Aβ
2
= 19.8 101
Figure 1 shows the circuit prepared for
determining the loop gain Aβ.
Vo = −gm1,2 [ro2 ro4 (R1 + R2 )]Vt
Vr =
R2
Vo = β Vo
R1 + R2
Thus,
Aβ ≡ −
(1)
10.32 Since the output voltage is sampled, the
resistance-with-feedback is lower. The reduction
is by the factor (1 + Aβ), thus
1 + Aβ = 200
Aβ = 199
Vr
= gm1,2 [ro2 ro4 (R1 + R2 )]β
Vt
Rof =
Ro
200
= 1(100 100 1000)β
⇒ Ro = 200 × 100 = 20, 000 = 47.62β
= 20 k
Chapter 10–14
10.33 A = 1000 V/V
Rin = Rif − Rs 667 M
Ri = 1 k
Ro = ro RL = 1 2 = 0.67 k
Rif = 10 k
Rof =
Thus, the connection at the input is a series one,
and
Rof = Rout RL
1 + Aβ =
Af =
=
10
= 10
1
0.67 k
Ro
=
= 0.11 1 + Aβ
6061.6
Rout 0.11 10.35 Refer to the solution to Problem 10.27.
A
1 + Aβ
(a) β =
1000
= 100 V/V
10
To implement a unity-gain voltage follower, we
use β = 1. Thus the amount of feedback is
1 + Aβ = 1 + 1000 = 1001
Af =
R1
R1 + R2
1
R2
=1+
β
R1
=1+
10
= 11 V/V
1
(b) From the solution to Problem 10.27, we have
and the input resistance becomes
IE1 0.1 mA
Rif = (1 + Aβ)Ri
IE2 0.3 mA
= 1001 × 1 = 1001 k = 1.001 M
VE2 = +7.7 V
10.34 (a) β = 1
Af ideal = 1 V/V
(b) Substituting R1 = ∞ and R2 = 0 in the
expression for A in Example 10.4, we obtain
A=μ
RL
Rid
RL + ro Rid + Rs
Aβ = A × 1 = A
(c) A = 104 ×
100
2
×
2 + 1 100 + 10
= 6060.6 V/V
Aβ = 6060.6
Af =
=
A
1 + Aβ
6060.6
= 0.9998 V/V
1 + 6060.6
From Example 10.4 with R1 = ∞ and RL = 0,
we have
Ri = Rs + Rid = 10 + 100 = 110 k
Rif = Ri (1 + Aβ)
= 110 × 6061.6 = 667 M
Figure 1
Chapter 10–15
(c) The A circuit is shown in Fig. 1.
Ie1 =
Vi
37.9 = Rout 1000
⇒ Rout = 39.4 Vo = Ie2 [RL (R1 + R2 )]
= (β2 + 1)α1 Vi
RL (R1 + R2 )
R1 R2
Rs + re1 +
β1 + 1
Since β1 = β2 = β and α =
Vo
=β
Vi
A≡
β
, we have
β +1
RL (R1 + R2 )
R1 R2
Rs + re1 +
β1 + 1
Substituting β = 100, RL = 1 k, R1 = 1 k,
R2 = 10 k, Rs = 0.1 k, and re1 = 0.25 k
gives
A = 100
1 11
0.1 + 0.25 +
1 10
101
= 255.3 V/V
Ri = Rs + re1 +
R1 R2
β1 + 1
= 0.1 + 0.25 +
1 10
= 0.359 k
101
Ro = RL (R1 + R2 )
= 1 11 = 0.917 k
(d) β =
=
(e)
R1
R1 + R2
1
1
=
1 + 10
11
Vo
A
= Af =
Vs
1 + Aβ
1 + Aβ = 1 +
Af =
255.3
= 24.21
11
255.3
= 10.5 V/V
24.21
Rif = Ri (1 + Aβ)
= 0.359 × 24.21 = 8.69 k
0.917 k
Ro
=
= 37.9 1 + Aβ
24.21
Rof = Rout RL
R1 R2
β1 + 1
Rs + re1 +
Rof =
The value of Af (10.5 V/V) is 0.5 less than the
ideal value of 11, which is 4.5%.
10.36 (a) Let Vs increase by a small increment.
Since Q1 is operating in effect as a CS amplifier, a
negative incremental voltage will appear at its
drain. Transistor Q2 is also operating as a CS
amplifier; thus a positive incremental voltage will
appear at its drain. Transistor Q3 is operating as a
source follower; thus the signal at its source
(which is the output voltage) will follow that at its
gate and thus will be positive. The end result is
that we are feeding back through the voltage
divider (R2 , R1 ) a positive incremental signal that
will appear across R1 and thus at the source of the
Q1 . This signal, being of the same polarity as the
originally assumed change in the signal at the
gate of Q1 (Vs ), will subtract from the original
change, causing a smaller signal to appear across
the gate-source terminals of Q1 . Hence, the
feedback is negative.
(b) β =
R1
R1 + R2
Thus,
β=
2
= 0.1 V/V
2 + 18
If the loop gain is large, the closed-loop gain
approaches the ideal value
1
R2
Af ideal = = 1 +
β
R1
Thus,
18
= 10 V/V
Af ideal = 1 +
2
(c) VG1 = 0.9 V
VS1 = VG1 − VGS1
= VG1 − Vt1 − VOV 1
= 0.9 − 0.5 − 0.2 = 0.2 V
VG2 = VDD − VSG2
Rin = Rif − Rs
= VDD − |Vt2 | − |VOV 2 |
= 8.69 − 0.1 = 8.59 k
= 1.80 − 0.5 − 0.2 = 1.1 V
Chapter 10–16
Thus, current source I1 will have 0.7-V drop
across it, more than sufficient for its proper
operation. Since VS1 = 0.2 V the dc current
through R1 will be
IR1
VS1
0.2 V
= 0.1 mA
=
=
R1
2 k
Now, a node equation at S1 reveals that because
ID1 = 0.1 mA and IR1 = 0.1 mA, the dc current in
R2 will be zero. Thus, it will have a zero voltage
drop across it and
Figure 1 shows the A circuit as well as the β
circuit and how the loading-effect resistances R11
and R22 are determined.
To determine A, let’s first determine the
small-signal parameters of all transistors as well
as ro of each of the three current sources.
gm1 =
2ID1
2 × 0.1
=
= 1 mA/V
VOV 1
0.2
ro1 =
|VA |
10
= 100 k
=
ID1
0.1
VS3 = VS1 = 0.2 V
Thus, current source I3 will have across it, the
minimum voltage required to keep it operating
properly. Finally,
rocs1 =
|VA |
10
=
= 100 k
I1
0.1
gm2 =
2ID2
2 × 0.1
= 1 mA/V
=
VOV 2
0.2
ro2 =
|VA |
10
=
= 100 k
ID2
0.1
VG3 = VS3 + VGS3
= VS3 + Vt3 + VOV 3
= 0.2 + 0.5 + 0.2 = 0.9 V
Thus, current source I2 will have across it a
voltage more than sufficient to keep it operating
properly.
(d)
rocs2 =
|VA |
10
=
= 100 k
I2
0.1
gm3 =
2ID3
2 × 0.1
=
= 1 mA/V
VOV 3
0.2
ro3 =
|VA |
10
=
= 100 k
ID3
0.1
rocs3 =
|VA |
10
= 100 k
=
I3
0.1
Refer to the A circuit.
Transistor Q1 is a CS amplifier with a resistance
R11 in its source:
Rs = R11 = R1 R2 = 2 18 = 1.8 k
Transistor Q1 will have an effective
transconductance:
Gm1 =
gm1
2
= 0.43 mA/V
=
1 + gm Rs
1 + 2 × 1.8
The output resistance of Q1 will be
Ro1 = (1 + gm1 Rs )ro1
= (1 + 2 × 1.8) × 100 = 460 k
The total resistance at the drain of Q1 is
Rd 1 = rocs1 Ro1
Figure 1
= 100 460 = 82.1 k
Chapter 10–17
Thus, the voltage gain of the first stage is
A1 = −Gm1 Rd 1
= −0.43 × 82.1 = −35.3 V/V
Rof =
935
= 5.6 166
Note: This problem, though long, is extremely
valuable as it exercises the student’s knowledge
in many aspects of amplifier design.
The gain of the second stage is
A2 = −gm2 (rocs2 ro2 )
= −1(100 100) = −50 V/V
To determine the gain of the third stage, we first
determine the total resistance between the source
of Q3 and ground:
Rs3 = rocs3 ro3 (R1 + R2 )
Rs3 = 100 100 20
= 14.3 k
(b) Figure 1 on the next page shows the circuit
prepared for dc analysis. We see that
Thus,
A3 =
=
10.37 (a) Refer to Fig. P10.37. Assume that for
some reason v S increases. This will increase the
differential input signal (v S − v O ) applied to the
differential amplifier. The drain current of Q1 will
increase, and this increase will be mirrored in the
drain current of Q4 . The increase in iD4 will cause
the voltage at the gate of Q5 to rise. Since Q5 is
operating as a source follower, the voltage at its
source, v O , will follow and increase. This will
cause the differential input signal (v S − v O ) to
decrease, thus counteracting the originally
assumed change. Thus, the feedback is negative.
Rs3
Rs3 +
1
gm3
14.3
= 0.935 V/V
1
14.3 +
1
ID1 = ID2 = 100 μA
ID3 = 100 μA
ID4 = 300 μA
ID5 = 0.8 mA
The overall voltage gain A can now be found as
A = A1 A2 A3
= −35.3 × −50 × 0.935 = 1650 V/V
For Q1 and Q2 , use
1
W
2
ID = μn Cox
VOV
2
L
1
20 2
× 120 × VOV
1,2
2
1
(e) We already found β in (b) as
100 =
β = 0.1 V/V
⇒ VOV 1,2 = 0.29 V
(f) 1 + Aβ = 1 + 1650 × 0.1 = 166
For Q3 , use
Af =
A
1650
=
= 9.94 V/V
1 + Aβ
166
which is lower by 0.06 or 0.6% than the ideal
value obtained in (b).
(g) Rof =
Ro
1 + Aβ
1
W
μp Cox
|VOV 3 |2
2
L
100 =
1
40
× 60 × |VOV 3 |2
1
2
⇒ |VOV 3 | = 0.29 V
To obtain Ro refer to the output part of the A
circuit.
Ro = (R1 + R2 ) rocs3 ro3 ID =
1
gm3
Since VSG4 = VSG3 , we have
|VOV 4 | = |VOV 3 | = 0.29 V
Finally for Q5 , use
1
20
2
× 120 ×
× VOV
5
2
1
= 20 100 100 1
800 =
= 935 ⇒ VOV 5 = 0.82 V
Chapter 10–18
This figure belongs to Problem 10.37, part (b).
2.5 V
Q3
(40/1)
Q4 (120/1)
Q5 (20/1)
300 A
Q1
(20/1)
VO
Q2
(20/1)
0.8 mA
200 A
Figure 1
This figure belongs to Problem 10.37, part (d).
Q3
Q4
3Id1
Q5
Vd4
Id1
Vo
Q1
Q2
Vi 0
Id1, 2
1
2
1
2
R11 0
R22 Figure 2
If perfect matching pertains, then
VD4 = VD3 = VDD − VSG3
= 2.5 − |Vt | − |VOV 3 |
= 2.5 − 0.7 − 0.29 = 1.51 V
which is approximately zero, as stated in the
Problem statement.
(c) gm1 = gm2 = gm3 =
=
2 × 0.1
= 0.7 mA/V
0.29
VO = VD4 − VGS5
= VD4 − Vt − VOV 5
= 1.51 − 0.7 − 0.82 = −0.01 V
2ID
|VOV |
gm4 =
2 × 0.3
2 mA/V
0.29
gm5 =
2 × 0.8
2 mA/V
0.82
Chapter 10–19
ro1 = ro2 = ro3 =
=
|VA |
|V | × L
= A
ID
ID
24 × 1
= 240 k
0.1
(e) Af =
=
A
1 + Aβ
82.6
= 0.988 V/V
1 + 82.6
Ro
492
=
= 5.9 1 + Aβ
1 + 82.6
ro4 =
24
= 80 k
0.3
Rof =
ro5 =
24
= 30 k
0.8
Rout = Rof = 5.9 (d) Figure 2 on the previous page shows the A
circuit. Observe that since the β network is
simply a wire connecting the output node to the
gate of Q2 , we have R11 = 0 and R22 = ∞. To
determine A, we write
Id 1,2
(f) To obtain a closed-loop gain of 5 V/V, we
connect a voltage divider in the feedback loop, as
shown in Fig. 3.
Q5
Vi
1
=
= gm1,2 Vi
2/gm1,2
2
Since
W
L
4
will be
W
=3
L
, the drain current of Q4
3
R1
Id 4 = 3Id 1
3
= gm1,2 Vi
2
The voltage at the drain of Q4 will be
Vd 4 = Id 4 ro4
=
3
gm1,2 ro4 Vi
2
Figure 3
β=
R1
R1 + R2
Af =
A
1 + Aβ
Finally, Vo is related to Vd 4 as
Vo
=
Vd 4
5=
ro5
ro5 +
1
gm5
Selecting R1 = 1 M, we obtain
3
Vo
= gm1,2 ro4
Vi
2
ro5
1
ro5 +
gm5
Substituting numerical values, we obtain
A=
30
3
× 0.7 × 80 ×
2
30 + 0.5
= 82.6 V/V
The output resistance Ro is
Ro = ro5 1
gm5
= 30 0.5 = 0.492 k
= 492 82.6
1 + 82.6β
⇒ β = 0.188
Thus,
A≡
R2
Q2
0.188 =
1
1 + R2
⇒ R2 = 4.319 M
Note that by selecting large values for R1 and R2 ,
we have ensured that their loading effect on the A
circuit would be negligible. The output resistance
will be Rout = 5 × 5.9 = 29.5 .
10.38 (a) Refer to Fig. P10.30. Let Vs increase
by a positive increment. This will cause the drain
current of Q1 to increase. The increase in Id 1 will
be fed to the Q3 − Q4 mirror, which will provide a
corresponding increase in the drain current of Q4 .
The latter current will cause the voltage at the
output node to rise. A fraction of the increase in
Vo is applied through the divider (R1 , R2 ) to the
Chapter 10–20
This figure belongs to Problem 10.38, part (c).
Q3
Q4
Vo
R1
Rs
Q1
Vi
Q2
R22
R2
R2
R1
R11
0
R1
1
R2
Ro
2
R1
1
R2
2
R11
R22
Figure 1
gate of Q2 . The increase in the voltage of the gate
of Q2 will subtract from the initially assumed
increase of the voltage of the gate of Q1 , resulting
in a smaller increase in the differential voltage
applied to the (Q1 , Q2 ) pair. Thus, the feedback
counter acts the originally assumed change,
verifying that it is negative.
ro2 = ro4 =
|VA |
10
= 100 k
=
ID3,4
0.1
R22 = R1 + R2 = 1 M
A = 1(100 100 1000) = 47.62 V/V
(b) The negative feedback will cause the dc
voltage at the gate of Q2 to be approximately
equal to the dc voltage at the gate of Q1 , that is,
zero. Now, with VG2 0, the dc current in R2 will
be zero and similarly the dc current in R1 will be
zero, resulting in VO = 0 V dc.
This is identical to the value found in the solution
to Problem 10.30.
(d)
A
Vo
= Af =
Vs
1 + Aβ
(c) Figure 1 shows the A circuit. It also shows
how the loading effect of the β network on the A
circuit, namely R11 and R22 , are found. The gain
of the A circuit can be written by inspection as
5=
47.62
1 + 47.62β
A = gm1,2 (ro2 ro4 R22 )
⇒ β = 0.179
Thus,
where
gm1,2 =
=
2ID1,2
VOV 1,2
2 × 0.1
= 1 mA/V
0.2
R2
= 0.179
R1 + R2
R2 = 0.179 M = 179 k
Chapter 10–21
R1 = 1000 − 179 = 821 k
Using β = 0.179, we obtain
Again, these values are identical to those found in
Problem 10.30.
Af =
which is identical to the value found in (f) above.
(e) Refer to Fig. 1 on the preceding page.
Ro = R22 ro2 ro4
10.39 All transistors have L = 1 μm, thus all
have |VA | = |VA | × L = 10 × 1 = 10 V. Also, all
have |Vt | = 0.75 V.
= 1000 100 100 = 47.62 k
Rout = Rof =
=
Ro
1 + Aβ
(a) Figure 1 shows the circuit prepared for dc
design. We have also indicated some of the
current and voltage values. We now find the
(W/L) ratios utilizing
1
W
2
VOV
ID = μn Cox
2
L
47.62
1 + 47.62 × 0.179
= 5 k
for the NMOS transistors, and
1
W
|VOV |2
ID = μp Cox
2
L
This value cannot be found using the loop-gain
analysis method of Problem 10.30.
(f) With RL = 10 k,
for the PMOS devices.
Vo
RL
=5×
Vs
RL + Rout
5×
8.26
= 3.33 V/V
1 + 8.26 × 0.179
For Q6 ,
1
× 100 ×
2
W
⇒
= 16
L 6
10
= 3.33 V/V
10 + 5
50 =
(g) As an alternative to (f), we shall redo the
analysis of the A circuit in (c) above with
RL = 10 k included:
W
L
× 0.252
6
For Q7 ,
A = gm1,2 (ro2 ro4 R22 RL )
100 μA
(W/L)7
=
=2
(W/L)6
50 μA
= 1(100 100 1000 10)
⇒ (W/L)7 = 2 × 16 = 32
= 8.26 V/V
This figure belongs to Problem 10.39, part (a).
VDD 2.5 V
1.5 V
Q3
Q4
50 A
80 k
2.5(1.5)
80
50 A
Q6
1.5 V
50 A
Q1
Q2
50 A
50 A
100 A
Q7
1.5 V
VSS 2.5 V
Figure 1
Q5
250 A
VO 0 V
250 A
Q8
Chapter 10–22
For Q8 ,
(c) gm1,2 =
(W/L)8
250 μA
=5
=
(W/L)6
50 μA
W
⇒
= 5 × 16 = 80
L 8
=
1
× 100 ×
2
50 =
⇒
W
L
=
1
W
L
W
L
1
× 50 ×
2
⇒
W
L
=
3
× 0.252
1,2
W
L
= 16
× 0.252
3,4
= 32
4
VOV 5 = 1.5 − 0.75 = 0.75 V
1
W
250 = × 100 ×
× 0.752
2
L 5
⇒
|VA |
=
ID
10
= 100 k
0.01
ro5 = ro8 =
VGS5 = 1.5 V
W
L
ro7 =
2
Finally, since VG3 = VD4 = VD3 = 1.5 V and we
require VO = 0 V, we have
10
= 200 k
0.05
W
L
2 × 0.25
2ID
=
= 0.67 mA/V
|VOV 5 |
0.75
(d) ro1 = ro2 = ro3 = ro4 = ro6 =
For Q3 and Q4 ,
50 =
2 × 0.05
= 0.5 mA/V
0.2
gm5 =
For Q1 and Q2 ,
2ID1,2
VOV 1,2
10
= 40 k
0.25
(e) Figure 2 on the next page shows the A circuit,
the β circuit, and how the loading effects of the β
circuit on the A circuit, namely R11 and R22 , are
determined.
Vg5
= gm1,2 (ro2 ro4 )
Vi
= 0.5(200 200) = 50 V/V
Vo
=
Vg5
Rs
Rs +
1
gm5
where
Rs = ro8 ro5 (R1 + R2 ) RL
= 8.9
5
(b) The maximum value of VICM is limited by Q1
leaving the saturation region,
= 40 40 100 100 = 14.3 k
Thus,
VICM max = VD1 + Vt
Vo
14.3
= 0.905 V/V
=
Vg5
14.3 + (1/0.67)
= 1.5 + 0.75 = 2.25 V
A=
The minimum value of VICM is limited by the
need to keep Q7 in saturation. This is achieved by
keeping VD7 at a minimum voltage of
Vg5
Vo
Vo
=
×
Vi
Vi
Vg5
= 50 × 0.905 = 45.3 V/V
Af = 10 =
−2.5 + |VOV 7 | = −2.5 + 0.25 = −2.25 V
A
1 + Aβ
45.3
1 + 45.3β
Thus,
10 =
VICM min = −2.25 + VGS1
⇒ β = 0.078
= −2.25 + 1 = −1.25 V
R2
= 0.078
R1 + R2
Thus,
R2 = 7.8 k
−1.25 V ≤ VICM ≤ +2.25 V
R1 = 100 − 7.8 = 92.2 k
Chapter 10–23
This figure belongs to Problem 10.39, part (e).
Q3
Q4
Vg5
Q1
Vi Q5
Vo
Q2
R1
R2
ro8
R1
RL
R2
R11
A Circuit
R2
1
R22
0
R1
R1
1
2
b Circuit
R2
b
R1R2
R2
Ro
2
1
R1
R2
2
R11 R2 R1
R22 R1R2
Figure 2
(f) Refer to Fig. 2.
Ro = RL (R1 + R2 ) ro8 ro5 = Rs 1
gm5
1
= 14.3 (1/0.67)
gm5
= 1.36 k
Rof =
=
Ro
1 + Aβ
1.36 k
300 1 + 45.3 × 0.078
originally assumed increase at the negative input
terminal, verifying that the feedback is negative.
1
(b) Af ideal =
β
where
β=
R1
R1 + R2
Thus, to obtain an ideal closed-loop gain of 5 V/V
we need β = 0.2:
0.2 =
20
20 + R2
Rout RL = Rof
⇒ R2 = 80 k
⇒ Rout 300 (c) Figure 1 on the next page shows the smallsignal equivalent circuit of the feedback amplifier.
10.40 (a) Refer to Fig. P10.40. If Vs increases,
the output of A1 will decrease and this will cause
the output of A2 to increase. This, in turn, causes
the output of A3 , which is Vo , to increase. A
portion of the positive increment in Vo is fed back
to the positive input terminal of A1 through the
voltage divider (R2 , R1 ), The increased voltage at
the positive input terminal of A1 counteracts the
(d) Figure 2 on the next page shows the A circuit
and the β circuit together with the determination
of its loading effects, R11 , and R22 . We can write
82
V1
= −0.766 V/V
=−
Vi
82 + 9 + 16
V2 = 20V1 ×
5
= 12.195V1
3.2 + 5
V3 = −20V2 (20 20) = −200V2
Chapter 10–24
This figure belongs to Problem 10.40, part (c).
Figure 1
This figure belongs to Problem 10.40, part (d).
Figure 2
Vo = V3
1 100
= 0.497V3
(1 100) + 1
(g) From the A circuit,
Thus,
A≡
Vo
= 0.497 × −200 × 12.195 × −0.766
Vi
= 928.5 V/V
(e) β =
20
= 0.2 V/V
20 + 80
1 + Aβ = 1 + 928.5 × 0.2 = 186.7
(f) Af ≡
=
which is nearly equal to the ideal value of 5 V/V.
Vo
A
=
Vs
1 + Aβ
928.5
= 4.97 V/V
186.7
Ri = 9 + 82 + 16 = 107 k
Rif = Ri (1 + Aβ)
= 107 × 186.7 = 19.98 M
Rin = Rif − Rs 19.98 M
(h) From the A circuit,
Ro = RL R22 1 k
= 1 100 1 = 497.5 Rof =
Ro
497.5
=
= 2.66 1 + Aβ
186.7
Chapter 10–25
Rout RL = Rof
R11 = RE RF = 50 1200 = 48 Rout 1000 = 2.66 gm2 =
IC2
IE2
2 mA
= 80 mA/V
=
VT
VT
0.025 mA
rπ2 =
100
β2
=
= 1.25 k
80
80
Rout 2.66 (i) fHf = fH (1 + Aβ)
α1 = 0.99 1
= 100 × 186.7
Vc1
RC1 1.25
= −10 = −
Vi
0.025 + 0.048
= 18.67 kHz
(j) If A1 drops to half its nominal value, A will
drop to half its nominal value:
1
A = × 928.5 = 464.25
2
and Af becomes
Af =
464.25
= 4.947 V/V
1 + 464.25 × 0.2
Thus, the percentage change in Af is
=
4.947 − 4.97
= −0.47%
4.97
10.41 (a) Figure 1 on the next page shows the A
circuit and the circuit for determining β as well as
the determination of the loading effects of the β
circuit.
(b) If Aβ is large, then
Af ≡
⇒ RC1 = 1.75 k
Next consider the second stage composed of the
CE transistor Q2 . The load resistance of the
second stage is composed of RC2 in parallel with
the input resistance of emitter-follower Q3 . The
latter resistance is given by
Ri3 = (β3 + 1)(re3 + R22 )
where
re3 =
R22 = RF + RE = 1.2 + 0.05 = 1.25 k
Thus,
Ri3 = 101 × 1.25 = 126.3 k
A2 ≡
Vc2
= −gm2 (RC2 Ri3 )
Vb2
−50 = −80(RC2 126.3)
Vo
1
Vs
β
⇒ RC2 = 628 Since
(e) A = A1 A2 A3
RE
β=
RF + RE
where
we have
A3 =
Af =
VT
25 mV
=5
=
IE3
5 mA
RF + RE
RE
(c) 25 = 1 +
Q.E.D.
RF
50 ⇒ RF = 1.2 k
(d) Refer to the A circuit in Fig. 1. The voltage
gain of Q1 is given by
Vc1
RC1 rπ 2
= −α1
Vi
re1 + R11
R22
1.25
=
= 0.996 V/V
R22 + re3
1.25 + 0.005
A ≡ −10 × −50 × 0.996
= 498 V/V
Af ≡
Vo
=
Vs
498
1 + 498 ×
50
1250
= 23.8 V/V
(f) Refer to the A circuit in Fig. 1.
Ri = (β1 + 1)(re1 + R11 )
where
Ri = 101(0.025 + 0.048)
VT
25 mV
re1 =
=
= 25 IE1
1 mA
= 7.37 k
Chapter 10–26
This figure belongs to Problem 10.41, part (a).
RF
Vf
1
RF
2 Vo
RE
RE
1
2
b Circuit
RE
b
RF RE
R11 RE // RF
0
RF
RE
1
2
R22 RE RF
RC2
RC1
Q3
Q2
Vo
Vi
Q1
R22
Ri
R11
Ro
A Circuit
Figure 1
Rif = Ri (1 + Aβ)
Rout = Rof =
where
1 + Aβ = 1 +
=
498
= 20.92
25
Rif = 7.37 × 20.92 = 154 k
RC2
Ro = R22 re3 +
β3 + 1
= 1.25 0.005 +
= 11.1 0.628
101
Ro
1 + Aβ
11.1
= 0.53 20.92
10.42 To obtain Af ≡
RF = β =
Io
10 mA/V, we select
Vs
1
= 100 Af
From Example 10.6, we obtain
A=
≡
gm (RF Rid ro2 )
μ
RF 1 + gm (RF Rid ro2 )
2(0.1 100 20)
1000
0.1 k 1 + 2(0.1 100 20)
Chapter 10–27
= 10, 000 × 0.1658
First, we express Id 2 in terms of Vt :
= 1.658 A/V
Id 2 = −gm2 Vt
Af =
A
1 + Aβ
(1)
Then we determine Id 1 :
Id 1 = Id 2
1658
=
= 9.94 mA/V
1 + 1658 × 0.1
RM
RM + RF +
(2)
1
gm1
The returned voltage Vr can now be obtained as
Vr = Id 1 RD
10.43 (a)
(3)
Combining Eqs. (1)–(3), we find Vr /Vt :
IF
RF
Vr
=−
Vt
RM
gm2 RD RM
RM + RF +
Io
1
gm1
Thus,
Aβ =
Figure 1
Figure 1 shows the β network with the input port
short-circuited. Thus,
β≡
If
RM
=−
Io
RM + RF
gm2 RD RM
RM + RF +
Dividing the expression for Aβ by
RM
β=−
yields
RM + RF
A=−
RF
1
Af ideal = = − 1 +
β
RM
gm2 RD
1 + 1/[gm1 (RM + RF )]
(c) A = −
(b) Figure 2 below shows the circuit for
determining the loop gain Aβ,
1
gm1
4 × 10
1 + 1/[4 × 1]
= −32 A/A
Af = −5 = −
32
1 − 32 × β
β = −0.169 A/A
RD
Vr
Q2
Vt
Id2
Id1
Q1
RL
RF
Aβ = −
Vr
Vt
RM
= −0.169
RM + RF
RM = 0.169 × 1 = 0.169 k
= 169 10.44 (a) Refer to Fig. P10.44(b).
Id1
RM
Figure 2
−
β≡
If
1
=−
Vo
RF
1
Af ideal = = −RF
β
For Af ideal = −1 k, we have
RF = 1 k
Q.E.D.
Chapter 10–28
Ro1 = 100 k
(b)
β = 200 RF
ro
Vr
Rid
Vt V1
R11 = 10 k
Rid
mV1
Rs = 10 k
RL = 10 k
To determine A,
Figure 1
Figure 1 shows the circuit for determining the
loop gain Aβ:
Vr
Aβ ≡ −
Vt
Io
Vi
A≡
we write
V1 = Vi
Writing Vr in terms of V1 = Vt yields
Vr = −μVt
R22 = 200 = Vi
Rid
Rid + RF + ro
Ri1
Ri1 + Rs + R11
1
10
= Vi
10 + 10 + 10
3
Io = Gm V1
Thus,
Aβ ≡ −
Vr
Rid
=μ
Vt
Rid + RF + ro
(c) Aβ = 1000
100
100 + 1 + 1
= 980.4
980.4
980.4
A=
=
β
−1/RF
= −980.4 k
= 0.6 ×
980.4
= −0.999 k
1 + 980.4
Ro1
Ro1 + RL + R22
100
Vi
100 + 10 + 0.2
= 0.544 Vi
1
Io = 0.544 × Vi = 0.1815 Vi
3
A = 0.1815 A/V
=
Io
A
=
Vs
1 + Aβ
0.1815
0.1815
=
= 4.88 mA/V
1 + 0.1815 × 200
1 + 36.2
Rif = Ri (1 + Aβ)
Ri is obtained from the A circuit as
10.45
Ri = Rs + Ri1 + R11
= 10 + 10 + 10 = 30 k
Thus,
Rif = 30 × 37.2 = 1.116 M
Figure 1
(2)
Combining (1) and (2), we obtain
Af =
A
Af =
1 + Aβ
=−
Q.E.D.
(1)
Rin = Rif − Rs
Figure 1 shows the A circuit where
= 1.116 − 0.010 = 1.006 M
Ri1 = 10 k
1 M
Chapter 10–29
Rof = Ro (1 + Aβ)
where RE2 = 100 , R22 (from β circuit)
= 740 , re3 = 5 , RC2 = 5 k, β3 = 100;
where Ro is obtained from the A circuit as
thus,
Ro = RL + Ro1 + R22
Ro = 100 740 5 +
= 10 + 100 + 0.2 = 110.2 k
5000
101
= 33.7 Rof = 110.2 × 37.2 = 4.1 M
Ro
1 + Aβ
Rof =
Rout = Rof − RL = 4.1 − 0.01 = 4.09 M
=
10.46 (a)
33.7
= 0.14 1 + 246.3
RF 640 10.47 (a)
RE1
1
2
RF
100 Vf
Figure 1
RS1
RS2
Io
Figure 1 shows the β circuit from which we obtain
β=
=
Figure 1
RE1
RE1 + RF
Figure 1 shows the β network. The value of β can
be obtained from
100
= 0.135 V/V
100 + 640
Vf
Io
(b) For Aβ 1,
β≡
Ve3
1
= Af ideal = = 7.4 V/V
Vs
β
=
(c)
If Aβ 1, then
RS1 RS2
RS2 + RF + RS1
Af RC2
RC3 600 5 k
1
1
1
RF
=
+
+
β
RS1
RS2
RS1 RS2
For Af 100 mA/V,
100 =
Q3
(1)
1
RF
1
+
+
0.1 0.1 0.1 × 0.1
⇒ RF = 0.8 k
Vo
Q2
RE2 100 R22
(b) Figure 2 on the next page shows the A circuit
and the determination of the loading effects of the
β circuit, namely R11 and R22 ,
R11 = RS1 (RF + RS2 )
Ro
Figure 2
= 100 (800 + 100) = 80 R22 = RS2 (RF + RS1 ) = 80 The value of A is determined as follows:
Figure 2 shows the portion of the A circuit
relevant for calculating Ro :
Ro = RE2 R22 re3 +
RC2
β3 + 1
RD1
Vd 1
=−
Vi
(1/gm1 ) + R11
=−
10
= −30.3 V/V
(1/4) + 0.08
Chapter 10–30
This figure belongs to Problem 10.47, part (b).
Figure 2
Vd 2
= −gm2 RD2 = −4 × 10 = −40 V/V
Vd 1
1
Io
=
Vd 2
1/gm5 + R22
=
1
3 mA/V
0.25 + 0.08
(d) From the A circuit in Fig. 2, we have
Ro = ro3 + R22 + gm3 ro3 R22
= 20 + 0.08 + 4 × 20 × 0.08
= 26.48 k
Rout = Rof = Ro (1 + Aβ)
Thus,
Io
= 3 × −40 × −30.3 = 3636 mA/V
A=
Vi
= 26.48 × 37.36 = 989.3 k
(e)
(c) β = 0.01 k
RF
RF
1 + Aβ = 1 + 3636 × 0.01
= 37.36
Af =
1 RS1
2
Io
3636
= 97.3 mA/V
=
Vi
37.36
1
RS1
R11
Difference from design value
0
97.3 − 100
× 100
=
100
= −2.7%
To make Af exactly 100 mA/V, we can increase
RF (see Eq. (1) to appreciate why we need to
increase RF ).
1
RF
RS1
2
R22
Figure 3
Chapter 10–31
Figure 3 on the preceding page shows the β
circuit for the case the output is Vo .
β=
Af =
=
RS1
RS1 + RF
A
1 + Aβ
306.9
= 8.74 V/V
35.1
(f) From the A circuit in Figure 4, we have
1
100
=
=
100 + 800
9
Ro = R22 Also shown is how R11 and R22 are determined in
this case:
Ro = 900 250 = 195.7 R11 = RS1 RF = 100 800 = 88.9 Rout2 = Rof =
R22 = RF + RS1 = 800 + 100 = 900 =
RD1
RD2
Vd2
1
gm3
Ro
1 + Aβ
195.7
= 5.6 35.1
10.48 (a)
Q3
Vd1
Vo
Q1
Vi
R22
R11
Figure 1
Ro
Figure 4
Figure 4 shows the A circuit for this case. To
determine A, we write
Vd 1
RD1
=−
Vi
1/gm1 + R11
Vd 1
10
= −29.5 V/V
=−
Vi
0.25 + 0.0889
Vd 2
= −gm2 RD2 = −4 × 10 = −40 V/V
Vd 1
Vo
=
Vd 2
R22
R22 +
1
gm5
=
88.9
= 0.26 V/V
88.9 + 250
Thus,
A≡
Vo
= 0.26 × −40 × −29.5 = 306.9 V/V
Vi
1 + Aβ = 1 + 306.9 ×
1
= 35.1
9
which is a little lower than the value (37.36)
found when we analyzed the amplifier as a
transconductance amplifier.
Figure 2
Figure 1 shows the small-signal equivalent circuit
of the feedback amplifier. Observe that the
resistance RF senses the output current Io and
provides a voltage Io RF that is subtracted from Vs .
Thus the feedback network is composed of the
resistance RF , as shown in Fig. 2. Because the
feedback is of the series-series type, the loading
resistances R11 and R22 are determined as
indicated in Fig. 2,
R11 = RF
R22 = RF
Chapter 10–32
(b) The β circuit is shown in Fig. 2 and
=
β = RF
gm
1 + gm RF +
RF
ro
From the A circuit in Fig. 3, we have
Figure 3 shows the A circuit.
Ro = ro + RF
(c)
Rof = (1 + Aβ)Ro
gm ro RF
= 1+
(ro + RF )
ro + RF
Io
Vgs
V
i
gmVgs
ro
= ro + RF + gm ro RF
Ro
R11
Io
which is a familiar relationship!
RF
10.49 (a) The β circuit is shown in Fig. 1:
β = RF
Figure 3
For Aβ 1, Af ≡ Io /Vs approaches the ideal
value
1
1
Af ideal = =
β
RF
To determine A = Io /Vi , we write
Vgs = Vi
Io = gm Vgs
ro
ro + RF
To obtain Af 5 mA/V, we use
RF =
Io
ro
A≡
= gm
Vi
ro + RF
(b) Determining the loading effects of the β
network is illustrated in Fig. 1:
gm ro RF
1 + Aβ = 1 +
ro + RF
R11 = R22 = RF
Io
A
= Af =
Vs
1 + Aβ
=
1
= 0.2 k = 200 5
Figure 2 (next page) shows the A circuit. An
expression for A ≡ Io /Vi can be derived as
follows:
gm ro /(ro + RF )
1 + gm ro RF /(ro + RF )
V1 = Vi
(1)
This figure belongs to Problem 10.49, part (a).
0
1
RF
2
1 V1
RF
b
0
1
RF
2
V1
RF
Io
0
2
1
R11 RF
RF
2
R22 RF
Figure 1
Io
Chapter 10–33
This figure belongs to Problem 10.49, part (b).
Io
Vi V1
Vgs
mV1
ro
gmVgs
Ro
R11 RF
R22 RF
Io
Figure 2
Vgs = μV1 − Io RF
(2)
ro
ro + RF
(3)
Io = gm Vgs
Rof = 20 + 0.2 + 1001 × 2 × 20 × 0.2
= 20 + 0.2 + 8008 = 8028.2 k
8 M
Combining Eqs. (1)–(3) yields
A≡
μgm ro
Io
=
Vi
ro + RF + gm ro RF
For μ = 1000 V/V, gm = 2 mA/V, ro = 20 k,
and RF = 0.2 k, we have
A=
1000 × 2 × 20
20 + 0.2 + 2 × 20 × 0.2
= 1418.4 mA/V
(c) Aβ =
μgm ro RF
ro + RF + gm ro RF
Aβ = 283.7
10.50 Figure 1 on the next page shows the
equivalent circuit with Vs = 0 and a voltage Vx
applied to the collector for the purpose of
determining the output resistance Ro ,
Ro ≡
Vx
Ix
Some of the analysis is displayed on the circuit
diagram. Since the current entering the emitter
node is equal to Ix , we can write for the emitter
voltage
Ve = Ix [Re (rπ + Rb )]
1 + Aβ = 284.7
Io
A
(d) Af ≡
=
Vs
1 + Aβ
1418.4
= 4.982 mA/V
=
284.7
which is very close to the ideal value of 5 mA/V.
(1)
The base current can be obtained using the
current-divider rule applied to Re and (rπ + Rb ) as
Ib = −Ix
Re
Re + rπ + Rb
(2)
The voltage from collector to ground is equal to
Vx and can be expressed as the sum of the voltage
drop across ro and Ve ,
(e) From the A circuit in Fig. 2, we have
Vx = (Ix − βIb )ro + Ve
Ro = ro + RF + gm ro RF
Substituting for Ve from (1) and for Ib from (2),
we obtain
Vx
Ro =
= ro + [Re (rπ + Rb )]
Ix
1 + Aβ = 1 +
μgm ro RF
ro + RF + gm ro RF
Rof = (1 + Aβ)Ro
= ro + RF + gm ro RF + μgm ro RF
= ro + RF + (μ + 1)gm ro RF
μgm ro RF
Ro = 20 + 0.2 + 2 × 20 × 0.2
= 28.2 k
+
Re βro
Re + rπ + Rb
= ro + [Re (rπ + Rb )] 1 + ro
β
rπ + Rb
Since β = gm rπ , we obtain
Ro = ro + [Re (rπ + Rb )] 1 + gm ro
rπ
rπ + Rb
Q.E.D.
Chapter 10–34
This figure belongs to Problem 10.50.
Ib
B
C
Ix
(Ix 2 bIb)
rp
bIb
ro
Ve
Rb
E
V
x
Ix
Re
Figure 1
For Rb = 0,
10.51
Ro = ro + (Re rπ )(1 + gm ro )
Ix
The maximum value of Ro will be obtained when
Re rπ . If Re approaches infinity (zero signal
current in the emitter), Ro approaches the
theoretical maximum:
(Ix 2 bIb)
Ib
rp
bIb
Romax = ro + rπ (1 + gm ro )
= ro + rπ + βro
ro
Ix
(3)
V
x
0
βro
E
B
Ix
C
Ix
( b1)Ix
rp
bIx
Ix
ro
Rout
V
x
Vx
Ix
Figure 1
E
Figure 2
The situation that pertains in the circuit when
Re = ∞ is illustrated in Fig. 2. Observe that since
the signal current in the emitter is zero, the base
current will be equal to the collector current (Ix )
and in the direction indicated. The
controlled-source current will be βIx , and this
current adds to Ix to provide a current (β + 1)Ix in
the output resistance ro . A loop equation takes
the form
Vx = (β + 1)Ix ro + Ix rπ
and thus
Vx
= rπ + (β + 1)ro
Ro ≡
Ix
which is identical to the result in Eq. (3).
Figure 1 shows the situation that pertains in the
transistor when μ is so large that Vb 0 and
Ie 0. Observe that
Ib = −Ix
Writing a loop equation for the C-E-B, we obtain
Vx = (Ix − βIb )ro − Ib rπ
Substituting Ib = −Ix , we obtain
Rout =
Vx
= rπ + (β + 1)ro
Ix
or if β is denoted hfe ,
Rout = rπ + (hfe + 1)ro
Q.E.D.
Thus, for large amounts of feedback, Rout is
limited to this value, which is approximately hfe ro
independent of the amount of feedback. This
phenomenon does not occur in MOSFET circuits
where hfe = ∞.
Chapter 10–35
10.52
R2
V1 1 R3
R1 2
Io
0
R2
1
0
R1 2
R3
R2
R1 2
1 R3
R11
R22
Figure 1
Figure 1 shows the feedback network fed with a
current Io to determine β:
β≡
Vf
R1 R3
=
Io
R1 + R2 + R3
Io
1
Vs
β
Vg
(1/gm ) + R22
Thus,
A≡
Thus,
Af =
Vg = μVi
Io =
For Aβ 1,
Af =
The A circuit is shown in Fig. 2. We can write
1
R2
1
+
+
R3
R1 R3
R1
Io
μ
=
Vi
(1/gm ) + R22
Since β = 0.01, we have
For R1 = R3 = 0.1 k and Af = 100 mA/V,
Aβ =
R2
+ 10
0.01
⇒ R2 = 0.8 k
100 = 10 +
=
To obtain the loading effects of the feedback
network, refer to Fig. 1.
0.01μ
1/gm + R22
0.01μ
= 9.17 × 10−3 μ
1 + 0.09
For a 60-dB amount of feedback,
1 + Aβ = 1000
R11 = R3 (R2 + R1 )
= 100 (800 + 100) = 90 Aβ = 999
R22 = R1 (R2 + R3 )
9.17 × 10−3 μ = 999
= 100 (800 + 100) = 90 ⇒ μ = 1.09 × 105 V/V
Rout = Rof = (1 + Aβ)Ro = 1000Ro
where Ro can be obtained from the A circuit as
Vi
m
R11
Vg
Io
Ro
Ro = ro + R22 + gm ro R22
= 50 + 0.09 + 1 × 50 × 0.09
R22
= 54.6 k
Thus,
Figure 2
Rout = 1000 × 54.6 = 54.6 M
(1)
(2)
Chapter 10–36
10.53 (a) Since Vs has a zero dc component, the
gate of Q1 is at zero dc voltage. The negative
feedback will force the gate of Q2 to be
approximately at the same dc voltage as that at
the gate of Q1 , thus
(c) From the β circuit in Fig. 1 and noting that
the feedback topology in series-series, the loading
effects of the feedback network are
VO = 0
Figure 2 shows the A circuit. We can write
VD1 = 1.2 − VSG3
Vg5
= −gm1,2 (ro2 ro4 )
Vi
R11 = R22 = RF = 10 k
= 1.2 − |Vt | − |VOV 3 |
Vg5
(1/gm5 ) + R22
= 1.2 − 0.4 − 0.2 = +0.6 V
Io =
VD2 = VO + VGS5
Thus,
= 0 + Vt + VOV 5
A≡
= 0.6 V
Io
gm1,2 (ro2 ro4 )
=
Vi
(1/gm5 ) + R22
gm1,2 =
(b)
Vf 1
RF 2
=
Io
2ID1,2
VOV 1,2
2 × 0.1
= 1 mA/V
0.2
ro2 = ro4 =
Vf
b
RF
Io
=
Figure 1
20
= 200 k
0.1
gm5 =
The feedback network is shown in Fig. 1, from
which we find
A=
β = RF = 10 k
|VA |
ID2,4
2ID5
2 × 0.8
=
= 8 mA/V
VOV 5
0.2
1 × (200 200)
0.125 + 10
= 9.88 mA/V
For Aβ 1,
Af 1
1
=
β
RF
Io
A
= Af =
Vs
1 + Aβ
Af =
1
= 0.1 mA/V
10 k
=
9.88
= 0.099 mA/V
1 + 9.88 × 10
This figure belongs to Problem 10.53, part (b).
Q3
Vg5
10 k
Vi
Io
Q4
Q1
Ro
Q5
Q2
R22 RF 10 k
R11 RF
10 k
Figure 2
(1)
Chapter 10–37
(d) From the A circuit, we have
Combining (1) and (2) yields
Ro = ro5 + R22 + gm5 ro5 R22
Aβ = −
where
ro5 =
Q.E.D.
|VA |
20
= 25 k
=
ID5
0.8
Ro = 25 + 10 + 8 × 25 × 10 = 2035 k
10.55 μ = 103 V/V, Rid = ∞, ro = 100 ,
RF = 10 k, and Rs = RL = 1 k. From
Example 10.9 Eqs. (10.37) and (10.41),
Rout = Rof = Ro (1 + Aβ)
= 2.035 × (1 + 9.88 × 10)
= 203 M
β=−
(e) Vo = Io RF
1
1
= −0.1 mA/V
=−
RF
10 k
A = −μRi
= Af Vs RF
Vo
= Af RF = 0.099 × 10 = 0.99 V/V
Vs
Rout
Vr
RF ro5
= gm1,2 (ro2 ro4 )
Vt
(RF ro5 ) + (1/gm5 )
(RF RL )
ro + (RF RL )
where
Ri = Rid RF Rs
Output resistance at source of Q5
=
1 + Aβ
Ri = ∞ 10 1 = 0.909 k
1/gm5
1 + Aβ
A = −103 × 0.909 ×
=
125 = 1.25 1 + 9.88 × 10
= −818.9 k
Af =
10.54
Q3
Q4
Vg5
Rs
Q1
Vo
A
=
Is
1 + Aβ
=−
818.9
1 − 818.9 × −0.1
=−
818.9
= −9.88 k
1 + 81.89
Rif = Ri /(1 + Aβ)
Q5
Q2
=
Vr
Vt (10 1)
0.1 + (10 1)
0.909 k
= 11 1 + 81.89
Rif = Rin Rs
= Rin 1 k
RF
Rin =
1
1
=
1
1
1
1
−
−
Rif
1000
11 1000
= 11.1 Figure 1
From Eq. (10.42), we have
Ro = ro RF RL
Figure 1 shows the circuit prepared for
determining the loop gain Aβ:
= 0.1 10 1 = 90.1 Vr
Aβ ≡ −
Vt
Rof =
First we write for the gain of differential amplifier
Vg5
= −gm1,2 (ro2 ro4 )
Vt
(1)
Next we write for the source follower,
RF ro5
Vr
=
Vg5
(RF ro5 ) + (1/gm5 )
=
Ro
1 + Aβ
90.1
= 1.1 1 + 81.89
Rof = Rout RL
= Rout /1 k
(2)
⇒ Rout 1.1 Chapter 10–38
Comparison to the values in Example 10.9:
μ = 104 V/V
μ = 103
Af
−9.99 k
−9.88 k
Rin
1.11 11.1 Rout
0.11 1.1 β=−
Aβ = 3.23
Af =
=−
10.56
RF
g
Vr Rs
Vt
1
= −0.1 mA/V
RF
gmVgs
Vgs
ro
Vgs Vt
Vo
A
=
Is
1 + Aβ
32.3
= −7.63 k
1 + 3.23
Compare these results to those found in
Exercise 10.19: A = −32.3 k (−30.3 k),
β = −0.1 mA/V (−0.1 mA/V),
Aβ = −3.23 (−3.03), and Af = −7.63 k
(−7.52 k). The slight differences are due to the
approximation used in the systematic analysis
method.
10.57 (a)
Figure 1
Figure 1 shows the circuit prepared for the
determination of the loop gain Aβ:
Aβ = −
Vr
Vt
An expression for Vr can be written by inspection
as
Rs
Vr = −gm Vt [ro (Rs + RF )]
Rs + RF
Thus,
Aβ = gm [ro (Rs + RF )]
If
Rs
Rs + RF
(1)
Figure 1
RF
1
2
Vo
Figure 2
The feedback network (β circuit) is shown in Fig.
2 fed with Vo at port 2 and with port 1
short-circuited to determine β:
If
1
=−
β≡
Vo
RF
(2)
Figure 1 illustrates the dc analysis. We can
express the dc collector voltage VC in two
alternative ways:
IC
VC = +15 − RC IC +
+ 0.07
β
and
VC = 0.7 + Rf
IC
+ 0.07
β
Equations (1) and (2) can how be used to
determine A:
Equating these two expressions yields
A = −gm [ro (Rs + RF )](Rs RF )
15 − 5.6(IC + 0.01IC + 0.07)
Using the numerical values given in
Exercise 10.19(e), we obtain
= 0.7 + 56(0.01IC + 0.07)
A = −5[20 (1 + 10)](1 10)
⇒ IC = 1.6 mA
= −32.3 k
VC 5.5 V
Chapter 10–39
This figure belongs to Problem 10.57, part (b).
Figure 2
The below two figures belong to Problem 10.57, part (c).
Figure 3
Figure 4
(b) Figure 2 above shows the small-signal
equivalent circuit of the amplifier where
Also, observe that
1.6 mA
= 64 mA/V
0.025 V
β
100
=
= 1.56 k
rπ =
gm
64
β=−
gm =
(c) Figure 3 above shows the A circuit. It includes
the loading effects of the feedback network:
R11 = R22 = Rf
1
Rf
From the A circuit in Fig. 4, we have
Ri = Rs Rf rπ
(1)
Vπ = Ii Ri
(2)
Vo = −gm Vπ (RC Rf )
(3)
Chapter 10–40
Combining (1), (2) and (3) gives
A≡
10.58
Vo
= −gm (Rs Rf rπ )(RC Rf )
Ii
VDD
Ri = 10 k 56 k 1.56 k
I
= 1.32 k
A = −64 × 1.32 × (5.6 56)
= −429 k
Q2
1.4 V
0.7 V
0.7 V
Q1
From the A circuit, we have
I
Ro = RC Rf
= 5.6 k 56 k
= 5.1 k
(d) β = −
Aβ =
(e) Af =
Vo
A
=
Is
1 + Aβ
429
= −49.5 k
8.67
Ri
Rif =
1 + Aβ
=
0
Figure 1
429
= 7.67
56
1 + Aβ = 8.67
=−
RF
1
1
=−
Rf
56 k
1.32 k
= 152 8.67
Rif = Rs Rin
152 = 10 k Rin
Rin = 155 Rout = Rof
Ro
=
1 + Aβ
5.1 k
=
= 588 8.67
Af
Vo
Vo
49.5
(f)
= −4.95 V/V
=
=
=−
Vs
Is Rs
Rs
10
(a) See Figure 1.
VG1 = VGS1 = Vt + VOV
= 0.5 + 0.2 = +0.7 V
(because the dc voltage across RF is zero)
VO = VG1
VO = +0.7 V
VD1 = VO + VGS2
= 0.7 + 0.5 + 0.2
= +1.4 V
(b) gm1,2 =
ro1,2 =
2I
2 × 0.4
= 4 mA/V
=
VOV
0.2
16 V
VA
=
= 40 k
I
0.4 mA
(c) Figure 2 on the next page shows the β circuit
and the determination of its loading effects,
R11 = R22 = RF
Refer to Fig. P10.57 and assume the gain of the
BJT to be infinite so that the signal voltage at its
base is zero (virtual ground). In this case, we have
Figure 2 shows also the A circuit. We can write
Rf
56
Vo
=−
=−
= −5.6 V/V
Vs
Rs
10
where
Thus, the actual gain magnitude ( 5 V/V) is
only about 12% below the ideal value; not bad for
a single transistor inverting op amp!
Vg1 = Ii Ri
(1)
Ri = R11 = RF
(2)
Vd 1 = −gm1 ro1 Vg1
(3)
Chapter 10–41
This figure belongs to Problem 10.58, part (c).
RF
RF
1
2
RF
1
2
1
2
R11 RF
R22 RF
Vd1
Q2
Vg1
Vo
Q1
R22 RF
R11 RF
Ii
Ro
Ri
Figure 2
Vo
=
Vd 1
R22 ro2
(4)
1
(R22 ro2 ) +
gm2
=−
Combining Eqs. (1)–(4) results in
A≡
(e) Af ≡
RF ro2
Vo
= −gm1 ro1 RF
Ii
(RF ro2 ) + 1/gm2
(d)
Vo
A
=
Is
1 + Aβ
gm1 ro1 RF (RF ro2 )
(RF ro2 ) + 1/gm2 + (gm1 ro1 )(RF ro2 )
(f) Ri = RF
Rin = Rif = Ri /(1 + Aβ)
= RF
If
RF
1 + gm1 ro1
Rout = Rof = Ro /(1 + Aβ)
V b
o
If
1
RF
Vo
where from the A circuit we have
Ro = RF ro2 Figure 3
1
RF
Aβ = gm1 ro1
RF ro2
(RF ro2 ) + 1/gm2
1 + Aβ = 1 + gm1 ro1
RF ro2
(RF ro2 ) + 1/gm2
1
gm2
1
Rout = RF ro2 gm2
1 + gm1 ro1
From Fig. 3 we see that
β=−
RF ro2
(RF ro2 ) + 1/gm2
RF ro2
(RF ro2 ) + 1/gm2
(g) A = −4 × 40 × 10
10 40
(10 40) + 0.25
= −1551.5 k
β=−
1
1
= −0.1 mA/V
=−
RF
10 k
Chapter 10–42
Aβ = 155.15
(b) Refer to the solution to Example 10.9.
1 + Aβ = 156.15
1551.5
= −9.94 k
Af = −
156.15
Ri = RF = 10 k
Rin = Rif =
10, 000 RF
=
= 64 1 + Aβ
156.15
1
Ro = RF ro2 gm2
Ro = 10 40 0.25 = 242 Rout = Rof =
Ro
1 + Aβ
242
= 1.55 =
156.15
β=−
1
1
= −0.05 mA/V
=−
RF
20 k
Using Eq. (10.39), we obtain
Ri = Rid RF Rs
= 100 20 2 = 1.786 k
Using Eq. (10.41) with RL = ∞, we get
A≡
Vo
20
= −103 × 1.786 ×
Ii
20 + 2
= −1623.6 k
Af ≡
Vo
A
=
Is
1 + Aβ
where
1 + Aβ = 1 + 1623.6 × 0.05
10.59 (a)
= 82.18
Af =
Vo
1623.6
=−
Is
82.18
= −19.76 k
Af
Vo
Vo
19.76
=
=
=−
Vs
Is Rs
Rs
2
= −9.88 V/V
Rif =
=
Ri
1 + Aβ
1.786
= 21.7 82.18
Rif = Rs Rin
Refer to the feedback network shown in
Fig. 10.24(b) and to the determination of β
illustrated in Fig. 10.24(c). Thus,
β=−
1
RF
21.7 = 2000 Rin
Rin 21.7 Rout = Rof =
Ro
1 + Aβ
If Aβ 1, then we have
where from Eq. (10.42) with RL = ∞ we get
Vo
1
= −RF
Af =
Is
β
Ro = ro RF = 2 20 = 1.818 k
and the voltage gain realized will be
Rout = Rof =
1.818
= 22.1 82.18
Vo
RF
Vo
=
−
Vs
Is Rs
Rs
(c) fHf = fH (1 + Aβ)
If Rs = 2 k, to obtain Vo /Vs −10 V/V, we
required
= 1 × 82.18
RF = 10 × Rs = 20 k
= 82.18 kHz
Chapter 10–43
This figure belongs to Problem 10.60.
RF
G
Vgs/Rs
Vgs
Rs
Is
(Vo – Vgs)/RF
Vo
Vo/ro
ro
gmVgs
Figure 1
This figure belongs to Problem 10.61, part (a).
5 V
RC
10 k
0.356 mA
10 1.44 V
0.7 V
50.356
Q1
0.35
mA
Q2
0.0058
mA
0.0035
mA
0.577 ~ 0.58 mA
VO 0.7 0.035
0.735 V
0.0035
RE
10 k
RF 10 k
5 V
0.735(5)
0.5735 mA
10
Figure 1
10.60 Figure 1 shows the small-signal-equivalent
circuit of the feedback amplifier of Fig. E10.19.
Analysis to determine Vo /Is proceeds as follows:
Substituting for Vgs from (1) into (2), we obtain
Is + Vo gm −
Writing a node equation at the output node
provides
gm −
1
RF
(1)
(ro RF )
Vgs
Vo − Vgs
+
=0
Rs
RF
Is −
Vgs
Vo
+
=0
(Rs RF ) RF
(ro RF )(Rs RF )
Vo
RF
For the feedback analysis to be reasonably
accurate, we use
gm Writing a node equation at node G provides
Is −
+
Vo
Is
1
gm −
(ro RF )(Rs RF )
RF
=
1
1 + gm −
(ro RF )(Rs RF )/RF
RF
1
1
+
r
RF
⇒ Vgs = −Vo o
1
gm −
RF
1
1
=0⇒
Vo − Vgs
Vo
gm Vgs +
+
=0
ro
RF
⇒ Vgs = −Vo 1
RF
1
RF
10.61 (a) Figure 1 (see figure above) shows the
dc analysis. We assumed IC1 = 0.35 mA and
found that IC2 = 0.58 mA, thus verifying the
given values. The dc voltage at the output is
(2)
VO = +0.735 V
Chapter 10–44
The collector voltage of Q1 is given by
(b)
Vc1 = −gm1 Vb1 RC (β2 + 1)[re2 + (RE RF )]
where
re2 =
VT
25 mV
=
= 43.1 IE2
0.58 mA
Vc1 = −14Vb1 10 101[0.0431 + (10 10)]
= −137.3Vb1
(2)
The gain of the emitter-follower Q2 is given by
Vo
RE RF
=
Vc1
(RE RF ) + re2
Figure 2
=
Figure 2 shows the β circuit and the determination
of its loading effects on the A circuit:
5
= 0.99 V/V
5 + 0.0431
Combining (1)–(3) gives
R11 = R22 = RF = 10 k
A≡
Vo
= −0.99 × 137.3 × 4.17
Ii
= −567.6 k
(c) The value of β can be obtained from the β
circuit as shown in Fig. 4:
Figure 4
Figure 3
β=−
1
1
= −0.1 mA/V
=−
RF
10 k
Figure 3 shows the A circuit. The input resistance
is given by
Aβ = −567.6 × −0.1
Ri = RF = RF rπ 1
= 56.76
where
1 + Aβ = 57.76
gm1
IC1
0.35
= 14 mA/V
=
=
VT
0.025
rπ 1 =
(d) Af ≡
β
100
= 7.14 k
=
gm1
14
Af = −
Thus,
Vo
A
=
Is
1 + Aβ
567.6
= −9.83 k
57.76
Rin = Rif =
Ri = 10 k 7.14 k = 4.17 k
Ri
1 + Aβ
The input voltage Vb1 is given by
Vb1 = Ii Ri = 4.17Ii
(1)
=
4.17 k
= 72.2 57.76
(3)
Chapter 10–45
This figure belongs to Problem 10.62.
If
RF
1
RF
Vo
2
b
If
1
RF
Vo
1
RF
2
1
R11 RF
2
R22 RF
Figure 1
Figure 2 shows the A circuit. For the CG amplifier
Q1 , we can write
From the A circuit, we have
RC
Ro = RF RE re2 +
β2 + 1
Ri = RF 10
= 10 10 0.0431 +
101
= 138.2 Ro
Rout = Rof =
1 + Aβ
138.2
=
= 2.4 57.76
10.62 Figure 1 shows the feedback network with
a voltage Vo applied to port 2 to determine β:
If
1
=−
β≡
Vo
RF
For Aβ 1, we have
1
Vo
≡ Af = −RF
Is
β
Vo
Thus, for
−10 k, we select
Is
RF = 10 k
The loading of the feedback network on the A
circuit can be determined as shown in Fig. 1:
1
gm1
Vsg = Ii Ri
(2)
Vd 1 = gm1 Vsg RD1
(3)
Combining (1)–(3) yields
1
Ii
Vd 1 = (gm1 RD1 ) RF gm1
Vo
= −gm2 (RD2 RF )
Vd 1
Substituting gm1 = gm2 = 4 mA/V,
RD1 = RD2 = 10 k, and RF = 10 k gives
Aβ =
RD2
Vo
Vd1
Q2
195
= 19.5
10
1 + Aβ = 20.5
Af ≡
R22 RF
Q1
=−
Vo
A
=
Is
1 + Aβ
195
= −9.52 k
20.5
Rin = Rif =
R11 RF
Ii
Ro
Ri
1 + Aβ
From Eq. (1), we obtain
Ri = 10 0.25 = 244 Ri
Figure 2
(5)
Combining (4) and (5), we obtain the open-loop
gain A:
1
Vo
= −(gm1 RD1 ) RF A≡
gm2 (RD2 RF )
Is
gm1
A = −195 k
RD1
(4)
For the CS stage Q2 , we can write
A = −(4 × 10) × (10 0.25) × 4 × (10 10)
R11 = R22 = RF
(1)
Rin =
244
= 11.9 20.5
Chapter 10–46
Now consider the amplifier stage shown in Fig.
P10.63(b). First, we determine the dc bias point as
follows:
From the A circuit,
Ro = RD2 RF
= 10 10 = 5 k
Rout = Rof
=
Ro
=
1 + Aβ
IE =
5000
= 244 20.5
IC = 1.11 × 0.99 = 1.1 mA
10.63 (a) Converting the signal source to its
Norton’s form, we obtain the circuit shown in
Fig. 1(a).
This is a shunt–shunt feedback amplifier with the
feedback network consisting of the resistor Rf . To
determine β, we use the arrangement shown in
Fig. 1(b),
IC
1.1
= 44 mA/V
=
VT
0.025
rπ =
β
100
=
= 2.27 k
gm
44
Rout = 7.5 k
Av o = −gm × 7.5 k
= −44 × 7.5 = −330 V/V
Now, for Aβ 1, the closed-loop gain becomes
Figure 2(a) (next page) shows the equivalent
circuit of the amplifier stage. Figure 2(b) shows
the A circuit of the feedback amplifier made up of
the cascade of three stage. Observe that we have
included Rs and RL as well as R11 and R22 . The
overall gain A ≡ Vo /Is cam be obtained as
follows:
Vo
1
= −Rf
Is
β
The voltage gain
Vo
is obtained as
Vs
Af
Vo
Vo
=
=
Vs
Is Rs
Rs
Ri = Rs RF 1.65 k
Thus,
= 10 1000 1.65 = 1.414 k
Rf
Vo
−
Vs
Rs
V1 = Ii Ri = 1.414Ii
Q.E.D.
(b) To obtain a closed-loop voltage gain of
approximately −100 V/V, we use
−100 = −
gm =
Rin = 10 15 2.27 = 1.65 k
1
β=−
Rf
Af ≡
10
− 0.7
10 + 15
= 1.11 mA
10 15
4.7 +
101
15 ×
Rf
Rs
For Rs = 10 k, we obtain
Rf = 1 M
V2 = −330V1 ×
1.65
= −59.5V1
1.65 + 7.5
(2)
V3 = −330V2 ×
1.65
= −59.5V2
1.65 + 7.5
(3)
Vo = −330V3 ×
1 1000
(1 1000) + 7.5
= −38.8V3
This figure belongs to Problem 10.63, part (a).
Figure 1
(1)
(4)
Chapter 10–47
This figure belongs to Problem 10.63, part (b).
7.5 k
V1
330V
1
1.65 k
(a)
7.5 k
Ii
Rs
V1
RF
1.65
k
Ri
7.5 k
V2
330V1
7.5 k
1.65
k
V3
330V2
1.65
k
RF
RL
330V3
10 k 1 M
1 M
1 k
Ro
(b)
Figure 2
Combining (1)–(4) gives
A≡
Vo
= −1.94 × 105 k
Ii
Since
1
1
=−
β=−
Rf
1 M
we have
Ro = 1 1000 7.5 = 881.6 Rof =
Ro
1 + Aβ
881.6
= 4.5 195
Rof = Rout RL
=
⇒ Rout = 4.5 Aβ = 194
and
10.64 (a)
1 + Aβ = 195
VDD 3.3 V
Thus,
Af ≡
I1
Vo
1.94 × 105
=−
Is
195
Q2
Q1
= −995 k
and the voltage gain realized is
Af
−99.5
Vo
= −99.5 V/V
=
=
Vs
Rs
10
Rif =
Ri
1 + Aβ
1414 = 7.3 195
Rif = Rs Rin
=
Rin 7.3 From the A circuit, we have
Ro = RL RF 7.5 k
VG
R1
0
VG
R1
ID2 1 mA
R2
VO
10 A
RL
0.99 mA
Figure 1
Figure 1 shows the circuit for the purpose of
performing a dc design.
ID1 = 100 μA ⇒ I1 = 100 μA
1
W
V2
ID1 = μn Cox
2
L 1 OV 1
Chapter 10–48
1
× 200 ×
2
W
⇒
= 25
L 1
W
L
100 =
× 0.22
1
Q2
Q1
VG1 = Vtn + VOV 1
R2
Vo
= 0.6 + 0.2 = 0.8 V
Since IR2,R1 = 10 μA, we have
Is 0.8 V
R1 =
= 80 k
0.01 mA
IRL = ID2 − IR2,R1
Vs
Rs
Rs
Rif
R1
RL
Rin
= 1 − 0.01 = 0.99 mA
Rout
Figure 3
VO = 0.99 × 2 = 1.98 V
1
W
V2
ID2 = μn Cox
2
L 2 OV 2
W
1
1 = × 0.2 ×
× 0.22
2
L 2
W
⇒
= 250
L 2
Af
Vo
Vo
=
=
Vs
Is Rs
Rs
Thus,
−6 = −
118
Rs
⇒ Rs = 19.7 k
VO − VG
0.01 mA
1.98 − 0.8
= 118 k
=
0.01
VGS2 = Vtn + VOV 2 = 0.8 V
R2 =
(d)
VD1 = VG2 = 1.98 + 0.8 = 2.78 V
Q2
(b) The β circuit consists of resistance R2 . The
value of β can be determined as shown in Fig. 2.
Vo
Q1
Ii
If
Rof
Rs
R1
R11
R2
R22
R2
RL
R2
1
2
Ri
V
o
Ro
Figure 4
Figure 2
The A circuit is shown in Fig. 4.
β≡
If
1
1
=−
=−
Vo
R2
118 k
Ri = Rs R1 R2
= 19.7 80 118 = 13.92 k
= −8.47 × 10−3 mA/V
Vgs1 = Ii Ri = 13.92Ii
Thus,
1
Af ideal ≡ = −118 k
β
Vd 1 = −gm1 Vgs1 ro1
(c) Converting the signal source to its Norton’s
form, the feedback amplifier takes the form
shown in Fig. 3.
where
gm1 =
2ID1
2 × 0.1
=
= 1 mA/V
VOV 1
0.2
ro1 =
VA
20
= 200 k
=
ID1
0.1
(1)
Chapter 10–49
10.65
Thus,
Vd 1 = −200Vgs1
(2)
Vo
RL R2 ro2
=
Vd 1
(RL R2 ro2 ) + 1/gm2
RD
where
gm2
Vo
2ID2
2×1
=
=
= 10 mA/V
VOV 2
0.2
ro2 =
Q1
Ro
VA
20
= 20 k
=
ID2
1
Thus,
Vo
(2 118 20)
= 0.947 V/V
=
Vd 1
(2 118 20) + 0.1
Ii
(3)
Ri
Combining (1)–(3), we obtain
A=
Figure 1
Vo
= −13.92 × 200 × 0.947
Ii
= −2636.7 k
1
Ro = RL R2 ro2 gm2
= 2 118 20 0.1
The A circuit is shown in Fig. 1.
Ri =
1
1
= = 0.2 k
gm1
5
A≡
Vo
= RD = 10 k
Ii
Ro = RD = 10 k
= 94.7 (e) Af =
Vo
A
=
Vs
1 + Aβ
=−
C1
If
2636.7
=−
1 + (2636.7/118)
Vo
Qf
C2
2636.7
= −113 k
23.34
Af
Vo
113
= −5.73 V/V
=
=−
Vs
Rs
19.7
(f) Rif =
13.92
Ri
=
= 0.596 k
1 + Aβ
23.34
Rif = Rs Rin
0.596 = 19.7 Rin
⇒ Rin = 615 Rof =
Ro
94.7
=
= 4.06 1 + Aβ
23.34
Rof = Rout RL
4.06 = Rout 2000 ⇒ Rout = 4.1 Figure 2
The β circuit is shown in Fig. 2.
β≡
If
C1
0.9
×2
=
gmf =
C1 + C2
0.9 + 0.1
Vo
= 1.8 mA/V
Vo
A
=
Af ≡
Vs
1 + Aβ
=
10
= 0.53 k
1 + 10 × 1.8
Rin = Rif =
Ri
200 =
= 10.5 1 + Aβ
19
Rout = Rof =
Ro
10 k
=
= 526 1 + Aβ
19
Chapter 10–50
These figures belong to Problem 10.66, part (a).
RF
1
RM
0
RF
2
1
RM
RF
2
1
RM
R11 RF RM
2
R22 RM // RF
Figure 1
RD
Vgs2
gm1Vsg1
Q1
Io gm2Vgs2
RL
Vsg1
Ii
Q2
R11
R22
Ri
Ro
Figure 2
10.66 (a) Figure 1 shows the β network as well
as the determination of its loading effects on the A
circuit:
The β circuit prepared for the determination of β
is shown in Fig. 3.
β≡
R11 = RF + RM
R22 = RM RF
Figure 2 shows the A circuit. Some of the analysis
is shown on the diagram.
1
gm1
If
RM
=−
Io
RM + RF
(c) From (5)–(6), we obtain
1
RM
R11 (gm1 RD )gm2
Aβ =
RM + RF
gm1
(1)
(d) gm1 = gm2 = 5 mA/V, RD = 20 k
Vsg1 = Ii Ri
(2)
RM = 10 k, and RF = 90 k, thus
Vgs2 = gm1 Vsg1 RD
(3)
R11 = RF + RM = 90 + 10 = 100 k
Io = −gm2 Vgs2
(4)
R22 = RM RF = 10 90 = 9 k
Ri = R11 Combining (1)–(4) gives
1
Io
= − R11 (gm1 RD )gm2
A≡
Ii
gm1
A = −(100 0.2) × (5 × 20) × 5 = −99.8 A/A
(5)
(b)
β=−
10
= −0.1 A/A
10 + 90
Aβ = 9.98
If
RF
1
1 + Aβ = 10.98
RM
Figure 3
2
(6)
Io
Af ≡
Io
A
99.8
=
=−
= −9.1 A/A
Is
1 + Aβ
10.98
Rin = Rif =
Ri
1 + Aβ
Chapter 10–51
where
Combining Eqs. (1) and (2), we obtain
Ri = 100 k 0.2 k 0.2 k
Aβ ≡ −
Rin =
200 = 18.2 10.98
Vr
ro2
R1
=μ
1
Vt
ro2 + R1
+ (ro2 R1 )
gm
For
(e) Breaking the output loop of the A circuit
between XX , we find
μ = 1000 V/V, R1 = 10 k,
Ro = R22 + RL + ro2
gm = 5 mA/V, and ro2 = 20 k
= (RM RF ) + RL + ro2
we obtain
= (10 90) + 1 + 20
Aβ = 1000 ×
= 30 k
= 970.9
Rof = Ro (1 + Aβ) = 30 × 10.98
which is slightly lower than the value found in
Example 10.10 (1076.4), the difference being
about −10%. This is a result of the assumptions
and approximations made in the general feedback
analysis method.
= 329.4 k
Rout = Rof − RL = 328.4 k
20
10
0.2 + (20 10) 20 + 10
From Example 10.10 (or directly from the β
circuit) we have
10.67
β = −0.1 A/A
Io
Thus,
A = −9709
m
Vr
ro2
Vt Af = −
Io
R2
0
Figure 1
10.68 Refer to Fig. 10.27(c), which shows the
determination of β,
Figure 1 shows the shunt-series feedback
amplifier circuit of Fig. 10.27(a) prepared for
determining the loop gain,
β=
If
R1
=−
Io
R1 + R2
Vr
Vt
Ri = Rs Rid (R1 + R2 )
Vt
1
+ (ro2 R1 )
gm
ro2
ro2 + R1
(1)
For our case here, Rs = Rid = ∞, thus
Ri = R1 + R2
For Rin = Rif = 1 k, we have
Rif =
The voltage Vr can be obtained as
Vr = Io R1 × −μ = −μR1 Io
(1)
Refer to Fig. 10.27(e), which shows the A circuit.
The input resistance Ri is given by
observe that here Rs = Rid = ∞. Thus Io can be
obtained as
Io =
9709
= −9.99 A/A
971.9
which is identical to the value obtained in
Example 10.10. Thus while Aβ and A differ
slightly for the earlier results, Af is identical; an
illustration of the power of negative feedback!
Io
R1
Aβ ≡ −
and
(2)
Ri
1 + Aβ
⇒ Ri = Rif (1 + Aβ)
Chapter 10–52
Figure 1 shows the dc analysis. It starts by noting
that ID1 = 0.2 mA. Thus VOV 1 = 0.2 V and
Thus
R1 + R2 = 1 k × (1 + Aβ)
Since 1 + Aβ is 40 dB, that is,
VG1 = VGS1 = Vt + VOV 1 = 0.5 + 0.2
1 + Aβ = 100
= 0.7 V
we have
R1 + R2 = 1 × 100 = 100 k
(2)
Now,
Af =
A
1 + Aβ
−100 =
VS2 = +0.7 V
A
100
and
⇒ A = −104 A/A
99
Aβ
=
= −0.0099
β=
A
−104
Using Eqs. (1) and (2), we obtain
−0.0099 = −
IR1 =
0.7 V
= 0.2 mA
3.5 k
Thus, Q2 is operating at
R1
R1 + R2
ID = 0.2 mA
⇒ R1 = 0.0099 × 100 = 0.99 k
(b) gm1 = gm2 =
R2 = 100 − 0.99 = 99.01 k
Now, using Eq. (10.53), (page 859), we obtain
ro2
Ri
A = −μ
1/gm + (R1 R2 ro2 ) ro2 + (R1 R2 )
=
100
20
0.2 + (0.99 99.01 20) 20 + (0.99 99.01)
μ = 119 V/V
Q.E.D.
2ID
VOV
2 × 0.2
= 2 mA/V
0.2
ro1 = ro2 =
−104 =
−μ
Since the dc current through R2 is zero, the dc
voltage drop across it will be zero, thus
10
= 50 k
0.2
(c)
R2
R2
From Example 10.10, we have
0
Ro = ro2 + (R1 R2 ) + gm2 ro2 (R1 R2 )
Ro = 20 + (0.99 99.01)(1 + 5 × 20)
R1
1
1
2
R1 2
= 119 k
R11 R1R2
Rout = Rof = Ro (1+Aβ) = 119×100 = 11.9 M
R2
10.69 (a)
1
R1
2
0.2 mA
R22 R1 R2
Q2
0.7 V
Q1
0.2 mA
R2
Figure 2
0.7 V
14 k 0
0.2 mA
R1
3.5 k
Figure 2 shows the β circuit and the
determination of its loading effects, R11 and R22 ,
R11 = R1 + R2 = 3.5 + 14 = 17.5 k
Figure 1
R22 = R1 R2 = 3.5 14 = 2.8 k
Chapter 10–53
(e) Aβ = −525.8 × −0.2
Io
Vd1
Q2
Vgs1
Ro
ro2
= 105.16
1 + Aβ = 106.16
Q1
Ii
Af = −
R22
R11
Io
525.8
= −4.95 A/A
106.16
(f) Rin = Rif =
Figure 3
=
Ri
1 + Aβ
17.5 k
= 164.8 106.16
Figure 3 shows the A circuit. To obtain A = Io /Ii ,
we write
Rout = Rof = Ro (1 + Aβ)
Vgs1 = Ii R11
(1)
= 332.8 × 106.16 = 35.3 M
Vd 1 = −gm1 ro1 Vgs1
(2)
ro2
Vd 1
1
ro2 + R22
+ (ro2 R22 )
gm2
Io =
(3)
Combining (1)–(3) yields
A=
R11
ro2
Io
(gm1 ro1 )
=−
1
Ii
ro2 + R22
+ (ro2 R22 )
gm2
A=−
17.5
50
× 2 × 50 ×
0.5 + (50 2.8)
50 + 2.8
A = −525.8 A/A
Ri = R11 = 17.5 k
10.70 (a) If μ is a very large, a virtual ground
will appear at the input terminal. Thus the input
resistance Rin = V− /Ii = 0. Since no current
flows in Rs , or into the amplifier input terminal,
all the current Is will flow in the transistor source
terminal and hence into the drain, thus
Io = Is
and
Io
=1
Is
(b) This is a shunt-series feedback amplifier in
which the feedback circuit consists of a wire, as
shown on the next page in Fig. 1. As indicated,
Ro = ro2 + R22 + gm2 ro2 R22
= 50 + 2.8 + 2 × 50 × 2.8
R11 = ∞
= 332.8 k
R22 = 0
(d)
If
The A circuit is shown in Fig. 2 (next page) for
which we can write
R2
R1
1
2
Io
Vid = −Ii (Rs Rid )
−Ii Rs
Figure 4
Figure 4 shows the determination of the value
of β:
β≡
If
R1
=−
Io
R1 + R2
β=−
(since Rid is very large)
Vgs = μVid
(2)
Io = gm2 Vgs
(3)
Combining (1)–(3), we obtain
Thus,
3.5
= −0.2 A/A
3.5 + 14
(1)
A≡
Io
= −μgm2 Rs
Ii
Chapter 10–54
These figures belong to Problem 10.70, part (b).
1
2
1
2
1
R22 0
2
R11 Figure 1
Io
G
Vid
Rid
mVid
0
Vgs
gm2Vgs
ro2
Ro
S
Ii
Rs
short because R22 0
Ri
Figure 2
Ri = Rs
Af 1
Ro = ro2
Ri
1 + Aβ
(e) Rif =
(c)
=
If
Rs
μgm2 Rs
Rif = Rin Rs
1
2
Io
1
1
1
=
+
Rif
R in Rs
1
1
1
+ μgm2 =
+
Rs
R in Rs
Figure 3
⇒ Rin =
From Fig. 3 we find
β≡
If
= −1
Io
(d) Aβ = μgm2 Rs
1
μgm2
Rout = Rof = Ro (1 + Aβ)
= ro2 (1 + μgm2 Rs )
(f)
A
Af =
1 + Aβ
Io
μgm2 Rs
=−
1 + μgm2 Rs
Note that the negative sign is due to our
assumption that Is flows into the input node (see
Fig. 2 for the way Ii is applied). If instead Is is
flowing out of the input node, as indicated in
Fig. P10.70, then
Af ≡
gm1Vi
Rout
m
ro1
Io
μgm2 Rs
=
Is
1 + μgm2 Rs
If μ is large so that μgm2 Rs 1,
Figure 4
Q2
Chapter 10–55
The circuit of the cascode amplifier in Fig. P10.70
with VG replaced by signal ground, and Q1
replaced by its equivalent circuit at the drain
(Fig. 4, previous page) looks identical to that of
Fig. 10.70(a). Thus we can write
thus
Vx = Ix ro1 − μgm1 ro1 Vx
⇒ Rin ≡
Vx
ro1
=
Ix
1 + μgm1 ro1
Since μgm1 ro1 1, we have
Io gm1 v i
1
μgm1
Rout = ro2 (1 + μgm2 ro1 ) = ro2 + μ(gm2 ro2 )ro1
Rin μ(gm2 ro2 )ro1
(d) Since the drain of Q2 is outside the feedback
loop, we have
Compared to the case of a regular cascode, we see
that while Io gm1 Vi as in the regular cascode,
utilizing the "super" CG transistor results in
increasing the output resistance by the additional
factor μ!
10.71 (a) Refer to Fig. P10.71. Let Is increase.
This will cause the voltage at the input node,
which is the voltage at the positive input of the
amplifier μ, to increase. The amplifier output
voltage will correspondingly increase. Thus, Vgs
of Q1 increases and Io1 increases. This counteracts
the originally assumed change of increased
current into the input node. Thus, the feedback is
negative.
(b) The negative feedback will cause the dc
voltage at the positive input terminal of the
amplifier to be equal to VBIAS . Thus, the voltage at
the drain of Q1 will be equal to VBIAS . For Q1 to
operate in the active mode, the minimum voltage
at the drain must be equal to VOV which is 0.2 V.
Thus the minimum value of VBIAS must be 0.2 V.
Rout = ro2
10.72
15 V
10
mA
200 A
VO 10 V
Q2
100 A
0.7 V
RL 500 100 A
Q1
10.07 mA
0.7 V
70 A
0
Rf 10 k
70 A
1.4 V
10 mA
Rs
10 k
RE
140 Figure 1
The dc analysis is shown in Fig. 1, from which we
see that
(c)
IC1 = 0.1 mA
IC2 = 10 mA
Thus,
gm1 = 4 mA/V
rπ1 = 25 k
Figure 1
Figure 1 shows the circuit for determining Rin ,
Rin ≡
Vx
Ix
A node equation at D1 gives
Vx = (Ix − gm1 Vgs )ro1
gm2 = 400 mA/V
The β circuit (Fig. 2, next page), also shows the
determination of its loading effects and of β.
R11 = Rf + RE = 10.14 k
R22 = Rf RE = 10 0.14 = 0.138 k
β=−
0.14
RE
=−
= 0.0138 A/A
Rf + RE
10 + 0.14
The A circuit is shown in Fig. 3.
⇒ Vx = Ix ro1 − gm1 Vgs ro1
Ri = Rs R11 rπ1
But,
= 10 10.14 25
Vgs = μVx ,
= 4.19 k
Chapter 10–56
These figures belong to Problem 10.72.
RE
1
0
Rf
Rf
1
2
b Circuit
If
RE
2
RE
2
R11 Rf RE
Rf
1
RE
2
Rf
1
R22 RE Rf
b
Io
RE
If
Rf RE
Io
Figure 2
RL 500 gm1Vp1
b2 gm1Vp1 Io
Q2
Ii
Rs
R11
Q1
R22
Vp1
Ri
Vp1 IiRi
Figure 3
Vπ 1 = Ii Ri
Io = −β2 gm1 Vπ 1
Io
⇒A=
= −β2 gm1 Ri
Ii
Vo
−Io RL
0.5
=
= 69.5 ×
= 3.47 V/V
Vs
−Is Rs
10
Rif =
Ri
1 + Aβ
4190 = 173.6 24.13
A = −100 × 4 × 4.19 = −1676 A/A
=
Aβ = −1676 × −0.0138 = 23.13
Rif = Rs Rin
1 + Aβ = 24.13
173.6 = 10, 000 Rin
Af =
Io
A
=
Is
1 + Aβ
⇒ Rin = 176.7 where
10.73 See figures on the next two pages.
Vs
Is =
Rs
(a) Refer to Fig. 1.
Af = −
1676
= −69.5 A/A
24.13
(b) Refer to Fig. 2.
(c) Routz = ro2 ro4
Chapter 10–57
These figures belong to Problem 10.73, part (a).
Q1
Vx
Q2
Vx /R
QN
x
Vx /R
0 m
0
Vy Vx
QP
Vx /R
y
Vx
Vx
R
R
Iz 0
z
0
Q3
Vx positive
Figure 1
Q4
Vx
R
Chapter 10–58
These figures belong to Problem 10.73, part (b).
Q1
0
QN
Vy 0
0
y
x
0
Q2
m
0
z
Iy
Vy 0
Iy
QP
Iz Iy
Iy
Rin 0
Iy
Q3
Q4
Iy positive
Q1
Q2
Iy
QN
x
0
m
Vy 0
Iy
0
Vy 0
Iy
QP
z
y
Iy
Iz Iy
0
0
Q3
Q4
Iy negative
Figure 2
Chapter 10–59
10.74 (a) Refer to the circuit in Fig. P10.74.
Observe that the feedback signal is capacitively
coupled and so are the signal source and RL ; thus,
these do not enter into the dc bias calculations and
the feedback does not affect the bias. The dc
emitter current in Q1 can be determined from
Is =
Vs
Rs
RB = RB1 RB2 = 13 k
(c) See figure on the next page. The
determination of the loading effects of the β
circuit on the A circuit is shown in Fig. 2:
15
− 0.7
100
+ 15
= 0.865 mA
IE1 =
100 15
0.870 +
101
IC1 = 0.99 × 0.865 = 0.86 mA
12 ×
R11 = Rf + RE2 = 10 + 3.4 = 13.4 k
R22 = RE2 Rf = 3.4 10 = 2.54 k
The A circuit is shown in Fig. 3 on the next page.
Next consider Q2 and let its emitter current
be IE2 . The base current of Q2 will be
IE2 /(β + 1) 0.01 IE2 . The current through RC1
will be (IC1 + IB2 ) = (0.86 + 0.01 IE2 ). We can
thus write the following equation:
Analysis of the A circuit to determine A ≡ Io /Is
proceeds as follows:
12 = (0.86 + 0.01 IE2 ) × 10 + 0.7 + 3.4 × IE2
Vπ1 = Ii Ri
Ri = Rs R11 RB rπ1
= 10 13.4 13 2.91 = 1.68 k
2.7
12 − 8.6 − 0.7
⇒ IE2 =
=
= 0.77 mA
3.4 + 0.1
3.5
IC2 = 0.76 mA
(1)
Ib2 = −gm1 Vπ1
RC1
RC1 + rπ2 + (β + 1)R22
(2)
Io = Ie2 = (β + 1)Ib2
The small-signal parameters of Q1 and Q2 can
now be obtained as
0.86
gm1 =
= 34.4 mA/V
0.025
100
rπ 1 =
= 2.91 k
34.4
0.76
gm2 =
= 30.4 mA/V
0.025
100
rπ 2 =
= 3.3 k
30.4
(b) The equivalent circuit of the feedback
amplifier is shown in Fig. 1, where
(3)
Combining Eqs. (1)–(3) results in
A≡
=
Io
(β + 1)Ri gm1 RC1
=−
Ii
RC1 + rπ2 + (β + 1)R22
101 × 1.68 × 34.4 × 10
10 + 3.3 + 101 × 2.54
= −216.3 A/A
Breaking the emitter loop of Q2 at XX gives
Ro = R22 +
= 2.54 +
Rs = 10 k
rπ2 + RC1
β +1
3.3 + 10
= 2.67 k
101
This figure belongs to Problem 10.74, part (b).
Ic2
Is
Rs
RB
rp1
RC1
Vp1
gm1Vp1
rp2
Vp2
gm2Vp2
Io
Rout
Rif
Rin
Rf
Rof
RE2
Figure 1
Iout
RL
RC2
Chapter 10–60
These figures belong to Problem 10.74, part (c).
Rf
Rf
1
RE2 2
1
0
Rf
1
RE2 2
RE2 2
b Circuit
R22 RE2 Rf
R11 Rf RE2
Figure 2
Figure 3
(d)
Iout = IC2
If
Rf
RE2
1
Iout
Iout
Io
RC2
= ×α
Iin
Is
Is
RC2 + RL
2
Figure 4
β≡
RC2
RC2
= αIo
RC2 + RL
RC2 + RL
Io
⇒
Iout
8
= −3.87 × 0.99 × 0.99 ×
Iin
8+1
= −3.41 A/A
If
RE2
=−
Io
RE2 + Rf
= −0.254 A/A
Rout
RC1
Q2
(e) Aβ = −216.3 × −0.254 = 54.88
1 + Aβ = 55.88
Af =
Io
216.3
= −3.87 A/A
=−
Is
55.88
Rif =
1.68 k
Ri
=
= 30.1 1 + Aβ
55.88
Rof
Rof = Ro (1 + Aβ) = 2.67 × 55.88
Figure 5
= 149.2 k
(f) Rif = Rs Rin
30.1 = 10 k Rin
To determine Rout , consider the circuit in
Fig. 5. Using the formula given at the end of
Example 10.8, adapted to our case here, we get
Rin = 30.2 Rout = ro2 + [Rof Rs
Is
Iin = Is
Rs + Rin
(rπ2 + RC1 )] 1 + gm2 ro2
rπ2
rπ2 + RC1
Chapter 10–61
At ω = ω180 , the magnitude of A becomes
where
| A(jω180 )| =
75 V
= 98.7 k
0.76 mA
ro2 =
105
2 2
20, 000 2
1 + 20, 000
1+
100
20, 000
Rout = 98.7 + [149.2 (3.3 + 10)] 1 + 30.3 × 98.7 ×
3.3
3.3 + 10
| A(jω180 )|βcr = 1
Check:
βcr =
Maximum possible Rout βro 10 M
Af =
10.75 A(s) =
φ = −tan−1
105
2
s
s 1+
1+
100
20, 000
=
ω
ω
− 2 tan−1
100
20, 000
180◦ = tan−1
105
1 + 105 × 4 × 10−3
105
250 V/V
1 + 400
10.76 A(s) =
ω180
ω180
+ 2 tan−1
100
20, 000
105
2
s
s
1+
1+
100
20, 000
105
2
ω
ω
1+j
1+j
100
20, 000
ω
ω − 2 tan−1
(1)
φ(ω) = −tan−1
100
20, 000
A(jω) =
Since ω180 will be much greater than 100 rad/s,
we can assume that at ω180 , tan−1 (ω180/100 ) is
approximately 90◦ , thus
ω180
= 90◦
20, 000
⇒ tan−1
1
= 4 × 10−3 V/V
250
Correspondingly,
So, our result is reasonable.
2 tan−1
105
= 250 V/V
200 × 2
| A(jω180 )| =
= 98.7 + 12.21 × 743 = 9.17 M
| A(jω)| = ω180
= 45◦
20, 000
⇒ ω180 = 20, 000 rad/s
105
2 (2)
ω 2
ω
1+
1+
100
20, 000
Using Eqs. (1) and (2), we can obtain the data
required to construct Nyquist plots for the two
cases: β = 1 and β = 10−3 . The results are given
in the following table.
which is indeed much greater than 100 rad/s,
justifying our original assumption.
This table belongs to Problem 10.76.
ω −2 tan−1
100
−tan−1
ω
rad/s
0
0
−45
10
ω
20, 000
0
◦
2
φ
| A|
| Aβ|
β=1
0
105
105
◦
−45.6
◦
◦
−0.6
◦
◦
0.7 × 10
5
10
−84.3
−5.7
−90
104
−89.4◦
−53.1◦
−142.5◦
3
2 × 10
4
∞
◦
−89.7
◦
−90
◦
−90
◦
−180
−180
◦
−270
4
◦
| Aβ|
β = 10−3
100
0.7 × 10
5
70
10
4
10
10
800
800
0.8
250
250
0.25
0
0
0
Chapter 10–62
This figure belongs to Problem 10.76.
Im
b1
v 2 10
250
v 10 4
800
4
1
v0
Ab 105
w 45.6º
v 102
0.7
v 10 3
10 4
Re
105
Not to scale
Im
b 103
v 2 10 4
0.25
1
v 104
0.8
v 103
10
w –45.6°
v0
100
Re
v 102
70
Not to scale
Figure 1
Using these data, we obtain the two Nyquist plots
shown in Fig. 1.
We observe that the amplifier with β = 1 will be
unstable and that with β = 10−3 will be
stable.
At this frequency,
| A| = √
104
√
1 + 10.952 1 + 1.0952
= 413.6
For stable operation,
| A|βcr < 1
10.77 A(s) =
104
s
s 2
1+ 4 1+ 5
10
10
104
ω
ω 2
1+j 4 1+j 5
10
10
ω
ω −1
φ = −tan−1
−
2
tan
104
105
ω180
ω180 − 2 tan−1
−180 = −tan−1
4
10
105
A(jω) =
By trial and error we find
ω180 = 1.095 × 105 rad/s
βcr < 2.42 × 10−3
Thus, oscillation will commence for
β ≥ 2.42 × 10−3
104 k
s 3
1+ 3
10
104 k
A(jω)β(jω) =
ω 3
1+j 3
10
104 k
| A(jω)β(jω)| = 3/2
ω2
1+ 6
10
10.78 A(s)β(s) =
Chapter 10–63
ω 103
ω180
−180◦ = −3 tan−1 3
10
φ(ω) = −3 tan−1
10.81 Af (0) =
10 =
⇒ ω180 = 103 tan 60 = 1732 rad/s
104 k
| A(jω180 )β(jω180 )| = 1+
17322
106
3/2
= 0.125 × 104 k
A0
1 + A0 β
1000
1 + 1000β
⇒ β = 0.099
To obtain a maximally flat response,
Q = 0.707
Using Eq. (10.70), we obtain
100 × 1 × fP2
0.707 =
1 + fP2
For stable operation,
| A(jω180 )β(jω180 )| < 1
⇒ 0.125 × 104 k < 1
1
100 fP2
=
2
(1 + fP2 )2
−4
k < 8 × 10
2
fP2
+ 2 fP2 + 1 = 200fP2
10.79 Af (0) =
A0
1 + A0 β
2
fP2
− 198 fP2 + 1 = 0
fP2 198 kHz
where
A0 =
1 MHz
= 105 V/V
10 Hz
(the other solution is a very low frequency which
obviously does not make physical sense).
Thus,
105
10 V/V
Af (0) =
1 + 105 × 0.1
f3dB = 10(1 + A0 β)
= 10(1 + 10 × 0.1) 10 Hz
5
5
Unity-gain frequency of closed-loop amplifier
= Af (0) × f3dB
= 10 × 105 = 106 Hz = 1 MHz
Thus, the pole shifts by a factor equal to the
amount-of-feedback, (1 + A0 β).
10.80 A0 = 10 V/V
fP = 100 Hz
fHf = fP (1 + A0 β) = 10 kHz
10 × 103
= 100
⇒ 1 + A0 β =
100
99
⇒ β = 4 = 0.0099 V/V
10
A0
Af (0) =
1 + A0 β
104
= 100 V/V
=
100
Af (0)
Af (s) =
s
1+
ωHf
Af (s) =
100
1 + s/2π × 104
The 3-dB frequency of the closed-loop amplifier
is f0 , which can be obtained from Eq. (10.68) and
the graphical construction of Fig. 10.32:
f0
1
= (fP1 + fP2 )
2Q
2
1
f0 = √ (1 + 198) = 140.7 kHz
2
10.82 (a) The closed-loop poles become
coincident when Q = 0.5. Using Eq. (10.70), we
obtain
√
(1 + A0 β)ωP1 ωP2
Q=
ωP1 + ωP2
√
(1 + A0 β)ωP1 ωP2
0.5 =
ωP1 + ωP2
⇒ 1 + A0 β = 0.52
(ωP1 + ωP2 )2
ωP1 ωP2
= 0.52 ×
(2π)2 (104 + 105 )2
(2π)2 × 104 × 105
= 0.52 ×
112
= 3.025
10
β = 2.025 × 10−4
ωc =
=
1
(ωP1 + ωP2 )
2
1
× 2π(fP1 + fP2 )
2
fc =
1
× (104 + 105 ) = 5.5 × 104 Hz
2
Chapter 10–64
(b) Af (0) =
=
A0
1 + A0 β
10.83 Af = 10
104
= 3306 V/V
1 + 2.205 × 10−4 × 104
Af (s) =
A(s)
1 + A(s)β
s
1+
ωP1
s
1+
ωP1
=
1+
s
ωP2
A0
1+
s
ωP2
+ A0 β
A0
1
1
s2
(1 + A0 β) + s
+
+
ωP1
ωP2
ωP1 ωP2
Af (jω) =
(1 + A0 β) + j
Af (jωc ) =
A0
ω
ω
ω
ω
+
−
ωP1
ωP2
ωP1
ωP2
104
3.025 + j(5.5 + 0.55) − 5.5 × 0.55
104
Af (jωc ) =
j 6.05
| Af |(jωc ) =
K2
1+
A0
Af (s) = Let each stage in the cascade have a dc gain K
and a 3-dB frequency fP , thus
A(s) = where
A(s) = Maximally flat response with fsdB = f0 = 1 kHz.
104
= 1653 V/V
6.05
s
ωP
2
Using the expression for Q in Eq. (10.70), we get
√
(1 + A0 β)ωP1 ωP2
Q=
ωP1 + ωP2
√
and substituting Q = 1/ 2, ωP1 = ωP2 = ωP ,
and A0 = K 2 , we obtain
1 + K 2β
1
√ =
2
2
1 + K 2β = 2
and
K 2β = 1
Now,
Af 0 =
A0
1 + A0 β
10 =
K2
1 + K 2β
(c) Q = 0.5.
K2
2
(d) If β = 2.025 × 10−3 V/V. Using Eq. (10.68),
we obtain
=
1
s = − × 2π(104 + 105 )
2
⇒ K 2 = 20 ⇒ K =
1
± ×
2
2π (104 + 105 )2 − 4(1 + 104 × 2.025 × 10−3 ) × 104 × 105
s
= −5.5 × 104
2π
±0.5 121 × 108 − 4 × 21.25 × 109
√
= −5.5 × 104 ± 0.5 × 104 121 − 40 × 21.25
= −5.5 × 104 ± j0.5 × 104 × 27
= (−5.5 ± j13.25) × 104 Hz
Using Eq. (10.70), we obtain
(1 + 104 × 2.025 × 10−3 )104 × 105
Q=
104 + 105
= 1.325
β=
√
20 = 4.47 V/V
1
= 0.05 V/V
20
Using Eq. (10.68), we obtain
ω0
1
= (ωP1 + ωP2 )
Q
2
1
f0
√ = × 2 fP
2
1/ 2
√
√
⇒ fP = 2f0 = 2 × 1 = 1.414 kHz
Af (s) =
Af (s) =
10ω02
ω0
s2 + s
+ ω02
Q
10(2π × 103 )2
2π × 103
s2 + s
+ (2π × 103 )2
√
1/ 2
Chapter 10–65
Im
10.84 Let each stage have the transfer function
T (s) =
3
Normalized s-plane
K
1+
s
ωP
K
60°
where ωP = 2π × 100 × 103 rad/s
⎞3
⎛
⎜
A(s) = ⎝
K
1+
(1K) 1
⎟
s ⎠
ωP
S s
vP
3
K
2
0
Re
K
2
3
β=1
Thus the characteristic equation is given by
1 + A(s)β = 0
1+ K3
s
1+
ωP
Figure 1
lines with 60◦ angles to the horizontal. These two
poles reach the jω axis (which is the boundary for
stable operation) at K = 2 at which point
√
S2,3 = ±j 3
3 = 0
s
= S, where S is a
ωP
normalized frequency variable, thus
To simplify matters, let
(1 + S)3 + K 3 = 0
(1)
This equation has three roots, which are the poles
of the feedback amplifier. One of the roots will be
real and the other two can be complex conjugate
depending on the value of K. The real pole can be
directly obtained from Eq. (1) as
Thus the minimum value of K from which
oscillations occur is K = 2. Oscillations will be at
√
ω = 3 × 2π fP
or
f =
√
3 × 100 kHz
= 173.2 kHz
(1 + S1 )3 = −K 3
10.85
(1 + S1 ) = −K
S1 = −(1 + K)
(2)
Now we need to obtain the two other poles. The
characteristic equation in (1) can be written as
S 3 + 3 S 2 + 3 S + (1 + K 3 ) = 0
(3)
Equivalently it can be written as
(S + 1 + K)(S 2 + aS + b) = 0
(4)
Equating the coefficients of corresponding terms
in (3) and (4), we can find a and b and thus obtain
the quadratic factor
S 2 + (2 − K)S + (1 − K + K 2 ) = 0
(5)
This equation can now be easily solved to obtain
the pair of complex conjugate poles as
√
K
3
S2,3 = −1 + ± j
K
2
2
Figure 1 shows the root locus of the three poles in
the normalized s plane (normalized relative to
ωP = 2π × 105 ). Observe that as K increases the
real pole S1 moves outwardly on the negative real
axis. The pair of conjugate poles move on straight
A(s) = 1+
s
2π × 10
105
1+
s
2π × 103
β = 0.01
Aβ(jω) =
ω
1+j
2π × 10
1000
1+j
| Aβ| =
1+
ω
2π × 10
ω
2π × 103
1000
2 1+
ω
2π × 103
(1)
2 (2)
Figure 1 (next page) sketches the Bode plot for
| Aβ|. The unity-gain frequency will occur on the
−40 dB/decade line. The value of f1 can be
obtained from the Bode plot as follows: The −40
dB/decade line represents gain drop proportional
to 103 /f 2 . For a drop by only 20 dB (a factor of
10) the change in frequency is
1
103
=
10
f12
√
f1 = 10 × 103 Hz = 3.16 × 103 Hz
Chapter 10–66
40
20 dB/decade
20
0
1
b 0.001
10
102 103
f1
f (Hz)
40 dB/decade
Figure 2
Figure 1
10.86 A0 = 105 with a single pole at
fP = 10 Hz
For a unity-gain buffer, β = 1, thus
However, the Bode plot results are usually
approximate. If we require a more exact value for
f1 we need to iterate a couple of times using the
exact equation in (2). The result is
f1 = 3.085 × 103 Hz
The phase angle can now be obtained using (1) as
follows:
ω1
ω1
φ = −tan−1
− tan−1
2π × 10
2π × 103
= −tan−1
A0 β = 105 and fP = 10 Hz
Since the loop gain rolls off at a uniform slope of
−20 dB/decade, it will reach the 0 dB line
(| Aβ| = 1) five decades beyond 10 Hz. Thus the
unity-gain frequency will be
f1 = 105 × 10 = 106 Hz = 1 MHz
The phase shift will be that resulting from a single
pole, −90◦ , resulting in a phase margin:
Phase margin = 180◦ − 90◦ = 90◦
f1
f1
− tan−1 3
10
10
= −tan−1 (3.085 × 102 ) − tan−1 (3.085)
10.87 Using Eq. (10.82), we obtain
= −89.81◦ − 72.03◦ = −161.84
| Af (jω1 )| =
Thus,
where
Phase margin = 180◦ − 161.84 = 18.15◦
θ = 180◦ − φ
To obtain a phase margin of 45◦ :
The phase shift due to the first pole will be 90◦ .
Thus, the phase shift due to the second pole must
be −45◦ , thus
◦
−45 = −tan
−1
f1
103
f1 103 rad/s.
Since f1 is two decades above fP we need A0 β to
be 100. Thus, β will now be
β = 100/105 = 10−3
Figure 2 shows a sketch of the Bode plot for | Aβ|
in this case.
1/β
|1 + e−jθ |
φ ≡ Phase margin
Peaking, P ≡
| Af (jω)|
1/β
Thus,
P = 1/|1 + e−jθ |
= 1/|1 + cos θ − j sin θ|
= 1/ (1 + cos θ)2 + sin2 θ
√
= 1/ 2 + 2 cos θ
= 1/ 2 + 2 cos(180◦ − φ)
P = 1/ 2(1 − cos φ)
1
⇒ φ = cos−1 1 −
2P 2
Chapter 10–67
At this frequency, | A| is 70 dB. The β horizontal
straight line drawn at 70-dB level gives
1
20 log
= 70 dB
β
We use this equation to obtain the following
results:
P
φ
1.05
56.9◦
⇒ β = 3.16 × 10−4
1.10
54.1◦
Correspondingly,
◦
0.1 dB ≡ 1.0115 59.2
1.0 dB ≡ 1.122
52.9◦
3 dB ≡ 1.414
41.4◦
Af =
104
= 2.4 × 103 V/V
1 + 104 × 3.16 × 10−4
or 67.6 dB
10.89 Figure 1, on the next page, is a replica of
Fig. 10.37 except here we locate on the phase plot
the points at which the phase margin is 90◦ and
135◦ , respectively. Drawing a vertical line from
each of those points and locating the intersection
with the | A| line enables us to determine the
maximum β
10.88 Figure 1 below shows magnitude and
phase Bode plots for the amplifier specified in this
problem. From the phase plot we find that
θ = −135◦ (which corresponds to a phase margin
of 45◦ ) occurs at
f = 3.16 × 105 Hz
This figure belongs to Problem 10.88.
80
20 dB/decade
20 log(1/b) 70 dB
20 log
70
40 dB/decade
60
50
40
60 dB/decade
30
20
10
0
°
0
105 3.16 105 106
fP1
fP2
fP3
104
Pole fP1 Pole fP2 Pole fP3
105 3.16 105 106
104
45°
90°
135°
180°
Total phase
225°
270°
Figure 1
107
f, Hz
107
f, Hz
Chapter 10–68
This figure belongs to Problem 10.89.
dB
20 dB/decade
100
90
20 log
X1
20 log 1/b 85 dB (stable)
80
45º PM
25 dB gain margin
70
60
20 log 1/b
for zero margins
50
40
90º PM
(a)
40 dB/decade
X2
(b)
20 log 1/b 50 dB (unstable)
30
60 dB/decade
20
f180º
10
0
10
102
10
102
103
w
0
45º
90º
104
105
106
f180º
107
108
f (Hz)
104
105
106
107
108
f(Hz)
90º PM
135º
108º
72º phase margin
180º
225º
45º phase margin
270º
Figure 1
that can be used in each case. Thus, for
PM = 90◦ :
1
20 log = 90 dB
β
⇒ β = 3.16 × 10−5
10.90 Figure 1 below shows the Bode plot for the
amplifier gain and for a differentiator. Observe
that following the rate-of-closure rule the
intersection of the two graphs is arranged so
that the maximum difference in slopes is 20
dB/decade.
and the corresponding closed-loop gain is
Af =
A0
105
=
1 + A0 β
1 + 105 × 3.16 × 10−5
dB
= 2.4 × 104 V/Vor 87.6 dB
and for PM = 45◦ , we have
1
20 log = 80 dB
β
⇒ β = 10−4 V/V
= 9.09 × 103 V/V
or 79.2 dB
40 dB/
decade
20 dB/decade 40
Bode plot
for differentiator
20
and the corresponding closed-loop gain is
A0
105
=
Af =
1 + A0 β
1 + 105 × 10−4
20 dB/decade
60
0.001
0.01
0
0.1
1
1
2pCR
Figure 1
10
100
f (MHz)
Chapter 10–69
Thus, to guarantee stability,
10.94 The fourth, dominant pole must be at
1
≤ 0.001 MHz or 1 kHz
2πCR
1
= 0.159 ms
⇒ CR ≥
2π × 103
fD =
=
fP1
A0
106
= 10 Hz
105
R 1 M
10.91 The new pole must be placed at
1 MHz
= 100 Hz
104
In this way the modified open-loop gain will
decrease at the uniform rate of −20 dB/decade,
thus reaching 0 dB in four decades, that is at 1
MHz where the original pole exists. At 1 MHz,
the slope changes to −40 dB/decade, but our
amplifier will be guaranteed to be stable with a
closed-loop gain at low as unity.
C
fD =
10.92 We must move the 1 MHz pole to a new
location,
20 MHz
= 2 kHz
104
This reduction in frequency by a factor of
1 MHz
= 500 will require that the total
2 kHz
capacitance at the controlling node must become
500 times what it originally was.
fD =
1 M
Figure 1
Refer to Fig. 1.
fD =
1
2πRC
10 =
1
2π × 1 × 106 × C
⇒ C = 15.9 nF
10.95 fP1 =
105 =
20 log
1
= 60 dB
β
A horizontal line at the 60-dB level will intersect
the vertical line at fP2 = 106 Hz at a point Z1 .
Drawing a line with a slope of −20 dB/decade
from Z1 will intersect the 100-dB horizontal line
at a frequency two decade lower than fP2 , thus the
frequency to which the 1st pole must be moved is
fD =
106
fP2
=
= 10 kHz
100
100
(b) For β = 0.1,
20 log
1
= 20 dB
β
Following a process similar to that for (a) above,
the first pole must be lowered to
fD =
106
= 100 kHz
104
1
2π × 150 × 10−12 × R1
⇒ R1 = 10.61 k
fP2 =
1
2πC2 R2
106 =
1
2π × 5 × 10−12 × R2
10.93 Refer to Fig. 10.38.
(a) For β = 0.001,
1
2πC1 R1
⇒ R2 = 31.83 k
First, we determine an approximate value of fP2
from Eq. (10.94)
fP2 =
gm Cf
2π[C1 C2 + Cf (C1 + C2 )]
Assume that Cf C2 , then
fP2 =
gm
2π(C1 + C2 )
40 × 10−3
2π(150 + 5) × 10−12
= 41.1 MHz
which is much greater than fP3 . Thus, we use fP3
to determine the new location of fP1 ,
2 × 106
= 200 Hz
104
Using Eq. (10.93), we obtain
fP1 =
fP1 =
1
2πgm R2 Cf R1
Chapter 10–70
200 =
A(s)β(s) = −
⇒ Cf = 58.9 pF
= A(s)
Since Cf is indeed much greater than C2 , the pole
at the output will have the frequency already
calculated:
A(s)β(s) =
1
2π × 40 × 10−3 × 31.83 × 103 × Cf × 10.61 × 103
fP2 41.1 MHz
1/sC
R + 1/sC
105
1
s 1 + sCR
1+
10
CR = 0.01 × 10−6 × 100 × 103 = 10−3 s
10.96
A(s)β(s) =
Rs 100 k
A (s)
Vt
Vr
Vt
(a) Bode plots for the magnitude and phase of Aβ
are shown in Fig. 2. From the magnitude plot we
find the frequency f1 at which | Aβ| = 1 is
R 100 k
Vr
105
s s 1+ 3
1+
10
10
f1 = 3.16 × 104 Hz
C 0.01 F
(b) From the phase plot we see that the phase at
f1 is 180◦ and thus the phase margin is zero. A
more exact value for the phase margin can be
obtained as follows:
Figure 1
This figure belongs to Problem 10.96, part (a).
100
20 dB/decade
80
40 dB/decade
60
40
f1 3.16
20
0
1
10
fP1
100
1000
fP2
10,000
f (Hz)
100,000
0º
45º
f (Hz)
Phase of
fP1
90º
135º
104 Hz
Total phase
180º
Figure 2
Phase of fP2
Chapter 10–71
θ (f1 ) = −tan−1
3.16 × 104
3.16 × 104
− tan−1
10
103
s = (−0.505 ± j31.62) × 103 rad/s
The poles and zero are shown in Fig. 3.
= −89.98 − 88.19 = −178.2
Thus the phase margin is 1.8◦ .
(c) Af (s) =
A(s)
1 + A(s)β(s)
105 / 1 +
=
1+
s 10
105
s s 1+ 3
1+
10
10
s 105 1 + 3
10
=
s s 105 + 1 +
1+ 3
10
10
s 1+ 3
10
=
1 + 10−5 (1 + 0.101s + 0.0001s2 )
At s = 0,
Figure 3
The pair of complex-conjugate poles have
ω0 31.62 krad/s
Q = 31.3
Thus, the response is very peaky, as shown
in Fig. 4.
Af 1
Af
1000
The transmission zero is
1000
2
1.01 krad/s
sZ = −103 rad/s
The poles are the roots of
10−9 s2 + 1.01 × 10−6 s + 1 = 0
which are
1
0
v0 31.62 krad/s
Figure 4
v
krad/s
Exercise 11–1
Ex: 11.1 To allow for v O to reach
−VCC + VCEsat = −15 + 0.2 = −14.8 V, with Q1
just cutting off (i.e. iE1 = 0),
vo
RL
1
=
=
= 0.995 V/V
vi
RL + re1
1 + 0.0052
At v O = 0 V,
14.8
14.8 V
= 14.8 mA
=
I=
RL
1 k
iE1 = 14.8 mA
The value of R can now be found from
VCC − VD
VR
=
I=
R
R
15 − 0.7
14.8 =
R
14.3
= 0.97 k
⇒R=
14.8
The resulting output signal swing will be −14.8 V
to +14.8 V. The minimum current in Q1 = 0. The
maximum current in
Q1 = 14.8 + 14.8 = 29.6 mA
re1 =
25 mV
= 1.7 14.8 mA
RL
1
vo
=
= 0.998 V/V
=
vi
RL + re1
1 + 0.0017
At v O = +10 V,
iE1 = 24.8 mA
re1 =
25 mV
= 1.0 24.8 mA
RL
1
vo
=
=
= 0.999 V/V
vi
RL + re1
1 + 0.001
Ex: 11.2 At v O = −10 V, we have
Ex: 11.3 −10
= −10 mA
1
iE1 = I + iL = 14.8 − 10 = 4.8 mA
4.8
v BE1 = 0.6 + 0.025 ln
1
a. PL =
iL =
= 0.64 V
v I = v O + v BE1
= −10 + 0.64 = −9.36 V
At v O = 0 V, we have
iL = 0 mA
iE1 = I = 14.8 mA
14.8
v BE1 = 0.6 + 0.025 ln
1
= 0.67 V
v I = v O + v BE1
= 0 + 0.67 = 0.67 V
10
= 10 mA
1
iE1 = I + iL = 14.8 + 10 = 24.8 mA
24.8
v BE1 = 0.6 + 0.025 ln
1
RL
=
√ 2
8/ 2
100
=2W
Efficiency η =
=
PL
× 100
PS
0.32
× 100
2
= 16%
Ex: 11.4 (a) PL =
=
1 Vˆo2
2 RL
1 (4.5)2
= 2.53 W
2 4
(b) PS+ = PS− = VCC ×
=6×
1 Vˆo
π RL
1
4.5
×
= 2.15 W
π
4
(c) η =
2.53
PL
× 100
× 100 =
PS
2 × 2.15
= 59%
(d) Peak input currents =
1 Vˆo
β + 1 RL
v I = v O + v BE1
1
4.5
×
51
4
= 22.1 mA
= 10 + 0.68 = 10.68 V
(e) Using Eq. (11.22), we obtain
= 0.68 V
At v O = −10 V, we have
iE1 = 4.8 mA
re1 =
25 mV
= 5.2 4.8 mA
= 0.32 W
PS = 2VCC × I = 2 × 10 × 100 × 10−3
At v O = 10 V
iL =
√ 2
V̂o / 2
=
PDN max = PDPmax =
=
2
VCC
π 2 RL
62
= 0.91 W
π2 × 4
Exercise 11–2
VT
25
= 0.25 =
iN + iP
100.04 + 0.04
Ex: 11.5 (a) The quiescent power dissipated in
each transistor = IQ × VCC
Rout =
Total power dissipated in the two transistors
RL
vo
=
1
vi
RL + Rout
= 2IQ × VCC
= 60 mW
1 − 0.94
× 100 = 6%
1
For IQ = 10 mA, change is 1.2%
(b) IQ is increased to 10 mA
For IQ = 2 mA, change is 6%
At v O = 0, we have iN = iP = 10 mA
(c) The quiesent power dissipated in each
transistor = IQ × VCC
= 2 × 2 × 10−3 × 15
From Eq. (11.31), we obtain
Rout
VT
25
= 1.25 =
=
iP + iN
10 + 10
RL
100
vo
=
=
vi
RL + Rout
100 + 1.25
vo
= 0.988 at v O = 0 V
vi
At v O = 10 V, we have
10 V
= 0.1 A = 100 mA
100 Use Eq. (11.27) to calculate iN :
iL =
iN2 − iN iL − IQ2 = 0
% Change =
Total power dissipated = 2 × 10 × 10−3 × 15
= 300 mW
Ex: 11.6 From Example 11.4, we have VCC = 15
V,
RL = 100 QN and QP matched and IS = 10−13 A and
β = 50, IBias = 3 mA
10
= 0.1 A
100
As a first approximation, iN 0.1 A,
For v O = 10 V, we have iL =
0.1 A
2 mA
50 + 1
iN2 − 100 iN − 102 = 0
iP = 0, iBN ⇒ iN = 101.0 mA
iD = IBias − iBN = 3 − 2 = 1 mA
⎛
⎞
Using Eq. (11.26), we obtain
iP =
IQ2
iN
Rout =
1 mA
VT
25
0.2451 =
iN + iP
101.0 + 1
RL
100
vo
=
=
1
vi
RL + Rout
100 + 0.2451
−3
⎜ 10
⎟
(1)
VBB = 2VT ln⎝
⎠
1
−13
× 10
3
1
1
This is because biasing diodes have area of
3
3
the output devices.
⫹VCC
1 − 0.988
× 100 = 1.2%
1
In Example 11.3, IQ = 2 mA, and for v O = 0
% change =
Rout
IBias
VT
25
= 6.25 =
=
iN + iP
2+2
QN
RL
100
vo
= 0.94
=
=
vi
RL + Rout
100 + 6.25
iD
iN
v O = 10 V
10 V
= 100 mA
iL =
100 Again calculate iN (for IQ = 2 mA) using
Eq. (11.27) (iN = 100.04 mA):
iP =
IQ2
IN
=
vO
iP
vI
Qp
22
= 0.04 mA
100.04
⫺VCC
iL
RL
Exercise 11–3
But VBB = VBEN + VBEP
iN
i N − iL
= VT ln
+ VT ln
IS
IS
iN (iN − iL )
= V T ln
IS2
Expressing currents in mA, we have
iP (iP − 100) = 81
iP2 − 100 iP − 81 = 0
(2)
⇒ iP = 100.8 mA
iN = iP + iL = 0.8 mA
Equating Eqs. 1 and 2, we obtain
⎛
⎞
−3
iN (iN − iL )
⎜ 10
⎟
2VT ln⎝
⎠ = VT ln
1
IS2
× 10−13
3
⎛
⎞2
Ex: 11.7 IC = gm × 2 mV/◦ C × 5 ◦ C, mA
where gm is in mA / mV
10 mA
= 0.4 mA/mV
25 mV
Thus, IC = 0.4 × 2 × 5 = 4 mA
gm =
−3
iN (iN − 0.1)
⎜ 10
⎟
⎝1
⎠ = −13 2
10
× 10−13
3
iN (iN − 0.1) = 9 × 10−6
If iN is in mA, then
Ex: 11.8 Refer to Fig. 11.15.
iN (iN − 100) = 9
iN2 − 100 iN − 9 = 0
(a) To obtain a terminal voltage of 1.2 V, and
since β 1 is very large, it follows that
VR1 = VR2 = 0.6 V.
⇒ iN = 100.1 mA
Thus IC1 = 1 mA
iP = iN − iL = 0.1 mA
For v O = −10 V and iL =
IR =
−10
= −0.1 A
100
Thus, I = IC1 + IR = 1.5 mA
= −100 mA:
As a first approximation assume iP ∼
= 100 mA,
iN 0. Since iN = 0, current through diodes
= 3 mA
⎛
⎞
−3
⎜ 3 × 10 ⎟
∴ VBB = 2VT ln⎝
⎠
1
× 10−13
3
iN
iP
+ VT ln
But VBB = VT ln
−13
−13
10
10
i P + iL
iP
+ VT ln
= V T ln
−13
10
10−13
Here iL = −0.1 A
Equating Eqs. (3) and (4), we obtain
⎛
⎞
−3
⎜ 3 × 10 ⎟
2VT ln⎝
⎠=
1
× 10−13
3
iP − 0.1
iP
ln
+
V
VT ln
T
10−13
10−13
⎛
⎞2
−3
iP (iP − 0.1)
⎜ 3 × 10 ⎟
⎝1
⎠ = −13 2
10
× 10−13
3
iP (iP − 0.1) = 81 × 10−6
1.2 V
1.2
= 0.5 mA
=
R1 + R2
2.4
(b) For VBB = +50 mV:
VBB = 1.25 V IR =
VBE =
(3)
1.25
= 0.52 mA
2.4
1.25
= 0.625 V
2
IC1 = 1 × eVBE /VT = e0.025/0.025
= 2.72 mA
I = 2.72 + 0.52 = 3.24 mA
For VBB = +100 mV, we have
(4)
VBB = 1.3 V,
VBE =
IR =
1.3
= 0.54 mA
2.4
1.3
= 0.65 V
2
IC1 = 1 × eVBE /VT = 1 × e0.05/0.025
= 7.39 mA
I = 7.39 + 0.54 = 7.93 mA
For VBB = +200 mV:
VBB = 1.4 V,
IR =
1.4
= 0.58 mA
2.4
VBE = 0.7 V
IC1 = 1 × e0.1/0.025 = 54.60 mA
I = 54.60 + 0.58 = 55.18 mA
Exercise 11–4
At this current, |VBE | is given by
2.86 × 10−3
|VBE | = 0.025 ln
0.63 V
−14
3.3 × 10
For VBB = −50 mV:
VBB = 1.15 V,
IR =
1.15
= 0.48 mA
2.4
1.15
2
= 0.575
Thus VE1 = 0.63 V and I1 = 2.87 mA
IC1 = 1 × e−0.025/0.025 = 0.37 mA
iC1 = iC2 = iC3 = iC4 2.87 mA
I = 0.48 + 0.37 = 0.85 mA
(b) For v I = +10 V:
For VBB = −100 mV:
To start the iterations, let VBE1 0.7 V
VBE =
No more iterations are required and
VBB = 1.1 V
IR =
Thus,
1.1
= 0.46 mA
2.4
VE1 = 10.7 V
VBE = 0.55 V
and
IC1 = 1 × e−0.05/0.025 = 0.13 mA
I1 =
I = 0.46 + 0.13 = 0.59 mA
15 − 10.7
= 0.86 mA
5
For VBB = −200 mV:
VBB = 1.0 V IR =
⫹15 V
1
= 0.417 mA
2.4
VBE = 0.5 V
IC1 = 1 × e
5 k⍀
I1
−0.1/0.025
= 0.018 mA
Q3
I = 0.43 mA
Q1
Ex: 11.9 (a) From symmetry we see that all
transistors will conduct equal currents and have
equal VBE ’s. Thus,
⫹10 V
vO
Q2
vO = 0 V
Q4
⫹15 V
I2
I1
5 k⍀
5 k⍀
VE1
⫺15 V
Q3
Q1
Neglecting IB3 , we obtain
vO
0V
Q2
Q4
5 k⍀
IC1 IE1 I1 = 0.86 mA
But at this current
IC1
|VBE1 | = VT ln
IS
0.86 × 10−3
= 0.025 ln
3.3 × 10−14
= 0.6 V
⫺15 V
Thus, VE1 = +10.6 V and I1 = 0.88 mA. No
further iterations are required and IC1 0.88 mA.
If VBE 0.7 V, then
To find IC2 , we use an identical procedure:
15 − 0.7
= 2.86 mA
VE1 = 0.7 V and I1 =
5
If we neglect IB3 , then
VBE2 0.7 V
IC1 2.86 mA
I2 =
VE2 = 10 − 0.7 = +9.3 V
9.3 − (−15)
= 4.86 mA
5
Exercise 11–5
VBE2 = 0.025 ln
4.86 × 10−3
3.3 × 10−14
I1 =
15 − 10.6
= 0.88 mA
5
= 0.643 V
IE1 = I1 − IB3 = 0.88 − 0.5 = 0.38 mA
VE2 = 10 − .643 = +9.357
IC1 0.38 mA
I2 = 4.87 mA
|VBE1 | = 0.025 ln
IC2 4.87 mA
0.38 × 10−3
3.3 × 10−14
= 0.58 V
Finally,
VE1 = 10.58 V
IC3 = IC4 = 3.3 × 10−14 eVBE /VT
I1 =
where
VE1 − VE2
= 0.62 V
2
Thus, IC3 = IC4 = 1.95 mA
VBE =
15 − 10.58
= 0.88 mA
5
Thus, IC1 0.38 mA
Now for Q2 we have
The symmetry of the circuit enables us to find the
values for v I = −10 V as follows:
IC1 = 4.87 mA IC2 = 0.88 mA
VBE2 = 0.643 V
VE2 = 10 − 0.643 = 9.357
I2 = 4.87 mA
IC3 = IC4 = 1.95 mA
IB4 0
For v I = +10 V, we have v O = VE1 − VBE3
IC2 4.87 mA (as in (b))
= 10.6 − 0.62 = +9.98 V
Assuming that IC3 100 mA, we have
100 × 10−3
VBE3 = 0.025 ln
3.3 × 10−14
For v I = −10 V, we have v O = VE1 − VBE3
= −9.357 − 0.62 = −9.98 V
(c) For v I = +10 V, we have
= 0.72 V
v O 10 V
IL 100 mA
Thus, v O = VE1 − VBE3
IC3 100 mA
= 10.58 − 0.72 = +9.86 V
IB3 =
100
0.5 mA
201
|VBE4 | = v O − VE2
9.86 − 9.36 = 0.5 V
Thus, IC4 = 3.3 × 10−14 e0.5/0.025
5 k⍀
I1
0.02 mA
Q3
Q1
From symmetry we find the values for the case
IB3
v I = −10 V as:
vI
IL
Q2
vO
100 k⍀
IC1 = 4.87 mA,
IC2 = 0.38 mA
IC3 = 0.02 mA,
IC4 = 100 mA
v O = −9.86 V.
Q4
I2
5 k⍀
Ex: 11.10 For Q1 :
iC1 = ISP ev EB /VT
Assuming that |VBE1 | has not changed much from
0.6 V, then
iC
= ISP ev EB /VT
βN + 1
VE1 10.6 V
iC β N ISP ev EB /VT
Exercise 11–6
Thus, effective scale current = β N ISP
(b) Effective current gain ≡
iC
= βPβN
iB
= 20 × 50 = 1000
100 × 10−3 = 50 × 10−14 ev EB /0.025
v EB = 0.025 ln 2 × 1011
= 0.651 V
Ex: 11.11 See Figure 11.21
When VBE5 = 150 × 10−3 × RE1 , then ICS = IBias
= 2 mA
VBE5 = VT ln
= 25 × 10−3
IC5
IS
2 × 10−3
ln
10−14
= 0.651 V
1 W
kn
(VGS − Vtn )2
2
L 1
1
W
0.2 = × 0.250
(0.2)2
2
L 1
W
⇒
= 40
L 1
1
W
Q2 : IBias = k P
(VGS − |Vt |)2
2
L 2
1
W
0.2 = × 0.100 ×
× (0.2)2
2
L 2
W
⇒
= 100
L 2
1
W
QN : IQ = k n
(VGS − Vt )2
2
L N
1
W
1 = × 0.250 ×
0.22
2
L n
W
⇒
= 200
L n
1
W
QP : IQ = k p
(VGS − |Vt |)2
2
L p
W
1
1 = × 0.100 ×
× 0.22
2
L p
W
= 500
L p
Q1 : IBias =
Now VGG = VGS1 + VGS2
= (Vov1 + Vt ) + (Vov2 + |Vt |)
= (0.2 + 0.5) + (0.2 + 0.5)
= 1.4 V
150 × 10−3 RE1 = 0.651
RE1 = 4.34 If peak output current = 100 mA
VBE5 = RE1 × 100 mA = 4.34 × 100 × 10−3
Ex: 11.13 IN = iLmax = 10 mA
W
1
V2
∴ 10 = k n
2
L n OV
1
2
× 0.250 × 200 × VOV
2
⇒ VOV = 0.63 V
10 =
= 0.434 V
iC5 = IS eVBE5 /VT
−3
= 10−14 e0.434/25×10
Using equation 11.46, we obtain
0.35 μA
v Omax = VDD − VOV |Bias − Vtn − VOVN
= 2.5 − 0.2 − 0.5 − 0.63
Ex: 11.12 Using Eq. (11.43), we obtain
IQ = IBias
1 = 0.2
(W/L)n
(W/L)1
(W/L)n
(W/L)P
(W/L)n
=5
(W/L)1
= 1.17 V
Ex: 11.14 New values of W/L are
2000
W
=
= 1000
L P
2
W
800
= 400
=
L N
2
Exercise 11–7
1 W
V2
kp
2
L P OV
Gain error
0.14
VOV
=−
=−
4μI Q RL
4 × 10 × 1 × 10−3 × 100
Ex: 11.16 From Fig. 11.31 we see that for
Pdissipation to be less than 2.9 W, a maximum supply
voltage of 20V is called for. The 20-V-supply
curve intersects the 3% distoration line at a point
for which the output power is 4.2 W. Since
√ 2
Vˆo / 2
PL =
RL
√
we have Vˆo = 4.2 × 2 × 8 = 8.2 V
= −0.035
or 16.4 V peak-to-peak
IQ =
1
2
× 0.1 × 10−3 × 1000 × VOV
2
= 0.14 V
1 × 10−3 =
⇒ VOV
Gain error = −0.035 × 100 = −3.5%
gmn = gmp =
2IQ
2 × 1 × 10−3
=
VOV
0.14
Ex: 11.17 Voltage gain = 2 K
where K =
= 14.14 mA/V
Rout =
R2
R4
=1+
= 1.5
R3
R1
Thus, Av = 3 V/V
1
μ gmp + gmn
Input resistance = R3 = 10 k
1
=
10 × (14.14 + 14.14) × 10−3
Peak-to-Peak v o = 3 × 20 = 60 V
3.5 Peak load current =
2v i
vo
Ex: 11.15 Total current into node B =
+
R3
R2
Thus
vo
vo
2v i
+
R=−
R3
R2
A
R
1
2R
+
= − vi
⇒ vo
A R2
R3
PL =
√ 2
30/ 2
8
30 V
= 3.75 A
8
= 56.25 W
Ex: 11.18 See Fig. 1.
2R
−
vo
R3
=
1
R
vi
+
A R2
=
−2R2 /R3
1 + (R2 /AR)
Q.E.D.
Q4
B
vi
vo
R3 ⫹ R2
Q6
For AR
⫺A
vi
R3
⫺
vo
vo
A
R2 , we have
2R2
vo
−
vi
R3
Figure 1 continued
Exercise 11–8
Ex: 11.19
fs = 10 × highest frequency in audio signal
= 10 × 20 = 200 kHz
Since fs is a decade higher than fP , the gain will
have fallen by 40 dB. Thus the PWM component
at fs will be attenuated by 40 dB.
Ex: 11.20 Maximum peak amplitude = VDD
√
(VDD / 2)2
Maximum power delivered to RL =
RL
=
2
VDD
2RL
For VDD = 35 V and RL = 8 :
Peak amplitude = 35 V
Maximum power =
352
= 76.6 W
2×8
Power delivered by power supplies
=
76.6
PL
=
= 85.1 W
η
0.9
Ex: 11.21 TJ − TA = θ JA PD
200 − 25 = θ JA × 50
175
= 3.5◦ C/W
50
But, θ JA = θ JC + θ CS + θ SA
θ JA =
3.5 = 1.4 + 0.6 + θ SA
⇒ θ SA = 1.5◦ C/W
TJ − TC = θ JC × PD
TC = TJ − uJC × PD
= 200 − 1.4 × 50
Figure 1
= 130◦ C
Chapter 11–1
0 − (−VCC ) − VD
R
10 − 0.7
=
= 9.3 mA
1
Upper limit on v O = VCC − VCEsat
11.1 I =
I=
1
W
μn Cox
(VGS − Vt )2
2
L
But
VGS = 2.5 − IR = 2.5 − I
= 10 − 0.3 = 9.7 V
Thus
Corresponding input = 9.7 + 0.7 = 10.4 V
I=
Lower limit on v O = −IRL = −9.3 × 1
= −9.3 V
Corresponding input = −9.3 + 0.7 = −8.6 V
If the EBJ area of Q3 is twice as large as that of
Q2 , then
=
W
1
μn Cox
(2.5 − I − Vt )2
2
L
1
× 20(2.5 − I − 0.5)2
2
I = 10(2 − I )2
⇒ I 2 − 4.1I + 4 = 0
I = 1.6 mA and VGS = 0.9 V
1
× 9.3 = 4.65 mA
2
There will be no change in v Omax and in the
corresponding value of v I . However, v Omin will
now become
The upper limit on v O is determined by Q1
leaving the saturation region (and entering the
triode region). This occurs when v I exceeds VDD
by Vt volts:
v Omin = −IRL
v I max = 2.5 + 0.5 = 3 V
I=
= −4.65 × 1 = −4.65 V
and the corresponding value of v I will be
To obtain the corresponding value of v O , we must
find the corresponding value of VGS1 , as follows:
v I = −4.65 + 0.7 = −3.95 V
v O = v I − VGS1
If the EBJ area of Q3 is made half as big as that of
Q2 , then
iL =
I = 4 × 9.3 = 18.6 mA
iL = 3 − VGS1
There will be no change in v Omax and in the
corresponding value of v I . However, v Omin will
now become
iD1 = iL + I = 3 − VGS1 + 1.6
= 4.6 − VGS1
v Omin = −VCC + VCEsat
But,
= −10 + 0.3 = −9.7 V
and the corresponding value of v I will be
v I = −9.7 + 0.7 = −9 V
11.2 First we determine the bias current I as
follows:
vO
v I − VGS1
v I − VGS1
=
=
RL
RL
1
iD1 =
1
W
μn Cox
(VGS1 − Vt )2
2
L
4.6 − VGS1 =
1
× 20(VGS1 − 0.5)2
2
2
⇒ VGS1
− 0.9VGS1 − 0.21 = 0
VGS1 = 1.09 V
v Omax = v I max − VGS1
= 3 − 1.09 = +1.91 V
The lower limit of v O is determined either by Q1
cutting off,
v O = −IRL = −1.6 × 1 = −1.6 V
or by Q2 leaving saturation,
v O = −VDD + VOV 2
where
VOV 2 = VGS2 − Vt = 0.9 − 0.5 = 0.4 V
Thus,
v O = −2.5 + 0.4 = −2.1 V
Chapter 11–2
We observe that Q1 will cut off before Q2 leaves
saturation, thus
v Omin = −1.6 V
Since we are provided with four devices, we can
minimize the total supply current by paralleling
two devices to form Q2 as shown below.
and the corresponding value of v I will be
5 V
v I min = v Omin + Vt
= −1.6 + 0.5 = −1.1 V
vI
11.3 Refer to Fig. 11.2. For a load resistance of
100 and v O ranging between –5 V and +5 V,
the maximum current through Q1 is
5
= I + 50, mA and the minimum current
0.1
5
is I −
= I − 50, mA.
0.1
For a current ratio of 15, we have
I+
I + 50
= 15
I − 50
vO
R
I
RL
Q2A
Q3
Q2B
5 V
⇒ I = 57.1 mA
9.3 V
= 163 R=
57.1 mA
The incremental voltage gain is Av =
Q1
I
rather
2
than 2I which is the value obtained in the circuit
of Fig. 11.2. Then the supply current is 4.5 mA.
The value of R is found from
4.3 V
R=
= 2.87 k
1.5 mA
In a practical design we would select a standard
value for R that results in I somewhat larger than
3 mA. Say, R = 2.7 k. In this case I = 3.2 mA.
The resulting supply current will be 3 ×
RL
RL + re1
For RL = 100 ;
At v O = +5 V, iE1 = 57.1 + 50 = 107.1 mA
25
= 0.233 107.1
100
= 0.998 V/V
Av =
100 + 0.233
re1 =
Power from negative supply = 3 × 1.6 × 5
= 24 mW.
At v O = 0 V, iE1 = 57.1 mA
25
= 0.438 57.1
100
= 0.996 V/V
Av =
100.438
At v O = −5 V, iE1 = 57.1 − 50 = 7.1 mA
re1 =
11.5 Refer to Figs. 11.2 and 11.4.
For v O being a square wave of ±VCC levels:
25
= 3.52 7.1
100
= 0.966 V/V
Av =
103.52
Thus the incremental gain changes by
0.998 − 0.966 = 0.032 or about 3% over the
range of v O .
re1 =
11.4 Refer to Fig. 11.2. With VCC = +5 V, the
upper limit on v o is 4.7 V, which is greater than
the required value of +3 V. To obtain a lower
limit of −3 V, we select I so that
IRL = 3
⇒ I = 3 mA
PD1 |average = 0. For the corresponding sine wave
1
curve [Fig. 11.4], we have PD1 |avg = VCC I .
2
Chapter 11–3
For v O being a square wave of ±VCC /2 levels:
1 V̂
V̂
=
= 0.25
4 V̂
V̂
or 25%
11.8 Refer to Figs. 11.6 and 11.7. A 10% loss in
peak amplitude is obtained when the amplitude of
the input signal is 5 V.
11.9
vO 0.7
vO
vI
vO =
iC1
1
v CE1 = VCC − VCC sin θ
2
1
1
PD1 = VCC − VCC sin θ I + I sin θ
2
2
1
= VCC I − VCC I sin2 θ
4
1
1
= VCC I − VCC I × (1 − cos 2θ )
4
2
1
7
= VCC I + VCC I cos 2θ
8
8
7
PD1 |average = VCC I
8
vO
100
For a sine-wave output of VCC /2 peak amplitude:
1
VCC sin θ
2
1
VCC
1
=I+ 2
sin θ = I + I sin θ
RL
2
QN
PD1 |average = 0.75VCC I
QP
RL
With v I sufficiently positive so that QN is
conducting, the situation shown obtains. Then,
(v I − v O ) × 100 = v O + 0.7
1
(v I − 0.007)
1.01
This relationship applies for v I ≥ 0.007.
Similarly, for v I sufficiently negative so that QP
conducts, the voltage at the output of the amplifier
becomes v O − 0.7, thus
⇒ vO =
(v I − v O ) × 100 = v O − 0.7
1
(v I + 0.007)
1.01
This relationship applies for v I ≤ −0.007.
⇒ vO =
11.6 In all cases, the average voltage across Q2 is
equal to VCC . Thus, since Q2 conducts a constant
current I, its average power dissipation is VCC I.
11.7 The minimum required value of VCC is
VCC = V̂
and the minimum required value of I is
I=
V̂
RL
From Eq. (11.10),
V̂o
1 V̂o
η=
4 IRL
VCC
The result is the transfer characteristic
Chapter 11–4
Without the feedback arrangement, the deadband
becomes ±700 mV and the slope change a little
(to nearly +1 V/V).
11.10
iD = 4 mA and RL =
Devices have |Vt | = 0.5 V
W
= 2 mA/V2
L
For RL = ∞, the current is normally zero, so
μC ox
VGS = Vt
∴ v O = v I − VGS1 = 5 − 0.5 = 4.5 V
The peak output voltage will be 4.5 V
0.5
⇒ θ = 5.74◦
sin θ =
5
Crossover interval = 4θ = 22.968
22.96
× 100
=
360
= 6.4%
2.5 V
= 625 4 mA
11.11 For VCC = 10 V and RL = 8 , the
maximum sine-wave output power occurs when
2
1 VCC
V̂o = VCC and is PLmax =
2 RL
1 100
= 6.25 W
= ×
2
8
Correspondingly,
PS+ = PS− =
1 V̂o
VCC
π RL
10
1
×
× 10 = 3.98 W
π
8
for a total supply power of
=
PS = 2 × 3.98 = 7.96 W
The power conversion efficiency η is
η=
PL
6.25
× 100 = 78.5%
× 100 =
PS
7.96
For V̂o = 5 V,
PL =
1 V̂o2
1 25
= 1.56 W
= ×
2 RL
2
8
PS+ = PS− =
1 V̂o
VCC
π RL
5
1
× × 10 = 2 W
π
8
PS = 4 W
1.56
× 100 = 39%
η=
4
Thus, the efficiency reduces to half its maximum
value.
=
For υI = 5 V, υO = 2.5 V:
∴ VGS = 5 − 2.5 = 2.5 V
iD =
=
1
W
μC ox (VGS − Vt )2
2
L
1
× 2 × (2.5 − 0.5)2
2
11.12 PL =
50 =
1 V̂o2
2 RL
1 V̂o2
2 8
⇒ V̂o = 28.3 V
Chapter 11–5
VCC = 28.3 + 4 = 32.3 → 33 V
Peak current from each supply =
Pdissipation/device =
28.3
V̂o
=
RL
8
= 3.54 A
PS+ = PS− =
1
× 3.54 × 33 = 37.2 W
π
11−η
PL = 0.772PL
2 η
1 = 0.772PL
⇒ PL = 1.3 W
=
1 52
2 RL
⇒ RL = 9.62 (i.e., ≥ 9.62 )
Thus,
PS = 2 × 37.2 = 74.4 W
η=
50
PL
= 67.2%
=
PS
74.4
Using Eq. (11.22), we obtain
PDN max = PDPmax =
2
VCC
332
= 13.8 W
= 2
2
π RL
π ×8
11.14 PL =
PS+ = PS−
PS =
11.13 VCC = 10 V
For maximum η,
V̂o = VCC = 10 V
The output voltage that results in maximum
device dissipation is given by Eq. (11.20),
V̂o =
2
VCC
π
2
× 10 = 6.37 V
π
If operation is always at full output voltage,
η = 78.5% and thus
=
Pdissipation = (1 − η) PS
1 − 0.785
PL
=
PL = 0.274PL
= (1 − η)
η
0.785
1
× 0.274PL = 0.137PL
2
For a rated device dissipation of 2 W, and using a
factor of 2 safety margin,
η=
V̂o2
RL
1 V̂o
=
VSS
2 RL
V̂o
VSS
RL
PL
Vˆ2 /RL
V̂o
= o
=
PS
VSS
V̂o VSS RL
ηmax = 1(100%) , obtained for V̂o = VSS
PLmax =
2
VSS
RL
Pdissipation = PS − PL
=
V̂o
V̂ 2
VSS − o
RL
RL
∂Pdissipation
∂ V̂o
=
= 0 for V̂o =
VSS
2V̂o
−
RL
RL
VSS
2
Correspondingly, η =
Pdissipation/device =
Pdissipation/device = 1 W
= 0.137PL
⇒ PL = 7.3 W
1 100
7.3 = ×
2
RL
⇒ RL = 6.85 (i.e. RL ≥ 6.85 )
The corresponding output power (i.e., greatest
possible output power) is 7.3 W.
1
VSS /2
= or 50%
VSS
2
11.15 VBB = 2VT ln(IQ /IS )
= 2 × 0.025 ln(10−3 /10−14 )
= 1.266 V
At v I = 0, iN = iP = IQ = 1 mA, we have
25 mV
= 25 1 mA
reP = 12.5 reN = reP =
Rout = reN
Av =
vo
RL
100
=
=
vi
RL + Rout
100 + 12.5
= 0.889 V/V
1
If operation is allowed at V̂o = VCC = 5 V,
2
At v O = 10 V, we have
π V̂o
(Eq. 11.15)
η=
4 VCC
iL =
=
1
π
× = 0.393
4
2
10
= 0.1 A = 100 mA
100
To obtain iN , we use Eq. (11.27):
iN2 − iL iN − IQ2 = 0
Chapter 11–6
iN2 − 100 iN − 1 = 0
11.17 Av =
⇒ iN = 100.01 mA
Now Av ≥ 0.97 for RL ≥ 100 iP = iN − iL = 0.01 mA
Rout
VT
=
iP + iN
25 mV
= 0.25 100 mA
RL
100
=
= 0.998 V/V
RL + Rout
100 + 0.25
Av =
∴ 0.97 =
100
100 + Rout
⇒ Rout
3
Rout = 3 =
11.16 At iL = 0, we have iN = iP = IQ and
Rout =
VBB
Thus,
100
12.5
100 +
IQ
(1)
reN =
ip
iN
iL
−
=
βN + 1 βP + 1
β +1
where β N = β P = β = 49
0
Using values of v I from the table, one can
evaluate Rin as
vI
Rin =
iI
Thus,
Rout
= 1.24 V
iI =
For iL = 50 mA, we have
50 mA and iP
25 × 10−3
VT
=
= 4.17 mA
6
6
4.17
= 2VBE = 2 0.7 + VT ln
100
11.18 The current iI can be obtained as
where IQ is in mA.
iN
VT
2IQ
IQ =
1 VT
2 IQ
RL
vo
=
=
vi
RL + Rout
RL
re
VI
and Rout =
=
RL + Rout
2
2IQ
VT
25 mV
= 0.5 =
iN
50 mA
100
vo
= 0.995 V/V
=
vi
100 + 0.5
Using the resistance reflection rule
To limit the variation to 5%, we use
v o = 0.995 − 0.05 = 0.945 V/V
v i iL =0
Rin
(β + 1)RL = 50 × 100
= 5000 For large input signal, the two values of Rin are
somewhat the same. For the small values of v I ,
the calculated value in the table is larger.
Substituting this value in Eq. (1) yields
IQ = 2.15 mA
This table belongs to Problem 11.18.
vO
(V)
+10.0
+5.0
+1.0
+0.5
+0.2
+0.1
0
–0.1
–0.2
–0.5
–1.0
–5.0
–10.0
iL
iN
(mA) (mA)
100 100.04
50
50.08
10
10.39
5
5.70
2
3.24
1
2.56
0
2
–1
1.56
–2
1.24
–5
0.70
–10
0.39
–50
0.08
–100
0.04
iP
(mA)
0.04
0.08
0.39
0.70
1.24
1.56
2
2.56
3.24
5.70
10.39
50.08
100.04
v BEN
(V)
0.691
0.673
0.634
0.619
0.605
0.599
0.593
0.587
0.581
0.567
0.552
0.513
0.495
v EBP
(V)
0.495
0.513
0.552
0.567
0.581
0.587
0.593
0.599
0.605
0.619
0.634
0.673
0.691
vi
v O /v I
(V)
(V/V)
10.1
0.99
5.08
0.98
1.041
0.96
0.526
0.95
0.212
0.94
0.106
0.94
0
–
–0.106 0.94
–0.212 0.94
–0.526 0.95
–1.041 0.96
–5.08
0.98
–10.1
0.99
Rout v o /v i
() (V/V)
0.25 1.00
0.50 1.00
2.32 0.98
4.03 0.96
5.58 0.95
6.07 0.94
6.25 0.94
6.07 0.94
5.58 0.95
4.03 0.96
2.32 0.98
0.50 1.00
0.25 1.00
iI
(mA)
2
1
0.2
0.1
0.04
0.02
0
–0.02
–0.04
–0.1
–0.2
–1
–2
Rin
()
5050
5080
5205
5260
5300
5300
5300
5300
5260
5205
5080
5050
Chapter 11–7
RL
vo
=
and
vi
RL + Rout
11.19
Largest possible positive output from 6 to 10,
i.e., 4 V
VT
VT
=
at v O = 0
iP + iN
IQ + IQ
v o =1−
v 1 v O =0
Rout =
(a)
RL
=1−
=1−
RL + Rout
VT /2IQ
RL + VT /2IQ
=
RL
VT
RL +
2IQ
=
VT /2IQ
VT
=
2RL IQ + VT
RL + VT /2IQ
If 2IQ RL
VT , then we have
VT
2IQ RL
Q.E.D.
(b) Quiescent power dissipation = 2VCC IQ = PD
× Quiescent power dissipation =
VCC
VT
× 2VCC IQ = VT ×
2IQ RL
RL
VCC
∴ PD = VT
RL
(c)
VCC
10
= 25 × 10−3 ×
(d) PD = VT
RL
100
= 2.5 mW
PD =
Largest negative output from 6 to 0, i.e., 6 V
11.21 Rout = re /2 = 8 ⇒ re = 16 IQ =
VT
25
= 1.56 mA
=
re
16
Thus, n =
1.56
= 7.8
0.2
11.22 IQ IBIAS = 1 mA, neglecting the base
current of QN . More precisely,
IQ = IBIAS −
⇒ IQ =
IQ
β +1
IBIAS
1
1+
β +1
0.98 × 1 = 0.98 mA
The largest positive output is obtained when all of
IBIAS flows into the base of QN , resulting in
v O = β N + 1 IBIAS RL
= 51 × 1 × 100 = 5.1 V
The largest possible negative output voltage is
limited by the saturation of QP to
−10 + VECsat = −10 V
To achieve a maximum positive output of 10 V
without changing IBIAS , β N must be
2.5 × 10−3
10 = β N + 1 × 1 × 10−3 × 100 0.05
0.02
0.01
PD (mW) IQ (mA)
50
125
250
2.5
6.25
12.5
⇒ β N = 99
Alternatively, if β N is held at 50, IBIAS must be
increased so that
10 = 51 × IBIAS × 10−3 × 100 ⇒ IBIAS = 1.96 mA
11.20 IQ = 1 mA
For output of –1 V, we have
1
= −10 mA
iL = −
100
Using Eq. (11.27), we obtain
iN2 − iL iN − IQ2 = 0
iN2 + 10iN − 1 = 0
iN = 0.1mA
iP = 10.1mA
10.1
= 0.06 V
1
and the input step must be –1.06 V.
Thus v EBP increases by VT ln
for which
IBIAS
= 1.92 mA
IQ =
1
1+
β +1
11.23 Figure 1(a) shows the small-signal
equivalent circuit of the class AB circuit in Fig.
11.14. Here, each of QN and QP has been replaced
with its hybrid-π model, and the small resistances
of the diodes have been neglected. As well, we
have not included ro of each of QN and QP .
The circuit in Fig. 1(a) can be simplified to that in
Fig. 1(b) where
rπ = rπN rπP
(1)
gm = gmN + gmP
(2)
Chapter 11–8
This figure belongs to Problem 11.23.
vp
vi
gmNvp
rpN
E
vp
gmPvp
rpP
vo
RL
E
(a)
ii vp /rp
vi
vp
rp rpN // rpP
gmvp
gm gmN gmP
E
vo
(
1
gm rp
)v
p
RL
(b)
Figure 1
Since gm
1
, then from (2) we obtain
re
Equations (5) and (6) can be used to obtain the
incremental (or small-signal) gain,
1
gm +
RL
vo
rπ
= 1
vi
gm +
RL + 1
rπ
1
1
1
=
+
re
reN
reP
or, equivalently,
re = reN reP
(3)
We observe that the circuit in Fig. 1(b) is the
equivalent circuit of an emitter follower with the
small-signal parameters rπ , gm , and re given in
Eqs. (1), (2), and (3). Furthermore, its β is
given by
β = gm rπ = (gmN + gmP )(rπ N rπ P )
(4)
For the circuit in Fig. 1(b), we can write
vi = vπ + vo
1
v o = gm +
v π RL
rπ
(5)
(6)
But,
gm +
1
1
=
rπ
re
Thus,
vo
RL /re
=
vi
RL /re + 1
vo
RL
=
=
vi
RL + re
RL
RL + (reN reP )
⇒
Q.E.D.
The input resistance is found as follows:
vi
vi
Rin =
=
ii
v π /rπ
(7)
Chapter 11–9
Substituting for v i from (5) together with utilizing
(7) gives
1
v π 1 + gm +
RL
rπ
Rin =
v π /rπ
= rπ + (gm rπ + 1)RL
At 77.9◦ C:
25
VT =
(273 + 77.9) = 29.9 mV
293
IQ = 3.78 × 10−11 × (1.14)57.9 e(0.6/0.0299)
= 37.6 mA
etc., etc.
= rπ + (β + 1)RL
= (β + 1)(RL + re )
11.26 (a) VBE = 0.7 V at 1 mA
β[RL + (reN reP )]
Q.E.D.
(8)
At 0.5 mA,
VBE = 0.7 + 0.025 ln
11.24 Refer to Fig. P11.24. Neglecting the small
resistances of D1 and D2 , we can write for the
voltage gain of the CE amplifier transistor Q3 ,
v c3
= −gm3 Rin
(1)
vi
where Rin is the input resistance of the class AB
circuit, given in the statement of Problem 11.23 as
β[RL + (reN reP )]
Rin
(2)
where
β = (gmN + gmP )(rπ N rπ P )
(3)
The voltage gain of the class AB circuit is given
in the statement of Problem 11.23 as
RL
vo
=
(4)
v c3
RL + (reN reP )
Now, we can combine (1), (2), and (4) to obtain
the voltage gain of the circuit in Fig. P11.24 as
RL
vo
= −gm3 β[RL + (reN reP )]
vi
RL + (reN reP )
vo
= −gm3 βRL
⇒
vi
where β is given by Eq. (3).
0.5
= 0.683 V
1
0.683
= 1.365 k
0.5
and R2 = 1.365 k
Thus, R1 =
VBB = 2VBE = 1.365 V
(b) For Ibias = 2 mA, IC increases to nearly
1.5 mA for which
1.5
= 0.710 V
VBE = 0.7 + 0.025 ln
1
0.710
= 0.52 mA is very nearly
Note that IR =
1.365
equal to the assumed value of 0.50 mA, thus no
further iterations are required.
VBB = 2VBE = 1.420 V
(c) For Ibias = 10 mA, assume that IR remains
constant at 0.5 mA, thus IC1 = 9.5 mA
and VBE = 0.7 + 0.025 ln
9.5
= 0.756 V
1
at which
0.755
= 0.554 mA
IR =
1.365
Thus,
IC1 = 10 − 0.554 = 9.45 mA
9.45
= 0.756 V
1
= 2 × 0.756 = 1.512 V
11.25 At 20◦ C, IQ = 1mA = IS e(0.6/0.025)
and VBE = 0.7 + 0.025 ln
⇒ IS (at 20◦ C) = 3.78 × 10−11 mA
Thus, VBB
◦
−11
At 70 C, IS = 3.78 × 10
(1.14)
50
= 2.64 × 10−8 mA
At 70◦ C, VT = 25
273 + 70
= 29.3 mV
273 + 20
Thus, IQ (at 70◦ C) = 2.64 × 10−8 e0.6/0.0293
= 20.7 mA
Additional current = 20.7 − 1 = 19.7 mA
Additional power = 2 × 20×19.7 =788 mW
Additional temperature rise = 10 × 0.788
= 7.9◦ C,
(d) Now for β = 100,
0.756
= 0.554 mA
1.365
9.45
= 0.648 mA
IR2 = 0.554 +
101
IC = 10 − 0.648 = 9.352 mA
IR1 =
Thus, VBE = 0.7 + 0.025 ln
VBB = 0.756 + IR2 R2
= 0.756 + 0.648 × 1.365
= 1.641 V
9.352
= 0.756 V
1
Chapter 11–10
This figure belongs to Problem 11.27.
ix
X
R2
X
R2
Q ⇒ vx
R1
R1
vp /(R1 // rp )
vp
rp
gmvp
X
X
Figure 1
11.27 Figure 1 shows the VBE multiplier together
with its small-signal equivalent circuit prepared
for determining the incremental terminal
resistance r,
vx
r≡
ix
Now,
vπ
(1)
ix = gm v π +
R1 rπ
vπ
R2
(2)
vx = vπ +
R1 rπ
Dividing (2) by (1) gives
1 + R2 /(R1 rπ )
r=
1
gm +
R1 rπ
R2 + (R1 rπ )
=
1 + gm (R1 rπ )
For R1 = R2 = 1.2 k, IC = 1 mA, and β = 100,
we have
At v I = 0 V, we have
gm = 40 mA/V
100
= 2.5 k
rπ =
40
Thus,
1.2 + (1.2 2.5)
= 60.2 r=
1 + 40(1.2 2.5)
At v I = 0 V, we have II = 0
2.87
200
II = IB2 − IB1 = 0
IB1 = IB2 =
At v I = +10 V, we have
0.88
mA = 4.4 μA
200
4.87
mA = 24.4 μA
IB2 =
200
II = IB2 − IB1 = 20 μA
IB1 =
At v I = −10 V, we have
4.87
mA = 24.4 μA
200
0.88
IB2 =
mA = 4.4 μA
200
II = IB2 − IB1 = −20 μA
IB1 =
(b) For RL = 100 :
At v I = +10 V, we have
0.38
= 1.9 μA
200
4.87
= 24.4 μA
IB2 =
200
II = IB2 − IB1 = 22.5 μA
IB1 =
11.28 (a) For RL = ∞:
At v I = –10 V, we have II = −22.5 μA
IB1
Q1
11.29 Circuit operating near v I = 0 and is fed
with a signal source having zero resistance.
The resistance looking as shown by the arrow X is
II
= R1 re1
vI
Q2
IB2
This resistance is reflected from base to the
emitter of Q3 as(R1 re1 ) /(β3 + 1).
The resistance seen by arrow Y , from the upper
half of the circuit
= R3 + re3 + (R1 re1 ) /(β3 + 1)
Chapter 11–11
A similar resistance is seen by the arrow Z and
both of these resistances (seen by arrows Y and
arrow Z) are in parallel, therefore
Rout =
1
R3 + re3 + (R1 re1 ) / β 3 + 1
2
More precisely,
IE3
+ IE1 = 1 mA
β +1
thus,
1
+1 =1
IQ
(β + 1)
⇒ IQ
0.99 mA
Input bias current is zero because IB1 = IB2 .
(b) From the equivalent half circuit, we have
2Rin = β 1 + 1 re1 + β 3 + 1 (re3 + 2RL )
re1 = re3 =
VT
25
= 25 =
IE
1
2Rin = (100 + 1)[25 + (100 + 1)(25 + 2 × 100)]
⇒ Rin = 1.15 M
Q3
vi
Q1
2Rout
vo
2RL 200 2Rin
11.30
Av =
VCC
=
1 mA
Q3
IB1
iI
200
200 + 25 +
2Rout = re3 +
VCC
vO
VCC
re1
β3 + 1
25
101
0.89 V/V
Q1
vI
vo
2RL
=
vi
2RL + re3 +
re1
β +1
25
101
= 12.6 = 25 +
Rout
RL 100 Q2
IB2
Q4
At v I = 5 V, we have
1 mA
VE1 = +5.7 V
VCC
IR1 =
(a) v I = 0 and transistors have β = 100.
vO = 0 V
IQ = IE3 = IE4 = IE1 = IE2
11.31 See figure on the next page.
1 mA
VCC − VE1
10 − 5.7
4.3
=
=
R1
R1
R1
To allow for IB3 = 10 mA if needed while
reducing IE1 by no more than half, then IR1 must
be 2 × 10 = 20 mA. Thus,
R1 =
VR1
4.3
=
= 0.215 k = 215 IR1
20
Chapter 11–12
25 mV
= 1.25 20 mA
1
215 1.25
=
0.75 + 0.625 +
2
51
re1 =
Rout
Rout = 0.7 Next, consider the situation when
v I = +1 V and RL = 2 Let v O
1 V, then
1V
= 0.5 A = 500 mA
2
Now if we assume that iE4 0, then
iL =
iE3 = iL = 500 mA
VBE3 = 0.7 + 0.025 ln
500
30
Similarly,
= 0.770 V
500
10 mA
iB3 =
51
Assuming that VEB1 0.7 V, then
R2 = 0.215 k = 215 v E1 = 1 + 0.7 = 1.7 V
Next, we determine the values of R3 and R4 : At
v I = 0, assume VEB1 = 0.7. Then
iR1 =
VE1 = 0.7 V
iE1
10 − 1.7
= 38.6 mA
0.215
= iR1 − iB2 = 38.6 − 10 = 28.6 mA
VEB1 = 0.7 + 0.025 ln
10 − 0.7
= 43.3 mA
IR1 =
0.215
43.3
VEB1 = 0.7 + 0.025 × ln
10
= 0.726 V
= 0.737 V
iL =
VE1 = 1.726 V
VE1 = 0.737 V
Meanwhile Q3 will be conducting IQ = 40 mA.
Since IS3 = 3IS1 then Q3 has VBE = 0.7 V at
IC = 30 mA. At 40 mA,
40
VBE3 = 0.7 + 0.025 × ln
30
= 0.707 V
For v O = 0,
VE1 − VBE3 − IE3 R3 = 0
0.737 − 0.707 − 40R3 = 0
⇒ R3 = 0.75 Similarly,
R4 = 0.75 1
R1 re1
R3 + re3 +
Rout =
2
β3 + 1
where
re3 =
25 mV
= 0.625 40 mA
28.6
10
=
VE1 − VBE3
R3 + RL
1.726 − 0.770
0.75 + 2
= 0.348 A
v O = iL RL
= 0.348 × 2 = 0.695 V
Let’s check that iE4 is zero. The voltage at the
base of Q4 is
VB4 = 1 − VBE2
1 − 0.74 = 0.26 V
The voltage across R4 and VEB4 is
= v O − 0.26 = 0.695 − 0.26 = 0.435 V
which is sufficiently small to keep Q4 cutoff,
verifying our assumption that iE4 0.
Let’s now do more iterations to refine our
estimate of v O :
iL = 0.35 A
Chapter 11–13
0.35
7 mA
51
10 − 1 − 0.726
− 7 = 31.5 mA
iE1 =
0.215
31.5
VEB1 = 0.7 + 0.025 ln
10
(a) For the composite transistor, we have
iB3 =
β=
Refer to the diagram.
IB =
= 0.729 V
IC =
VE1 = 1 + 0.729 = 1.729 V
iE3 = iL = 350 mA
VBE3
350
= 0.7 + 0.025 ln
30
=
1
IE
β1 + 1 β2 + 1
β1
β2
IE +
IE
β1 + 1 β2 + 1
β2 + 1
β1 + β2 β1 + 1
β1 + 1 β2 + 1
· IE
For the composite transistor, β is given by
= 0.761 V
VE1 − VBE3
iL =
R3 + R2
=
IC
IB
β1 + β2 β1 + 1
× IE
β1 + 1 β2 + 1
IC
=
β=
1
IB
· IE
β1 + 1 β2 + 1
1.729 − 0.761
= 0.352 A
0.75 + 2
= β1 + β2 β1 + 1
v O = iL RL
β 1 β 2 since β 1
= 0.352 × 2 = 0.704 V
1 and β 2
1
(b) Refer to the diagram.
Operating current of Q2
11.32
= IC2 =
C
where β = β 1 β 2
IC
b1
b11
•
IC since β 2
IE
b2
b21
b21
Q1
B
β +1
β2
β2
IE =
×
IC
β2 + 1
β2 + 1
β
IB
Q2
IE
IE
b21
E
C
1 and β
Operating current of Q1
• IE
= IC1 =
=
β1
IE
β1 + 1 β2 + 1
β1
β +1
IC
·
β
β1 + 1 β2 + 1
IC
since β
β2
1, β 2
B
IB
IE
and β 1
1.
(c) Again refer to the diagram and part (b).
IC2
IC1
+ VT In
VBE = VBE2 + VBE1 = VT In
IS
IS
From part (b), IC2
IC
1
IC and IC1
IC
β2
IC
1 IC
∴ VBE = VT ln
+ VT ln
IS
β 2 IS
IC
IC
1
+ VT ln
+ VT ln
= VT ln
IS
IS
β2
IC
− VT ln β 2
VBE = 2VT ln
IS
(d) rπeq = β 1 + 1 re1 + β 2 + 1 re2
E
Here, re2 =
VT
IE2
VT
IC2
VT
IC
Chapter 11–14
re1 =
VT
IE2
VT
IC1
VT
= β 2 re2
IC /β 2
From Figure 1 we can write
= 2 β 1 + 1 β 2 re2
⇒ IC2 =
∼
= 2β 1 β 2 re2
= 2β 1 β 2
VT
IC
=
(e) To find gmeq , apply a signal v be and find the
corresponding current ic :
v be
+
β 2 + 1 re2
re1 + β 2 + 1 re2
v bc
=
· v be
RC
(v Rv )
i
RB
o
vo
B
ic/b
1,
v bc
gmeq
(b)
β2
· v be
β 2 r e2 + β 2 + 1 re2
v bc
1.64
IC2
=
= 0.0164 mA
β
100
1
β 2 r e2 + β 2 + 1 re2
∵ gm re
ic
5 − 1.4
RB
RC + 2
β
3.6
= 1.64 mA
2000
2+
10, 000
IC1
ic = ic1 + ic2 = gm1v be1 + gm2v be2
re1
= gm1v be
re1 + β 2 + 1 re2
+gm2
IC2
RB + 1.4
β2
5 = IC2 RC +
β 1 + 1 [β 2 re2 + β 2 re2 ]
rπ eq
vi
1
β2
+ v be
2β 2 re2
2β 2 re2
ic
Q1
β2 + 1
2β 2 re2
ic/b
re1
vb2
1
2re2
Rin
Rb1
ic
1
=
=
v be
2re2
Q2
(b1)re2
Figure 2
1 IC
2 VT
v b2 = v i
11.33 (a)
(β + 1)re2
(β + 1)re2 + re1
where
5 V
RC
1.4 V
IC2
VT
25 mV
= 15.2 =
IC2
1.64 mA
re1 =
VT
IE1
VT
25 mV
= 1.52 =
IC1
0.0164 mA
v b2 = v i
101 × 15.2
= 0.5v i
101 × 15.2 + 1520
ic = gm2 v b2
IC2
b
= gm2 × 0.5v i
IC2
Q1
where
gm2 =
IC2 /b
0.7 V
VT
IE2
2 k
RB 2 M
IC2 /b2
re2 =
Q2
IC2
1.64
= 65.6 mA/V
=
VT
0.025
ic = 65.6 × 0.5v i = 32.8v i
Writing a node equation at the output provides
Figure 1
vo − vi
ic
vo
+ ic + +
=0
RC
β
RB
Chapter 11–15
Substituting ic = 32.8v i , we obtain
1
1
1
1
32.8 −
+
= −v i 1 +
vo
RC
RB
β
RB
1
1
1+
32.8 −
vo
β
RB
=−
Av ≡
1
1
vi
+
RC
RB
0.978
VC = −0.7 − 100 0.0214 +
1010
= −2.94 V
(b) Small-signal parameters:
gm1 =
9.7 × 10−6
= 0.388 mA/V
25 × 10−3
1.01 × 32.8 − (1/2000)
=−
1
1
+
2 2000
= −66.2 V/V
rπ 1 =
β1
= 25.77 k
gm1
ro1 =
|VA |
100
=
= 10.31 M
IC1
9.7 μA
(c) Rb1 = (β + 1)[re1 + (β + 1)re2 ]
gm2 =
0.97 × 10−3
= 38.8 mA/V
25 × 10−3
= 318.7 k
rπ 2 =
β2
= 2.58 k
gm2
The component of Rin arising from RB can be
found as
vi
Ri2 =
(v i − v o )/RB
ro2 = |VA | /IC2 = 103.1 k
= 101[1.52 + 101 × 0.0152]
Node equation at b2 :
v b2
v π2
gm1v π1 +
+
=0
ro1
rπ2
RB
2000
= 29.8 k
=
1 − (v o /v i )
1 − (−66.2)
=
But v b2 = v o + v p2 , then
v o + v π2
v π2
+
=0
ro1
rπ2
1
1
vo
⇒ v π2
+
+ gm1v π1
=−
rπ2
ro1
ro1
Thus
gm1v π1 +
Rin = Rib Ri2
= 318.7 29.8 = 27.2 k
11.34 (a) DC Analysis:
or, v π2
10 V
vo
+ gm1v π1
ro1
=−
1
1
+
rπ2
ro1
Node equation at output:
10.7
RB
500
500 k 0.0214 mA
0.7 V
vo
v o − v π1
1
+
= gm2 v π2 +
v π2
ro2
Rf
rπ2
1
= gm2 +
v π2
rπ2
1
vo
gm2 +
+ gm1v π1
rπ2
ro1
=−
1
1
+
rπ2
ro1
Q1
IE2
1010
IE2
101
Rf
100 k
Q2
IE2
(
0.0214 +
IE2
1010
(
IE2
+ IE2
1010
= 0.978 mA
1 mA = 0.0214 +
⇒ IE2
IC2 = 0.99 × 0.978 = 0.97 mA
IC1 =
0.978
= 9.7 μA
101
VC
1 mA
Substituting v π1 = v i and collecting terms, we
obtain
⎤
⎡
1
gm2 +
⎥
⎢ 1
1
rπ2
⎥
v o⎢
⎣ ro2 + Rf +
1 ⎦
1
ro1
+
rπ2
ro1
⎡ ⎤
1
gm1 gm2 +
⎢
1⎥
rπ2
= −v i⎢
− ⎥
⎣
1
1
Rf ⎦
+
rπ2
ro2
Chapter 11–16
This figure belongs to Exercise 11.34, part (b).
Rf
rp2
c1 , b2
b1
vi RB
rp1
gm1vp1
1
gm1 gm2 +
1
rπ 2
−
1
1
Rf
+
vo
rπ 2
ro2
=−
1
vi
gm2 +
1
1
rπ 2
+
+ 1
1
ro2
Rf
ro1
+
rπ 2
ro1
Since rπ 2
vo
vi
vp2 ro1
gm2vp2
vp1
= 500 25.77 vo
vi
100
1 + 1320
11.35 First consider the situation in the quiescent
state and find VBB .
IQ2 = IQ4 = 2 mA
ro1 , we have
VBE2 = VBE4 = 0.7 + 0.025 ln
IBias
Substituting β 2 = β N and noting that β N
obtain
1
vo
−gm1
1
1
1
1
vi
+
+
β N ro2
ro1
Rf
Q1
B
Q2
R2
Q5
1, we
vI
B
⎥
vo ⎦
1−
vi
Rf
RL
Q3
Q4
Q.E.D.
vi − vo
vi
Rf
⎤
⎡
⎢
= 500 25.77 ⎣
vO
R1
VCC
(c)
vo
= −0.388 10.31 × 103 100 (103.1 100)
vi
Rin = RB rπ 1
VCC
gm1 β 2 + 1
−
1
1
1
β +1
+
+
ro2
Rf
ro1 2
= −1320 V/V
2
10
= 0.660 V
gm1 β 2 + 1 , we have
= −gm1 ro1 β N ro2 Rf
c2
= 75.5 1
gm1 (gm2 rπ 2 + 1) −
Rf
−
1
1
1
+
+
(gm2 rπ 2 + 1)
ro2
Rf
ro1
1
Rf
ro2
= 500 25.77 0.0757
1
gm1 β 2 + 1 −
Rf
= −
1
1
1
β +1
+
+
ro2
Rf
ro1 2
Since
vo
e2
For Q1 and Q3 , we have
2
2
IC = =
= 0.02 mA
β
100
VBE1
0.02
= |VBE3 | = 0.7 + 0.025 ln
1
= 0.602 V
0.02
0.02 mA
=
= 0.2 μA
IB1 =
β
100
Chapter 11–17
IBias = 100 × Base current in B1
Now find v I for v O = –10 V and RL =1 k.
= 100 × 0.2 = 20 μA
−10
= −10 mA
1 k
Assume that current through Q2 is almost zero.
1
× 20 μA = 2 μA
10
and IC5 = 20 − 2 = 18 μA
18 μ
VBE5 = 0.7 + 0.025 ln
1m
iL =
IR1,R2 =
∴ IC4
0.600 V
VBB = VBE1 + VBE2 + |VBE3 |
= 0.602 + 0.660 + 0.602
= 1.864 V
1.864
= 932 k
R1 + R2 =
2 μA
R1 =
0.600
= 300 k
2 μA
R2 = 932 − 300 = 632 k
Now find v I for v O = 10 V and RL = 1 k.
Q2 is conducting most of the current and Q4
conducting a negligible current.
10 V
= 10 mA
1 k
∴ The current through each of Q1 and Q2
10
=5
increases by a factor of
2
Thus VBE2 = 0.66 + 0.025ln5 = 0.700 V
∴ I C2
IL =
VBE1 = 0.602 + 0.025ln5 = 0.642 V
and IB1 = 5 × 0.2 μA = 1 μA
∴ The current through the multiplier is
IBias − 1 = 20 − 1 = 19 μA. Assuming most of
the decrease occurs in IC5 , we obtain
10 mA
The current through Q4 increases by a factor of 5
(relative to the quiescent value).
∴ The current through Q3 must also
increase by the same factor. Thus
|VBE3 | = 0.602 + 0.025 ln5 = 0.642 V
|VBE3 | has increased by 0.642 − 0.602 = 0.04 V.
Since Q1 and Q2 are almost cut off, all of the IBias
now flows through the VBE multiplier. That is an
increase of 0.2 μ. Assuming that most of the
increase occurs in IC5 , VBE5 becomes
18.2 μA
VBE5 = 0.7 + 0.025 ln
0.600 V
1 mA
The voltage VBE5 remains almost constant, and
the voltage across the multiplier will remain
almost constant. Thus the increase in |VEB3 | will
result in an equal decrease in |VBE1 | + |VBE2 |, i.e.
VBE1 + VBE2 = 0.660 + 0.602 − 0.04
The current through each of Q1 and Q2 decreases
by the same factor, let it be m; then
0.025 ln m + 0.025 ln m = −0.04 V
⇒ m = 0.45
Thus IC2 = 0.45 × 2 = 0.9 mA
Now do iteration
IC4 = 10.9
∴ I C5 = 18 − 1 = 17 μA
17 μA
= 0.598 V
VBE5 = 0.7 + 0.025 ln
1 μA
10.9
= 5.45
2
∴ |VBE3 | = 0.602 + 0.025 ln 5.45
∴ VBB1 , the voltage across the multiplier is
= 0.644
932
= 1.858 V
300
It follows that VEB3 becomes
v I = v O + |VEB3 |
VBB = 0.598 ×
VEB3 = 1.858 – 0.700 – 0.642 = 0.516 V
i.e. VEB3 has decreased by 0.600 – 0.516 = 0.084 V
Correspondinly, IC3 will decrease by a factor of
e
−0.084
0.025
= 0.035.
∴ I C4 becomes 0.035 × 2 = 0.07 mA
This value is close to zero, no iteration required.
∴ v I = 10 + 0.7 + 0.642 − 1.858
v I = 9.484 V
IC4 has increased by a factor of
vI ∼
= − 10.644 V
11.36 (a) Refer to the circuit in Fig. P11.36.
While D1 is conducting, the voltage at the emitter
of Q3 is (VCC1 − VD ). For Q3 to turn on, the
voltage at its base must be at least equal to
VCC1 = 35 V. This will occur when v I reaches the
value
v I = VCC1 − VZ1 − VBB
= 35 − 3.3 − 1.2 = 30.5 V
This is the positive threshold at which Q3 is
turned on.
Chapter 11–18
(b) The power dissipated in the circuit is given by
Eq. (11.19):
PD =
VBE = 6.5 × 75 = 487.5 mV
2 V̂o
1 V̂o2
VCC −
π RL
2 RL
IC5 = 10−14 × e487.5/25 = 2.9 μA
For 95% of the time, V̂o = 30 V, VCC = 35 V,
1 2
1
PD =
× 30 × 35 − × 302
RL π
2
=
11.38 Refer to Fig. P11.38.
2 × 10−3 = 10−14 eVEB5 /VT
218.5
RL
VEB5 = 0.025 ln(2 × 1011 )
= 0.650 V
0.650 V
= 6.5 R=
100 mA
For a normal peak output current of 75 mA,
we have
For 5% of the time, V̂o = 65 V, VCC = 70 V,
1 2
1
PD =
× 65 × 70 − × 652
RL π
2
=
784.1
RL
VEB5 = 6.5 × 75 = 487.5 mV
Thus, the total power dissipation is
IC5 = 10−14 × e487.5/25
218.5
784.1
PD =
× 0.95 +
× 0.05
RL
RL
=
246.8
RL
= 2.9 μA
(1)
This should be compared to the power dissipation
of a class AB output stage operated from ±70 V.
Here,
PD (for 95% of the time)
1 2
1
2
=
× 30 × 70 − × 30
RL π
2
=
886.9
RL
VZ = 6.8 + (125 − 25) × 2 = 7.0 V
Similarly, for Q2 to conduct 200 μA, we need
VBE2 = 0.517 V
Now, the voltage across R1 and R2 is
V(R1 +R2 ) = VZ − VBE1
784.1
RL
881.8
RL
At 125◦ C, we have
= 0.517 V
= 7 − 0.517 = 6.483 V
886.9
784.1
Total dissipation =
× 0.95 +
× 0.05
RL
RL
=
11.39 Refer to Fig. 11.22.
Since IC2 = 200 μA, then
200
− 2 mV × 100
VBE1 = 0.7 + 0.025 ln
100
PD (for 5% of the time)
1 2
1
=
× 65 × 70 − × 652
RL π
2
=
From a normal peak output current of 75 mA,
we get
(2)
The results in (1) and (2) indicate that using the
Class G circuit in Fig. P11.36 results in a
reduction in PD by a factor of 3.6!
The voltage across R2 is equal to VBE1 , thus
0.517
= 2.59 k
0.2 mA
The voltage across R1 is given by
6.487 − 0.517 = 5.966 V. Thus,
R2 =
5.966 V
= 29.8 k
0.2 mA
Now, at 25◦ C, we have
R1 =
11.37 Refer to Exercise 11.11 and Fig. 11.21.
VZ = 6.8 V
2 × 10−3 = 10−14 eVBE /VT
Assume VBE1 = 0.7 V, then
⇒ VBE = 0.650 V
V(R1 +R2 ) = 6.8 − 0.7 = 6.1 V
RE1 =
0.650 V
= 6.5 100 mA
I(R1 +R2 ) =
6.1
= 0.188 μA
2.59 + 29.8
Chapter 11–19
11.41
Thus
188
= 0.716 V
VBE1 = 0.7 + 0.025 ln
100
V(R1 +R2 ) = 6.8 − 0.716 = 6.084
VBE2 = 6.084 ×
VDD
R2
R1 + R2
IBias
2.59
= 0.486 V
2.59 + 29.8
= 6.084 ×
Thus,
Q1
QN
IC2 = 100 e(486−700)/25 = 0.019 μA
vO
11.40 (a) Refer to the circuit in Fig. 11.23.
Rout = Ron Rop
Q2
where
Ron =
1
ron
gmn
1/gmn
Rop =
1
rop
gmp
1/gmp
Rout = Ron Rop
vI
VSS
(a) Equation (11.43)
1
gmn + gmp
Q.E.D.
IQ = IBias
For matched devices, we have
1 = 0.1
gmn = gmp = gm
Rout =
1
2gm
Q.E.D.
(b) Rout = 20 1
= 20
2gm
⇒ gm =
1
A/V = 25 mA/V
40
But,
gm = k (W/L)VOV
25 = 200VOV
⇒ VOV =
25
= 0.125 V
200
VGG = 2VGS
= 2(|Vt | + |VOV |)
= 2(0.5 + 0.125)
= 2 × 0.625 = 1.25 V
1 W
2
VOV
IQ = k
2
L
=
RL
1
1
gmn gmp
Thus,
Rout
QP
1
× 200 × 0.1252 = 1.56 mA
2
(W/L)n
(W/L)1
(W/L)n
(W/L)1
(W/L)n
= 10
(W/L)1
1 W
kn
V2
2
L 1 OV
W
1
0.1 = × 0.250 ×
× (0.15)2
2
L 1
W
⇒
= 35.6
L 1
W
1
× (0.15)2
Q2 : 0.1 = × 0.100 ×
2
L 2
W
⇒
= 88.9
L 2
W
1
× (0.15)2
QN : 1 = × 0.250 ×
2
L N
W
⇒
= 356
L N
W
1
QP : 1 = × 0.100 ×
× (0.15)2
2
L P
W
= 889
L P
Q1 : IBias =
Chapter 11–20
(b) From the circuit we get v I = v O − VSGP
Substituting for Rout above, we obtain for
Since v O = 0, we have
vo
=
vi
v I = −VSGP
RL
1
2g m
RL +
VSGP = |VOV | + |Vt |
Q.E.D.
(b) Voltage gain = 0.98 =
= 0.15 + 0.45
= 0.6 V
∴ v I = −VSGP = −0.6 V
0.98 =
(c) Using Eq. (11.46), we obtain
1000 +
RL +
1
2g m
1
2g m
⇒ gm = 24.5 mA/V
To find VGSN , use the equations
For Q1 , we have IBias = ID .
VGSN = Vt + 0.47 = 0.45 + 0.47
RL
1000
v Omax = VDD − VOV |Bias − VGSN
1 W
iDN max = k n (VGSN − Vt )2
2 L
1
10 = × 0.250 × 356 (VGSN − Vt )2
2
⇒ VGSN − Vt = 0.47 V
vo
vi
∴ 0.2 =
1
k1V 2
2 OV
1
2
× 20 × VOV
2
⇒ VOV = 0.14 V
0.2 =
0.92 V
For QN , we have
∴ v Omax = 2.5 − 0.2 − 0.92 = 1.38 V
gm = k n VOV
24.5 = k n × 0.14
11.42
k n = 173 mA/V2
n=
VDD
kn
173
=
k1
20
= 8.66
IBias
and IQ = nIbias
= 8.66 × 0.2
Q1
= 1.73 mA
QN
vO
Q2
QP
RL
11.43 Refer to Fig. 11.24. Consider the situation
when QN is conducting the maximum current of
20 mA,
20 =
1 2
k nv
2 OVN
1
× 200v 2OVN
2
⇒ v OVN = 0.45 V
=
vI
VSS
Thus,
v Omin = −VSS + v OVN
(a) under quiescent condition
Voltage gain =
RL
vo
=
vi
RL + Rout
As shown in problem 11.40, for matched
transistors we have
1
Rout =
2gm
= −2.5 + 0.45 = −2.05 V
Because QN and QP are matched, a similar
situation pertains when QP is supplying
maximum current, and
v Omax = +2.05 V
Thus, the output voltage swing realized is
±2.05 V.
Chapter 11–21
11.44 From Eq. (11.57), we obtain
Substituting this into Eq. (2) gives
Rout = 1/μ(gmp + gmn )
iDN = IQ (1 + 1)2 = 4IQ
where
Since iL = −iDN , we have
gmp = gmn
Rout =
2IQ
2×2
=
= 20 mA/V
=
|VOV |
0.2
v O = iL RL = −4IQ RL
1
1
=
k = 5 5(20 + 20)
200
Similarly, Eq. (2) shows that QN turns off and
iDN = 0 when
μ
11.45 (a) From Eq. (11.68), we obtain
| Gain error | =
1
2μgm RL
(1)
From Eq. (11.57), we get
Rout =
(2)
Combining (1) and (2) yields
Q.E.D.
(b) For RL = 100 and | Gain error | = 3%,
Rout = 0.03 × 100 = 3 But,
Rout =
3=
1
2μgm
1
2 × 5 × gm
⇒ gm =
1
= 33.3 mA/V
30
Using
gm =
substituting this into Eq. (1) gives
iDP = IQ (1 + 1)2 = 4IQ
v O = iL RL = 4IQ RL
1
2μgm
Rout
| Gain error | =
RL
vO − vI
= −1
VOV
Since in this case iL = iDP , then
1
μ(gmn + gmp )
For gmn = gmp = gm , we have
Rout =
Q.E.D.
2IQ
VOV
we obtain
2 × 2.5
33.3 =
VOV
5
⇒ VOV =
= 0.15 V
33.3
11.46 iDP and iDN are given by Eqs. (11.61) and
(11.62) as
vO − vI 2
iDP = IQ 1 − μ
(1)
VOV
vO − vI 2
iDN = IQ 1 + μ
(2)
VOV
Equation (1) shows that QP turns off and iDP = 0
when
vO − vI
=1
μ
VOV
Q.E.D.
Thus, one of the two transistors turns off when
| iL | reaches 4IQ .
1 W 2
k
V
2 L OV
W
1
1.5 = × 0.1
(0.15)2
2
L P
W
⇒
= 1333.3
L P
W
(W/L)P
= L N
k n /k p
W
1333.3
= 533.3
=
L N
2.5
11.47 (a) IQ =
(b) gm =
2IQ
2 × 1.5
= 20 mA/V
=
VOV
0.15
Rout =
1
(where gmn = gmp = gm )
2μgm
2.5 =
1
2μ × 20 × 10−3
⇒ μ = 10 V/V
(c) Gain error = −
=−
1
2μgm RL
1
= −0.05
2 × 10 × 20 × 10−3 × 50
or − 5%
(d) In the quiescent state the dc voltage at the
output of each amplifier must be of the value that
causes the current in QN and QP to be IQ . Thus,
for the QP amplifier the output voltage is
VDD − VSG = VDD − |Vtp | − |VOV |
= 2.5 − 0.5 − 0.15 = 1.85 V
Chapter 11–22
11.48 (a) From the circuit in Fig. P11.48 we see
that
R3
R1
VB1 − VB4 = 1 +
VBE6 + 1 +
VBE5
R4
R2
Similarly, the voltage at the output of the QN
amplifier must be
−VSS + VGS = −2.5 + 0.5 + 0.15
= −1.85 V
and
(e) QP will be supplying all the load current
when QN cuts off. From Eq. (11.62) we see that
QN cuts off when
μ
VGG = (VB1 − VB4 ) − (VBE1 + VBE2 + VEB3 + VEB4 )
Thus
vO − vI
= −1
VOV
R3
R1
VGG = 1 +
VBE6 + 1 +
VBE5
R4
R2
Substituting this in Eq. (11.61), we find the
current iDP to be
− 4VBE
iDP = IQ (1 + 1) = 4IQ
Q.E.D.
(1)
2
where VBE denotes the magnitude of the
base-emitter voltage of each of Q1 − Q4 .
Since in this situation
iL = iDP
(b) From the circuit diagram we see that as the
output transistors heat up, Q6 also heats up. Thus
in Eq. (1) only VBE6 changes with the temperature
of the output stage, thus VGG changes with
temperature according to
R3 ∂VBE6
∂VGG
= 1+
Q.E.D.
(2)
∂T
R4
∂T
then
iL = 4IQ
and
v O = 4IQ RL
= 4 × 1.5 × 10−3 × 50 = 0.3 V
(c) To stabilize the operation of QN and QP as
temperature changes, we arrange that
Similarly, when v O = −0.3 V, QP will cut off
and all the current (4IQ = 6 mA) will be supplied
by QN .
∂VGG
∂(VtN + |VtP |)
=
∂T
∂T
(f) The situation at v O = v Omax is illustrated in
Fig. 1. Analysis of this circuit provides
1
W
iDP = × k n
[2.5 − (v Omax − 0.5) − 0.5]2
2
L n
= −3 − 3 = −6 mV/◦ C
From Eq. (2), we obtain
R3 ∂VBE6
∂VGG
= 1+
∂T
R4
∂T
R3
× −2
= 1+
R4
R3
mV/◦ C
= −2 1 +
R4
1
v Omax
= × 0.25 × 533.3(2.5 − v Omax )2
RL
2
⇒ v Omax = 1.77 V
Similarly,
v Omin = −1.77 V
This figure belongs to Problem 11.47, part (f).
VDD 2.5 V
vOmax Vt
m
Vt
vImax
QP
vOVmax
iDP
0
A the edge
of triode
region
iLmax
vOmax
RL 50 Figure 1
(3)
(4)
Chapter 11–23
From Eqs. (3) and (4), we obtain
1+
⇒
R3
=3
R4
R3
=2
R4
(d) IDN = IDP = 100 mA
W
1
V2
100 = μn Cox
2
L N OVN
1
2
× 2 × 103 × VOVN
2
⇒ VOVN = 0.316 V
100 =
=
R2
3R2
VS + 2 −
VEB
R1
R1
2
R2
2
VS , select
=
3
R1
3
For VO
R2 =
100
2R1
=
= 33.3 k
3
3
To keep the gain unchanged, we must change R3
so that
2R2
= 50
R3
R3 =
Similarly,
4
2 × (100/3)
= = 1.33 k
50
3
|VOVP | = 0.316 V
11.50 Refer to Fig. 11.29 with VS = 22 V.
Thus,
VB1
0
VE1
0.7 V
VE3
1.4 V
VGSN = |VGSP | = 0.316 + 3 = 3.316 V
and
VGG = 2 × 3.316 = 6.632 V
To establish a quiescent current of 20 mA in the
driver stage, we use
VC10 = 22 − 0.7 = 21.3 V
IE3 =
21.3 − 1.4
50
6.632
VGG
=
= 0.3316 k
R=
20
20
332 IE1 = IB3 =
VB1 − VB4 = VGG + 4VBE
IB1 =
= 6.632 + 4 × 0.7 = 9.432 V
Thus,
R1
R3
VBE6 + 1 +
VBE5 = 9.432 V
1+
R4
R2
R1
× 0.7 = 9.432
(1 + 2) × 0.7 + 1 +
R2
R1
= 9.47
⇒
R2
11.49 Refer to the circuit of Fig. 11.29.
Resistors R2 and R3 control the gain,
2R2
Av = −
R3
0.4 mA
0.4
IE3
=
= 19 μA
βP + 1
21
19
IE1
=
= 0.9 μA
βP + 1
21
VB1 = IB1 × R4 = 0.9 × 10−3 × 150 = 0.136 V
We can use this value to obtain IE1 :
VE1 = 0.836 V
VE3 = 1.536 V
IE3 =
21.3 − 1.536
50
(almost no change)
IE1
19 μA
IE4 = IE3 = 0.4 mA
IE2 = IE1 = 19 μA
IE5
IC3 = 0.4 ×
20
= 0.38 mA
21
Resistor R3 controls the gain alone. Resistor R2
affects both the gain and the dc output level.
To see the later point, equate I3 and I4 from
Eqs. (11.69) and (11.70) to obtain
IE6 = IE5 = 0.38 mA
VO − 2VEB
VS − 3VEB
=
R1
R2
= VE3 + IR2 R2
R2
3R2
⇒ VO = 2VEB + VS −
VEB
R1
R1
0.4 mA
IR1 = IR2
0.4 mA
VO = VE4 + IR2 R2
= 1.536 + 0.4 × 25
= 11.54 V
Chapter 11–24
Consider next the effect of finite transistor β. For
the case in Fig. 1, we have
vI
iE1 =
R
β vI iC1 = α1 iE1 =
β +1 R
1
iC4 = iC1
2
1+
β
Thus,
β
β vI
iO =
β +1 β +2 R
100 100 v I
×
×
=
101 102
R
vI
0.97
R
11.51 Refer to Fig. 11.31. To limit PD to 2 W, we
need to limit the supply voltage to
VS = 16 V
The VS = 16 V graph intersects the THD = 3%
line at PL = 2.7 W, which is the maximum
possible load power. Thus,
√
(V̂o / 2)2
= 2.7
RL
V̂o =
√
2.7 × 8 × 2 = 6.57 V
which means that an approximately 13-V
peak-to-peak sinusoid is needed.
11.52 Figure 1 shows the currents in the circuit
for the case where v I is positive and assuming an
op amp with very high gain (hence the 0 V
between its two input terminals) and all β’s are
very high. The result is that
iO =
11.53 Refer to Fig. 11.32.
Gain = 2K = 8
K =4
R4
=K =4
R3
⇒ R4 = 40 k
R2
=4
1+
R1
R2
=3
R1
⇒ R2 = 30 k
vI
R
If v I is negative, the current through R reverses
direction and is thus supplied by Q2 and then
mirrored to the output by the mirror Q5 − Q6 ,
resulting in iO = v I /R but reversed in direction.
This figure belongs to Problem 11.52.
VCC
Q3
5
Q4
vI /R
Q1
1
0V
vI /R
0
4
Q2
vI
vI /R
0
vI
3
vI
R
R
vI / R
Q6
Q5
2
0
VCC
Figure 1
6
iO vI / R
7
Chapter 11–25
2
(b) Power loss = 4fs CVDD
11.54 The analysis is shown in Fig. 1 (below),
from which the gain is found as
PL
PL + Ploss
vO
R2 + R3
=1+
vI
R1
η=
The largest sinusoid that can be provided across
RL will have a peak amplitude of 2 × 13 = 26 V.
To ensure that the signals v O1 and v O2 are
complementary, then
=
2
VDD
/2R
2
2
(VDD /2R) + 4fs CVDD
=
1
1 + 8fs CR
1+
For fs = 250 kHz,C = 1000 pf and R = 16 R2
R3
=
R1
R1
η=
Selecting R1 = 1 k, we obtain
1 + R2 = R3
1
1 + 8 × 250 × 103 × 1000 × 10−12 × 16
= 97%
(1)
and to obtain a gain of 8 V/V we write
1+
R2 + R3
=8
R1
1 + R2 + R3 = 8
11.58
(2)
Solving (1) and (2) simultaneously gives
2(1 + R2 ) = 8
⇒ R2 = 3 k
R3 = 4 k
11.55 See figure on the next page.
11.56
Average = +10 × 0.65 − 10 × 0.35 = +3 V
If duty cycle changed to 0.35, the average
becomes
= +10 × 0.35 − 10 × 0.65 = −3 V
Figure 1
11.57 (a) Maximum peak voltage across
R = VDD
(a) Figure 1 shows the SOA boundaries.
Maximum power supplied to load
√
(VDD / 2)2
V2
=
= DD
R
2R
(b) For the CS configuration in Fig. P11.58,
VDS = VDD − RID
This figure belongs to Problem 11.54.
Figure 1
(1)
Chapter 11–26
This figure belongs to Problem 11.55.
We see that maximum VDS occurs when ID = 0
and the resulting maximum VDS is
VDSmax = VDD
Writing (1) in the alternative form
VDD − VDS
R
shows that maximum ID is obtained when
VDS = 0 and the resulting maximum ID is
ID =
(2)
VDD
R
The power dissipation in the transistor is given by
IDmax =
(c) For VDD = 40 V, v DSmax = 40 V. Now, since
VDS and ID are related by the linear relationship in
(1) or (2), the straight line representing this
relationship on the iD − v DS plane must pass by
the point v DS = 40 V and iD = 0. Now we are
searching for the straight line with maximum
slope that clears the hyperbola and intersects the
vertical axis at 5 A or less. For this case, this
straight line is the one joining the points (40, 0)
and (0, 5). It is a tangent to the hyperbola at
VDD
v DS =
= 20 V, which is the point of
2
maximum power dissipation. For this straight line
= (VDD − RID )ID
40 V
=8
5A
IDmax = 5 A
PD will be maximum when
PDmax =
PD = VDS ID
∂PD
=0
∂ID
2
VDD
402
=
= 50 W
4R
4×8
(d) For VDD = 30 V: Following a process similar
to that in (c), we find
that is,
VDD − 2RID = 0
⇒ RID =
R=
VDD
2
30 V
=6
5A
IDmax = 5 A
R=
302
= 37.5 W
4×6
or
PDmax =
VDD
2
The corresponding PDmax is
The locus of the operating point is shown in
Fig. 1.
VDS =
PDmax = VDS ID
=
VDD VDD
2 2R
=
2
VDD
4R
(e) For VDD = 15 V, we have
15 V
=3
5A
IDmax = 5 A
R=
PDmax =
152
= 18.75 W
4×3
Chapter 11–27
The locus of the operating point is shown in
Fig. 1.
11.62 θ JC =
TJ − TC
180◦ − 30◦
= 3◦ C/W
=
PD
50
TJ − TS = θ JS PD
11.59 Power rating =
ICav
130 − 30
= 40 W
2.5
40
= 2.0 A
≤
20
11.60 (a) θ JA =
TJ max − TA0
PD0
100 − 25
= 37.5◦ C/W
2
(b) At TA = 50◦ C, we have
=
PDmax
TJ max − TA
=
θ JA
100 − 50
= 1.33 W
=
37.5
(c) TJ = 25◦ + 37.5 × 1 = 62.5◦ C
180◦ − TS = (θ JC + θ CS )PD
⇒ TS = 180 − (3 + 0.6) × 30 = 72◦
TS − TA = θ SA PD
72 − 27 = θ SA × 30
⇒ θ SA = 1.5◦ C/W
Required heat-sink length =
6◦ C/W/cm
1.5◦ C/W
= 4 cm
11.63 TC − TA = θ CA PD
= (θ CS + θ SA ) PD
⇒ PD =
TC − TA
97 − 25
= 120 W
=
θ CS + θ SA
0.5 + 0.1
11.61 TJ ≤ 50 + 3 × 20 = 110◦ C
TJ − TC = θ JC PD
VBE = 800 − 2 × (110 − 25) = 630 mV
150 − 97 = θ JC × 120
= 0.63 V
⇒ θ JC = 0.44◦ C/W
Exercise 12–1
Ex: 12.1 Using Eq. (12.2), we obtain
A = gm1 (ro2 ro4 )gm6 (ro6 ro7 )
VICM min = −VSS + Vtn + VOV 3 − |Vtp |
β=1
= −1.65 + 0.5 + 0.3 − 0.5
Thus,
= −1.35 V
Rout =
Using Eq. (12.3), we get
VICM max = VDD − |VOV 3 | − |Vtp | − |VOV 1 |
= 1.65 − 0.3 − 0.5 − 0.3
= +0.55 V
Usually,
A1
Thus,
Rout Thus,
ro6 ro7
1 + gm1 (ro2 ro4 )gm6 (ro6 ro7 )
1
gm6 [gm1 (ro2 ro4 )]
−1.35 V ≤ VICM ≤ +0.55 V
Using Eq. (12.5), we obtain
−VSS + VOV 6 ≤ v O ≤ VDD − |VOV 7 |
Thus
−1.65 + 0.5 ≤ v O ≤ 1.65 − 0.5
⇒ −1.15 V ≤ v O ≤ +1.15 V
Ex: 12.4 Using Eq. (12.36), we get
ft =
Gm1
2πCC
⇒ CC =
=
Gm1
2πft
0.3 × 10−3
2π × 10 × 106
= 4.8 pF
Ex: 12.2 For all devices, we have
From Eq. (12.31), we have
|VA | = 20 V
fZ =
Using Eq. (12.13), we get
2
1
1
+
A1 = −
|VOV 1 |
|VA2 | VA4
2
2
= −100 V/V
=−
0.2 20
Using Eq. (12.20), we obtain
1
2
1
+
A2 = −
|VOV 6 |
VA6
|VA7 |
2
2
= −40 V/V
=−
0.5 20
A = A1 A2
= −100 × −40 = 4000 V/V
20
|VA |
=
= 40 k
ro6 = ro7 =
0.5 mA
0.5
Ro = ro6 ro7 = 40 40 = 20 k
=
Rout = Rof
Ro
=
1 + Aβ
where
Ro = ro6 ro7
0.6 × 10−3
2π × 4.8 × 10−12
20 MHz
From Eq. (12.35), we have
fP2 =
=
Gm2
2πC2
0.6 × 10−3
= 48 MHz
2π × 2 × 10−12
Thus, ft is lower than fZ and fP2 .
Ex: 12.5 (a) Using Eq. (12.36), we have
ft =
Gm1
2πCC
⇒ CC =
=
Ex: 12.3 The feedback is of the voltage sampling
type (i.e., the connection at the output is a shunt
one), thus
Gm2
2πCC
Gm1
2πft
1 × 10−3
2π × 100 × 106
= 1.6 pF
A0 = Gm1 (ro2 ro4 )Gm2 (ro6 ro7 )
= 1(100 100) × 2(40 40)
= 50 × 2 × 20 = 2000 V/V
f3dB =
ft
100 × 106
=
= 50 kHz
A0
2000
Exercise 12–2
gm13 = gm8 = 0.6 mA/V
(b) From Eq. (12.34), we have
R=
gm12 =
1
1
=
= 500 Gm2
2 × 10−3
=
(c) From Eq. (12.35), we have
fP2 =
φP2 = −tan−1
Now,
2
RB = √
2μn Cox (W/L)12 IREF
ft
fP2
=
100
318
= −tan−1
2μn Cox × 4(W/L)13 IREF
= 2gm13 = 1.2 mA/V
Gm2
2πC2
2 × 10−3
= 318 MHz
2π × 1 × 10−12
=
2μn Cox (W/L)12 IREF
√
2
( 4 − 1)
−3
1.2 × 10
= 1.67 k
= −17.4◦
From Example 8.6, we have
PM = 90 − 17.4 = 72.6◦
VDD = VSS = 2.5 V
IREF = 90 μA
Ex: 12.6 Using Eq. (12.47), we obtain
Vtn = 0.7 V
SR = VOV 1 ωt
|Vtp | = 0.8 V
= 0.2 × 2π × 100 × 106
|VOV 8 | = 0.3 V
= 126 V/μs
IREF RB = 0.09 × 1.67
Using Eq. (12.45),
= 150 mV
SR =
Since
I
CC
gm13 =
−12
⇒ I = 126 × 10 × 1.6 × 10
6
= 200 μA
0.6 =
2IREF
VOV 13
2 × 0.09
VOV 13
⇒ VOV 13 = 0.3 V
Ex: 12.7
2
RB = √
2μn Cox (W/L)12 IREF
=
√
2
2 × 90 × 10−6 × 80 × 10 × 10−6
= 5.27 k
Using Eq. (12.61), we obtain
(W/L)12
2
−1
gm12 =
RB
(W/L)13
80
2
−1
=
5.27
20
= 0.379 mA/V
Ex: 12.8 From Example 8.6, Q8 has
W
L
=
8
40
0.8
gm8 = 0.6 mA/V
VGS13 = 0.3 + 0.7 = 1 V
(W/L)12
−1
(W/L)13
VG13 = −VSS + VGS13
80
−1
20
= −2.5 + 1 = −1.5 V
VGS11 = VGS13 = 1 V
VG11 = VG13 + VGS11
= −1.5 + 1 = −0.5 V
VSG8 = |Vtp | + |VOV 8 |
= 0.8 + 0.3 = 1.1 V
VG8 = VDD − VSG8
= 2.5 − 1.1 = +1.4 V
Ex: 12.9 Total bias current = 300 μA = 2IB
⇒ IB = 150 μA
IB = ID1 + ID3
150 = ID1 + 0.25ID1
⇒ ID1 = 120 μA
(W/L)12
−1
(W/L)13
Exercise 12–3
I = ID1 + ID2
Ro4 = (gm4 ro4 )(ro2 ro10 )
= 120 + 120 = 240 μA
= (0.3 × 666.7)(166.7 133.3)
ID3,4 = 0.25ID1,2 = 0.25 × 120
= 30 μA
= 14.8 M
2ID6
2 × 0.03
= 0.3 mA/V
=
gm6 =
VOV
0.2
Ex: 12.10 Using Eq. (12.64), we get
ro6 = ro8 =
VICM max = VDD − |VOV 9 | + Vtn
Ro6 = gm6 ro6 ro8
= 1.65 − 0.3 + 0.5 = +1.85 V
= 0.3 × 666.7 × 666.7 = 133.3 M
Using Eq. (12.65), we obtain
Ro = Ro4 Ro6
VICM min = −VSS + VOV 11 + VOV 1 + Vtn
= 14.8 133.3 = 13.3 M
VICM min = −1.65 + 0.3 + 0.3 + 0.5
Av = Gm Ro = 1.2 × 13.3 × 103 = 16,000 V/V
= −0.55 V
|VA |
20
= 666.7 k
=
ID6,8
0.03
Thus,
Ex: 12.12 (a) The NMOS input stage operates
over the following input common-mode range:
−0.55 V ≤ VICM ≤ +1.85 V
−VSS + 2VOV + Vtn ≤ VICM ≤ VDD − |VOV | + Vtn
Using Eq. (12.68), we get
that is,
VOmax = VDD − |VOV 10 | − |VOV 4 |
= 1.65 − 0.3 − 0.3 = +1.05 V
Using Eq. (12.69), we obtain
VOmin = −VSS + VOV 7 + VOV 5 + Vtn
= −1.65 + 0.3 + 0.3 + 0.5
= −0.55 V
Thus,
−0.55 V ≤ v O ≤ +1.05 V
Ex: 12.11 Gm = gm1 = gm2
2(I /2)
I
Gm =
=
VOV 1
VOV 1
0.24
= 1.2 mA/V
0.2
20
|VA |
=
= 166.7 k
ro2 =
I /2
0.12
=
ro4 =
20
|VA |
|VA |
=
=
I
ID4
0.150 − 0.120
IB −
2
20
= 666.7 k
0.03
|VA |
ro10 =
IB
=
20
=
= 133.3 k
0.15
2ID4
2 × 0.03
=
= 0.3 mA/V
gm4 =
|VOV |
0.2
(−2.5 + 0.6 + 0.7) ≤ VICM ≤ (2.5 − 0.3 + 0.7)
−1.2 V ≤ VICM ≤ +2.9 V
(b) The PMOS input stage operates over the
following input common-mode range:
−VSS +VOV −|Vtp | ≤ VICM ≤ VDD −2|VOV |−|Vtp |
that is,
(−2.5 + 0.3 − 0.7) ≤ VICM ≤ (2.5 − 0.6 − 0.7)
−2.9 V ≤ VICM ≤ +1.2 V
(c) The overlap range is
−1.2 V ≤ VICM ≤ +1.2 V
(d) The input common-mode range is
−2.9 V ≤ VICM ≤ +2.9 V
Ex: 12.13 Denote the (W/L) of the transistors in
the wide-swing mirror by (W/L)M . Transistor Q4
has
1
(W/L)5 = (W/L)M
4
IREF =
1
W
μn Cox
2
L
2
VOV
5
5
=
1
W
μn Cox
2
L
1 2
× VOV
5
4
M
=
1
W
μn Cox
2
L
M
Thus,
VOV 5
= VOV
2
(VOV 5 /2)2
Exercise 12–4
where VOV is the overdrive voltage for each of the
mirror transistors. Thus,
V5 = Vtn + 2VOV
which is the value of VBIAS needed in the circuit
of Fig. 12.13(b).
Ex: 12.14 At IC = 0.1 mA,
VBE = 25 ln
Thus,
IC10
= 9.5 μA
2
resulting in
I=
IC1 = IC2 = IC3 = IC4 = 9.5 μA
Ex: 12.17 Figure 1 on next page shows the
determination of the loop gain of the feedback
circuit that stabilizes the bias currents of the first
stage of the 741 op amp. Note that since IC10 is
assumed to be constant, we have shown its
incremental value at node X to be zero. Observe
that this circuit shows only incremental
quantities. The analysis shown provides the
returned current signal as
−3
0.1 × 10
10−14
= 575.6 V
IC
0.1 mA
= 4 mA/V
=
gm =
VT
0.025 V
re 1
= 250 gm
rπ =
β
200
= 50 k
=
gm
4
Ir = −It
ro =
VA
125 V
=
= 1.25 M
IC
0.1 mA
For βP 1, we have
Ex: 12.15 VT ln
βP
1+
2
βP
Ir −βP It
IREF
= IC10 R4
IC10
and the loop gain Aβ is
730
25 ln
= 5IC10
IC10
(1)
where IC10 is in μA, and both sides of Eq. (1) are
in mV. Using iteration:
IC
LHS of Eq. (1) RHS of Eq. (1)
(μA)
(mV)
(mV)
100
49.5
500
50
67
250
20
89.9
100
19
91.2
95
18
92.6
90
Aβ ≡ −
Ir
= βP
It
Ex: 12.18 VBE6 = VT ln
9.5 × 10−6
= 517 mV
10−14
= VBE6 + IR2
= 25 ln
VR3
= 517 + 9.5 × 10−6 × 1 = 526.5 mV
IC7 IE7 =
VR3
R3
526.5
= 10.5 μA
50
Ex: 12.19 IB =
Thus,
=
1
2
Ex: 12.16 Refer to Fig. 12.15. At node X,
=
I
I
βN + 1
βN
IC10
2I
+
2
βP
1+
βP
⎡
2
⎢ βP + 1 + βP
= 2I⎢
⎣
2
βP 1 +
βP
2I
2I
2I
βP + 1
βP + 2
1
(IB1 + IB2 )
2
I
I
+
βN + 1 βN + 1
IC10 19 μA
IC10 =
IC6
IS
9.5
= 47.5 nA
200
IOS = 0.1 × IB = 4.75 nA
=
⎤
⎥
⎥
⎦
Ex: 12.20
VC1 = VCC − VEB8 = 15 − 0.6 = 14.4 V
Q1 and Q2 saturate when VICM exceeds VC1 by
0.3 V. Thus,
VICM max = +14.7 V
Exercise 12–5
This figure belongs to Exercise 12.17.
Figure 1
VC5 −VEE + VBE5 + VBE7
Ex: 12.21 IC13B = 0.75IC12
= −15 + 0.6 + 0.6 = −13.8 V
= 0.75 × 0.73 = 0.55 mA
Q3 (and Q4 ) saturate when
= 550 μA
VB3 = VC5 − 0.3
IC17 = IC13B = 550 μA
= −13.8 − 0.3 = −14.1 V
But,
VB3 = VICM − VBE1 − VEB3
= VICM − 1.2 V
Thus,
VICM min = VB3 + 1.2 V
= −14.1 + 1.2 = −12.9 V
Thus,
−12.9 V ≤ VICM ≤ +14.7 V
VBE17 = VT ln
= 25 ln
IC17
IS
550 × 10−6
10−14
= 618 mV
VR9 = VBE17 + IE17 R8
618 + 550 × 0.1
= 673 mV
IR9 =
673
= 13.46 μA
50
Exercise 12–6
550
= 2.74 μA
201
= IR9 + IB17 = 16.30 μA
|VAp |
50 V
=
= 5.26 M
I
9.5 μA
IB17 =
Ex: 12.25 ro4 =
IE16
gm4 = 0.38 mA/V
200
× 16.3 = 16.2 μA
IC16 =
201
16.2
= 0.08 μA
IB16 =
200
Ex: 12.22 The two diode-connected transistors
will carry a bias current of 0.25IREF = 180 μA.
Since the output transistors have three times the
values of IS as that of the diode-connected
transistors, the bias current in the output
transistors will be
= 3 × 180 = 540 μA
Ex: 12.23 re =
VT
25 mV
= 2.63 k
IE
9.5 μA
1
= 0.38 mA/V
re
gm1 1
gm1 = 0.19 mA/V
2
Rid = (βN + 1) × 4re
Gm1 =
= 201 × 4 × 2.63
= 2.1 M
re2 = 2.63 k
rπ4 =
βP
50
= 131.6 k
=
gm4
0.38
Ro4 = ro4 [1 + gm4 (re2 rπ4 )]
= 5.26[1 + 0.38(2.63 131.6)]
= 10.4 M
(The answer in the book was obtained by
neglecting rπ4 .)
ro6 =
125 V
VAn
=
= 13.16 M
I
9.5 μA
gm6 = 0.38 mA/V
R6 = 1 k
200
= 526.3 k
0.38
Ro6 = ro6 [1 + gm6 (R2 rπ6 )]
rπ6 =
= 13.16[1 + 0.38(1 526.3)]
= 18.2 M
Ro1 = Ro9 Ro6
= 10.4 18.2 = 6.62 M
Ex: 12.24 refer to Fig. 12.19.
Ex: 12.26 | Av o | = Gm1 Ro1
(a) v b6 = ie6 (re6 + R2 )
Using Gm1 given in the answer to Exercise 12.23,
= ie (re6 + R2 )
Gm1 = 0.19 mA/V
re6 =
VT
25 mV
= 2.63 k
IE6
9.5 μA
v b6 = ie (2.63 + 1) = 3.63 k × ie
(b) ie7 = iR3 + ib5 + ib6
v b6
2αie
=
+
R3
βN
3.63
2
ie +
ie
50
201
= 0.08ie
and Ro1 given in the answer to Exercise 12.25,
Ro1 = 6.7 M
we obtain
| Av o | = Gm1 Ro1
= 0.19 × 6.7 = 1273 V/V
=
(c) ib7 =
0.08
ie7
=
ie = 0.0004ie
βN + 1
201
(d) v b7 = ie7 re7 + v b6
v b7 = 0.08 × 2.63ie + 3.63ie
= 3.84 k × ie
v b7
(e) Rin =
3.84 k
αie
Ex: 12.27 Refer to Fig. 12.22, which shows the
current mirror with an imbalance between R1 = R
and R2 = R + R. Observe that the imbalance
causes an error in the mirror transfer ratio of
I
m =
I
I
is given by Eq. (12.94). Thus,
where
I
R
m =
R + R + re
Exercise 12–7
where re = re5 = re6 ,
m =
R
R + re5
R+
R
= 0.02 and re5 = 2.63 k,
R
For R = 1 k,
m =
Q.E.D.
0.02
= 5.5 × 10−3
1 + 0.02 + 2.63
Ex: 12.28
|VAp |
50 V
Ro9 = ro9 =
=
= 2.63 M
IC9
19 μA
Ex: 12.31 Using Eq. (12.104), we get
α
ic17 =
v b17
re17 + R8
=
1
200
v b17 = 6.85v b17
201 0.0455 + 0.1
Using Eq. (12.106), we obtain
Ri17 = 201(0.0455 + 0.1) = 29.25 k
Using Eq. (12.105), we get
v b17 = v i2
50 29.25
= 0.92v i2
(50 29.25) + 1.54
Ro10 = ro10 [1 + gm10 (R4 rπ 10 )]
Combining Eqs. (1) and (2), we obtain
where
ic17 = 6.32v b17
ro10
VAn
125 V
=
=
= 6.58 M
IC10
19 μA
gm10 =
IC10
19 μA
=
= 0.76 mA/V
VT
0.025 V
R4 = 5 k
rπ 10 =
βN
200
= 263.2 k
=
gm10
0.76
Ro10 = 6.58[1 + 0.76(5 263.2)]
(1)
(2)
Thus,
Gm2 = 6.32 mA/V
This value is somewhat lower than the value
generally published for Gm2 , namely
Gm2 = 6.5 mA/V
To conform with published literature, we shall use
the latter value in future calculations.
= 31.1 M
Ro = Ro9 Ro10
Ex: 12.32 Ro13B = ro13B =
= 2.63 31.1 = 2.43 M
=
Ex: 12.29 Using Eq. (12.100), we obtain
m
Gmcm =
2Ro
=
−3
5.5 × 10
= 1.13 × 10−6 mA/V
2 × 2.43 × 106
CMRR =
0.19
Gm1
=
= 1.68 × 105
Gmcm
1.13 × 10−6
or 104.5 dB
Without common-mode feedback, the CMRR is
reduced by a factor equal to βP . Equivalently,
CMRR = 104.5 − 20 log βP
= 104.5 − 20 log 50
|VAp |
IC13B
50
= 90.9 k
0.55
Ro17 = ro17 [1 + gm17 (R8 rπ17 )]
where
ro17 =
125
= 227.3 k
0.55
gm17 =
0.55
= 22 mA/V
0.025
R8 = 0.1 k
rπ17 =
200
= 9.09 k
22
Ro17 = 227.3[1 + 22(0.1 9.09)]
= 722 k
Ro2 = Ro13B Ro17
= 70.5 dB
= 90.9 722 81 k
Ex: 12.30 re16
re17 =
VT
25 mV
=
= 1.54 k
IE16
16.2 mA
VT
25 mV
= 45.5 IE17
0.55 mA
Ex: 12.33 Open-circuit voltage gain = −Gm2 Ro2
= −6.5 × 81 = −526.5 V/V
Using Eq. (12.103), we obtain
Ri2 =
Ex: 12.34 re23 =
(200 + 1) {1.54 + [50 (200 + 1)(0.0455 + 0.1)]}
4 M
VT
IE23
25 mV
= 138.9 0.18 mA
Exercise 12–8
Ro23 =
=
Ro2
+ re23
β23 + 1
i=
vt
+ gm18 × 0.917v t
(40 30.3) + 1.56
= 6.11 × 10−3 v t
vt
rAA ≡
163 i
81
+ 0.139
50 + 1
= 1.73 k
VT
re20 =
IE20
Ex: 12.36 For v O = 10 sinωt
25 mV
=
=5
5 mA
Ro23
Rout = re20 +
β20 + 1
dv O
= ω × 10 cosωt
dt
dv O = ωM × 10 = 2πfM × 10
SR =
dt 1730
= 39 =5+
50 + 1
fM =
max
Total output resistance = Rout + R7
= 39 + 27 = 66 Ex: 12.37 IS2 = 2IS1
Using Eq. (12.127), we obtain
Ex: 12.35
i
I=
A
⫺
⫹
vp
⫺
R10
40 k⍀
gm18vp
vi
i
Figure 1 shows the equivalent circuit model of the
circuit in Fig. E12.35. Note that the
diode-connected transistors Q19 is replaced with
re19 ,
VT
IE19
25 mA
= 1.56 k
16 μA
Transistor Q18 is replaced with its hybrid-π
model,
gm18 =
IC18
0.165 mA
=
VT
0.025 V
= 6.6 mA/V
βN
200
= 30.3 k
=
rπ 18 =
gm18
6.6
Now,
vπ = vt
R3 = R4 =
rp18
A'
0.025
ln2
R2
⇒ R2 = 1.73 k
vt ⫹
rAA'
VT IS2
ln
R2 IS1
0.01 =
re19
re19 =
0.63 × 106
SR
=
= 10 kHz
20π
20π
R10 rπ
(R10 rπ ) + re19
40 30.3
= vt
= 0.917v t
(40 30.3) + 1.56
0.2 V
= 20 k
0.01 mA
Ex: 12.38 To obtain I8 = 10 μA, transistor Q8
must have the same (ratio = 1) emitter area as
Q3 , and
R8 = R3 = 20 k
To obtain I9 = 20 μA, Q9 must have an EBJ area
twice (ratio = 2) that of Q3 and
1
R3 = 10 k
2
To obtain I10 = 5 μA, Q10 must have an EBJ area
half (ratio = 0.5) that of Q3 and
R9 =
R10 = 2R3 = 40 k
Ex: 12.39 Refer to the circuit in Fig. 12.42.
(a) Current gain from v IP to output
= (β1 + 1)(β2 + 1)βP
β1 β2 βP = βN βP2
Current gain from v IN to output = (β3 + 1)βN
β3 βN = βN2
(b) For iL = +10 mA,
current needed at v IP input
=
10
10
=
= 2.5 μA
40 × 102
βN βP2
Exercise 12–9
For iL = −10 mA,
where IREF is in μA. Thus,
current needed at v IN input =
10
10
= 2
40
βN2
= 6.25 μA
For iL = −10 mA, then
iP = 10 + iN
Ex: 12.40 IQ = 0.4 mA, I = 10 μA,
ISN
IS7
= 10,
=2
IS10
IS11
Using Eq. (12.136), we obtain
0.4 × 103 = 2
IREF = 10 μA
2
IREF
10
× 10 × 2
Using Eq. (12.137), we get
iN (10 + iN )
= 0.2
iN + 10 + iN
⇒ iN2 − 9.6iN + 2 = 0
⇒ iN = 0.2 mA
iP = 10.2 mA
Chapter 12–1
12.1 Using Eq. (12.2), we get
VICM min = −VSS + Vtn + VOV 3 − |Vtp |
= −1 + 0.4 + 0.2 − 0.4 = −0.8 V
Using Eq. (12.3), we obtain
VICM max = VDD − |VOV 5 | − |Vtp | − |VOV 1 |
= 1 − 0.2 − 0.4 − 0.2 = +0.2 V
Thus,
−0.8 V ≤ VICM ≤ +0.2 V
12.3 For the op amp to not have a systematic
offset voltage, the condition in Eq. (12.1) must be
satisfied, that is,
(W/L)6
(W/L)7
=2
(W/L)4
(W/L)5
45/0.3
W /0.3
=2
6/0.3
30/0.3
⇒ W = 18 μm
Refer to Fig. 12.1:
ID8 = IREF = 40 μA
Using Eq. (12.5), we get
−VSS + VOV 6 ≤ v O ≤ VDD − |VOV 7 |
Thus,
I = ID5 = IREF
ID7 = IREF
−0.8 V ≤ v O ≤ +0.8 V
30
W5
= 200 μA
= 40 ×
W8
6
45
W7
= 40 ×
= 300 μA
W8
6
ID6 = 300 μA
I
= 100 μA
2
The overdrive voltage at which each transistor is
operating is determined from
ID1 = ID2 = ID3 = ID4 =
12.2 For NMOS devices, we have
VA = 25 × 0.3 = 7.5 V
For PMOS devices,
|VA | = 20 × 0.3 = 6 V
Using Eq. (12.13),
2
1
1
+
A1 = −
|VOV 1 |
|VA2 | VA4
1
1
2
+
=−
0.15
6 7.5
= −44.4 V/V
Using Eq. (12.20), we obtain
2
1
1
+
A2 = −
VOV 6
VA6
|VA7 |
1
1
2
+
=−
0.2
7.5 6
1
W 2
μCox VOV
2
L
Then VGS is found from
ID =
|VGS | = |Vt | + |VOV |
The transconductance at which each transistor is
operating is obtained from
gm =
2ID
VOV
The output resistance of each transistor is found
from
|VA |
ro =
ID
A1 = −gm1,2 (ro2 ro4 )
= −1.33(150 150) = −100 V/V
= −33.3 V/V
A2 = −gm6 (ro6 ro7 )
A = A1 A2 = 1478.5 V/V
= −3.16(50 50) = −79 V/V
7.5
= 25 k
ro6 =
0.3
6
= 20 k
ro7 =
0.3
Ro = ro6 ro7 = 11.1 k
A = A1 A2 = 7900 V/V
For a unity-gain voltage amplifier using this op
amp, we have
Rout = Rof =
Ro
1 + Aβ
11.1 k
=
1 + 1481.5 × 1
= 7.5 Using Eq. (12.2), we obtain
VICM min = −VSS + Vtn + VOV 3 − |Vtp |
VICM min = −1 + 0.45 + 0.19 − 0.45
= −0.81 V
Using Eq. (12.3), we get
VICM max = VDD − |VOV 5 | − |Vtp | − |VOV 1 |
= 1 − 0.24 − 0.45 − 0.15
= +0.16 V
Chapter 12–2
The results are summarized in the following table:
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
I D (μA)
100
100
100
100
200
300
300
40
|VOV | (V)
0.15 0.15 0.19 0.19 0.24 0.19 0.24 0.24
|VGS | (V)
0.6
0.6
0.64 0.64 0.69 0.64 0.69 0.69
g m (mA/V) 1.33 1.33 1.05 1.05 1.67 3.16
ro (k)
150
150
150
150
75
50
2.5
0.33
50
375
Thus,
Thus,
−0.8 V ≤ VICM ≤ +0.16 V
CMRR =
Using Eq. (12.5), we obtain
−VSS + VOV 6 ≤ v O ≤ VDD − |VOV 7 |
Thus,
−1 + 0.19 ≤ v O ≤ 1 − 0.24
−0.81 V ≤ v O ≤ 0.76 V
12.4 For all transistors, we have
|VA | = 20 × 0.3 = 6 V
Using Eq. (12.13), we get
2
2
6
=−
A1 = −
|VOV | |VA |
|VOV |
Using Eq. (12.20), we obtain
2
6
2
=−
A2 = −
|VOV | |VA |
|VOV |
36
A = A1 A2 =
|VOV |2
1600 =
36
|VOV |2
I
1 2|VA |
I
|VA |
× ×
×2×
×
|VOV | 2
I
|VOV |
I
|VA |2
|VOV |2
For CMRR = 72 dB = 4000, we have
=2
|VA |2
0.152
⇒ |VA | = 6.7 V
4000 = 2 ×
Since |VA | = |VA |L, we have
6.7 = 15L
⇒ L = 0.45 μm
2
VA 2
= 6.7
= 2000 V/V
Av̂ = VOV 0.15
12.6 From Eq. (12.36), we obtain
Gm1
ft =
2πCC
Thus,
Gm1
0.8 × 10−3
=
= 1.06 pF
2πft
2π × 120 × 106
From Eq. (12.35), we get
Gm2
fP2 =
2πC2
CC =
CMRR = [gm1 (ro2 ro4 )] [2gm3 RSS ]
2.4 × 10−3
= 318.3 MHz
2π × 1.2 × 10−12
From Eq. (12.31), we get
Gm2
fZ =
2πCC
where
=
⇒ |VOV | = 0.15 V
12.5 From Eq. (12.24), we have
gm1 =
ro2
I
|VOV |
2|VA |
= ro4 = |VA |/(I /2) =
I
gm3 =
I
|VOV |
RSS = ro5 =
|VA |
I
=
2.4 × 10−3
= 360 MHz
2π × 1.06 × 10−12
12.7 (a) A = Gm1 R1 Gm2 R2
= 1 × 100 × 2 × 50 = 10, 000 V/V
(b) Without CC connected:
1
1
=
ωP1 =
C1 R1
0.1 × 10−12 × 100 × 103
= 108 rad/s
Chapter 12–3
This figure belongs to Problem 12.7, part (b).
, dB
20 dB/decade
80
20 dB/decade
60
40 dB/decade
40
20
vt
v (rad/s)
0
105
104
vP1
(with CC)
106
107
vP2
108
vP1
without CC
109
1010
vZ vP2
with CC
Figure 1
ωP2 =
1
1
=
C2 R2
2 × 10−12 × 50 × 103
= 107 rad/s
Figure 1 shows a Bode plot for the gain
magnitude.
(c) With CC connected:
=
100 ×
ωP2
2 × 10−3
=
= 109 rad/s
2 × 10−12
×4×
10−12
1
× 2 × 10−3 × 50 × 103
105
rad/s = 25,000 rad/s
=
4
Using Eq. (12.31), we get
ωZ =
Using Eq. (12.35), we obtain
Gm2
=
C2
103
=
Gm2
CC
2 × 10−3
109
rad/s = 5 × 108 rad/s
=
4 × 10−12
2
The Bode plot for the gain magnitude with CC
connected is shown in Fig. 1.
For ωt two octaves below ωP2 , we have
ωt =
109
rad/s
4
12.8 Gm1 = 0.3 mA/V
Gm2 = 0.6 mA/V
Using Eq. (12.36), we get
ro2 = ro4 = 222 k
Gm2
ωt =
CC
ro6 = ro7 = 111 k
Thus,
1 × 10−3
109
=
4
CC
⇒ CC = 4 pF
Now using Eq. (12.34), we obtain
ωP1 =
1
R1 CC Gm2 R2
C2 = 1 pF
(a) A = Gm1 (ro2 ro4 )Gm2 (ro6 ro7 )
= 0.3(222 222) × 0.6(111 111)
= 33.3 × 33.3 = 1109 V/V
(b) fP2 =
=
Gm2
2πC2
0.6 × 10−3
= 95.5 MHz
2π × 1 × 10−12
Chapter 12–4
1
1
=
= 1.67 k
Gm2
0.6 × 10−3
ft
−1
(d) Phase margin = 180 − 90 − tan
fP2
ft
80◦ = 90 − tan−1
fP2
(c) R =
ft = fP2 tan10◦
= 95.5 × 0.176 = 16.8 MHz
Using Eq. (12.36), we obtain
CC =
Gm1
0.3 × 10−3
=
= 2.84 pF
2πft
2π × 16.8 × 106
The dominant pole will be at a frequency
16.8 × 106
ft
=
DC Gain
1109
fP1 =
= 15.1 kHz
(e) Since
ft =
Gm1
2πCC
to double ft , CC must be reduced by a factor of 2,
CC =
2.84
= 1.42 pF
2
At the new ft = 2 × 16.8 = 33.6 MHz, we have
ft
fP2
33.6
= −tan−1
= −19.4◦
95.5
φP2 = −tan−1
To reduce this phase lag to −10◦ , we need to
change R so that the zero moves to the negative
real axis and introduces a phase lead of 9.4◦ . Thus,
−1 ft
tan
fZ
◦
= 9.4
33.6
ft
fZ =
=
= 203 MHz
tan 9.4
0.166
fZ =
1
1
2πCC R −
Gm2
⇒R−
1
1
=
Gm2
2π × 203 × 106 × 1.42 × 10−12
= 552 Gm1
2πft
CC =
=
1 × 10−3
= 1.59 pF
2π × 100 × 106
(b) fP2 =
=
Gm2
2πC2
2 × 10−3
= 318 MHz
2π × 1 × 10−12
Gm2
2 × 10−3
=
2πCC
2π × 1 × 1.59 × 10−12
fZ =
= 200 MHz
To obtain fP1 , we need to know the dc gain of the
op amp, A0 , then
fP1 =
ft
A0
The value of A0 is not specified in the problem
statement!
ft
−1
(c) φP2 = −tan
fP2
100
= −17.5◦
= −tan−1
318
ft
φZ = −tan−1
fZ
−1 100
= −26.6◦
φZ = −tan
200
φtotal = 90◦ + 17.5 + 26.6 = 134◦
Phase margin = 180 − 134 = 46◦
(d) From Eq. (12.44), for
fZ = ∞
we select
R=
1
1
= = 0.5 k = 500 Gm2
2
Phase margin = 180◦ − (90◦ + 17.5◦ ) = 72.5◦
(e) To obtain a phase margin of 85◦ , we need the
left-half plane zero to provide at ft a phase angle
of 85◦ − 72.5◦ = 12.5◦ . Thus,
ft
12.5◦ = tan−1
fZ
ft
100
=
= 451 MHz
tan 12.5◦
tan 12.5◦
R = 1670 + 552 = 2222 fZ =
= 2.22 k
From Eq. (12.44), we have
−fZ =
12.9 (a) Using Eq. (12.36), we get
Gm1
ft =
2πCC
2πCC
⇒ R = 722 1
1
−R
Gm2
Chapter 12–5
12.10 Using Eq. (12.46), we obtain
SR = 2πft VOV 1,2
C2 =
5 × 10−3
= 1.51 pF
2π × 529 × 106
This is the maximum value that C2 can have; if C2
is larger, then fP2 will be lower; and the phase it
introduces at ft will increase, causing the phase
margin to drop below 70◦ .
= 2π × 100 × 106 × 0.2
= 125.6 V/μs
Using Eq. (12.45),
SR =
12.12 C2 = 0.7 pF.
I
CC
I
100 × 10−6
⇒ CC =
=
SR
125.6 × 106
= 0.8 pF
For a phase margin of 72◦ , the phase due to fP2 at
ft must be 18◦ ; thus,
ft
= tan 18◦
fP2
⇒ fP2 =
12.11 Gm1 = 1 mA, Gm2 = 5 mA/V
But
(a) Using Eq. (12.36), we obtain
fP2 =
ft =
Gm1
2πCC
⇒ CC =
Gm1
1 × 10−3
=
2πft
2π × 80 × 106
= 2π × 307.8 × 106 × 0.7 × 10−12
= 1.35 mA/V
Thus,
(b) Phase margin
=
ft
ft
◦
−1
90 − tan
− tan−1
fP2
fZ
where
gm6 = 1.35 mA/V
For the transmission zero to be at ∞,
R=
Gm2
2πC2
1
1
=
= 739 Gm2
1.35 × 10−3
SR = 2πft |VOV 1,2 |
and
fZ =
Gm2
2πC2
⇒ Gm2 = 2πfP2 C2
= 2 pF
fP2 =
= 2π × 100 × 106 × 0.15
Gm2
2πCC
= 94.2 V/μs
For a PM of 70◦ , we have
ft
ft
+ tan−1
= 20◦
tan−1
fP2
fZ
SR =
I
CC
⇒ CC =
But,
fZ =
and
tan−1
100
= 307.8 MHz
tan 18◦
5 × 10−3
= 398 MHz
2π × 2 × 10−12
ft
fZ
= tan−1
80
398
= 11.4◦
Thus,
ft
= 20 − 11.4◦ = 8.6◦
tan−1
fP2
ft
= tan 8.6◦
fP2
⇒ fP2 =
80
= 529 MHz
tan 8.6◦
Gm2
= 529 × 106
2πC2
100 × 10−6
I
=
= 1.06 pF
SR
94.2 × 106
12.13 SR = 60 V/μs, ft = 60 MHz
(a) Using Eq. (12.46), we obtain
SR = 2πft |VOV 1 |
⇒ |VOV 1 | =
60 × 106
= 0.16 V
2π × 60 × 106
(b) Using Eq. (12.45), we get
SR =
I
CC
⇒ CC =
120 × 10−6
I
=
= 2 pF
SR
60 × 106
(c) For Q1 and Q2 , we have
1
W
|VOV 1,2 |2
ID1,2 = μp Cox
2
L 1,2
Chapter 12–6
W
1
× 0.162
× 60 ×
2
L 1,2
W
W
⇒
=
= 78.1
L 1
L 2
60 =
2ID6
|VOV |
ro6 =
|VA |
ID6
Thus,
PSRR− =
12.14 Gm1 = 0.8 mA/V, Gm2 = 2 mA/V
1 2|VA |
I
2ID6
|VA |
× ×
×
×
|VOV | 2
I
|VOV |
ID6
VA 2
= 2 VOV (a) Using Eq. (12.36), we obtain
gm1
ft =
2πCC
⇒ CC =
gm6 =
Q.E.D.
(b) A PSRR− of 72 dB means
Gm1
0.8 × 10−3
=
= 1.27 pF
2πft
2π × 100 × 106
(b) Phase margin
=
ft
◦
−1
−1 ft
− tan
90 − tan
fP2
fZ
ft
ft
− tan−1
60◦ = 90 − tan−1
fP2
fZ
PSRR− = 4000
Thus,
|VA |2
0.152
⇒ |VA | = 6.71 V
4000 = 2
Now,
|VA | = |VA |L
Thus,
ft
ft
+ tan−1
= 30◦
tan−1
fP2
fZ
6.71 = 15L
⇒ L = 0.45 μm
where
Gm2
2πC2
fP2 =
fZ =
2πCC
=
1
1
−R
Gm2
1
2π × 1.27 × 10−12 (0.5 − 0.5) × 103
Thus,
ft
= 30◦
tan−1
fP2
ft
= 173.2 MHz
tan 30
We now can obtain C2 from
fP2 =
2 × 10−3
173.2 × 106 =
2πC2
⇒ C2 =
2 × 10−3
= 1.84 pF
2π × 173.2 × 106
12.15 (a) From Eq. (12.54), we have
PSRR− = gm1 (ro2 ro4 )gm6 ro6
where
I
I
2
=
=
|VOV |
|VOV |
2×
gm1
ro2 = ro4 =
12.16 For Q8 and Q9 , we have
1
W
|VOV 8,9 |2
IREF = μp Cox
2
L 8,9
|VA |
2|VA |
=
I /2
I
60
1
× 60 ×
× |VOV 8,9 |2
2
0.5
⇒ |VOV 8,9 | = 0.25 V
225 =
=∞
gm8 = gm9 =
2ID
2 × 0.225
=
|VOV |
0.25
= 1.8 mA/V
For Q10 , Q11 and Q12 , we have
gm = gm8 = 1.8 mA/V
2IREF
= 1.8
VOV
⇒ VOV = 0.25 V
and
W
1
× 180 ×
× 0.252
2
L
W
W
W
⇒
=
=
= 40
L 10
L 11
L 12
225 =
Using Eq. (12.61), we obtain
2
(W/L)12
−1
RB =
gm12
(W/L)13
√
2
4−1
1.8 × 10−3
= 1.11 k
=
Chapter 12–7
Voltage drop across RB = IREF × 1.11
VICM max = VDD − |VOV 9 | + Vtn
= 0.225 × 1.11 = 0.25 V
W
The
ratios of Q10 , Q11 and Q12 are given
L
above. For Q13 , we have
W
W
=4
L 13
L 12
W
⇒
= 160
L 13
= 1 − 0.15 + 0.4 = +1.25 V
VICM min = −VSS + |VOV 11 | + VOV 1 + Vtn
= −1 + 0.15 + 0.15 + 0.4 = −0.3 V
Thus,
−0.3 V ≤ VICM ≤ +1.25 V
v Omax = VBIAS1 + |Vtp |
= 0.3 + 0.4 = +0.7 V
DC voltage at gate of Q12
v Omin = −VSS + VOV 7 + Vtn + VOV 5
= −VSS + IREF RB + Vtn + VOV 12
= −1 + 0.15 + 0.4 + 0.15 = −0.3 V
= −1.5 + 0.25 + 0.5 + 0.25 = −0.5 V
Thus,
DC Voltage at gate of Q10
−0.3 V ≤ v O ≤ +0.7 V
= VG12 + Vtn + VOV 11
I
= 0.2 mA
2
W
1
× 0.04
0.2 = × 0.4 ×
2
L 1,2
W
W
=
= 25
⇒
L 1
L 2
= −0.5 + 0.5 + 0.25 = +0.25 V
12.19 ID1 = ID2 =
DC Voltage at gate of Q8
= VDD − |Vtp | − |VOV 8 |
= 1.5 − 0.5 − 0.25 = +0.75 V
12.17 2IB × 2 = 1 mW
IB =
I
= 250 − 200 = 50 μA
2
W
1
× 0.04
50 = × 100 ×
2
L 3,4
W
W
=
= 25
⇒
L 3
L 4
ID3 = ID4 = IB −
10−3
= 0.25 mA = 250 μA
4
ID1 = 4ID3
ID1 + ID3 = IB
5ID3 = 250 μA
ID5 = ID6 = ID7 = ID8 = 50 μA
W
1
× 0.04
50 = × 400 ×
2
L 5−8
W
W
W
W
⇒
=
=
=
L 5
L 6
L 7
L 8
ID3 = 50 μA, ID4 = 50 μA
ID1 = 200 μA, ID2 = 200 μA
I = 400 μA
12.18 VBIAS1 = VDD − |VOV 9 | − |VOV 3 | − |Vtp |
= 6.25
= 1 − 0.15 − 0.15 − 0.4 = +0.3 V
VBIAS3 = −VSS + VOV 11 + Vtn
ID9 = ID10 = IB = 250 μA
W
1
× 0.04
250 = × 100 ×
2
L 9,10
W
W
=
= 125
⇒
L 9
L 10
= −1 + 0.15 + 0.4 = −0.45 V
ID11 = I = 400 μA
VBIAS2 = VDD − |VOV 9 | − |Vtp |
= 1 − 0.15 − 0.4 = +0.45 V
This table belongs to Problem 12.19.
Transistor Q1
W/L
25
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
25
25
25 6.25 6.25 6.25 6.25 125 125
50
Chapter 12–8
1
× 400 ×
2
W
⇒
= 50
L 11
400 =
W
L
11
10 × 106 =
Summary: See table on previous page.
12.20 Gm = gm1 = gm2 =
=
2(I /2)
VOV
IB
10 × 10−12
⇒ IB = 10−4 A = 0.1 mA = 100 μA
I
I
= 3 IB −
2
2
I
(1 + 3) = 3IB = 300
2
I
0.4
= 2 mA/V
=
VOV
0.2
I
= 0.25 − 0.2 = 0.05 mA
2
2 × 0.05
2ID4
=
= 0.5 mA/V
=
|VOV |
0.2
ID4 = IB −
gm4
IB
CL
12.21 SR =
× 0.04
I = 150 μA
Now,
ft =
Gm
2πCL
ro4 =
|VA |
10
= 200 k
=
ID4
0.05
where
ro2 =
|VA |
10
|VA |
=
= 50 k
=
ID2
I /2
0.2
Gm = gm1,2 =
ro10 =
|VA |
|VA |
10
= 40 k
=
=
ID10
IB
0.25
Ro4 = (gm4 ro4 ) (ro2 ro10 )
=
2(I /2)
I
=
VOV 1,2
VOV 1,2
0.15 mA
= 1 mA/V
0.15 V
Thus,
= 0.5 × 200 (50 40)
ft =
= 2.22 M
1 × 10−3
2π × 10−12
ID6 = 50 μA = 0.05 mA
= 15.92 MHz
2 × 0.05
= 0.5 mA/V
0.2
|VA |
10
=
= 200 k
ro6 =
ID6
0.05
Phase due to the two nondominant poles at ft
15.92
= −2 tan−1
= −35.3◦
50
gm6 =
ro8 =
Thus,
|VA |
10
= 200 k
=
ID8
0.05
Phase margin = 90 − 35.3 = 54.7◦
Ro6 = gm6 ro6 ro8
To increase the phase margin to 75◦ , the phase
due to the two nondominant poles must be
reduced to 90 − 75 = 15◦ , i.e. each should
contribute 7.5◦ , thus we must reduce ft to the
value obtained as follows:
ft
tan−1
= 7.5◦
50 MHz
= 0.5 × 200 × 200 = 20 M
Ro = Ro4 Ro6
= 2.22 20 = 2 M
Av = Gm Ro
= 2 × 2000 = 4000 V/V
ft = 50 × tan 7.5◦ = 6.58 MHz
For the closed-loop amplifier:
This is achieved by increasing CL ,
A = Av = 4000
β=
C
= 0.1
C + 9C
6.58 × 106 =
A
4000
Vo
= Af =
=
Vi
1 + Aβ
1 + 4000 × 0.1
4000
= 9.975 V/V
401
Ro
2 M
=
Rout = Rof =
1 + Aβ
401
=
⇒ CL =
1 × 10−3
2πCL
10−3
= 24.2 pF
2π × 7.92 × 106
The new value of slew-rate will be
5 k
SR =
0.1 × 10−3
IB
=
= 4.13 V/μs
CL
24.2 × 10−12
Chapter 12–9
Ro = Ro4 Ro6
4 |VA |2
|VA |2
=
3 |VOV |I
|VOV |I
12.22 Refer to Fig. 12.9. When Vid is sufficiently
large to cause Q1 to cut off and Q2 to conduct all
of I , Q3 will carry a current IB . However, Q4 will
carry (IB − I ). The current IB in Q3 will be
mirrored in the drain of Q6 . Thus, at the output
node the current available to charge CL will be
=
IO = IB − (IB − I ) = I
The voltage gain can now be found as
and the slew rate becomes
A = Gm Ro = gm1,2 Ro
I
SR =
CL
=
|VA |2
I
|VOV | |VOV |I
=
|VA |2
|VOV |2
12.23 A = 80 dB ≡ 104 V/V
ft = 20 MHz, CL = 10 pF
IB = I
|VA | = 12 V
Refer to Figs. 12.9 and 12.10. For I = IB , the dc
operating currents of the 11 transistors are as
follows:
Q1 − Q8 :
I
2
|VA |2
|VOV |I
V A 2
10,000 = VOV ⇒
|VA |
= 100
|VOV |
12
= 0.12 V
100
To obtain ft = 20 MHz, we use
gm1,2
20 × 106 =
2π × 10 × 10−12
⇒ |VOV | =
Q9 , Q10 , and Q11 : I
gm1,2 = 2π × 10 × 10−12 × 20 × 106
Thus, for Q1 − Q8 , we have
= 1.257 × 10−3 A/V
gm =
I
|VOV |
Thus,
2|VA |
I
⇒ I = 1.257 × 0.12 × 10−3
I
= 1.257 × 10−3
|VOV |
and
ro =
while, for Q9 − Q11 ,
ro =
|VA |
I
I
=
VOV
Ro4 = (gm4 ro4 ) (ro2 ro10 )
2|VA | 2|VA | |VA |
I
×
=
|VOV |
I
I
I
=
2 |VA |
2|VA |
×
|VOV | 3 I
=
4|VA |2
3|VOV |I
Ro6 = gm6 ro6 ro8
=
2|VA | 2|VA |
I
|VOV | I
I
4|VA |2
=
|VOV |I
IB = I = 150 μA
SR =
Now,
Gm = gm1,2
= 0.15 mA = 150 μA
150 × 10−6
IB
=
CL
10 × 10−12
= 15 V/μs
For Q1 and Q2 , we have
1
I
W
= 75 μA = k n
V2
2
2
L 1,2 OV
W
1
75 = × 400 ×
× 0.122
2
L 1,2
W
W
⇒
=
= 26
L 1
L 2
ID =
For Q3 and Q4 , we have
ID = IB −
I
= 150 − 75 = 75 μA
2
Thus,
75 =
1 400
×
×
2
2.5
W
L
× 0.122
3,4
Chapter 12–10
Summary (Approximate Values):
Transistor Q1
W/L
⇒
W
L
26
=
3
W
L
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q10
Q11
26
65
65
26
26
26
26 130 130
52
Q9
= 65.1
4
For Q5 , Q6 , Q7 , and Q8 , we have
Thus,
−1.3 V ≤ VICM ≤ +0.25 V
(c) The overlap range is
ID = IB = 75 μA
1
W
× 400 ×
× 0.122
2
L 5−8
W
W
W
W
⇒
=
=
=
= 26
L 5
L 6
L 7
L 8
75 =
−0.25 V ≤ VICM ≤ +0.25 V
(d) −1.3 V ≤ VICM ≤ +1.3 V
For Q9 and Q10 , we have
12.25 First we determine VOV :
ID = IB = 150 μA
90 =
1 400
W
×
×
× 0.122
2
2.5
L 9,10
W
W
⇒
=
= 130.2
L 9
L 10
150 =
1
2
× 400 × 20 VOV
2
⇒ VOV = 0.15 V
VBIAS = Vt + 2VOV = 0.45 + 2 × 0.15
= 0.75 V
For Q11 , we have
ID = I = 150 μA
1
× 400 ×
2
W
⇒
= 52
L 11
150 =
W
L
× 0.122
11
See table above for a summary.
12.24 (a) Refer to Fig. 12.12. For the NMOS
input stage
Figure 1
VICM max = VDD − |VOV | + Vtn
= 1 − 0.15 + 0.45 = +1.3 V
VICM min = −VSS + VOV + VOV + Vtn
= −1 + 0.15 + 0.15 + 0.45
Figure 1 shows the voltages at the various nodes
in the mirror circuit. The minimum voltage
allowable at the output terminal is
= −0.25 V
v Omin = VBIAS − Vtn
Thus,
= 0.75 − 0.45 = 0.3 V
−0.25 V ≤ VICM ≤ +1.3 V
which is 2VOV .
(b) For the PMOS input stage
The output resistance is
VICM max = VDD − |VOV | − |Vtp |
Ro
= 1 − 0.15 − 0.15 − 0.45 V
where
= +0.25 V
ro1 = ro3 =
gm3 ro3 ro1
VICM min = −VSS + VOV − |Vtp |
VA
10
= 111.1 k
=
ID
0.09
2ID
2 × 0.09
= 1.2 mA/V
=
VOV
0.15
= −1 + 0.15 − 0.45
gm3 =
= −1.3 V
Ro = 1.2 × 111.1 × 111.1 = 14.8 M
Chapter 12–11
12.26 Since Q3 is operating in the common-gate
configuration and since the resistance in its drain
is low, the input resistance at its source is 1/gm3 .
This resistance appears in parallel with ro1 which
is much larger. Thus, the total resistance at this
node is 1/gm3 and since the total capacitance is
CP , the pole introduced will have a frequency
1
gm3
=
2πCP /gm3
2πCP
fP
Q.E.D.
VBE2 = VT ln
I1
IS2
VBE3 = VT ln
I3
IS3
VBE4 = VT ln
I3
IS4
I1
IS1
VBE3 + VBE4 = VBE1 + VBE2
Now,
ft =
12.28 VBE1 = VT ln
gm1
2πCL
where gm1 = gm3 because all transistors are
operating at the same values of ID and |VOV |.
For a phase margin of 80◦ the phase at ft
introduced by the pole at fP must be only 10◦ ,
ft
= 10◦
tan−1
fP
VT ln
I3
I3
I1
I1
+ VT ln
= VT ln
+ VT ln
IS3
IS4
IS1
IS2
VT ln
I32
I2
= VT ln 1
IS3 IS4
IS1 IS2
⇒
I32
I2
= 1
IS3 IS4
IS1 IS2
⇒ I3 = I1
IS3 IS4
IS1 IS2
Q.E.D.
√
150 = I1 3 × 3 = 3I1
ft
ft
=
tan 10◦
0.176
gm1
gm3
=
2πCP
2πCL × 0.176
fP =
⇒ I1 = 50 μA
⇒ CP = 0.176CL
12.29 For the A and B devices, we have
This is the largest value that CP can have.
VEB = VT ln
0.73 × 10−3
10−14
= 625 mV
12.27 For each transistor we use
IC
VBE = VT ln
IS
IC
= 25 ln
10−14
For the A device, we have
gmA =
ICA
0.25 × 0.73
=
= 7.3 mA/V
VT
0.025
reA
1
= 137 gmA
gm =
IC
IC
=
VT
0.025 V
rπA =
β
50
= 6.85 k
=
gmA
7.3
re
1
gm
roA =
|VA |
50
= 278 k
=
ICA
0.18
rπ = β/gm = 200/gm
For the B device, we have
ro = VA /IC = 125/IC
We obtain the following results:
Q1
Q2
Q5
Q6
Q16
Q17
9.5
9.5
9.5
9.5 16.2
550
517 517 517 517 530
618
gm (mA/V) 0.38 0.38 0.38 0.38 0.65
22
IC (μA)
VBE (mV)
gmB =
ICB
0.75 × 0.73
=
= 21.9 mA/V
VT
0.025
reB
1
= 46 gmB
rπB =
β
50
=
= 2.28 k
gmB
21.9
roB =
|VA |
50
= 90.9 k
=
ICB
0.55
re (k)
2.63 2.63 2.63 2.63 1.54 0.045
12.30 VSG1 = |Vtp | + |VOV 1 |
rπ (k)
526 526 526 526 308
VGS2 = Vtn + VOV 2
ro (M)
13.2 13.2 13.2 13.2 7.72 0.227
9.1
VGS3 = Vtn + VOV 3
Chapter 12–12
VSG4 = |Vtp | + |VOV 4 |
= 25 ln
But,
VBEO = VT ln
VSG1 + VGS2 = VGS3 + VSG4
⇒ |VOV 1 | + VOV 2 = VOV 3 + |VOV 4 |
= 25 ln
Since
|VOV 1 | =
2I1 /k2
VOV 3 =
2I3 /k3
|VOV 4 | =
then
IO
IS
10 × 10−6
10−14
= 603 mV
= 518 mV
2I1 /k1
VOV 2 =
0.3 × 10−3
10−14
VBER − VBEO = 603 − 518 = 85 mV
R=
85 mV
= 8.5 k
10 μA
2I3 /k4
1
1
√ +√
k1
k2
⎡
1
√ +
⎢ k1
⇒ I3 = I1 ⎢
⎣ 1
√ +
k3
=
2I1
2I3
1
1
√ +√
k3
k4
⎤2
1
√
k2 ⎥
⎥
1 ⎦
√
k4
12.33 Refer to Fig. 12.15.
(a) A node equation at X yields
2I
2I
+
= IC10
1 + 2/βP
βP
For k1 = k2 and k3 = k4 = 16 k1 , we have
√ 2
2/ k1
= 16 I1
I3 = I1
√
2/ k3
2
βP + 1 +
βP
= IC10
2I
2
βP 1 +
βP
IC10 βP (βP + 2)
I=
2 βP2 + βP + 2
For I3 = 1.6 mA, we have
For βP = 50, we have
I1 = 0.1 mA
I=
IC10
× 1.019
2
For βP = 20, we have
12.31 Differential input breakdown voltage
I=
= 0.6 + 0.6 + 50 + 7
IC10
× 1.043
2
= 58.2 V
Thus, I increases by
where we have assumed that a forward
conducting transistor exhibits |VBE | = 0.6 V.
(b)
IC10
× 0.024, which is 2.4%.
2
12.32
IREF
IO
QO
QR
R
Figure 1
Figure 1
Refer to Fig. 1,
IREF = 0.3 mA, IO = 10 μA
VBER = VT ln
IREF
IS
Figure 1 shows the suggested alternative design.
As shown, here
I
1
βP IC10
2
Chapter 12–13
For βP = 50, we have
Thus,
I = 25IC10
2nI = IC10
For βP = 20, we have
For I = 10 μA and IC10 = 40 μA, we have
I = 10IC10
n=2
Thus, I changes by −15IC10 , which is −60%
change! This is a result of the absence of the
desensitivity effect of negative feedback.
12.36 Figure 1 shows the circuit when R3 is
adjusted so that IC5 = IC6 = IC7 . Denoting the
new value of these three currents I1 , we obtain the
various currents indicated in Fig. 1. Now, at the
input node X, we have
1
I1 1 +
= 9.5 μA
βN
12.34 Refer to Fig. 12.15.
For IS9 = 2IS8 , the collector current of Q9 will be
IC9 =
4I
1+
2
βP
⇒ I1 =
If βP is large, a node equation at X yields
4I
9.5
= 9.45 μA
1 + (1/200)
At this collector current, we have
IC10
9.45 × 10−6
= 516.7 μA
10−14
The voltage drop across R3 becomes
1
R1
VR3 = VBE5 + I1 1 +
βN
VBE = 25 ln
1
19
= 4.75 μA
⇒ I = IC10 =
4
4
To establish IC1 = IC2 = 9.5 μA, we need to
redesign the Widlar source to provide
IC10 = 38 μA. From Eq. (12.86), we obtain
= 516.7 + 9.5 × 1
IREF
= IC10 R4
VT ln
IC10
= 526.2 mV
730
= 38R4
38
⇒ R4 = 1.94 k
The value of R3 can now be found as
12.35 Refer to Fig. 12.15. For βP large, a node
equation at X yields
= 56 k
IC9
12.37 Refer to the circuit in Fig. 12.16. The
current in Q5 remains equal to
25 × ln
VR3
526.2
=
R3 = 1
1
I1 1 −
9.45 1 −
βN
200
IC10
If the ratio of the area of Q9 to that of Q8 is n, then
I = 9.5 μA
IC9 = n × 2I
This figure belongs to Problem 12.36.
9.5 A
I1
I1/BN
Q7
X
I1
(
1
I1 1
bN
Q5
)
R1 1 k
I1/BN
(
I1 1– 1
bN
(
I1 1
I1/BN
)
Y
1
bN
)
I1
Q6
(
I1 1
R3
VEE
Figure 1
1
bN
R2 1 k
)
Chapter 12–14
The voltage between the base of Q5 and −VEE is
= VBE5 + IR1
9.5 × 10−6
= 25 ln
+ 9.5 × 1
10−14
= 517 + 9.5 = 526.5 mV
With R2 shorted, this voltage appears across the
BE junction of Q6 . Thus,
IC6 = IS eVBE6 /VT
= 10−14 e526.5/25
12.40 VC1 = VCC − VEB8 = 5 − 0.6 = 4.4 V
Q1 and Q2 saturate when VICM exceeds VC1 by
0.4 V. Thus,
VICM max = +4.8 V
VC5
−VEE + VBE5 + VBE7
= −5 + 0.6 + 0.6 = −3.8 V
Q3 and Q4 saturate when
VB3 = VC5 − 0.4 = −4.2 V
= 14 μA
But,
12.38 2I = 19 μA
VB3 = VICM − VBE1 − VEB3
Assuming
= VICM − 1.2
IC1 = IC2 = I = 9.5 μA
Thus,
then
IB1 =
9.5
= 63.3 nA
150
IB2 =
9.5
= 43.2 nA
220
1
IB = (IB1 + IB2 ) = 53.3 nA
2
VICM min = VB3 + 1.2
= −4.2 + 1.2 = −3.0 V
Thus,
−3 V ≤ VICM ≤ +4.8 V
IOS = |IB1 − IB2 | = 20.1 nA
12.41 IC18 + IC19 = 0.25 × 0.73 = 180 μA
12.39 Refer to Fig. 12.14 and to Exercise 12.21.
From the answers to Exercise 12.21, we find that
Require
VBE17 = 618 mV
IC18 = IC19 = 90 μA
IE17
IC17 = 550 μA
IB17 =
550
= 2.75 μA
200
Voltage across R9 = VBE17 + IE17 R8
= 618 + 550 × 0.1
VR9
R9
For IC16 = 9.5 μA, we have
IE16
90 × 10−6
10−14
= 573 mV
Current through R10 = IC19 + IB19 − IB18
IC19 = 90 μA
= 673 mV
IE16 = IB17 +
VBE18 = 25 ln
9.5
= 9.55 μA
= 9.5 +
200
Thus,
673 (mV)
9.55 = 2.75 +
R9 (k)
⇒ R9 = 98.9 k
R10 =
573
= 6.4 k
90
VBB = VBE18 + VBE19
= 2 × 0.573 = 1.146 V
Since VBB appears across the series combination
of Q14 and Q20 , we can write
VBB = VT ln
IC14
IC20
+ VT ln
IS14
IS20
Chapter 12–15
Substituting VBB = 1.146 V,
IS14 = IS20 = 3 × 10−14 , we obtain for the equal
currents IC14 and IC20
1.146 = 2 × 0.025 ln
IC14
3 × 10−14
Ix
R2
Vx
⇒ IC14 = IC20 = 270 μA
B
rp
R1
Vp
C
gmVp
12.42
E
I 180 A
R2
90.55 A
R1
90 A
0.45 A
VBB 1.118 V
90 A
Figure 1
Refer to Fig. 1.
180
= 90 μA
=
2
90
IB =
= 0.45 μA
201
IC =
=
βN
IE
βN + 1
200
× 90 = 89.55 μA
201
VBE = VT ln
= 25 ln
Figure 2
89.55 A 180 A
IE = IR1
r
Vx
Ix
IC
IS
89.55 × 10−6
10−14
= 573 mV
To determine the incremental resistance between
the two terminals of the VBE multiplier, we
replace the transistor with its hybrid-π model, as
shown in Fig. 2. Here
gm =
IC
89.55 μA
= 3.6 mA/V
=
VT
25 mV
rπ =
β
200
=
= 55.6 k
gm
3.6
R1 rπ = 6.37 55.6 = 5.7 k
Vπ = Vx
R1 rπ
(R1 rπ ) + R2
= Vx
5.7
= 0.49 Vx
5.7 + 6.03
Ix =
Vx
+ gm × 0.49 Vx
5.7 + 6.03
= Vx (0.085 + 1.764)
r≡
1
Vx
= 0.541 k
=
Ix
0.085 + 1.764
= 541 12.43 Refer to Fig. 12.14 and Table 12.1. The
current ICC drawn from VCC can be found as
follows:
ICC = IE12 + IE13 + IC14 + IE9 + IE8 + IC7 + IC16
573 mV
R1 =
= 6.37 k
90 μA
Assuming βP and βN
IR2 = IR1 + IB = 90 + 0.45 = 90.45 μA
ICC = 730 + 730 + 154 + 19 + 19 + 10.5
VR2 = VBB − VR1 = 1.118 − 0.573
= 0.545 V
545 mV
R2 =
= 6.03 k
90.45 μA
1,
+ 16.2
= 1678.7 μA = 1.68 mA
PD = ICC (VCC + VEE )
= 1.68(15 + 15) = 50.4 mW
Chapter 12–16
To find Ro4 , refer to the circuit in Fig. 2.
12.44
Ro4 = ro4 [1 + gm4 (2 re rπ4 ]
where
50 V
= 5.26 M
9.5 μA
ro4 =
gm4 = 0.38 mA/V
50
= 131.6 k
0.38
Ro4 = 5.26[1 + 0.38(5.26 131.6)]
rπ4 =
= 15.4 M
Ro1 = Ro4 Ro6
= 15.4 18.2 = 8.33 M
Open-circuit voltage gain = Gm1 Ro1
= 0.13 × 8.33 × 103 = 1083 V/V
Figure 1
Figure 1 shows the input stage with the two extra
diode-connected transistors Q1a and Q2a . Since
these devices are simply in series with Q1 − Q4 ,
they will have the same dc bias current, namely
9.5 μA. Thus, each of Q1a and Q2a will have an
incremental resistance equal to re of each of Q1
to Q4 ,
re =
Comparison
Original
Design
Modified
Design
Rid (k)
2.1
3.2
Gm1 (mA/V)
0.19
0.13
Ro4 (M)
10.5
15.4
Ro1 (M)
6.7
8.3
|Av o | (V/V)
1273
1083
25 mV
= 2.63 k
9.5 μA
The input differential resistance Rid now becomes
Rid = (βN + 1) × 6re
= 201 × 6 × 2.63
= 3.2 M
The effective transconductance of the input stage,
Gm1 , now becomes
Gm1 ≡
2αie
v id
Thus the input resistance increases but the gain
decreases: The additional diodes introduce
negative feedback in the input stage; same effect
as adding a resistance in the emitter of a
common-emitter amplifier.
12.45 From Fig. 12.20(b) and Eq. (12.91), we get
Ro6 = ro6 [1 + gm6 (R2 rπ6 )]
=
2αie
1
= gm1
6ie re
3
=
1 9.5 μA
= 0.13 mA/V
3 25 mV
where
125 V
= 13.6 M
9.5 μA
ro6 =
9.5 μA
= 0.38 mA/V
25 mV
200
= 526.3 k
rπ6 =
0.38
1 + 0.38(R2 526.3)
Ro6 (modified)
=
Ro6 (original)
1 + 0.38(1 526.3)
gm6 =
2
1 + 0.38 R2
1 + 0.38
⇒ R2 = 4.63 k
Figure 2
Thus, R2 must be increased by a factor of 4.63.
Chapter 12–17
Substituting for Gm1 by
12.46 Refer to Fig. 12.19.
(a) v b6 = ie6 (re6 + R2 )
1
1 I
gm1 =
2
2 VT
Gm1 =
= ie (re6 + R2 )
where
we obtain
25 mV
= 2.63 k
re6 =
9.5 μA
I
v b6 = ie (2.63 + 2) = 4.63 k × ie
=
v b6
2αie
+
R3
β
re =
2
4.63
ie +
ie
50
201
= 0.1ie
ie7
0.1
(c) ib7 =
=
ie = 0.0005ie
βN + 1
201
25 mV
= 2.63 k and R = 1 k
9.5 μA
3
1 + (2.63/1)
R
=
R
2 × 25 1 − (3/50)
R
= 0.23
R
= 0.1 × 2.38ie + 4.63ie
= 4.89ie
or 23%
v b7
(e) Rin ≡
αie
For VOS = −3 mV, we have
4.9 k
12.47 Output current of first stage = (1 − 0.8)I
= 0.2I
0.2I
Gm1
R
= −0.205 or − 20.5%
R
(c) The maximum offset voltage than can be
trimmed this way corresponds to R2 completely
shorted, that is, R = −R, thus
−1 =
where
1
1 I
gm1 =
2
2 VT
VOS 1 + 2.63
VOS
2VT
1−
2VT
⇒ VOS = −
Thus,
VOS =
0.2I
0.5I /VT
2VT
= −19 mV
2.63
12.49
= 0.4 × VT = 10 mV
12.48 Refer to Fig. 12.22 which shows the
situation when R1 = R and R2 = R + R. The
result of this mismatch is an output current I
given by Eq. (12.94):
I =I
R+
R
R + re
(1)
If we have an input offset voltage VOS , this offset
results in an output current I given by
I = Gm1 VOS
(2)
The offset can be nulled by introducing a
mismatch R that results in an equal magnitude
and opposite polarity output current. The required
R can be found by equating (1) and (2), thus
I
R+
Q.E.D.
then
(d) v b7 = ie7 re7 + v b6
Gm1 =
VOS
R
1 + re /R
=
R
2VT 1 − VOS /2VT
(b) For VOS = 3 mV and recalling that
=
VOS =
R+
⇒
(b) ie7 = iR3 + ib5 + ib6
R
1 I
=
VOS
R + re
2 VT
R
= Gm1 VOS
R + re
Figure 1
Chapter 12–18
Figure 1 (see preceding page) shows the analysis
when the β of Q4 is reduced to 10. The output
current of the mirror is
I = 0.691 μA
which corresponds to an input offset voltage of
VOS =
Thus, io of the mirror becomes
io = 2.38αie
with the result that the gain of the 741 increases
2.38
= 1.19.
by a factor of
2
I
1
, where Gm1 = gm1 = 0.19 mA/V
Gm1
2
(c) If both R1 and R2 are shorted, the gain
remains unchanged.
0.691
= 3.6 mV
0.19
12.52 Please note that an error occurred in the
first printing of the text: Q9 is biased at 19 μA.
With a resistance R in the emitter of Q9 , Ro9
becomes
Thus,
VOS =
12.50 From Eq. (12.102) we have
CMRR = gm1 (Ro9 Ro10 )/m
Ro9 = ro9 [1 + gm9 (R rπ9 )]
where
where
gm1 = 0.38 mA/V
Ro9 = 2.63 M
Ro10 = 31.1 M
m = 1 − 0.995 = 0.005
Thus,
CMRR = 0.38(2.63 31.3) × 103 /0.005
= 1.84 × 105
or 105.3 dB
ro9 =
|VAp |
50 V
= 2.63 M
=
IC9
19 μA
gm9 =
IC9
19 μA
=
= 0.76 mA/V
VT
0.025 V
rπ9 =
βP
50
= 65.8 k
=
gm9
0.76
Thus, to obtain Ro9 = Ro10 = 31.1 M, we use
31.1 = 2.63[1 + 0.76(R 65.8)]
⇒ R = 18.2 k
Thus, Ro to the left of node Y becomes
12.51 Refer to Fig. 12.19.
(a) If R1 is short-circuited, the incremental
transfer ratio of the mirror can be found as
follows:
Ro = 31.1 M 31.1 M = 15.55 M
12.53
ie5 re5 = ie6 (re6 + R2 )
Thus,
ie6
re5
2.63
ic6
=
=
=
ic5
ie5
re5 + R2
2.63 + 1
= 0.72
Thus, the output current of the mirror becomes
io = 1.72αie
rather than 2αie . Thus, the gain of the 741 will be
1.72
= 0.86.
reduced by a factor of
2
(b) If R2 is short-circuited, then
ie5 (re5 + R1 ) = ie6 re6
⇒
ic6
ie6
re5 + R1
=
=
ic5
ie5
re6
=
2.63 + 1
= 1.38
2.63
Figure 1
Chapter 12–19
Figure 1 (see previous page) shows the input
stage with the approach suggested for
determining Gmcm . Here
Rf = Ro (1 + Aβ) = Ro (1 + βP )
βP Ro
=
IC13B
R13B
IC13A
=
550
× 366 = 1.12 k
180
IE13B
R13B
IE12
A node equation at the common bases of the Q3
and Q4 yields
R12 =
v icm
2i
=
βP
Rf
=
IC13B
R13B
IC12
=
550
× 366 = 275 730
⇒i=
βP
v icm
2Rf
βP
v icm
2βP Ro
v icm
=
2Ro
=
12.55 Using Eq. (12.110), we obtain
v Omax = VCC − |VCEsat | − VBE14
= 5 − 0.2 − 0.6 = +4.2 V
Thus,
io = m i =
m
v icm
2Ro
and
Gmcm
Using Eq. (12.111), we get
v Omin = −VEE + |VCEsat | + VEB23 + VBE20
= −5 + 0.2 + 0.6 + 0.6 = −3.6 V
io
m
≡
=
v icm
2Ro
which is the same result [Eq. (12.100)]
obtained by the alternative approach of
Example 12.5.
12.54 Refer to the results of Exercise 12.32. We
need to raise ro13B from 90.9 k to 722 k by
inserting a resistance R13B in the emitter of Q13B .
Since
Ro13B = ro13B [1 + gm13B (R13B rπ 13B ]
Thus,
−3.6 V ≤ v O ≤ +4.2 V
12.56 Refer to Fig. P12.56.
Rout = re14 +
where
re14 =
25 mV
=5
5 mA
where
rAA = 163 ro13B = 90.9 k
re23 =
gm13B =
rπ 13B =
0.55 mA
= 22 mA/V
0.025 V
βP
gm13B
=
50
= 2.27 k
22
Thus,
rAA + re23 + [Ro2 /(βP + 1)]
β14 + 1
25 mV
= 139 0.18 mA
Ro2 = 81 k
βP = 50
β14 = 200
Thus
722 = 90.9[1 + 22(R13B 2.27)]
⇒ R13B = 366 Rout = 5 +
163 + 139 + (81000/51)
201
= 14.4 The resistors in the emitters of Q13A and Q12 must
be of values that will result in
IE13B R13B = IE12 R12 = IE13A R13A
Thus,
R13A =
IE13B
R13B
IE13A
12.57 Refer to Fig. 12.25 and Example 12.6 with
Q23 having its emitter and base shorted together.
In such a situation the input resistance of the
output stage becomes
Rin3 = (β20 RL ) (ro13A + rAA )
(1)
Chapter 12–20
IE14
21.85
= 108.7 μA
=
βN + 1
201
where we have assumed the situation with v O
negative and Q20 supplying the load current.
IB14 =
In Eq. (1),
Iteration #2:
β20 = 50
IC15 = 180 − IB14 = 180 − 108.7 = 71.3 μA
RL = 2 k
VBE15 = 25 ln
ro13A =
|VAp |
50
=
= 280 k
IC13A
0.18
and rAA is the incremental resistance of the
Q18 − Q19 bias network; very small ( 160 ).
Thus,
IE14 =
567.2
= 21 mA
27
IB14 =
21 mA
= 104.5 μA
201
Iteration #3:
(50 × 2) 280
Rin3
71.3 × 10−6
= 567.2 mV
10−14
= 74 k
IC15 = 180 − 104.5 = 75.5 μA
The gain of the second stage becomes
VBE15 = 25 ln
A2 =
v i3
Rin3
= −Gm2 Ro2
v i2
Rin3 + Ro2
= −6.5 × 81 ×
IE14 =
74
74 + 81
75.5 × 10−6
= 568.6
10−14
568.6
= 21.06 mA
27
which is very close to the value found in Iteration
#2; thus, no further iterations are necessary and
= −215.4 V/V
IE14
Compare to the value with Q23 included
(−515 V/V).
21 mA
12.59 Refer to Fig. 12.14.
12.58
Maximum current available from input stage
= 19 μA
Q13A
IC22 = 19 μA
180 A
IB14
VBE22 = 25 ln
Q14
IC15
Q15
0
= 534 mV
IE14
VBE24 = 534 mV
IE14
IC24 = 19 μA
R6
27 IR11 =
out
Figure 1
Refer to Fig. 1.
Iteration #1:
IC15 = 180 μA
VBE15
IE14
180 × 10−6
= 25 ln
= 590 mV
10−14
VBE15
590 mV
= 21.85 mA
=
=
R6
27 19 × 10−6
10−14
534 mV
= 10.7 μA
50 k
IC21 = IC24 + IR11
= 19 + 10.7 = 29.7 μA
VEB21 = 25 ln
29.7 × 10−6
10−14
= 545.3 mV
IR7 =
545.3
= 20.2 mA
27
This is the maximum current that the 741 can
sink. To reduce this current limit to 10 mA, we
need to double the value of R7 .
Chapter 12–21
12.60 The factor 0.97 is simply
=
12.64
RL
RL + Rout
Thus, for RL = ∞,
A0 = 243, 147/0.97 = 250, 667 V/V
This is the open-circuit voltage gain. The output
resistance is found from
2
= 0.97
2 + Rout
⇒ Rout = 62 Figure 1
The gain with RL = 500 is
A0 = 250, 667 ×
500
500 + 62
= 223, 013 V/V
For a phase margin of 85◦ with a closed loop gain
of 100, the phase at f1 due to the pole at 5 MHz
must be at most 5◦ ; thus,
12.61 If the phase margin is 80◦ , the phase due to
the second pole fP2 at the unity gain frequency ft
must be 10◦ . Thus,
tan−1
ft
= 10◦
fP2
tan−1
Since ft = 1 MHz,
1 MHz
= 5.67 MHz
tan 10◦
fP2 =
12.62 The phase introduced at ft = 1 MHz by
each of the coincident second and third poles
must be 5◦ . Thus, fP2 = fP3 can be obtained from
ft
= 5◦
fP2
tan−1
⇒ fP2 = fP3
1 MHz
=
= 11.4 MHz
tan 5◦
⇒ f1 = 5 × tan 5◦ = 437 kHz
Thus, the new dominant pole must be at fD ,
fD ×
A0
= 437
100
fD ×
243, 147
= 437
100
⇒ fD = 180 Hz
To find the required value of CC , we use
Eq. (12.116) to determine Cin :
Cin = CC (1 + |A2 |)
= CC × 516
Then,
fD =
12.63 fP =
ft
5 MHz
=
= 5 Hz
A0
106
1
2πCin Rt
where
Rt = 2.5 M
But,
fP =
f1
= 5◦
5 MHz
1
2πCR
where
180 =
1
2π × 516CC × 2.5 × 106
⇒ CC = 0.7 pF
C = (1 + |A|)CC
= (1 + 1000) × 50
= 50.05 nF
1
5=
2π × 50.05 × 10−9 × R
⇒ R = 636 k
12.65 DC gain A0 = Gm1 R
= 2 × 10−3 × 2 × 107
= 4 × 104 V/V
20 log A0 = 92 dB
Chapter 12–22
1
2πCC R
fP =
=
1
2π × 100 × 10−12 × 2 × 107
= 79.6 Hz
106
= 159.2 kHz
2π
fM =
80 Hz
If the topology is similar to that of the 741, then
we can use Eq. (12.126),
SR = 4VT ωt
ft = A0 fP = 4 × 104 × 80
⇒ ωt =
= 3.2 MHz
, dB
SR
10 × 106
=
4VT
4 × 25 × 10−3
= 108 rad/s
ft =
100
92
80
60
20 dB/decade
108
= 15.9 MHz
2π
40
12.67 Including a resistance RE in the emitter of
each of Q3 and Q4 cause Gm1 to become
20
Gm1 =
0
3.2 106 f (Hz)
ft
80
fP
Figure 1
Figure 1 shows a sketch of the Bode plot for the
magnitude of the open-loop gain of the op amp.
SR =
I
CC
1
2re + RE
where re is the emitter resistance of each of
Q1 − Q4 ,
re =
VT
I
Thus,
But,
Gm1
=
2
4re + 2RE
Gm1 =
I
=
2VT
I
2VT + IRE
(1)
The slew rate is still given by (12.125),
Thus,
SR =
I = 2VT Gm1
and
2I
CC
(2)
Also, the model in Fig. 12.30 still applies; thus,
SR = 2VT
Gm1
CC
= 2 × 25 × 10−3 ×
ωt =
2 × 10−3
100 × 10−12
= 1 V/μs
12.66 For a sine-wave output, we have
Gm1
CC
Equations (1)–(3) can be combined to obtain
SR =
2I
2Gm1 (2VT + IRE )
=
CC
CC
= 2ωt (2VT + IRE )
v O = V̂o sin ωt
= 4(VT + IRE /2)ωt
d vO
= ωV̂o cos ωt
dt
d v O = ωV̂o
dt Since for the 741
max
10 × 10 = ωM × 10
6
ωM = 106 rad/s
(3)
Q.E.D.
SR = 4VT ωt
to double SR while keeping ωt unchanged, we
select
1
IRE = VT
2
Chapter 12–23
fP = 8.2 Hz
If we also keep I unchanged, then
RE =
2 × 25 × 10−3
2VT
=
I
9.5 × 10−6
This is a result of CC in Eq. (12.116) being is
halved and thus fP in Eq. (12.118) is doubled.
= 5.26 k
12.68 (a) Refer to Fig. P12.68.
From Eq. (1), the new value of Gm1 is
Gm1 =
=
IC1 = IC2 = IC3 = IC4 = 0.05 mA
I
2VT + IRE
IC5 = 1 mA
IC7 = IC6 = IC5 = 1 mA
I
I
=
2VT + 2VT
4VT
(b) For Q1 and Q2 , we have
= 0.095 mA/V
0.05 mA
= 2 mA/V
0.025 V
β
100
= 50 k
=
rπ =
gm
2
gm =
which is half the original value. From Eq. (3), we
see that CC will have to be one half the original
value, thus
CC = 15 pF
Rid = 2rπ = 100 k
This result could have been obtained also from
SR = I /CC ; doubling SR with I unchanged
requires halving CC . Now, with Gm1 half the
original value, the dc gain also will be half the
original value,
(c) Figure 1 shows the small-signal analysis
where
vi
ie =
2re1,2
v o = (β + 2)βαie RL
1
A0 = × 243, 147 = 121, 573 V/V
2
Av =
vo
(β + 2)βαRL
=
vi
2re1,2
Av
1 2 RL
β
2 re1,2
or 101.7 dB
Finally, since
fP =
where
ft
A0
re1,2 =
halving A0 with ft unchanged means fP is doubled,
25 mV
= 0.5 k
0.05 mA
This figure belongs to Problem 12.68, part (c).
vid
Q7
ie
Q1
(b1) baie
Q2
baie
aie
2aie
aie
aie
aie
Q5
aie
Q3
Q4
Figure 1
(b2) baie
baie
Q6
RL
vo
Chapter 12–24
Av =
1
5
1002 ×
= 5 × 104 V/V
2
0.5
12.70 For I5 = 10 μA = I , then
Q5 emitter area
=1
Q1 emitter area
or 94 dB
(d)
C
For I6 = 40 μA = 4I , then
Q6 emitter area
=4
Q1 emitter area
0V
A2
2aie
gm1,2vi
If we connect a resistance R6 in the emitter of Q6 ,
then I6 changes to a new value determined as
follows:
VBE6 + I6 R6 = VBE1
I6 R6 = VBE1 − VBE6
Figure 2
Replacing the second stage with an amplifier
having a large negative gain, we obtain the
equivalent circuit shown in Fig. 2. From this
equivalent circuit we see that the gain is
approximately given by
A(s) =
gm1,2
sC
Thus, the unity gain frequency ωt is given by
ωt =
gm1,2
C
ωt
gm1,2
=
ωP =
A0
A0 C
gm1,2
fP =
2πA0 C
For fP = 100 Hz and substituting gm1,2 = 2 mA/V
and A0 = 5 × 104 , we find
2 × 10−3
2π × 100 × 5 × 104
= 63.7 pF
12.69 I = 5 μA
Using Eq. (12.127), we obtain
IS2
VT
ln
I=
R2
IS1
0.025
ln 4
R2
⇒ R2 = 6.93 k
R3 = R4 =
But I6 is to be equal to I , thus
IR6 = VT ln
R6 =
IS6
IS1
VT
ln 4
I
⇒ R6 =
0.025
ln 4 = 3.47 k
0.01
Ro5 = ro5 =
VAn
30 V
=
= 3 M
I5
10 μA
Ro6 = ro6 + (R6 rπ6 )(1 + gm6 ro6 )
where
ro6 =
30 V
= 3 M
10 μA
gm6 =
10 μA
= 0.4 mA/V
0.025 V
rπ6 =
βN
40
= 100 k
=
gm6
0.4
Ro6 = 3 + (3.47 100) × 10−3 (1 + 1200)
Ro6 = 3 + 4 = 7 M
IS2
=4
IS1
5 × 10−3 =
I
I6
− VT ln
IS1
IS6
If the VBIAS1 line has a low incremental resistance
to ground, then
and the 3-dB frequency ωP is
C=
= VT ln
0.15 V
= 30 k
0.005 mA
Thus, increasing the BEJ area by a factor of 4 and
adding a resistance R6 to restore the current to the
desired value of 10 μA increases the output
resistance by a factor of about 2.5!
12.71 (a) The bias current I of the differential
pair is given by Eq. (12.127),
VT
IS5
I=
ln
(1)
R5
IS1
Chapter 12–25
(b)
The voltage gain of the differential pair is
given by
VCC 3 V
Ad = gm RC
where gm is the transconduuctance of each of the
two transistors in the differential pair,
gm =
Q3
Q4
vo
I /2
I
=
VT
2VT
Q1
Q2
Thus,
Ad =
IRC
2VT
(3)
Substituting for I from Eq. (1) into Eq. (3), we
obtain
Ad =
1 RC
IS5
ln
2 R5
IS2
which indicates that Ad will be independent of
temperature!
Q5
VBIAS
0.7 V
Figure 1
(4)
Figure 1 shows the complementary circuit to that
in Fig. 12.33(a).
Here,
IS5
(b) I = 20 μA, Ad = 10 V/V,
=4
IS1
0.8 V ≤ VICM ≤ 2.9 V
Using Eq. (1), we obtain
12.73 Refer to Fig. 12.35(b).
20 × 10−3 =
0.025
ln 4
R5
⇒ R5 = 1.73 k
Using Eq. (4), we get
10 =
1 RC
ln 4
2 1.73
⇒ RC = 25 k
VICM max = VCC − 0.1 − 0.7 = 3 − 0.8
= +2.2 V
VICM min =
=
1
IRC − 0.6
2
1
× 0.02 × 25 − 0.6
2
= −0.35 V
Thus,
−0.35 V ≤ VICM ≤ +2.2 V
Av = gm RC
12.72 (a) Refer to Fig. 12.35(a).
where
VICM min = VC1 − 0.6
gm =
= 0.7 − 0.6 = 0.1 V
Av = 0.4 × 25 = 10 V/V
IC
10 × 10−6
=
= 0.4 mA/V
VT
25 × 10−3
VICM max = VCC − 0.1 − 0.7
= 3 − 0.8 = 2.2 V
12.74 gm =
I /2
20 μA
= 0.8 mA/V
=
VT
25 mV
For Ad = 10 V/V, we have
Thus,
10 = gm RC
0.1 V ≤ VICM ≤ 2.2 V
⇒ RC = 12.5 k
Chapter 12–26
I
RC = 20 × 10−3 × 12.5 = 0.25 V
2
VICM min = 0.8 V
I
VICM max = VCC − RC + 0.6
2
= 3 − 0.25 + 0.6 = 3.35 V
Thus,
0.8 V ≤ VICM ≤ 3.35 V
Rid = 2rπ = 2
=2
βN
gm
40
= 100 k
0.8
To increase Rid by a factor of 4, gm and hence I
must be reduced by a factor of 4, thus IC6 becomes
IC6 = 10 μA
To keep the gain and the permissable range of
VICM unchanged, RC must be increased by a
factor of 4, thus RC becomes
RC = 50 k
βP
gm1
where
IC1
4 × 10−6
=
= 0.16 mA/V
VT
25 × 10−3
gm1 =
Gm1 ≡
io
αie7
=
Vid /2
Vid /2
= 0.876gm1 = 0.137 mA/V
The total resistance between the output node and
ground for the circuit in Fig. 12.38(a) is
R = Ro9 Ro7 (RL /2)
The resistances Ro9 is the output resistance of Q9 ,
which has an emitter-degeneration resistance R9 .
Thus,
where
ro9 =
|VAp |
20 V
= 2.5 M
=
IC9
8 μA
gm9 =
IC9
8 μA
= 0.32 mA/V
=
VT
25 mV
rπ9 =
βP
10
=
= 31.25 k
gm9
0.32
Thus,
Ro9 = 12.5 + (33 31.25)
Thus,
2 × 10
= 125 k
0.16
Rid =
The short-circuit transconductance Gm1 can be
found from Fig. 12.38(b):
Gm1 =
io
v id /2
At node X we have four resistances to ground:
ro1 =
Thus,
Ro9 = ro9 + (R9 rπ9 )(1 + gm9 ro9 )
12.75 Refer to Fig. 12.38, which shows the
differential half-circuit of the differential
amplifier of Fig. 12.37.
Rid = 2rπ 1 = 2
Obviously, ro1 and ro7 are much larger than re7
and R7 . Then, the portion of gm1 (v id /2) that flows
into the emitter proper of Q7 can be found from
Vid
R7
ie7 gm1
2 R7 + re7
22
Vid
= gm1
2 22 + 3.125
Vid
= 0.876gm1
2
|VAp |
20 V
=
= 5 M
IC1
4 μA
× 10−3 (1 + 0.32 × 2.5 × 103 )
= 15.3 M
The resistance Ro7 is the output resistance of Q7 ,
which has an emitter-degeneration resistance
(R7 ro1 ) R7 . Thus,
Ro7 = ro7 + (R7 rπ7 )(1 + gm7 ro7 )
where
ro7 =
|VAn |
30 V
=
= 3.75 M
IC7
8 μA
gm7 =
IC7
8 μA
= 0.32 mA/V
=
VT
25 mV
rπ7 =
βN
40
= 125 k
=
gm7
0.32
R7 = 22 k
ro7 =
|VAn |
30 V
=
= 3.75 M
IC7
8 μA
re7
1
VT
25 mV
=
=
= 3.125 k
gm7
IC7
8 μA
Chapter 12–27
Thus,
ie7
Ro7 = 3.75 + (22 125) × 10−3 (1 + 0.32 × 3.75 × 103 )
=
= 26.2 M
RL
1.5
=
= 0.75 M
2
2
gm1
v id
2
R7
R7 + re7
0.067
I
v id
VT
2 0.067 + 0.0125
v id
I
= 0.84
VT
2
R = 15.3 26.2 0.75 = 0.696 M
The output short-circuit current io will be
I
v id
io ie7 = 0.84
VT
2
Finally, we can find the voltage gain as
Thus,
The load resistance R can now be found as
Av =
v od /2
= Gm1 R
v id /2
= 0.137 × 0.696 × 103 = 95.4 V/V
Gm1 = 0.84
I
VT
33.6I
To obtain the output resistance R,
R = Ro9 Ro7
12.76 IC1 = I
IC7 = IC9 = 2I
From Fig. 12.37 we see that the current through
R7 is approximately (IC1 + IC7 ), that is, 3I . Thus,
we determine Ro9 as follows:
Ro9 = ro9 + (R9 rπ9 )(1 + gm9 ro9 )
where
0.2
R7 =
3I
ro9 =
|VAp |
10
20
=
=
IC9
2I
I
Since Q3 and Q4 are cut off, the current through
R9 is equal to IE9 or approximately IC9 , thus
gm9 =
IC9
2I
= 80I
=
VT
0.025
R9 =
0.3
2I
To determine the short-circuit transconductance
Gm1 , refer to Fig. 12.38(b).
gm9 ro9 = 800
rπ9 =
Thus,
gm1 =
IC1
I
=
VT
VT
Ro9 =
Gm1 =
io
v id /2
=
At node X we have four resistances in parallel,
namely, ro1 , R7 , ro7 , and re7 :
ro1
|VAp |
20
=
=
IC1
I
βP
10
0.125
=
=
gm9
80I
I
10
+
I
0.15 0.125
I
I
× 801
64.6
I
We next determine Ro7 as follows:
Ro7 = ro7 + (R7 rπ7 )(1 + gm7 ro7 )
where
R7 =
0.067
0.2
=
3I
I
ro7 =
15
I
ro7 =
VAn
30
15
=
=
IC7
2I
I
R7 =
0.067
I
re7
VT
0.025
0.0125
=
=
IC7
2I
I
gm7 =
Thus, ro1 and ro7 are much greater than re7 and R7 ,
v id
and the portion of gm1
that flows into the
2
emitter proper of Q7 is given by
IC7
2I
=
VT
VT
gm7 ro7 = 1200
rπ7 =
βN
40
0.5
=
=
gm7
2I /VT
I
Chapter 12–28
Thus,
Ro7 =
=
15
+
I
0.067 0.5
I
I
IE8 =
× 1201
86
I
IE7 =
The corresponding change in the collector
voltages of Q7 and Q8 will be
v O2 =
We now can determine the output resistance R as
VB
re7 + R7
v O1 = −
IC7 Ro
Now,
36.9
64.6 86
=
R = Ro9 Ro7 =
I
I
I
IE7
IC7
The open-circuit voltage gain can be obtained as
and
Av o = Gm1 R
36.9
I
= 0.84
VT
I
Ro = Ro7 Ro9
thus
v O1 = −
= 1240 V/V
VB
(Ro7 Ro9 )
re7 + R7
With a load resistance RL , we have
This is the returned voltage, thus
RL
Av = Av o
RL + R
Aβ ≡ −
= 1240
RL
36.9
RL +
I
= 1240
IRL
IRL + 36.9
For RL = 1 M and I in μA, we have
I
Av = 1240
I + 36.9
From this equation we can obtain
I=
v O1
VCM
Ro7 Ro9
re7 + R7
=
Q.E.D.
(b) From Example 12.8, we have
Ro7 = 23 M, Ro9 = 12.9 M,
re7
VT
25 mV
=
= 2.5 k,
IC7
10μA
R7 = 20 k
thus
36.9
1240
−1
Av
Aβ =
(23 12.9) × 103
2.5 + 20
Thus, for Av = 150 V/V, the required value of I is
= 367.3
36.9
= 5.1 μA
I=
1240
−1
150
For a change I = 0.3 μA, the corresponding
change in VCM without feedback is
and for Av = 300 V/V, we require
I=
36.9
= 11.8 μA
1240
−1
300
VCM =
12.77 (a) Refer to Fig. 12.39. Break the loop at
the input of the CMF circuit and apply a
common-mode input signal VCM . The CMF
circuit will respond by causing a change VB in
its output voltage that can be found from its
transfer characteristic as
I (Ro7 Ro9 )
Aβ
Substituting for Aβ from Eq. (1), we obtain
VCM =
I (re7 + R7 )
= 0.3 × 10−6 (2.5 + 20)
= 6.75 mV
VCM
Now, a change
Q8 results in
I (Ro7 Ro9 )
The negative feedback reduces this change by the
amount of negative feedback 1 + Aβ Aβ, thus
the actual VCM becomes
VCM
VB =
(1)
VB in the base voltage of Q7 and
which is identical to the value found in
Example 12.8.
Chapter 12–29
12.78 (a) v O can range to within 0.1 V (the
saturation voltage) of ground and VCC , thus
But,
i5 = i4 and R5 = R4
0.1 V ≤ v O ≤ 2.9 V
thus
(b) For iL = 0, the output resistance is
v B6 = v BE5 + i4 R4
Ro = roN roP
Using Eq. (2), we obtain
where
roN
v B6 = v BE5 + v EBP − v EB4
VAn
30 V
=
= 50 k
=
IQ
0.6 mA
roP =
= (v BE5 − v EB4 ) + v EBP
IS4
iP
= VT ln
+ VT ln
IS5
ISP
IS4 iP
= VT ln
IS5 ISP
|VAp |
20 V
= 33.3 k
=
IQ
0.6 mA
Thus,
Ro = 50 33.3 = 20 k
(c) Rout = Rof =
=
20 k
1 + 105
Now, using the given relationship
Ro
1 + Aβ
ISN
ISP
=
IS4
IS5
0.2 in Eq. (3), we get
iP
v B6 = VT ln
ISN
(d) For iL = 12 mA, we have
IQ
iN =
= 0.3 mA
2
Using Eqs. (1) and (4), we obtain
iP
v B6 − v B7 = VT ln
iN
iP = 12 + 0.3 = 12.3 mA
roN =
roP
30 V
= 100 k
0.3 mA
This is the differential voltage input for the
differential amplifier Q6 − Q7 . Thus,
20 V
= 1.63 k
=
12.3
Ro = 100 1.63 = 1.6 k
(e) For iL = −12 mA, we have
iC6 =
I
1 + e(v B6 −v B7 )/VT
=
I
iP = 0.3 mA
iN = 12.3 mA
roN
=
30 V
= 2.44 k
=
12.3 mA
roP =
v EBP − v EB4
R4
v B6 = v BE5 + i5 R5
iP
iN
iN
I
i P + iN
iC7 =
Ro = 2.44 66.7 = 2.4 k
i4 =
1+
Q.E.D.
Similarly,
20 V
= 66.7 k
0.3 mA
12.79 Refer to Fig. 12.43.
iN
v B7 = v BEN = VT ln
ISN
(3)
=
=
I
1+
e(v B7 −v B6 )/VT
I
1+
iN
iP
iP
I
i P + iN
Q.E.D.
(1)
(2)
12.80 v E = v EB7 + v BEN
Since Q7 conducts a current iC7 given by
Eq. (12.131),
(4)
Chapter 12–30
iC7 = I
iP
iP + iN
and QN conducts a current iN , then
I iP
iN
1
v E = VT ln
+ VT ln
iP + iN IS7
ISN
iP iN
I
Q.E.D.
= VT ln
iP + iN ISN IS7
ISN
=8
IS10
IS7
=4
IS11
Using Eq. (12.136), we have
2 I
600 = 2 REF × 8 × 4
12
⇒ IREF = 10.6 μA
12.81 IQ = 0.6 mA = 600 μA
I = 12 μA
The minimum current in each transistor is about
0.3 mA.
Exercise 13–1
Ex: 13.1 A = −20 log|T | [dB]
From Fig.1 we see that the real pole is at
|T | =
A
s = −1
1 0.99 0.9 0.8 0.7 0.5 0.1 0
0 0.1
1
2
3
6
20 ∞
Ex: 13.2
Amax = 20 log1.05 − 20 log 0.95 0.9 dB
1
= 40 dB
Amin = 20 log
0.01
and thus gives rise to a factor (s + 1) in the
denominator. The pair of complex conjugate
poles are at
−cos 60◦ ± j sin 60◦
√
= −0.5 ± j 3/2
Ex: 13.3
T (s) = k (s + j2) (s − j2)
1
1
3
3
s+ +j
s+ −j
2
2
2
2
2
s +4
=k
1 3
s2 + s + +
4 4
2
s +4
=k 2
s +s+1
4
T (0) = k = 1
1
1
k=
4
1 s2 + 4
∴ T (s) =
4 s2 + s + 1
The corresponding quadratic in the denominator
will be
√ √ 3
3
= s + 0.5 + j
s + 0.5 − j
2
2
s s2 + 4
×
T (s) = a3
(s + 0.1 + j0.8) (s + 0.1 − j0.8)
|T (jω)| = √
1
(s + 0.1 + j1.2) (s + 0.1 − j1.2)
s s2 + 4
= a3 2
s + 0.2s + 0.65 s2 + 0.2s + 1.45
=
= s2 + s + 1
Since the filter is of the all-pole type, the transfer
function will be
T (s) = k
1
(s + 1)(s2 + s + 1)
Since the dc gain is unity, k = 1 and
T (s) =
Ex: 13.4
=
1
1+
ω2
(1 − ω2 )2 + ω2
1
(1 + ω2 )(1 − ω2 )2 + ω2 (1 + ω2 )
1
(1 − ω4 )(1 − ω2 ) + ω2 + ω4
= √
Ex: 13.5
1
(s + 1)(s2 + s + 1)
jv
= √
1
1 − ω4 − ω2 + ω6 + ω2 + ω4
1
Q.E.D.
1 + ω6
√
|T (jω)| = 1/ 2 at ω = ω3dB , thus
1
30°
1+
⫺1
0
30°
s
6
ω3dB
1
= √
2
⇒ ω3dB = 1 rad/s
At ω = 3 rad/s, we have
|T | = √
1
1+
36
1
= √
730
√
A = −20 log |T | = −20 log(1/ 730)
Figure 1
= 10 log(730) = 28.6 dB
Exercise 13–2
Ex: 13.6
=
10
Amax
10
Ex: 13.8
1
10 10 − 1 = 0.5088
−1=
1
|T (jω)| =
1 + 2
2N
ω
ωp
A(ωs ) = −20 log|T (jωs )|
2N
2 ωs
= 10 log 1 + ωp
Thus, 10 log 1 + 0.50882 × 1.52N ≥ 30
N = 11: LHS = 32.87 dB
∴ Use N = 11 and obtain
Amin = 32.87 dB
1 + 0.36542
= 0.54 dB
Ex: 13.7 The real pole is at s = –1
The complex conjugate poles are at
s = − cos 60◦ ± j sin 60◦
3
= −0.5 ± j
2
π
, k = 0, 1, 2
2
(2k + 1) π
∴ ω̂ = ωp cos
, k = 0, 1, 2
10
π = 0.95ωp
ω̂1 = ωp cos
10
ω̂
ωp
1
(s + 1) s2 + s + 1
DC gain = 1
= (2k + 1)
ω̂2 = ωp cos
3
π
10
= 0.59ωp
ω̂3 = ωp cos
5
π
10
=0
5 cos−1
s
30⬚
1
3
3
s + 0.5 − j
(s + 1) s + 0.5 + j
2
2
=
for ω < ωp .
ω̌
ωp
∴ ω̌ = ωp cos
T (s) =
ω
ωP
Valleys are obtained when
ω̌
=1
cos2 N cos−1
ωp
jw
60⬚
1
1 + 2 cos2 N cos−1
5 cos−1
For Amin to be exactly 30 dB, we need
10 log 1 + 2 × 1.522 = 30
1/3
wp ( e1 ) ⫽1
Peaks are obtained when
ω̂
=0
cos2 N cos−1
ωp
ω̂
cos2 5 cos−1
=0
ωp
N = 10: LHS = 29.35 dB
⇒ 0.3654 ⇒ Amax = 20 log
|T (jω)| =
= kπ, k = 0, 1, 2
kπ
, k = 0, 1, 2
5
ω̌1 = ωp cos 0 = ωp
π
= 0.81ωp
5
2π
ω̌3 = ωp cos
= 0.31ωp
5
ω̌2 = ωp cos
Ex: 13.9
Amax
10
0.5
− 1 = 10 10 − 1 = 0.3493
ωs
A(ωs ) = 10 log 1 + 2 cosh2 N cosh−1
ωp
2
−1
2
= 10 log 1 + 0.3493 cosh 7 cosh 2
=
10
= 64.9 dB
Exercise 13–3
For Amax = 1 dB, = 100.1 − 1 = 0.5088
A (ωs ) = 10 log 1 + 0.50882 cosh2 7 cosh−1 2
= 68.2 dB
This is an increase of 3.3 dB
Ex: 13.10 =
10
1
10
Ex: 13.12 Refer to Fig. 13.14.
1
= 103 rad/s
CR
For R arbitrarily selected to be 10 k,
ω0 =
C=
1
= 0.1 μF
103 × 104
The two resistors labeled R1 can also be selected
to be a convenient value, say 10 k each.
− 1 = 0.5088
(a) For the Chebyshev filter:
Ex: 13.13 T (s) =
A (ωs )
= 10 log 1 + 0.50882 cosh2 N cosh−1 1.5
√
For maximally flat response, Q = 1/ 2, thus
≥ 50 dB
T (s) =
N = 7.4 ∴ choose N = 8
(b) For a Butterworth filter
=
2N
ωs
ωp
A(ωs ) = 10 log 1 + 2
ω02
(ω02
−
ω2 )
√
+ j 2 ωω0
ω02
|T (jω)| =
= 55 − 50 = 5 dB
ω2
√ 0
s2 + s 2 ω0 + ω02
T (jω) =
Excess attenuation =
10 log 1 + 0.50882 cosh2 8 cosh−1 1.5 − 50
= 0.5088
ω02
ω0
+ ω02
s2 + s
Q
(ω02 − ω2 )2 + 2ω2 ω02
ω02
ω04 + ω4
1
=
ω
ω0
1+
4
˙ 2 (1.5)2N ≥ 50
= 10 log 1 + 0.5088
At ω = ω0 ,
N = 15.9 ∴ choose N = 16
1
1
|T (jω0 )| = √
= √
1+1
2
Excess attenuation =
˙ 2 (1.5)32 − 50 = 0.5 dB
10 log 1 + 0.5088
which is 3 dB below the value at
ω = 0 (0 dB).
Q.E.D.
ω0
Q
Ex: 13.14 T (s) =
ω0
s2 + s
+ ω02
Q
sK
Ex: 13.11
R2
R1
C
⫺
⫹
Vi
Vo
where K is the center-frequency gain. For
ω0 = 105 rad/s and 3-dB bandwidth = 103 rad/s,
we have
ω0
3-dB BW =
Q
103 =
104 =
1
, R1 = 10 k
CR 1
C = 0.01 μF
105
Q
⇒ Q = 100
Also, for a center-frequency gain of 10, we have
K = 10
−R2
H.F. gain =
= −10
R1
Thus,
R2 = 100 k
T (s) =
s2
104 s
+ 103 s + 1010
Exercise 13–4
Ex: 13.15 (a) T (s) = a2
ω02
|T (jω)| = |a2 |
s2 + ω02
ω0
s2 + s
+ ω02
Q
−ω
1+
Q=
ω2 ω02
Q2
ω2 ω02
Q2 (ω02 − ω2 )2
(1)
a2
v1 v0 v2
√
ω0
BWa 103/10 − 1
ω0
Q.E.D.
⇒ BWa =
Q
2
(ω02 − ω2 )2 +
= |a2 |
(b) For A = 3 dB we have
v
Figure 1
Refer to Fig. 1 and note that at any value of |T |
there are two frequencies, ω1 and ω2 , with this
gain value. From Eq. (1) we obtain
Ex: 13.16 From Fig. 13.16(e) we have
ωn 2
1
ω0 (1 − 2Q2 ) − 1
ωmax = 1
ωn 2
+
−1
ω0
2Q2
1.2 2
1
−1
1−
1
2
×
100
=
1
1.2 2
+
−1
1
2 × 100
= 0.986 rad/s
2
|a2 | |ωn2 − ωmax
|
Tmax =
2 )2 +
(ω02 − ωmax
DC gain = |a2 |
ω1 ω22 − ω1 ω02 = ω2 ω02 − ω12 ω2
Thus,
ω1 ω2 (ω1 + ω2 ) = (ω1 + ω2 )ω02
Tmax = ⇒ ω1 ω2 =
2
ωmax
ωn2
=1
ω02
1
= 0.694
1.44
⇒ |a2 | =
0.694 |1.44 − 0.972|
(1 −
Q.E.D.
Now if ω1 and ω2 differ by BWa ,
2
where
ω2 ω2
ω12 ω02
= 2 22 0 2 2
2
2 2
2
Q (ω0 − ω1 )
Q (ω2 − ω0 )
ω1
ω2
⇒ 2
= 2
ω0 − ω12
ω2 − ω02
ω02
ω0
Q
0.972)2
= 3.17
1
+
× 0.972
100
HF transmission = |a2 | = 0.694
ω2 − ω1 = BWa
and if the attenuation over this band of
frequencies is to be greater than A dB, then by
using Eq. (1) we have
ω2 ω2
10 log10 1 + 2 0 21 2 2 ≥ A
(ω0 − ω1 ) Q
ω1 ω0
≥ 10A/10 − 1
(ω02 − ω12 )Q
ω1 ω0
1
≥
Q (ω1 ω2 − ω12 )
ω0
1
≥
Q ω2 − ω1
1 ω0
≥
Q BWa
Q≤
10A/10 − 1
√
BWa 10A/10 − 1
1
⇒Q= √
2
ω0 = 2π × 100 × 103
Arbitrarily selecting R = 1 k, we get
1
Q = ω0 CR ⇒ C = √
2 × 2π 105 × 103
= 1125 pF
L
10A/10 − 1
10A/10 − 1
ω0
Ex: 13.17 Maximally flat
⫹
Vi
⫺
⫹
C
R
Vo
⫺
Exercise 13–5
Also Q =
R
ω0 L
R
∴L=
=
ω0 Q
The circuit consists of 3 sections in cascade:
103
1
2π105 × √
2
(a) First-order section:
= 2.25 mH
R2
Ex: 13.18
⫹
Vi
C
R1
L
⫺
⫹
⫹
R
C
⫺
Vo
⫺
T (s) =
From Exercise 13.15 above, 3-dB bandwidth
= ω0 /Q
−0.2895ωp
s + 0.2895ωp
2π10 = 2π60/Q ⇒ Q = 6
where the numerator coefficient is set so that the
dc gain = −1.
Q = ω0 CR
Let R1 = 10 k
6 = 2π60 × C × 104 ⇒ C = 1.6 μF
dc gain = R2 /R1 = 1 = R2 = 10 k
R
Q=
ω0 L
ω0 = 0.2895ωp
R
104
L=
=
= 4.42 H
ω0 Q
2π60 × 6
Ex: 13.19 f0 = 10 kHz, f3dB = 500 Hz
f
104
Q=
= 20
=
f3dB
500
1
= 0.2895ωp
CR2
⇒C=
(b) Second-order section with transfer function:
T (s) =
Using the data at the top of Table 13.1, we get
C4 = C6 = 1.2 nF
R1 = R2 = R3 = R5 =
1
ω0 C
1
= 5.5 nF
0.2895 × 2π104 × 104
s2
0.4293ω2P
+ s0.4684ωp + 0.4293ω2P
where the numerator coefficient is selected to
yield a dc gain of unity.
1
= 13.26 k
2π104 × 1.2 × 10−9
20
R6 = Q/ω0 C =
= 265 k
4
2π10 × 1.2 × 10−9
Now using the data in Table 13.1 for the bandpass
case, we obtain
=
K = center-frequency gain = 10
Referring to Fig. 13.21(c), we have
1 + r2 /r1 = 10
Selecting r1 = 10 k, we obtain r2 = 90 k.
Ex: 13.20 From Eq. (13.25),
we have ωp = 2π104 and
T (s) =
ωp 5
×
8.1408 s + 0.2895ωp
1
×
s2 + s0.4684ωp + 0.4293ωp 2
1
s2 + s0.1789ωp + 0.9883ωp 2
Select R1 = R2 = R3 = R5 = 10 k
⇒C= √
1
0.4293 × 2π104 × 104
= 2.43 nF
C4 = C6 = C = 2.43 nF
√
0.4293ωp
Q
= 14 k
= 1.4 ⇒ R6 =
Q=
0.4684ωp
ω0 C
(c) Second-order section with transfer function:
T (s) =
0.9883ω2 p
s2 + s0.1789ωp + 0.9883ω2 p
Exercise 13–6
The circuit is similar to that in (b) above but with
R1 = R2 = R3 = R5 = 10 k
1
C4 = C6 =
ω0 × 104
1
= √
0.9883 × 2π104 × 104
= 1.6 nF
√
0.9883
Q=
= 5.56
0.1789
Thus R6 = Q/ω0 C = 55.6 k
given C = l nF, RL = 10 k, then
R=
1
1
=
= 31.83 k
ω0 C
2π5 × 103 × 10−9
R1 = 10 k ⇒ Rf = 10 k
R2 = 10 k ⇒ R3 = R2 (2Q − 1)
= 10 (10 − 1) = 90 k
Placing the three sections in cascade, i.e.
connecting the output of the first-order section to
the input of the second-order section in (b) and
the output of of section (b) to the input of (c)
results in the overall transfer function in
Eq. (13.25) except for an inversion.
Ex: 13.21 Refer to the KHN circuit in Fig. 13.24.
Choosing C = l nF, we obtain
1
1
R=
=
= 15.9 k
4
ω0 C
2π10 × 10−9
Using Eq. (13.62) and selecting R1 = 10 k,
we get
Rf = R1 = 10 k
Using Eq. (13.63) and setting R2 = 10 k, we
obtain
R3 = R2 (2Q − 1) = 10 (2 × 2 − 1) = 30 k
1
= 1.5 V/V
High-frequency gain = K = 2 −
Q
The transfer function to the output of the first
integrator is
Vhp
Vbp
1
sK/ (CR)
×
=−
=
ω0
Vi
sCR
Vi
2
+ ω20
s +s
Q
Thus the center-frequency gain is given by
K Q
= KQ = 1.5 × 2 = 3 V/V
CR ω0
RH 2
8
ω = ω2n ⇒ RH = 10
RL 0
5
DC gain = K
RF =
R1
Rf
⫺
⫹
C
R
R2
C
R
⫺
⫹
⫺
⫹
CR =
⫺
⫹
RF
=3
RL
3 × 10
= 16.7 k
2 − 1/5
1
1
⇒C=
= 1.59 nF
ω0
2π104 × 104
Rd = QR = 20 × 10 = 200 k
Center frequency gain = KQ = 1
∴K =
1
1
=
Q
20
Rg = R/K = 20R = 200 k
Ex: 13.24 Refer to Fig. 13.26 and Table 13.2
(AP entry).
C = 10 nF
1
1
= 10 k
= 4
R=
ω0 C
10 × 10 × 10−9
QR = 5 × 10 = 50 k
C1 = C × flat gain = 10 × 1 = 10 nF
R1 = ∞
R
= R/1 = 10 k
gain
r = 10 k
5 × 10
Qr
=
= 50 k
R3 =
gain
1
CR =
RF
RH
= 25.6 k
Ex: 13.25 From Eq. (13.76) we have
RL
R3
1
RF
= 2−
RL
Q
2
Ex: 13.23 Refer to Fig. 13.25 (b)
R2 =
Ex: 13.22
Vi
Vo
(RF /RH ) s2 + (RF /RL ) ω2 0
= −K
Vi
s2 + sω0 /Q + ω20
2×1
2Q
=
= 2 × 10−4 s
ω0
104
For C = C1 = C2 = l nF
Vo
2 × 10−4
= 200 k
10−9
Thus R3 = 200 k
R=
Exercise 13–7
Ex: 13.28
From Eq. (13.75) we have
m = 4Q2 = 4
⫺
⫹
⫹
200
R
=
= 50 k
m
4
⫺
0
Ex: 13.26 The transfer function of the feedback
network is given in Fig. 13.28(a). The poles are
the roots of the denominator polynomial,
1
1
1
1
s +s
+
+
=0
+
C1 R3
C2 R3
C1 R4
C1 C2 R3 R4
sC3Vo
2
1
+ −9
5
10 × 5 × 104
× 2 × 10
R1
+
Figure 1
=0
10−18 1010
s2 + s 3 × 104 + 108 = 0
s=
C3
⫺
1
C4
Vi
R4 = 5 × 104 ,
10
X
sC3Vo
For C1 = C2 = 10−9 F, R3 = 2 × 105 ,
−9
R2
Vo
2
s2 + s
Vo
⫹
Thus, R4 =
−3 × 104 ±
9 × 108 − 4 × 108
2
= −0.382 × 104 and −2.618 × 104 rad/s
Figure 1 shows the circuit of Fig. 13.34(c) with
partial analysis to determine the transfer function.
The voltage at node X can be written as
Vx = Vo + sC3 Vo R2
= (1 + sC3 R2 )Vo
(1)
Now a node equation at X takes the form
Ex: 13.27 Refer to the circuit in Fig. 13.30(a),
where the transfer function is given on page 1126
as
−s(α/C1 R4 )
T (s) =
1
1
1
1
s2 + s
+
+
C1
C2 R3
C1 C2 R3 R4
Now, using the component value obtained in
Exercise 13.25, namely
C1 = C2 = 1 nF
R3 = 200 k
R4 = 50 k
the center-frequency gain is given by (note that
Q = 1)
R3
C1
|T (jωa )| = α
1+
R4
C2
1=α×
4
= 2α
1+1
Vi − Vx
= sC3 Vo + sC4 (Vx − Vo )
R1
Substituting for Vx from Eq. (1) gives
Vi − Vo (sC3 R2 + 1) = sC3 R1 Vo + sC4 R1 (sC3 R2 Vo )
Vi = Vo [s2 C3 C4 R1 R2 + sC3 (R1 + R2 ) + 1]
⇒
Vo
=
Vi
1
s2 + s
C4
1/C3 C4 R1 R2
1
1
1
+
+
R1
R2
C3 C4 R1 R2
Thus,
ω0 = 1/ C3 C4 R1 R2
and
Q=
√
C3 C4 R1 R2
C4
1
1
+
R1
R2
−1
which are identical to Eqs. (13.77) and (13.78),
respectively.
Q.E.D.
⇒ α = 0.5
From Eq. (2) we see that
Thus,
Vo
(0) = 1
Vi
50
R4
=
= 100 k
α
0.5
(2)
Q.E.D.
and
Ex: 13.29 The design equations are Eqs. (13.79)
and (13.80). Thus,
50
R4
=
= 100 k
1−α
0.5
R1 = R2 = R = 10 k
Exercise 13–8
and
Using Eq. (13.99), we obtain
C4 = C
Gm = ω0 C = 2π × 20 × 106 × 2 × 10−12
C3 = C/4Q2 = C
4×
1
2
= 0.5C
where
1
2× √
2Q
2
=
CR =
ω0
2π × 4 × 103
√
2
⇒C=
= 5.63 nF
2π × 4 × 103 × 10 × 103
= 0.251 mA/V
Thus,
Gm1 = Gm2 = 0.251 mA/V
Gm3 =
0.251
Gm
= √ = 0.355 mA/V
Q
1/ 2
Gm4 = Gm | Gain | = Gm = 0.251 mA/V
Thus,
Ex: 13.32 From Eq. (13.109)
C4 = 5.63 nF
C3 = C4 = ω0 Tc C
C3 = 2.81 nF
= 2π 104 ×
Ex: 13.30 Refer to the results in Example 13.3
= 6.283 pF
(a) R3 /R3 = +2%
From Eq. (13.112)
ωo
= −1/2 ⇒
SR3
Q
SR3 =
ωO
1
= − × 2 = −1%
ωO
2
1
1
⇒ Q/Q = × 2 = 1%
2
2
(b) R4 /R4 = 2%
SRω4o = −
Q
SR4 = −
C5 =
1
× 20
200 × 103
6.283
C4
=
= 0.314 pF
Q
20
From Eq. (13.113)
Centre-frequency gain =
1
ωO
= −1%
⇒
2
ωO
C6 = C5 = 0.314 pF
1
Q
1
⇒
= − × 2 = −1%
2
Q
2
Ex: 13.33 Rp = ω0 LQ0
(c) Combining the results in (a) & (b), we get
ωO
= −1 − 1 = −2%
ωO
Q
= 1 − 1 = 0%
Q
(d) Using the results in (c) for both resistors
being 2% high, we have
= 2π106 × 3.18 × 10−6 × 150 = 3 k
R = RL
ro
Rin ) /ω0 L
103 103
= 35
2π × 455 × 103 × 5 × 10−6
= BW = f0 /Q = 455/35 = 13 kHz
C1 + Cin =
−1
1
= − (−2) +
(−2) − 2
2
2
= Q
Q C1
Q C2
= SC1
+ SC2
+0
Q
C
C2
Rp = 2 k ⇒ RL = 15 k
Ex: 13.34 Q = (R1
ωO
ωo C1
ωo C2
= SC1
+ SC2
−2
ωO
C1
C2
= 2 − 2 = 0%
C6
=1
C5
1
ω20 L
1
2π × 455 × 103
2
× 5 × 10−6
= 24.47 nF
C1 = 24.47 − 0.2 = 24.27 nF
= 0 (−2) + (0) (−2) + 0 = 0%
Ex: 13.35 To just meet specifications,
Ex: 13.31 f0 = f3dB = 20 MHz
√
Q = 1/ 2
Q=
DC gain = 1
∴
R1
455
f0
=
= 45.5
BW
10
n2 Rin
= 45.5
ω0 L
Exercise 13–9
R1
n2 Rin = 45.5 × 2π × 455 × 103 × 5 × 10−6
= 650 n2 Rin = 1.86 k
1.86
= 1.36
n=
1
C1 +
Cin
1
= 2 = 24.47 nF
2
n
ω0 L
Ex: 13.36 200 = (f0 /Q) 21/2 − 1
Eq. (13.123)
f0
= 310.8 kHz
Q
C=
1
1
= 2
ω20 L
2π × 10.7 × 106 × 3 × 10−6
= 73.75 pF
C1 = 24.36 nF
1
ωO
=
Q
CR
At resonance, the voltage developed across R1 is
I R1 n2 Rin = IR. Thus, Vbe = IR/n &
Ic = gm Vbe = gm IR/n,
R=
40 × 0.65
A
Ic
= gm R/n =
= 19.1
I
1.36
A
73.7 × 10
= 6.94 k
−12
1
× 2π × 310.8 × 103
Chapter 13–1
13.1 T (s) =
|T (jω)| = ω0
ω0
, T (jω) =
s + ω0
jω + ω0
ω0
ω20 + ω2
φ (ω) ≡ tan−1
= −tan
−1
1
= 1+
Im (T (jω))
Re (T (jω))
ω
ω0
2
Peak amplitude of output sinusoid = 0.707 V
Phase of output relative to that of input = −45◦ .
(c) f = 100 kHz
ω = 2π × 105 rad/s
√
|T | = 1/ 1 + 100 0.1 V/V
φ = −tan−1 (10) = −84.3◦
(ω/ωO )
Peak amplitude of output sinusoid = 0.1 V
G = 20 log10 |T (jω)|
Phase of output relative to that of input =
−84.3◦ .
A = −20 log10 |T (jω)|
(d) f = 1 MHz
ω = 2π × 106 rad/s
|T | = 1/ 1 + 104 = 0.01 V/V
ω
|T (jω)|
[V/V]
G
[dB]
0
1
0
0
0
0.5ω0
0.8944
–0.97
0.97
–26.57
Peak amplitude of output sinusoid = 0.01 V
ω0
0.7071
–3.01
3.01
–45.0
2ω0
0.4472
–6.99
6.99
–63.43
Phase of output relative to that of input =
−89.4◦ .
5ω0
0.1961
–14.1
14.1
–78.69
10ω0
0.0995
–20.0
20.0
–84.29
100ω0
0.010
–40.0
40.0
–89.43
A
φ
[dB] [degrees]
φ = −tan−1 (100) = −89.4◦
13.3 T (s) =
=
1
(s + 1) s2 + s + 1
1
s3 + 2s2 + 2s + 1
T (jω) = j 2ω − ω3 + 1 − 2ω2
13.2 T (s) =
T (jω) =
2π × 104
s + 2π × 104
|T (jω)| =
2π × 104
2π × 104 + jω
1
1 + j[ω/2π × 104 ]
1+
|T (jω)| = 1
2
+ 1 − 2ω2
1
2 −2
= 4ω2 − 4ω4 + ω6 + 1 − 4ω2 + 4ω4
= 1 + ω6
=
ω
2π × 104
−1
2ω − ω3
−1
2
φ(ω) = −tan (ω/2π × 10 )
4
(a) f = 1 kHz
ω = 2π × 103 rad/s
√
|T | = 1/ 1 + 0.01 0.995 V/V
φ = −tan−1 (0.1) = −5.7◦
Peak amplitude of output sinusoid = 0.995 V
Phase of output relative to that of input = −5.7◦ .
= √
−
−
1
2
1
2
1
Q.E.D.
1 + ω6
For phase angle:
Im (T (jω))
φ(ω) = tan−1
Re (T (jω))
2ω − ω3
= − tan−1
1 − 2ω2
For ω = 0.1 rad/s:
|T (jω)| = 1 + 0.16
−1/2
1
◦
φ (ω) = −11.5 = −0.20 rad
For ω = 1 rad/s:
ω = 2π × 104 rad/s
√
|T | = 1/ 2 = 0.707 V/V
√
−1/2
|T (jω)| = 1 + 16
= 1/ 2 = 0.707
1
= −135◦ = −2.356 rad
φ = −tan−1
−1
φ = −tan−1 (1) = −45◦
Note: G = –3 dB
(b) f = 10 kHz
Chapter 13–2
For ω = 10 rad/s:
13.6
6 −1/2
|T (jω)| = 1 + 10
= 0.001
3
−1 2 (10) − 10
φ = −tan
1 − 2 102
−980
= −tan−1
−199
980
= − 180◦ + tan−1
199
= −258.5◦
= −4.512 rad
Figure 1
Now consider an input of A sin ωt to T(s). The
output is then given by
A |T (jω)| sin (ωt + φ (ω))
Refer to Fig. 1.
Using this result, the output to each of the
following inputs will be:
T (s) =
2π × 104
s + 2π × 104
T (jω) =
INPUT
OUTPUT
10 sin(0.1t)
10 sin(0.1t –0.2)
10 sin(1t)
7.07 sin(t − 2.356)
10 sin(10t)
0.01 sin(10t − 4.512)
1
ω
2π × 104
f 2
|T | = 1
1+
104
1+j
At f = fp = 5 kHz, we have
2
5 × 103
1+
= 0.894
|T | = 1
104
13.4 Refer to Fig. 13.3.
Thus,
Amax = 20 log 1.05 = 0.42 dB
1
Amin = 20 log
0.0005
Amax = −20 log 0.894 = 0.97 dB
= 66 dB
Selectivity factor ≡
=
fs
fp
5
= 1.25
4
At f = fs = 10 fp = 50 kHz, we have
2
50 × 103
1+
= 0.196
|T | = 1
104
1
Amin = 20 log
= 14.15 dB
0.196
13.7 See Fig. 1.
13.5 At ω = 0, we have
20 log |T | = 0 dB
⇒ |T | = 1 V/V
At ω = ωp , we have
20 log|T | = −Amax = −0.2 dB
⇒ |T | = 0.977 V/V
At ω = ωs , we have
20 log|T | = −Amin = −60 dB
⇒ |T | = 0.001 V/V
Figure 1
Chapter 13–3
This pole pair gives rise to a factor
13.8 See Fig. 1.
= (s + 0.809 × 104 + j 0.588 × 104 )(s + 0.809 ×
104 − j0.588 × 104 )
= (s2 + 1.618 × 104 s + 108 )
Thus the denominator polynomial of T (s) is
D(s) = (s + 104 )(s + 0.618 × 104 s + 108 )(s2 +
1.618 × 104 s + 108 )
(a) The filter is a low-pass of the all-pole type,
T (s) =
Figure 1
k
(s + 104 )(s2 + 0.618 × 104 s + 108 ) ×
(s2 + 1.618 × 104 s + 108 )
Since the dc gain is unity, we have
k = 1020
13.9
Thus,
T (s) =
1020
(s + 10 )(s + 0.618 × 104 s + 108 ) ×
(s2 + 1.618 × 104 s + 108 )
4
2
(b) The filter is a high pass,
T (s) =
ks5
(s + 104 )(s2 + 0.618 × 104 s + 108 ) ×
(s2 + 1.618 × 104 s + 108 )
Since the high-frequency (s → ∞) gain is unity,
k must be unity, thus
T (s) =
s5
(s + 10 )(s + 0.618 × 104 s + 108 ) ×
(s2 + 1.618 × 104 s + 108 )
13.10 T (s) =
Figure 1
s = −104 sin 18◦ ± j104 cos 18◦
= −0.309 × 104 ± j0.951 × 104
This pole pair gives rise to a factor
= (s + 0.309 × 104 + j 0.951 × 104 )(s + 0.309 ×
104 − j0.951 × 104 )
= s2 + 0.618 × 104 s + 108
The pair of complex conjugate poles p2 and
are at
◦
◦
s = −10 sin 54 ± j10 cos 54
4
4
= −0.809 × 104 ± j0.588 × 104
p2∗
2
k(s2 + 4)
(s + 0.25 + j)(s + 0.25 − j)
k(s2 + 4)
+ 0.5s + 1.0625
4k
=1
T (0) =
1.0625
1.0625
= 0.2656
⇒k=
4
0.2656(s2 + 4)
T (s) = 2
s + 0.5s + 1.0625
T (∞) = 0.2656
=
Figure 1 shows the location of the five poles in
the s plane. The real-axis pole at s = −104 gives
rise to a factor (s + 104 ). The pair of conjugate
poles p1 and p1∗ are at
4
s2
13.11 T (s)
=
k(s2 + 4)
(s + 1)(s + 0.5 − j 0.8) × (s + 0.5 − j 0.8)
=
k(s2 + 4)
(s + 1)(s2 + s + 0.89)
4k
=1
0.89
0.89
= 0.2225
⇒k=
4
T (0) =
Chapter 13–4
I6 = I3 + I5 = (s + 1)Vo + s(s2 + s + 1)Vo
Thus,
T (s) =
0.2225(s2 + 4)
(s + 1)(s + s + 0.89)
Vi = V4 + I6 × 1
= (s2 + s + 1)Vo + (s3 + s2 + 2s + 1)Vo
13.12
T (s) =
= (s3 + s2 + 2s + 1)Vo
s6
s(s2 + 106 )(s2 + 9 × 106 )
+ b5 s5 + b4 s4 + b3 s2 + b1 s + b0
= (s3 + 2s2 + 3s + 2)Vo
Vo (s)
1
= 3
Vi (s)
s + 2s2 + 3s + 2
Note that we started with the numerator factors
(which represent the given transmission zeros).
We used the fact that there is one transmission
zero at s = ∞ to write the denominator
sixth-order polynomial. Thus,
N =6
A sketch of the magnitude response, |T |, is given
in Fig. 1.
All the transmission zeros are at s = ∞. To find
the poles, we have to factor the third-order
denominator polynomial. Toward this end, we
find by inspection that one of the zeros of the
denominator polynomial is at s = −1. Thus, the
polynomial will have a factor (s + 1) and can be
written as
s3 + 2s2 + 3s + 2 = (s + 1)(s2 + as + b)
where by equating corresponding terms on both
sides we find that
|T|
b=2
a+1=2⇒a =1
Thus,
s3 + 2s2 + 3s + 2 = (s + 1)(s2 + s + 2)
and the poles are at
0
1
v, krad/s
2
3
Figure 1
s = −1
and at the roots of
s2 + s + 2 = 0
13.13
which are
1 I6
I5
1F
Vi
1H
V4
I2
1F
√
1−8
s=
2
√ = −0.5 ± j 7/2
−1 ±
I3
I1
Vo
1 = −0.5 ± j1.323
Figure 1
13.14 Amax = 0.5 dB, Amin ≥ 20 dB,
Refer to Fig. 1.
Vo
= Vo
I1 =
1
I2 = sCVo = s × 1 × Vo = sVo
Using Eq. (13.14), we obtain
= 10Amax /10 − 1
= 100.05 − 1 = 0.3493
I3 = I1 + I2 = (s + 1)Vo
Using Eq. (13.15), we have
V4 = Vo + sLI3
A(ωs ) = 10 log[1 + 2 (ωs /ωp )2N ]
= Vo + s × 1(s + 1)Vo
= 10 log[1 + 0.34932 × 1.72N ]
= (s2 + s + 1)Vo
For N = 5, A(ωs ) = 14.08 dB
I5 = s × 1 × V4
For N = 6, A(ωs ) = 18.58 dB
= s(s + s + 1)Vo
For N = 7, A(ωs ) = 23.15 dB
2
ωs
= 1.7
ωp
Chapter 13–5
Thus, to meet the As ≥ 20 dB specification,
we use
For the case N = 7,
A = 10 log(1 + 1.814 ) = 35.7 dB
N =7
in which case the actual minimum stopband
attenuation realized is
13.17 Amax = 0.5 dB, N = 5, ωp = 103 rad/s
Amin = 23.15 dB
Using Eq. (13.14), we obtain
= 10Amax /10 − 1 = 100.05 − 1
If Amin is to be exactly 20 dB, we can use Eq.
(13.15) to obtain the new value of as follows:
= 0.3493
20 = 10 log[1 + 2 × 1.714 ]
100 − 1
= 0.2425
=
1.714
Now, using Eq. (13.13) we can determine the
value to which Amax can be reduced as
Amax = 20 log 1 + 2
Amax = 20 log 1 + 0.24252
= 0.25 dB
13.15 Using Eq. (13.15), we have
A(ωs ) = 10 log[1 + 2 (ωs /ωp )2N ]
For large A(ωs ), we can neglect the unity term in
this expression to obtain
A(ωs ) 10 log [ 2 (ωs /ωp )2N ]
Substituting A(ωs ) ≥ Amin we obtain
The natural modes can be determined by
reference to Fig. 13.10(a):
1/N
1
ω0 = ωp
1/5
1
3
ω0 = 10 ×
0.3493
= 1.234 × 103 rad/s
π π ± jcos
p1 , p1∗ = ω0 sin
10
10
= ω0 (−0.309 ± j0.951)
= 1.234 × 103 (0.309 ± j0.951)
3π
3π
± jcos
p2 , p2∗ = ω0 −sin
10
10
= 1.234 × 103 (−0.809 ± j0.588)
p3 = −ω0 = −1.234 × 103
13.18
20 log + 20N log(ωs /ωp ) ≥ Amin
⇒N ≥
Amin − 20 log 20 log(ωs /ωp )
Q.E.D.
13.16 For an N th-order Butterworth filter, we
have from Eq. (13.11)
1
|T (jω)| = 1 + 2
ω
ωp
2N
At the 3-dB frequency ω3 dB we have:
1/2N
ω3 dB 2N
1
= 1 ⇒ ω3 dB =
2
ωp . Thus,
ωp
2
from Eq. (13.15) the attenuation at ω = 1.8ω3 dB
is:
1.8ω3 dB 2N
2
A = 10 log 1 + ωp
= 10 log 1 + 2
1
1.8 2
= 10 log(1 + 1.82N )
1/2N 2N
Figure 1
Chapter 13–6
(a) See previous page: Fig. 1(a).
13.20
(b) See previous page: Fig. 1(b).
13.19 fp = 10 kHz, Amax = 3 dB,
fs = 20 kHz, Amin = 20 dB
Using Eq. (13.14), we obtain
= 10Amax /10 − 1
= 103/10 − 1 = 1
Using Eq. (13.15), we have
A(ωs ) = 10 log[1 + 2 (ωs /ωp )2N ]
Thus,
Figure 1
Amin ≥ 10 log[1 + 2 (ωs /ωp )2N ]
20 ≥ 10 log (1 + 22N )
For N = 3,
10 log(1 + 26 ) = 18.1 dB
For N = 4,
From Fig. 1 we see that at the stopband edge, ωs ,
the Chebyshev filter provides A(dB) greater
attentuation than the Butterworth filter of the
same order and having the same Amax .
10 log(1 + 28 ) = 24.1 dB
13.21 N = 7, ωp = 1 rad/s, Amax = 0.5 dB
Thus,
N =4
The poles can be determined by reference to
Fig. 13.10(a):
1/4
1
ω0 = ωp
= ωp = 2π × 104 rad/s
1
π π ± jcos
p1 , p1∗ = ω0 −sin
8
8
= 2π × 104 (−0.383 ± j0.924)
3π
3π
± jcos
p2 , p2∗ = ω0 −sin
8
8
= 2π × 104 (−0.924 ± j0.383)
Thus,
T (s) =
(s2
+ 0.765ω0 s +
ω04
2
ω0 )(s2
+ 1.848ω0 s + ω02 )
where ω0 = 2π × 104 and where we have
assumed the dc gain to be unity.
Using Eq. (13.11), we obtain
|T (jω)| = 1+
1
ω
ωp
8
At f = 30 kHz = 3 fp , the attenuation is
A = −20 log|T | = 10 log(1 + 38 )
= 38.2 dB
Using Eq. (13.21), we obtain
= 10Amax /10 − 1
= 10 0.05 − 1 = 0.3439
From Eq. (13.18), we have
|T (jω)| = 1
1+
2
cos2 [N
cos−1 (ω/ωp )]
1
= 1 + 2 cos2 (7 cos−1 ω)
(1)
|T (jω)| will be equal to unity at the values of ω
that make
cos(7 cos−1 ω) = 0
(2)
Since the cosine function is 0 for angles that are
odd multiples of π/2, the solutions to Eq. (2) are
π
7 cos−1 ωk = (2k + 1)
2
where
k = 0, 1, 2, ....
Thus,
(2k + 1)π
14
We now can compute the values of ωk as
π
= 0.975 rad/s
ω1 = cos
14
3π
= 0.782 rad/s
ω2 = cos
14
ωk = cos
Chapter 13–7
5π
= 0.434 rad/s
14
7π
= 0 rad/s
ω4 = cos
14
Next, we determine the passband frequencies at
which maximum deviation from 0 dB occurs.
From Eq. (1) we see that these are the values of ω
that make
ω3 = cos
−1
cos (7 cos ω) = 1
2
(3)
Since the magnitude of the cosine function is
unity for angles that are multiples of π, the
solutions to Eq. (3) are given by
Finally, we note that since this is a 7th-order
all-pole filter, for s → ∞, T will be proportional
to 1/s7 ; that is, |T | will be proportional to 1/ω7 ,
thus the asymptotic response will be 7 × 6 = 42
dB/octave.
13.22
Amax = 1 dB ⇒ = 101/10 − 1 = 0.5088
fp = 3.4 kHz, fs = 4 kHz ⇒
fs
= 1.176
fp
Amin = 35 dB
7 cos−1 ωm = mπ
(a) To obtain the required order N , we use
Eq. (13.22),
or
A(ωs ) = 10 log[1 + 2 cosh2 (N cosh−1 (ωs /ωp )]
mπ
ωm = cos
7
where
Thus,
10 log[1 + 0.50882 cosh2 (N cosh−1 1.176)] ≥ 35
m = 0, 1, 2, ....
We attempt various values for N as follows:
We now can compute the values of ωm as
N
A(ωs )
8
28.8 dB
9
33.9 dB
ω0 = cos0 = 1 rad/s
π
ω1 = cos = 0.901 rad/s
7
2π
= 0.623 rad/s
ω2 = cos
7
3π
= 0.223 rad/s
ω3 = cos
7
10 39.0 dB
Use N = 10.
Excess attenuation = 39 − 35 = 4 dB
(b) The poles can be determined using
Eq. (13.23), namely
2k − 1 π
1
1
sinh
sinh−1
pk /ωp = −sin
N 2
N
2k − 1 π
1
1
+j cos
cosh
sinh−1
N 2
N
|T |, dB
0.434 0.782 0.975
0
0.5
0.223 0.623 0.900
k = 1, 2, ..., N
64.9
0
1
2
v, rad/s
Figure 1
Figure 1 shows a sketch of |T | for this 7th-order
Chebyshev filter, with the passband maxima and
minima identified. Note that the frequencies of
the maxima and minima do not depend on the
value of Amax .
First we determine
1
1
sinh−1
sinh
N
1
1
sinh−1
= 0.1433
= sinh
10
0.5088
and
1
−1 1
sinh
= 1.0102
cosh
N
Thus,
= 64.9 dB
π π + j1.0102 cos
p1 /ωp = −0.1433 sin
20
20
= −0.0224 + j0.9978
3π
3π
+ j1.0102 cos
p2 /ωp = −0.1433 sin
20
20
This point also is indicated on the sketch in Fig. 1.
= −0.0651 + j0.9001
To determine the attenuation at the stopband
frequency ω = 2 rad/s, we utilize the expression
in Eq. (13.22), thus
A(2) = 10 log[1 + 0.34932 cosh2 (7 cosh−1 2)]
Chapter 13–8
5π
5π
+ j1.0102 cos
p3 /ωp = −0.1433 sin
20
20
= −0.1013 + j0.7143
7π
7π
p4 /ωp = −0.1433 sin
+ j1.0102 cos
20
20
= −0.1277 + j0.4586
9π
9π
p5 /ωp = −0.1433 sin
+ j1.0102 cos
20
20
= −0.1415 + j0.1580
p6 = p5∗ , p7 = p4∗ , p8 = p3∗ , p9 = p2∗ , p10 = p1∗
Each pair of complex conjugate poles,
pk , pk∗ = ωp (−k ± j k )
gives rise to a quadratic factor in the denominator
of T (s) given by
= 3.84 × 10−3 × (2π × 3.4 × 103 )10
= 7.60 × 1040
13.23 Refer to Fig. 13.13 (row a).
Input resistance = R1
Thus, to obtain an input resistance of 12 k, we
select
R1 = 12 k
|DC gain| = 10 =
R2
R1
⇒ R2 = 10 R1 = 120 k
CR2 =
⇒C=
1
1
=
ω0
2π × 5 × 103
1
= 265 pF
2π × 5 × 103 × 120 × 103
s2 + sωp (2k ) + ωp2 (k2 + 2k )
13.24 Refer to Fig. 13.13 (row b).
where
H.F. Input resistance = R1
ωp = 2π × 3.4 × 10 rad/s
Thus,
Thus, we obtain for the five pole pairs:
R1 = 120 k
p1 , p1∗ : (s2 + s 0.0448ωp + 0.9961ωp2 )
CR1 =
3
p2 , p2∗ : (s2 + s 0.1302ωp + 0.8144ωp2 )
p3 , p3∗ : (s2 + s 0.2026ωp + 0.5205ωp2 )
⇒C=
1
1
=
ω0
2π × 200
1
2π × 200 × 120 × 103
= 6.63 nF
p4 , p4∗ : (s2 + s 0.2554ωp + 0.2266ωp2 )
High-frequency gain = −
p5 , p5∗ : (s2 + s 0.2830ωp + 0.0450ωp2 )
⇒ R2 = R1 = 120 k
R2
= −1
R1
The transfer function T (s) can now be written as
T (s) =
B
Product of five quadratic terms
The value of B determines the required dc gain,
specifically
DC gain =
B
ωp10 × 0.9961 × 0.8144 × 0.5205 × 0.2266 × 0.0450
=
B
4.31 × 10−3 ωp10
1
1
For DC gain = √
= √
1 + 2
1 + 0.50882
= 0.891
we select
B = 4.31 × 10−3 × ωp10 × 0.891
13.25 Refer to the op-amp-RC circuit in Fig.
13.13 (row c). Assuming an ideal op amp, we
have
Z2 (s)
Vo
=−
T (s) =
Vi
Z1 (s)
Since both Z1 and Z2 have a parallel structure, it is
far more convenient to work in terms of Y1 (s) and
Y2 (s), thus
T (s) = −
Y1 (s)
Y2 (s)
1
+ s C1
R1
=−
1
+ s C2
R2
C1
=−
C2
1
C1 R1
1
s+
C2 R2
s+
Chapter 13–9
Figure 1 shows a sketch of the magnitude of the
transfer function. Note that the magnitude of the
high-frequency gain is C1 /C2 = 100 or 40 dB.
Thus,
ωZ =
1
C1 R1
ωP =
1
C2 R2
DC gain = T (0) = −
R2
R1
HF gain = T (∞) = −
C1
C2
13.26 We use the op-amp-RC circuit of
Fig. 13.13(c).
Low-frequency input resistance = R1
Figure 1
Thus,
R1 = 10 k
DC gain = −
13.27 Figure 1 (below) shows the bandpass filter
realized as the cascade of a first-order low-pass
filter and a first-order high-pass filter. The
component values are determined as follows:
R2
= −1
R1
⇒ R2 = R1 = 10 k
1
ωZ
=
2π
2πC1 R1
fZ =
100 =
To make Rin as large as possible while satisfying
the constraint that no resistance is larger than
100 k, we select
1
2πC1 × 10 × 103
⇒ C1 =
fP = f0 =
1
= 0.16 μF
2π × 106
R1 = 100 k
The low-frequency gain of the low-pass circuit is
(−R2 /R1 ). With R1 = 100 k, the maximum gain
obtained is unity and is achieved by selecting
1
2πC2 R2
10 × 103 =
C2 =
Rin = R1
1
2πC2 × 10 × 103
R2 = 100 k
This implies that the required gain of 12 dB or
4 V/V must be all realized in the high-pass circuit.
1
= 1.6 nF
2π × 108
This figure belongs to Problem 13.27.
R2
R4
Vi
R1
C1
V1
Vi
0 dB
R3
V1
20 dB/decade
C2
Vo
Vo
V1
12 dB
Vo
20 dB/decade
Vi
12 dB
20 dB/decade
50 kHz
f
50 Hz
Figure 1
20 dB/
decade
f
50 Hz
50 kHz f
Chapter 13–10
The upper 3-dB frequency of the bandpass filter is
the 3-dB frequency of the low-pass circuit, that is,
1
50 × 10 =
2πC1 R2
3
⇒ C1 =
1
2π × 50 × 103 × 100 × 103
Thus,
Vo
sCR − 1
=−
Vi
sCR + 1
or
s − ω0
s − 1/CR
Vo
=−
=−
T (s) =
Vi
s + 1/CR
s + ω0
= 31.8 pF
where
Next, we consider the high-pass circuit. The
high-frequency (f
50 Hz) gain of this circuit is
(−R4 /R3 ). To obtain a gain of −4 V/V, we select
ω0 =
R4 = 100 k
100
= 25 k
4
The lower 3-dB frequency of the bandpass filter
(50 Hz) is the 3-dB frequency of the high-pass
circuit, thus
R3 =
1
2πC2 R3
50 =
⇒ C2 =
1
2π × 50 × 25 × 103
= 0.127 μF
R1
R1
R
V
I
V
C
Vi
T (jω) = −
=
ω0 − jω
ω0 + jω
1 − j(ω/ω0 )
1 + j(ω/ω0 )
1 + (ω/ω0 )2
=1
|T (jω)| =
1 + (ω/ω0 )2
ω
φ(ω) = −2 tan−1
ω0
1
ω
= tan − φ(ω)
⇒
ω0
2
=
Vo
R=
The results obtained are as follows:
= Vi
ω/ω0
0.268 0.577
1
1.732
3.732
ω0 (krad/s) 18.66 8.66
5
2.89
1.34
20
34.60
74.63
R (k)
1
sCR + 1
1
sCR + 1
Vi
1
Vi − V−
=
1−
I=
R1
R1
sCR + 1
Vi sCR
R1 sCR + 1
Vo = V− − IR1
=
5.36 11.55
1/sC
R + (1/sC)
13.29
I
V− = V+ = Vi
=
−30◦ −60◦ −90◦ −120◦ −150◦
φ
Figure 1
V+ = Vi
(1)
1
108
=
ω0 × 10 × 10−9
ω0
Refer to Fig. 1.
jω − ω0
jω + ω0
Thus, for a given phase shift φ, we can use Eq. (1)
to determine (ω/ω0 ). For ω = 5 × 103 rad/s, we
can then determine the required value of ω0 .
Finally, for C = 10 nF, the required value for R
can be found from
13.28
I
1
CR
Vi
sRCVi
−
sCR + 1 sCR + 1
I
Vi
R1
R1
C
V
V
R
Vo
Figure 1
Chapter 13–11
Im
Figure 1 (see previous page) shows the
circuit of Fig. 13.14 with R and C
interchanged. To determine the transfer function
T (s) = Vo (s)/Vi (s), we analyze the circuit as
follows:
jv
f
fN
R
V+ = Vi
1
R+
sC
s
= Vi
1
s+
CR
V− = V+ = Vi
Vi
R1
s
s+
1
CR
⎛
A graphical construction showing φN and φD and
their difference φ is depicted in Fig. 2 above.
⎞
Observe that the difference, φ, is a positive angle
whose value ranges from 180◦ (at ω = 0) to 0◦ (at
ω = ∞). The two end points should also be
obvious from T ( jω) which is −1 at ω = 0 and
+1 at ω = 0.
⎟
1 ⎠
s+
CR
s
1/CR
1
s+
CR
Vo = V− − IR1
⎡
13.30 Figure 1 shows a circuit composed of the
cascade connection of two all-pass circuits of the
type shown in Fig. 13.14. We require that each
circuit provide −120◦ phase shift at ω = 2π × 60
rad/s. From the data in Fig. 13.14(a),
⎤
1/CR ⎥
⎢
= Vi ⎣
−
1
1 ⎦
s+
s+
CR
CR
s
φ(ω) = −2 tan−1 (ωCR)
Thus,
T (s) =
s − (1/CR)
Vo (s)
=
Vi (s)
s + (1/CR)
Thus,
−120◦ = −2 tan−1 (ωCR)
s − ω0
=
s + ω0
ωCR = tan 60◦
where
2π × 60 × 1 × 10−6 × R =
ω0 = 1/CR
T (jω) =
Re
v0
0
Figure 2
Vi ⎜
Vi − V−
=
I=
⎝1 −
R1
R1
=
fD
v0
−ω0 + jω
ω0 + jω
R=
√
3
2
√
3
= 2.3 k
2π × 60 × 10−6 × 2
φ(ω) = φN (ω) − φD (ω)
The value of R1 can be selected arbitrarily, say
where φN is the phase angle of the numerator
and φD is the phase angle of the denominator.
R1 = 10 k
This figure belongs to Problem 13.30.
R1
R1
R1
R1
V1
R
C
R
V2
Figure 1
C
V3
Chapter 13–12
(a) Butterworth filter:
13.31 Refer to Fig. 13.16(a).
For a second-order
Butterworth, we have
√
Q = 1/ 2 = 0.707 and ω0 = ωp = 1 rad/s. The
dc gain is unity. Thus,
ω02
ω0
+ ω02
s2 + s
Q
T (s) =
1
√
+ 2s + 1
1
|T (jω)| = √
1 + ω2N
Thus,
T (s) =
108
= 2
s + 5000 s + 108
1
ωmax = ω0 1 −
2Q2
= 10
4
|T (j2)| = √
1
1−
= 9354 rad/s
2×4
(b) Chebyshev filter:
=1
|Tmax | = Q
1−
1
4Q2
= 2
1−
1
16
1
1 + 24
√
Amin = A(ωs ) = 20 log10 17 = 12.3 dB
Since the dc gain is unity, we have
|ao /ω02 |
s2
For a second-order Chebyshev filter, the poles are
given by Eq. (13.23), which for N = 2, ωp = 1,
and = 1 yields
π 1
sinh
sinh−1 1
p1 , p1∗ = −sin
4
2
π 1
cosh
sinh−1 1
±j cos
4
2
= 2.066
13.32 There are many possibilities, but only two
are optimal. The first is the Butterworth filter
which exhibits maximum flatness of |T | at ω = 0.
The second is the Chebyshev for which |T |
exhibits equiripple response in the passband.
= −0.3218 ± j0.7769
Thus, for this pair of complex-conjugate poles,
we have
ω0
= 2 × 0.3218 = 0.6436
Q
See Figure 1 below. Figure 1(a) shows the
second-order Butterworth filter that just meets the
given passband specifications. Figure 1(b) shows
the second-order Chebyshev filter that just meets
the given passband specifications. Note that no
stopband specifications were given (otherwise the
problem would be overspecified); we are simply
asked to calculate the attenuation at
ωs = 2ωp = 2 rad/s.
and
ω02 = 0.32182 + 0.77692 = 0.7071
Thus,
K
s2 + 0.6436 s + 0.7071
From
Fig. 1(b) we see that the dc gain is
1/ 1 + 2 = 0.7071
T (s) =
For both filters, since Amax = 3 dB, we have
Thus,
K = 0.7071 × 0.707 = 0.5
=1
This figure belongs to Problem 13.32.
Figure 1
Chapter 13–13
and
0.5
s2 + 0.6436 s + 0.7071
At s = j2, we have
T (s) =
0.5
|T (j2)| = (0.7071 − 4)2 + (0.6436 × 2)2
= 0.1414
Amin = A(2) = −20 log 0.1414
= 17.0 dB
13.33 Refer to Fig. 13.16(b). For a maximally
flat response, we have
√
Q = 1/ 2
and
−ω0
1
Poles are at
± jω0 1 −
2Q
4Q2
π
1
3
4
= − × 10 ± j2π × 10 1 −
2
4 × 202
π
= × 103 [−1 ± j40 × 0.9997]
2
= 1.57 × 103 (−1 ± j39.988)
Zeros are at s = 0 and s = ∞.
13.35 (a) A second-order bandpass filter with a
center-frequency gain of unity (arbitrary) has the
transfer function
T (s) =
s(ω0 /Q)
s2 + s(ω0 /Q) + ω02
ω3dB = ω0
Thus,
Thus,
ωω0 /Q
|T (jω)| = (ω02 − ω2 ) + (ωω0 /Q)2
(ω2 − ω2 )2
= 1/ 1 + Q2 0 2 2
ω ω0
ω0 = 1 rad/s
If the high-frequency gain is unity, then we have
a2 = 1
(1)
and
s2
√
s2 + 2 s + 1
The two zeros are at s = 0. The poles are complex
conjugate and given by
ω0
1
± jω0
s=−
1−
2Q
4Q2
T (s) =
⎞
!⎛
!
!
1 ⎟
1
⎜
±j !
=−
"⎝1 −
1
1⎠
2× √
4×
2
2
1
1
= −√ ± j√
2
2
= −0.707 ± j0.707
13.34 f0 = 10 kHz ⇒ ω0 = 2π × 104 rad/s
f0
BW =
= 500 Hz ⇒ Q = 20
Q
Center-frequency gain = 10
Thus,
ω0
s
10
Q
T (s) =
ω0
s2 + s
+ ω02
Q
=
π × 104 s
s2 + sπ × 103 + (2π × 104 )2
|T|
v1
v0
v2
v
Figure 1
From Fig. 1 we see that at each |T | (below the
peak value) there are two frequencies ω1 < ω0
and ω2 > ω0 with the same |T |. The relationship
between ω1 and ω2 can be determined by
considering the second term in the denominator
of Eq. (1), as follows:
ω02 − ω12
ω2 − ω02
= 2
ω1 ω0
ω2 ω0
Cross multiplying and collecting terms results in
ω1 ω2 = ω02
Q.E.D.
(b) Since the two edges of the passband must be
geometrically symmetric around ω0 , we have
√
ω0 = ωP1 ωP2
= 8100 × 10,000
= 9000 rad/s
Chapter 13–14
This figure belongs to Problem 13.35, part (b).
| T|, dB
0
3
22.1
3,000
fs1
27,000 f, Hz
fs2
8,100 9,000 10,000
fp1
f0
fp2
Figure 2
13.37 Since near the poles, |T | exhibits a peak,
and near the zeros it exhibits a dip, the results
shown in Fig. 1 are obtained.
The Q factor can now be found from
ω0
3-dB BW =
Q
10,000 − 8100 =
9000
Q
9000
= 4.74
1900
The geometric symmetry of |T | enables us to find
ωs2 from
⇒Q=
ωs1 ωs2 = ω02
13.38 Refer to Fig. 13.17(c). Using the voltage
divider rule, we obtain
(9000)
= 27,000 rad/s
3000
Using Eq. (1), we obtain
(ω2 − ω2 )2
Amin = A(ωs1 ) = 10 log 1 + Q2 0 2 2s1
ωs1 ω0
(90002 − 30002 )2
= 10 log 1 + 4.742
30002 × 90002
⇒ ωs2 =
Figure 1
2
Vo
ZRC
=
Vi
ZRC + sL
=
1
1 + sLYRC
=
1
1 + sL sC +
= 22.1 dB
T (s) =
Figure 2 shows a sketch of |T |.
13.36 An increase in Qp increases the magnitude
of the peak. On the other hand, an increase in Qz
increases the magnitude of the dip. Thus, the
results shown in Fig. 1 are obtained.
Vo (s)
=
Vi (s)
1
R
1
s2 LC + s
L
+1
R
1/LC
1
1
+
s2 + s
CR LC
Thus,
=
1
ω0 = √
[which is Eq. (13.34)]
LC
1
ω0
⇒ Q = ω0 CR
=
CR
Q
Qp > Qz
[which is Eq. (13.35)]
Qp < Qz
13.39 Q = ω0 CR
v
Figure 1
5 = 105 × C × 10 × 103
⇒ C = 5 nF
Q.E.D.
Chapter 13–15
Vo
sL2
L2
=
=
Vi
s(L1 + L2 )
L1 + L2
1
ω0 = √
LC
(c)
⇒ L = 1/ω02 C
L2
Vo
(0) =
Vi
L1 + L2
1
= 20 mH
1010 × 5 × 10−9
L=
13.40 (a) If L became 1.01L, we obtain
1
1
0.995
ω0 = √
√
√
1.01LC
1.005 LC
LC
L2
Vo
(∞) =
Vi
L1 + L2
No transmission zeros.
sL2
Vo
=
(d)
Vi
s(L1 + L2 ) + R
Thus, ω0 decreases by 0.5%.
Vo
(0) = 0
Vi
(b) If C increases by 1%, similar analysis as in
(a) results in ω0 decreasing by 0.5%.
L2
Vo
(∞) =
Vi
L1 + L2
(c) ω0 is independent of the value of R ⇒ no
change.
There is a transmission zero at 0 (dc) due to L2 .
13.42 Refer to the circuit in Fig. 13.18(b).
13.41 (a) As ω reaches 0 (dc), we get
Q = ω0 CR
Vo
=
Vi
1
√ = 106 × 1 × 10−9 × R
2
1/sC2
C1
=
1
1
C1 + C2
+
sC1
sC2
C1
Vo
=
Vi
C1 + C2
ω02 LC = 1
1012 × L × 1 × 10−9 = 1
As ω reaches ∞,
⇒ L = 1 mH
Vo
C1
=
Vi
C1 + C2
No transmission zero are introduced.
(b)
Vo
=
Vi
ZR,C2
ZR,C2 +
1
1
1+
YR,C2
sC1
=
1
1 1
+ sC2
1+
sC1 R
C2
1+
C1
1
=
Vo
(0) = 0
Vi
C2
1+
C1
ZLR +
1
sC
1
1
1+
YLR
sC
1
=
1
1 1
+
1+
sC R sL
=
1
+
sC1 R
1
ZLR
=
s
= C1
1
s 1+
+
C2
C1 R
Vo
(∞) =
Vi
13.43 Refer to Fig. 13.18(c). Using the voltage
divider rule, we obtain
Vo
=
Vi
1
sC1
=
= ⇒ R = 707 =
C1
C1 + C2
There is a transmission zero at s = 0, due to C1 .
1
1
1
+
1+
sCR s2 LC
s2
1
1
s2 + s
+
CR LC
13.44 Using superposition, we find the resulting
T (s) in each of the three cases and then sum the
results. Thus (see Figure 1 on the next page):
(a) When x is lifted off ground and connected to
Vx , the circuit becomes as shown in Fig. 1(a), and
the transfer function becomes that of a low-pass
Chapter 13–16
This figure belongs to Problem 13.44.
L
C
Vx
C
R
Vo1
Vy
L
(a)
R
Vo2
Vz
(b)
Figure 1
√
filter with ω0 = 1/ LC, Q = ω0 CR, and dc gain
of unity, thus
Vo1
ω02
=
ω0
Vx
+ ω02
s2 + s
Q
R
(1)
L
C
Vo3
(c)
13.46 (a) Figure 1 on the next page shows the
analysis. It is based on assuming ideal op amps
that exhibit virtual short circuits between their
input terminals, and draw zero currents into their
input terminals. Observe that:
(b) With y lifted off ground and connected to Vy ,
the resulting circuit [shown in Fig.
√ 1(b)], is that of
a high-pass filter with ω0 = 1/ LC, Q = ω0 CR,
and a high-frequency gain of unity, thus
(1) The circuit is fed at port-1 with a voltage V1 .
The virtual short circuit between the input
terminals of each of A2 and A1 cause the voltage
at port-2 to be
Vo2
s2
=
ω
0
Vy
+ ω02
s2 + s
Q
V2 = V1
(2)
(c) With z lifted off ground and connected to Vz ,
the resulting circuit shown in√Fig. 1(c) is that of a
bandpass filter with ω0 = 1/ LC, Q = ω0 CR,
and a center-frequency gain of unity, thus
ω0
s
Vo3
Q
=
(3)
ω
Vc
0
s2 + s
+ ω02
Q
Now summing (1), (2), and (3) gives
ω0
s2 Vy + s
Vz + ω02 Vx
Q
Vo =
ω0
s2 + s
+ ω02
Q
13.45 L = C4 R1 R3 R5 /R2
Selecting R1 = R2 = R3 = R5 = R = 10 k, we
have
L = C4 R
2
= C4 × 108
Thus,
C4 = L × 10−8
(a) For L = 15 H, we have
C4 = 15 × 10−8 F = 0.15 μF
(b) For L = 1.5 H, we have
C4 = 0.015 μF = 15 nF
(c) For L = 0.15 H, we have
C4 = 1.5 nF
(1)
(2) With port-2 terminated in an impedance Z5 ,
the current that flows out of port-2 is
I2 =
V2
Z5
(3) Following the analysis indicated, we find the
input current into port-1 as
I1 =
Z2 Z4
Z1 Z3 Z5
This current could have been written as
Z2 Z4
I2
I1 = V1
Z1 Z3
(2)
(4) Equations (1) and (2) describe the operation
of the circuit: It propagates the voltage applied to
port-1, V1 , and to port-2, V2 = V1 ; and whatever
current is drawn out of port-2 is multiplied by the
function (Z2 Z4 /Z1 Z3 ) and appears at port-1.
(5) The result of the two actions in (4) is that the
input impedance looking into port-1 becomes
V1
V2
=
I1
I2 (Z2 Z4 /Z1 Z3 )
V2
Z1 Z3
=
Z2 Z4
I2
or
Z1 Z3
Z5
Z11 =
Z2 Z4
Z11 ≡
(b) If port-1 is terminated in an impedance Z6 ,
the input impedance looking into port-2 can be
obtained by invoking the symmetry of the circuit,
thus
Z2 Z4
Z22 =
Z6
Z1 Z3
Chapter 13–17
This figure belongs to Problem 13.46.
I1 V1
1
Z2Z4
Z1Z3Z5
I1
Z1
V1
0
V1V1
V1
Z2
Z3
0
Z4
V1
Z2Z4
Z1Z3Z5
V1
A1
Z2Z4
Z3Z4
V1 (Z4/Z3Z5)
V1
V1
V1/Z5
( )
Z4
Z3Z5
V1V1
V1/Z5
2
V1/Z5
Z5
Z4
Z5
A2
Zin
V1
I1
( ZZ ZZ ) Z
1 3
5
2 4
Figure 1
Fig. 13.22(a) converts a resistance R5 into an
inductance L = C4 R1 R3 R5 /R2 . Other conversion
functions are possible and the circuit is known as
a Generalized Impedance Converter or GIC.
Thus, the circuit behaves as an impedance
transformer with the transformation ratio from
Z1 Z3
port-2 to port-1 being
and from port-1 to
Z2 Z4
Z2 Z4
port-2 being
.
Z1 Z3
13.47 Figure 1 below shows the suggested circuit
together with the analysis. The input impedance
looking into port-2 is
Since Z1 , Z2 , Z3 , and Z4 can be arbitrary functions
of s, the transformation ratio can be an arbitrary
function of s. Thus the circuit can be used as an
impedance converter. For instance, the particular
selection of impedances in Fig. 13.20(a) results in
the transformation ratio from port-2 to port-1
being (sC4 R1 R3 /R2 ). As a result, the circuit in
Z22 (s) ≡
V2
R2
= 2
I2
s C4 C6 R1 R3
For s = jω we have
Z22 (jω) = −
R2
ω2 C4 C6 R1 R2
This figure belongs to Problem 13.47.
A1
V2
1
0
R1
( sC RR V )
sC6V2
6 1 2
2
C6
sC6V2
0
R2
R3
sC6R1V2
R2
I2 V2
2
( s C CRR R V )
2
)
s2C4C6R1R3
R2
0
C4
V2
0
(
4
6 1 3
V
2
2
2
A2
Z22
Figure 1
Chapter 13–18
which is a negative resistance whose magnitude
depends on frequency ω; thus it is called a
Frequency Dependent Negative Resistance or
FDNR.
can be realized by the circuit in Fig. 13.13(a) with
R1 = R2 = 100 k (arbitrary but convenient
value).
1
ω0
CR1 =
13.48 Refer to Fig. 13.22(e) and the LPN entry in
Table 13.1.
⇒C=
Select
The second-order transfer function
C4 = C = 10 nF
T2 (s) =
Thus,
R1 = R2 = R3 = R5 =
=
1
ω0 C
R6 = Q × 1.59 = 15.9 k
2
2
ω0
10
C61 = C
= 10
= 6.94 nF
ωn
12
C62 = C − 6.94 = 3.06 nF
106
103
s2 + s
+ 106
1.618
C4 = C6 = C = 10 nF (practical value)
R1 = R2 = R3 = R5 =
=
1
ω0 C
1
= 100 k
103 × 10 × 10−9
R6 = Q/ω0 C = Q × 100 = 161.8 k
K =1
K =1
The second-order transfer function
13.49 For a fifth-order Butterworth filter with
Amax = 3 dB, and thus = 1, and ωp = 103 rad/s,
the poles can be determined using the graphical
construct of Fig. 13.10(a), thus
The pole pair p1 , p1∗ has ω0 = 103 rad/s and
π ω0
= 103 sin
= 103 × 0.309
2Q
10
1
= 1.618
2 × 0.309
p2∗
T3 (s) =
106
103
+ 106
s2 + s
0.618
can be realized using the circuit in Fig. 13.22(a)
with
C4 = C6 = C = 10 nF (practical value)
R1 = R2 = R3 = R5 =
R6 = Q
The pole pair p2 ,
has ω0 = 10 rad/s and
ω0
3π
= 103 sin
= 103 × 0.809
2Q
10
⇒Q=
1
= 0.01 μF = 10 nF
× 100 × 103
can be realized by the circuit in Fig. 13.22(a) with
1
= 1.59 k
2π × 10 × 103 × 10 × 10−9
⇒Q=
103
3
1
= 0.618
2 × 0.809
1
ω0 C
= 0.618 × 100 = 61.8 k
K =1
The complete filter circuit is obtained as the
cascade connection of the three filter sections, as
shown in Fig. 1 on the next page.
The real-axis pole p3 is at a
13.50 f0 = 2 kHz
s = −10 rad/s
Selecting,
3
1
= 100 k
ω0 C
Thus, the transfer function T (s) is
C4 = C6 = C = 1.0 nF, we obtain
103
T (s) =
×
s + 103
R1 = R2 = R3 = R5 =
106
×
103
+ 106
s2 + s
1.618
1
2π × 2 × 103 × 10 × 10−9
106
103
s2 + s
+ 106
0.618
=
The first-order factor,
R6 =
T1 (s) =
103
s + 103
1
ω0 C
= 79.6 k
Q
= 2 × 7.96 = 159.2 k
ω0 C
r1 = r2 = 10 k (arbitrary)
Chapter 13–19
This figure belongs to Problem 13.49.
100 k
10 nF
100 k
Vi
100 k
1
161.8 k
10 nF
100 k
100 k
10 nF
100 k
Vo
1
61.8 k
100 k
10 nF
100 k
100 k
10 nF
100 k
Figure 1
13.51 Refer to Fig. 13.22(f) and to the HPN entry
in Table 13.1.
T (s) =
K
s2 + (R2 /C4 C6 R1 R3 R51 )
1
R2
1
1
s2 + s
+
+
C6 R6
C4 C6 R1 R3 R51
R52
R2
=
C4 C6 R1 R3 R51
R2
1
1
ω02 =
+
C4 C6 R1 R3 R51
R52
ωn2
Thus,
ω02
R51
=
ωn2
R5
where
R5 = R51
R52
Thus,
ω02
R51 = R5
ωn2
2 ωn
R52 = R5 / 1 −
ω0
Choosing C4 = C5 = C (practical value) and
R1 = R2 = R3 = R4 = R, we get
R
1
ω02 = 2 3 = 2 2
C R
C R
⇒ R = 1/ω0 C
1
1
ω0
=
=
Q
C6 R6
CR6
Q
⇒ R6 =
ω0 C
Finally,
K = High-frequency gain
Chapter 13–20
then
13.52
(a) T (s) =
0.4508(s2 + 1.6996)
(s + 0.7294)(s2 + s0.2786 + 1.0504)
R=
= 9.76 k
2
ω0
C61 = C
ωn
Replacing s by s/105 , we obtain
T (s) =
2
s
+
1.6996
0.4508
1010
s2
s
s
+
0.7294
+
0.2786
+
1.0504
105
1010
105
= 1 × 10−9
C62 = 1 − 0.618 = 0.382 nF = 382 pF
√
1.0504
= 3.679
Q=
0.2786
(b) First-order section:
0.7294 × 105
s + 0.7294 × 105
R6 =
where the dc gain is made unity. This function can
be realized using the circuit of Fig. 13.13(a) with
Q
= 3.679 × 9.76 = 35.9 k
ω0 C
Finally,
K = DC gain = 1
C = 1 nF (arbitrary but convenient value)
R2 =
1.0504 × 1010
= 0.618 nF
1.6996 × 1010
= 618 pF
0.4508 × 105 (s2 + 1.6996 × 1010 )
=
(s + 0.7294 × 105 ) ×
(s2 + s0.2786 × 105 + 1.0504 × 1010 )
T1 (s) =
1
1
= √
ω0 C
1.0504 × 105 × 1 × 10−9
The complete circuit is shown in Fig. 1 below.
1
1
=
ω0 C
0.7294 × 105 × 1 × 10−9
= 13.71 k
13.53 Bandpass with f0 = 2 kHz, 3-dB
bandwidth of 50 Hz, thus
For dc gain of unity, we have
R1 = R2 = 13.71 k
Q=
Second-order LPN section:
f0
2 kHz
=
= 40
BW
50 Hz
Refer to the circuit in Fig. 13.24(a). Using
0.618(s2 + 1.6996 × 105 )
T2 (s) = 2
s + s0.2786 × 105 + 1.0504 × 1010
C = 10 nF
Selecting, we obtain
then
C4 = C61 + C62 = C = 1 nF
R=
and
1
1
=
3
ω0 C
2π × 2 × 10 × 10 × 10−9
= 7.96 k
R1 = R2 = R3 = R5 = R
This figure belongs to Problem 13.52, part (b).
Figure 1
Chapter 13–21
Select
then
R1 = 10 k
Rf = R1 = 10k
then
Selecting
Rf = R1 = 10 k
R2 = 10 k
Select
then
R2 = 1 k
R3 = R2 (2Q − 1) = 70 k
then
Selecting
R3 = (2Q − 1)R2 = (80 − 1) × 1 = 79 k
RL = RH = 10 k
1
1
=2−
= 1.975
K =2−
Q
40
then
Center-frequency gain = KQ = 1.975 × 40 = 79
RB = QRH = 4 × 10 = 40 k
Now,
1
1
= 2 − = 1.75
Q
4
13.54 (a) Refer to the circuits in Fig. 13.24 and
the transfer function in Eq. (13.66), that is,
K =2−
T (s) =
(RF /RH )s2 − s(RF /RB )ω0 + (RF /RL )ω02
−K
ω0
+ ω02
s2 + s
Q
Flat gain = −10 = −K
= −K
RF
RH
⇒ RF =
s2 − s(RH /RB )ω0 + (RH /RL )ω02
ω0
+ ω02
s2 + s
Q
T (s) =
(RF /RH )s2 − s(RF /RB )ω0 + (RF /RL )ω02
−K
s2 + s(ω0 /Q) + ω02
s2 − s(ω0 /Q) + ω02
T (s) = −Flat gain × 2
s + s(ω0 /Q) + ω02
(2)
That is,
Flat gain = −K
T (s) = −G
Q.E.D.
RF
RH
Q.E.D.
RH 2
ω
RL 0
2
RH
ω0
⇒
=
RL
ωn
Selecting
where
C = 1 nF
K =2−
1
1
= 10 k
= 5
ω0 C
10 × 1 × 10−9
Selecting
R1 = 10 k
(3)
ωn2 =
G=K
then
(2)
where G is the high-frequency gain, then by
equating the coefficients of the corresponding
numerator terms, we obtain
(b) ω0 = 105 rad/s, Q = 4 and flat gain =
10, thus
R=
s2 + ωn2
ω0
s2 + s
+ ω02
Q
RB = ∞
RB
RL = RH =
Q
(1)
For this to be the transfer function of a notch
filter, that is,
(1)
and
1
RH
=
RB
Q
10RH
10 × 10
=
= 57.1 k
K
1.75
13.55 Consider Fig. 13.24 and Eq. (13.66),
that is,
For this to be an all-pass function, that is,
then
RH
=1
RL
RF
RH
(4)
RF
RH
1
Q
thus
1 RF
G = 2−
Q RH
⇒
RF
G
=
RH
2 − (1/Q)
(5)
Chapter 13–22
Equations (3), (4), and (5) are the design
equations for the resistors associated with the
summer. Observe that the value of one of the
three resistors, RL , RH , and RF can be arbitrarily
selected.
13.57 Using Eq. (13.68) with R1 = ∞, we have
1
r
1
s2 − s
+
C1
Vo
R3
C1 R
CC1 RR2
=−
1
1
Vi
C
s2 + s
+
QCR C 2 R2
13.56 Refer to Fig. 13.26 and Table 13.2. Using
Thus,
ωz = 1/ CC1 RR2
1
R3
C1 R
Qz = √
CC1 RR2 r
C1
R
R3
=
C
R2
r
C = 10 nF,
then
R=
1
1
= 5
ω0 C
10 × 10 × 10−9
= 1 k
(1)
(2)
Rd = QR = 10 × 1 = 10 k
From Eqs. (1) and (2) we see that trimming ωz
and Qz can proceed in the following sequence:
Select
(a) Trim R2 to adjust ωz . This will affect Qz .
r = 20 k
(b) Trim R3 to adjust Qz . This will not affect ωz
R1 = R3 = ∞
13.58
If the dc gain is unity, then
1 = HF gain ×
⇒ HF gain =
T (s) =
ωn2
ω02
0.4508(s2 + 1.6996)
(s + 0.7294)(s2 + s0.2786 + 1.0504)
(a) Replacing s by s/105 , we obtain
105
1.3 × 105
T (s) =
2
0.4508 × 105 (s2 + 1.6996 × 1010 )
(s + 0.7294 × 105 )(s2 + s 0.2786 × 105 + 1.0504 × 1010 )
= 0.5917
(b) First-order section:
C1 = C × high-frequency gain
T1 (s) =
= 10 × 0.5917 = 5.92 nF
which is made to have a dc gain of unity, as
required. This function can be realized by the
circuit in Fig. 13.13(a). Selecting
(ω0 /ωn )2
R2 = R
= 1 k
HF gain
0.7294 × 105
s + 0.7294 × 105
C = 1 nF (arbitrary but convenient)
This figure belongs to Problem 13.58, part (b).
9.76 k
13.71 k
35.9 k
1 nF
1 nF
10 k
13.71 k
Vi
1 nF
618 pF
9.76 k
Vo
9.76 k
Figure 1
10 k
Chapter 13–23
we have
Thus,
1
R2 =
ω0 C
R3 = 14.14 k
R4 = 7.07 k
1
=
0.7294 × 105 × 1 × 10−9
= 13.71 k
13.60 Refer to Fig. 13.28(a).
For a dc gain of unity, we have
1
2
+ 2 2
CR
C
R
t(s) =
1
3
2
+
s +s
CR C 2 R2
s2 + s(2/τ ) + (1/τ 2 )
= 2
s + s(3/τ ) + (1/τ 2 )
s2 + s
R1 = R2 = 13.71 k
Second-order LPN section:
T2 (s) =
s2
0.618(s2 + 1.6996 × 1010 )
+ s0.2786 × 105 + 1.0504 × 1010
where the dc gain is unity. Refer to Fig. 13.26 and
Eq. (13.68).
Selecting
C = 1 nF
ω0 =
then
R=
If the network is placed in the negative-feedback
path of an ideal infinite-gain op amp, as in Fig.
13.24, the poles will be given by the roots of the
numerator polynomial, thus
1
τ
and
1
1
= √
ω0 C
1.0504 × 105 × 1 × 10−9
1/τ
= 0.5
2/τ
Thus, the poles will be coincident at
Q=
= 9.76 k
√
1.0504
Rd = QR =
× 9.76 = 35.9 k
0.2786
Select
s = −ω0 = −1/τ
13.61
r = 10 k
Now,
sC3Vo
C1 = C × high-frequency gain
= 1 × 0.618 = 0.618 nF = 618 pF
R2
R1 = ∞
C4 0
R3 = ∞
(ω0 /ωn )2
HF Gain
1
1.0504
×
= 9.76 ×
1.6996 0.618
= 9.76 k
R2 = R
Vi
sC4(ViVx)
X
C3
R1
VoVx
R1
sC3Vo
0V
Vo
Figure 1
The complete circuit is shown in Fig. 1.
13.59 Refer to Fig. 13.29 and Eqs. (13.75) and
(13.76):
C1 = C2 = C = 1 nF
R3 = R and R4 = R/4Q2 = R
4×
√
2Q
2/ 2
CR =
=
ω0
105
√
2
⇒R= 5
= 14.14 k
10 × 1 × 10−9
1
2
The circuit is shown in Fig. 1. The voltage at node
X can be found as
Vx = 0 − sC3 Vo R2
= −sC3 R2 Vo
=
R
2
(1)
A node equation at X can be written as
sC3 Vo + sC4 (Vi − Vx ) +
Vo − Vx
=0
R1
Substituting for Vx from Eq. (1), we obtain
(2)
Vo
1
sC3 Vo +sC4 Vi − (−sC3 R2 Vo ) sC4 +
+
=0
R1
R1
Chapter 13–24
1
R2
+
= −sC4 Vi
Vo sC3 +s2 C3 C4 R2 +sC3
R1
R1
Vo
=
Vi
=
−sC4
R2
1
s2 C3 C4 R2 + sC3 1 +
+
R1
R1
1
s2 + s
C4
where
ω0 = 2π × 10 × 103
f0
10
=
=5
BW
2
Thus,
Q=
−s/C3 R2
1
1
1
+
+
R1
R2
C3 C4 R1 R2
CR =
For R1 = R2 = R, C4 = C, and C3 = C/36, we
obtain
−s(36/CR)
Vo
=
36
2
Vi
+
s2 + s
CR C 2 R2
This is a bandpass function with
6
ω0 =
CR
6/CR
=3
Q=
2/CR
2×5
2π × 104
Selecting
C = 10 nF
we obtain
10
= 15.92 k
2π × 104 × 10 × 10−9
R=
Thus,
C1 = C2 = 10 nF
R3 = 15.92 k
R4 =
and
R
15.92
= 159.2 =
4Q2
100
Center-frequency gain = −18
Center-frequency gain = − 13.62
=−
1 R3
1
= − × 100 = −50 V/V
2 R4
2
13.63
R3
C2
1/C1 R4
1
1
1
+
C1
C2 R3
C1
R4
Vi
Vo
Figure 1
The circuit is shown in Fig. 1. The transfer
function can be obtained using the equation on
page 1126 with α = 1, thus
Vo
=
Vi
−s/C1 R4
1
1
1
1
s2 + s
+
+
C1
C2 R3
C1 C2 R3 R4
Figure 1
The circuit is shown in Fig. 1. The voltage at node
X is given by
R3 = R
1 Vo − βVi
sC
R
Vo
1
−
= βVi 1 +
sCR
sCR
R4 = R/4Q2
Writing a node equation at X gives
Using the design equations (13.75) and (13.76),
we obtain
CR =
2Q
ω0
Vx = βVi −
Vi − Vx
Vo − βVi
+
+ sC(Vo − Vx ) = 0
R
R/4Q2
(1)
Chapter 13–25
Substituting for Vx from Eq. (1) and collecting
terms gives
The analysis is shown in Fig. 1, below, left. The
voltage at node X is given by
Vi
=
Vx
Vo 1
R3 sC2
1
= Vo 1 +
sC2 R3
4Q2
2
1
2
s +s
1 + 2Q 1 −
+ 2 2
CR
β
C R
β
2
2
4Q
s2 + s
+
CR C 2 R2
We observe that, as expected,
2
2Q
CR
(a) To obtain an all-pass function, we set
2
1
2
1 + 2Q2 1 −
=−
CR
β
CR
ω0 =
⇒
A node equation at X provides
Vo − Vx
Vo
+ sC1 (Vi − Vx ) =
R4
R3
1
1
1
Vo
−
+ sCVi − Vx
+ sC1 = 0
R4
R3
R4
Vo
=
Vi
s2 + s
1
R3
s2
1
1
1
+
+
C1
C2
C1 C2 R3 R4
This is a high-pass function with a high-frequency
gain of unity. To obtain a maximally flat response
with ω3dB = 104 rad/s and using
But,
R2
R1 + R2
C1 = C2 = C = 10 nF
Thus,
then
R2
= Q2
R1
ω0 = ω3dB = 104 rad/s
1
1
1
+
Q = √ = ω0 R3
C1
C2
2
2
1
√ = 104 R3
10 × 10−9
2
(b) To obtain a notch function, we set
1
2
1 + 2Q2 1 −
=0
CR
β
⇒
(1)
Substituting for Vx from Eq. (1) and collecting
terms, we obtain
1
1
=1+ 2
β
Q
β=
Vx = Vo +
1
1
=1+
β
2Q2
1
2
⇒ R3 = √ × −8 × 10−4 = 14.14 k
2 10
1
ω02 =
C1 C2 R3 R4
1
108 = −8
10 × 10−8 × 14.4 × 103 × R4
100
k = 7.07 k
⇒ R4 =
14.14
or, equivalently,
R2
= 2Q2
R1
13.64
13.65
Vo
Vo
R3
C2 X
Vo
C1
Vo
R3
R3
R4
(VoVx)/R4
sC1(ViVx)
Vi
Figure 1
Figure 1
Chapter 13–26
Figure 1 (see previous page) shows a graphical
construct to determine the poles of the fifth order
Butterworth filter. The pair of complex conjugate
poles p1 and p1∗ have a frequency
The second second-order section also can be
realized using the circuit in Fig. 13.34(c). Here,
ω01 = ω3dB = 2π × 104 rad/s
C4 = C
and a Q factor
C3 =
Q1 =
R1 = R2 = R = 10 k
1
= 1.618
2 sin 18◦
C
4Q2
where Q = Q2 = 0.618. Thus
The pair of complex conjugate poles p2 and p2∗
have
ω02 = ω3dB = 2π × 104 rad/s
and a Q factor,
C3 =
C
= 0.655C
4 × 0.6182
CR =
2Q
2 × 0.618
=
ω0
2π × 104
2 × 0.618
= 1.97 nF
2π × 104 × 104
1
= 0.618
2 sin 54◦
The real-axis pole p3 is at
C3 = 1.29 nF
s = −ω0 = −2π × 10 rad/s
C4 = 1.97 nF
The first second-order section can be realized
using the circuit in Fig. 13.34(c). The design
equations are (13.77)–(13.80).
The first-order section can be realized using the
circuit in Fig. 13.13(a) with
⇒C=
Q2 =
4
R1 = R2 = R = 10 k
R1 = R2 = R = 10 k
C4 = C
C=
C3 = C/4Q2
=
Here, Q = Q1 = 1.618, thus
C3 =
C
= 0.095C
4 × 1.6182
CR =
2 × 1.618
2Q
=
ω0
2π × 104
⇒C=
1
ω0 R
1
= 1.59 nF
2π × 104 × 104
The complete circuit is shown in Fig. 2 below.
13.66 Refer to Fig. 13.31 and let the network n
have a transfer function
ω0
s
Va
Q
=
ω0
Vb
2
+ ω02
s +s
Q
2 × 1.618
= 5.15 nF
2π × 104 × 10 × 103
C3 = 0.492 nF = 492 pF
C4 = 5.15 nF
This figure belongs to Problem 13.65.
Figure 2
Chapter 13–27
which is a bandpass with a unity center-frequency
gain. The complementary network in (b) will
have a transfer function
Va
Va
=1−
Vc
Vb
ω0
s
Q
=1−
ω0
2
+ ω02
s +s
Q
=
s2 + ω02
ω0
+ ω02
s2 + s
Q
which is a notch function.
∂ω0
ω0
=−
∂C
2C
∂ω0
=0
∂R
∴ S ωL 0 =
∂ω0 L
= −1/2
∂L ω0
S ωC0 =
∂ω0
C
= −1/2
×
∂C
ω0
S ωR 0 =
∂ω0 R
=0
∂R ω0
For Q we have
√ R C −1
−Q
∂Q
= √
=
∂L
2
2L
L L
√
1 R
∂Q
Q
1R C
= √
=
√ =
∂C
2 LC
2C L
2C
∂Q R
= C/L =
C/L = Q/R
∂R
R
Q
SL = −
Q
Figure 1
SC =
As an example, consider the RLC bandpass circuit
shown in Fig. 1(a). It has the transfer function
SR =
1
CR
1
1
s2 + s
+
CR LC
Interchanging the input terminal with ground, we
obtain the circuit shown in Fig. 1(b).
Vo
T1 (s) =
=
Vi
Q
Q
L
1
×
=−
2L Q
2
Q
C
1
×
=
2C
Q
2
Q R
·
=1
R Q
s
Straightforward analysis shows that this circuit
has the transfer function
1
s2 +
LC
T2 (s) =
1
1
+
s2 + s
CR LC
which is a notch function. Observe that
T2 (s) = 1 − T1 (s)
that is, the circuits in (a) and (b) are
complementary.
13.67 For the circuit in Fig. 13.18(b) we have
1/LC
T (s) = 2
s + s/RC + 1/LC
1
C
Q=R
ω0 = √
L
LC
For ω0 we have
∂ω0
∂(LC)−1/2
1
ω0
=
= − L−3/2 C −1/2 =
∂L
∂L
2
2L
13.68 (a) y = uv
Sxy =
=v
=
∂(uv) x
∂x uv
∂u x
∂v x
+u
∂x uv
∂x uv
∂u x
∂v x
+
∂x u
∂x v
= Sxu + Sxv
(b) y = u/v
Sxy =
∂(u/v) x
∂y x
=
∂x y
∂x u/v
=
1 ∂u xv
u ∂v xv
− 2
v ∂x u
v ∂x u
=
∂u x
∂v x
−
∂x u
∂x v
= Sxu − Sxv
(c) y = ku
Sxy =
=
∂u x
∂y x
=k
∂x y
∂x ku
∂u x
∂x u
= Sxu
Chapter 13–28
∂ω0
−1
=
√
∂C3
2C3 C3 C4 R1 R2
−ω0
=
2C3
(d) y = un
Sxy =
∂y x
∂x y
∂u x
∂x un
∂u x
=n
∂n u
= nun−1
SCω30 =
Clearly, SCω30 = SCω40 = SRω10 = SRω20 = −
= nSxu
∂Q
=
∂C3
(e) y = f1 (u), u = f2 (x)
Sxy =
∂y x
∂x y
=
∂f1 (u) ∂u x u
∂u ∂x f1 (u) u
∂f2 (x) x
∂f1 (u) u
=
∂u f1 (u)
∂x u
∂f2 (x) x
∂f1 (u) u
=
∂u f1 (u)
∂x f2 (x)
=
Q
Similarly,
Q
SR2 = 0
−ω0
C4
1
×
=−
2C4
ω0
2
Similarly, SCω60 = SRω10 = SRω30 = SRω5o = −
1
2
ωO
1
∂ω0
=
⇒ SRω2o =
∂R2
2R2
2
Now for Q:
Q
∂Q R6
∂Q
Q
= +1
=
⇒ SR6 =
R6
∂R6 Q
∂R6
Q
1
∂Q
Q
Q
=
⇒ SC6 = SR2 = +
∂C6
2C6
2
13.71 Refer to the circuit in Fig. 13.35(f).
Vi
Io = gm1,2
2
Thus,
Gm =
gm1,2 = 2k n ID1,2
= 2k n (I /2)
= k nI
Thus,
13.70 Using Eqs. (13.78) and (13.79), we have
Gm =
1
C3 C4 R1 R2
1
1
1
1
+
C4
R1
R2
1
gm1,2
2
But,
Q
1
∂Q
Q
Q
=−
⇒ SC4 = SR1 ,R2 ,R3 = −
∂C4
2C4
2
C3 C4 R1 R2
1
2
If R1 = R2 ⇒ SR1 = 0.
−ω0
∂ω0
=
∂C4
2C4
√
−1
1
1
1
C3 C4 R1 R2
+
C4
R1
R2
∂Q
Q
1
Q
=
⇒ SC4 = +
∂C4
2C4
2
√
√
1/ R1 − R1 /R 2 Q
∂Q
= √ ·
∂R1
2
1
R1
R1 √ +
R2
R1
R2 /R 1 − R1 /R 2 Q
=
·
2
R2
R1
R1
+
R1
R2
1 R2 /R 1 − R1 /R 2
Q
∴ SR1 = 2 R2 /R 1 + R1 /R 2
13.69 From Table 13.1 we have
1
ω0 = C4 C6 R1 R3 R5 /R 2
C6 R2
Q = R6
C4 R1 R3 R5
Q=
√
1
2
−Q
2C3
Q
= Suy Sxu
ω0 = √
2C3
∴ SC3 = −
= Suf1 Sxf2
∴ S ωC40 =
∂ω0 C3
1
=−
∂C3 ωO
2
1
k nI
2
For Gm = 0.25 mA/V and k n = 0.5 mA/V2 ,
we have
1√
0.25 =
0.5I
2
⇒ I = 0.5 mA
Chapter 13–29
√
Since Gm is proportional to I , tuning Gm in the
range ±5% requires tuning I in the range
0.952 Inominal to 1.052 Inominal , which is
approximately ±10% of the nominal value.
13.72 R =
1
Gm
Thus,
10 × 106 =
Gm
2π × 5 × 10−12
⇒ Gm = 0.314 mA/V
13.75 Both Ro and Co will appear in parallel with
C, thus
1
1
= 3 = 10−3 A/V = 1 mA/V
R
10
Since the output terminal is connected back to the
input, the output resistance appears in effect in
parallel with the resistance 1/Gm , thus the actual
resistance realized is
1
Ro = 1 100 = 0.99 k
Gm
⇒ Gm =
Vo = Gm Vi
1
1
+ s(C + Co )
Ro
The transfer function realized will be
Vo
Gm
=
1
V1
+ s(C + Co )
Ro
The integrator time constant is
τ = (C + Co )/Gm
C
Co
=
1+
Gm
C
Co
The quantity 1 +
represents the error
C
factor. For the error to be less than 1%, we must
have
Co
≤ 0.01
C
⇒ C ≥ 100Co
13.73
Thus, the smallest value of C is 100Co .
Frequency of the low-frequency pole
Figure 1
The circuit is shown in Fig. 1, for which we can
write
1
(Gm1 V1 − Gm2 V2 + Gm3 V3 )
Vo =
Gm4
=
Gm2
Gm3
Gm1
V1 −
V2 +
V3
Gm4
Gm4
Gm4
To obtain
=
1
(C + Co )Ro
1
CRo
If this frequency is to be at least two decades
Gm
, then
lower than the unity gain frequency
C
1
Gm
≤ 0.01
CRo
C
100
Ro
Vo = V1 − 2V2 + 3V3
⇒ Gm ≥
we select
Thus, the smallest value of Gm must be 100/Ro .
Gm1 = Gm4
13.76 Refer to the circuit in Fig. 13.36(c) and its
transfer function in Eq. (13.91), namely
Gm2 = 2 Gm4
Gm3 = 3 Gm4
Vo
Gm1
=−
Vi
sC + Gm2
13.74 For the integrator in Fig. 13.36(b), we have
Gm
Vo
=
V1
sC
Unity-gain frequency =
Gm
2πC
Gm2
2πC
Gm2
20 × 106 =
2π × 2 × 10−12
Pole frequency =
⇒ Gm2 = 0.251 mA/V
Chapter 13–30
|DC gain| =
10 =
Gm1
Gm2
Thus,
Zin ≡
Gm1
Gm2
V1
C
=s
I1
Gm1 Gm2
which is that of an inductance L,
⇒ Gm1 = 2.51 mA/V
L=
13.77
C
Gm1 Gm2
Q.E.D.
(b) To obtain an LCR resonator, we connected a
capacitor C from node 1 to ground and a
resistance R realized by the transconductor Gm3 ,
as shown in Fig. 1 below.
(c) A fourth transconductor Gm4 is used to feed a
current Gm4 Vi to node 1, as shown in Fig. 1.
The resulting circuit is identical to that in
Fig. 13.37(b) except here C1 = C2 = C.
(d) With analogy to the identical circuit in
Fig. 13.37(b), V1 /Vi will be a second-order
bandpass filter with a transfer function given by
Eq. (13.93), and V2 /Vi will be a second-order
low-pass filter with a transfer function given by
Eq. (13.94). Thus,
Figure 1
Figure 1 shows the circuit. A node equation at X
yields
sC1 (Vi − Vo ) = Gm1 Vi + Gm2 Vo + sCVo
V1
=−
Vi
(sC1 Vi − Gm1 )Vi = Vo (Gm2 + sC + sC1 )
⇒
Vo
Gm1 − sC1
=−
Vi
Gm2 + s(C + C1 )
s(Gm4 /C)
Gm3
Gm1 Gm2
s2 + s
+
C1
C2
and,
V2
=−
Vi
13.78 (a) Refer to the circuit in Fig. P13.78. The
output current of the Gm2 transconductor is
Gm2 V1 . Thus,
Gm2
V1
sC
This is the input voltage to the negative
transconductor Gm1 . Thus the output current of
Gm1 , which is equal to I1 , will be
V2 =
Gm2 Gm4 /C 2
Gm1 Gm2
Gm2
s2 + s
+
C
C2
13.79 Using Eqs. (13.95) and (13.96), we have
Gm1 Gm2
(1)
ω0 =
C1 C2
√
Gm1 Gm2 C1
(2)
Q=
Gm3
C2
I1 = Gm1 V2
Gm1 Gm2
=
V1
sC
This figure belongs to Problem 13.78, part (b).
Gm3
Gm1
1
Vi
Gm4 C V
Gm2 C
V2
Figure 1
Chapter 13–31
Selecting Gm1 = Gm2 = Gm3 = Gm , we obtain
Gm
ω0 = √
C1 C2
C1
Q=
C2
Gm4 =
(3)
=
Gm
|Gain|
Q
0.785
× 5 = 0.785 mA/V
5
(4)
Selecting C2 = C, then from Eq. (4) we have
13.81 The resulting circuit is shown in Fig. 1. For
V2 we can write
C1 = Q2 C
V2 =
and from Eq. (3) we have
1
(Gm2 V1 − Gm5 Vi )
sC2
(1)
A node equation at X can be written as
Gm = ω0 QC
Gm1 V2 + sC3 (V1 − Vi ) + Gm4 Vi + Gm3 V1 + sC1 V1
13.80 f0 = 25 MHz, Q = 5,
=0
Center-frequency gain = 5
Substituting for V2 from Eq. (1) into Eq. (2) and
collecting terms results in the transfer function
The design equations are given by (13.99),
(13.100), and (13.101). Thus
(2)
V1
=
Vi Gm = ω0 C
s2
where
C = C1 = C2 = 5 pF
Gm = 2π × 25 × 106 × 5 × 10−12
= 0.785 mA/V
13.82 Req =
Thus,
−s
Tc
1
1
=
=
C1
fc C1
200 × 103 C1
For C1 = 1 pF,
Gm2 = Gm = 0.785 mA/V
Gm3 =
Gm1 Gm5
Gm4
+
C1 + C3
(C1 + C3 )C2
Gm3
Gm1 Gm2
2
s +s
+
C1 + C3
(C1 + C3 )C2
C3
C1 + C3
0.785
Gm
=
= 0.157 mA/V
Q
5
Req =
1
= 5 M
200 × 103 × 1 × 10−12
This figure belongs to Problem 13.81.
Gm1V2
X
Gm1 C3
Gm2Vi
Gm2 C2
V1
C1
Gm3V1
sC3 (V1 Vi)
Gm4 Gm3 Gm4Vi
Vi
Gm5Vi
Gm5 Figure 1
V2
Chapter 13–32
13.84 ω0 = ω3dB = 103 rad/s
√
Q = 1/ 2 and DC gain = 1
For C1 = 5 pF,
Req =
1
= 1 M
200 × 103 × 5 × 10−12
fc = 100 kHz, C1 = C2 = C = 5 pF
For C1 = 10 pF,
Req =
From Eqs. (13.109) and (13.110),
1
= 500 k
200 × 103 × 10 × 10−12
C3 = C4 = ω0 Tc C
1
× 5 × 10−12
100 × 103
13.83 Change transferred ⇒ Q = CV
= 103 ×
= 10−12 (1)
= 0.05 pF
= 1 pC
From Eq. (13.112),
For f0 = 100 kHz, average current is given by
IAV
C5 =
Q
=
= 1 pC × 100 × 103
T
The dc gain of the low-pass circuit is
= 0.1 μA
DC gain =
For each clock cycle, the output will change by
the same amount as the change in voltage
across C2 .
∴
V = Q/C2 =
C6 = C4 = 0.05 pF
1 pC
= 0.1 V
10 pF
13.85 Refer Fig. 1 below and Fig. 2 on next page.
For the BJT we have
10 V
= 100 cycles
0.1 V
slope =
C6
C4
For DC gain = 1,
For V = 0.1 V for each Clock cycle, the
amplifier will saturate in
=
0.05
C4
= √ = 0.071 pF
Q
1/ 2
10V
V
=
t
(100 cycles) 1/100 × 103
= 104 V/s
gm =
IC
1 mA
= 40 mA/V
VT
0.025 V
rπ =
β
200
=
= 5 k
gm
40
Cπ = 10 pF
This figure belongs to Problem 13.85, part (a).
RL
5 k
Vo
Rs 10 k
Vs
L 0.5 H
Vbe
C 200
pF
1 mA
Zin
Figure 1
Chapter 13–33
Miller capacitance = Cμ (1 + gm RL )
= 0.5(1 + 40 × 5)
= 100.5 pF
Total capacitance = C + Cπ + CMiller
= 200 + 10 + 100.5
= 310.5 pF
Thus, the additional parallel resistance required,
Ra , can be determined from
Ra
Rp = R
Ra
15.71 = 5.23
⇒ Ra = 7.84 k
13.87 f0 =
=
Zin
rp
Cp
Cm(1gmRL)
Q=
1
ω0 = √
LCtotal
= √
√
2π 36 × 10−6 × 103 × 10−12
= 838.8 kHz
Equivalent parallel resistance = 32 × 1 = 9 k
Figure 2
1
0.5 × 10−6 × 310.5 × 10−12
1
√
2π LC
1
= 80.3 Mrad/s
Total effective parallel resistance =
10 k 5 k = 3.33 k
Rp
ω0 L
9 × 103
2π × 838.8 × 103 × 36 × 10−6
= 47.4
=
13.88
3.33 × 103
R
=
= 83
Q=
ω0 L
80.3 × 106 × 0.5 × 10−6
80.3 × 106
ω0
=
= 967 kHz
Q
83
rπ
Vbe (ω0 ) = Vs
rπ + Rs
Im sCm(VpVo)
3-dB BW =
rp
Yin
Vp
1
= −40 × 5 × Vs
3
= −66.7Vs
#
#
# Vo (ω0 ) #
#
#
# V (ω ) # = 66.7 V/V
s
0
13.86 Rp = ω0 LQ
= 2π × 106 × 10 × 10−6 × 250
= 15.71 k
1
C= 2
ω0 L
=
1
= 2.53 nF
6
2
(2π × 10 ) × 10 × 10−6
For a 3-dB bandwidth of 12 kHz, we have
Q=
1 × 106
= 83.3
12 × 103
which requires a parallel resistance of
R = ω0 LQ
= 2π × 106 × 10 × 10−6 × 83.3
= 5.23 k
Cp
L Vo
gmVp
Vo (ω0 ) = −gm RL Vbe
Cm
Figure 1
Refer to Fig. 1. A node equation at the output
node yields
sCμ (Vπ − Vo ) = gm Vπ +
Vo
sL
sCμ − gm
1
+ sCμ
sL
Now, we can find Iμ as
⇒ Vo = Vπ
Iμ = sCμ (Vπ − Vo )
= sCμ Vπ − sCμ Vo
Thus,
sCμ − gm
Iμ
= sCμ − sCμ
1
Vπ
+ sCμ
sL
⎡ 1
⎤
+ sCμ − sCμ + gm
⎢
⎥
= sCμ⎣ sL
⎦
1
+ sCμ
sL
1
+ gm
= sCμ sL
1
+ sCμ
sL
Chapter 13–34
ω02 − ω2
. For
ωω0
ω = ω0 + δω where (δω/ω0 ) 1,
δω
ω = ω0 1 +
ω0
2δω
ω2 ω02 1 +
ω0
For s = jω, we obtain
Iμ
= jωCμ
Vπ
= jωCμ
Now, consider the quantity
1
jωL
1
jωCμ +
jωL
gm +
1 + jωLgm
1 − ω2 LCμ
since ωCμ 1
ωL
Thus,
ω02 − ω2
ω2 − ω2 (1 + 2δω/ω0 )
= 0 2 0
ωω0
ω0 (1 + δω/ω0 )
⇒ ω2 LCμ 1
Thus,
Iμ
jωCμ (1 + jωLgm )
Vπ
=
= jωCμ − ω2 LCμ gm
Substituting in Eq. (1), we obtain
Returning to Fig. 1, we can write
Yin =
−2δω/ω0
2δω
−
δω
ω0
1+
ω0
1
Iμ
+ jωCμ +
rπ
Vπ
|T (jω)| = 1
+ jωCπ + jωCμ − ω2 Cμ Lgm
rπ
1
=
− ω2 Cμ Lgm + jω(Cπ + Cμ )
rπ
=
Q.E.D.
1
|T (jω)|N = √ |T (jω0 )|N
2
K = |T (jω0 )|
Thus,
|T (jω0 )|
2
2
ω − ω2
1 + Q2 0
ωω0
|T (jω0 )|N
[1 + 4Q2 (δω/ω0 )2 ]N /2
The 3-dB bandwidth is the value of (2δω) at
which
where
|T (jω)| = (b) For N syncronously tuned sections connected
in cascade, we obtain
|T (jω)|N =
ω0
sK
Q
13.89 (a) T (s) =
ω
0
+ ω02
s2 + s
Q
|T (jω0 )|
2
δω
1 + 4Q2
ω0
(1)
Denoting, 2δω = B, we obtain
√
[1 + Q2 (B/ω0 )2 ]N /2 = 2
ω0
B=
21/N − 1
Q.E.D.
Q
Exercise 14–1
Ex: 14.1 Pole frequency f0 = 1 kHz
Center-frequency gain =
=
Ex: 14.3 The square wave at the output of the op
amp will have amplitude V = 2 V. Now if the
bandpass circuit is of high selectivity, the signal
across the tank circuit√will be that whose
frequency is ω0 = 1/ LC, which is the
fundamental frequency in the Fourier series of the
square wave at the output. The fundamental
frequency at the output will have a peak
amplitude of 4V /π = 8/π = 2.55 V. Now, since
the center-frequency gain of the bandpass circuit
is unity, the voltage across the tank circuit will
have a peak amplitude of 2.55 V.
1
Amplifier gain
1
V/V
2
Ex: 14.2
r2
r1
⫺
Vo
Vo K
K
sCVo /K
C
Vo
⫹
R
Vo /sKL
L
Ex: 14.4 L+ = V
Vo
sC ⫹ 1
K
sL
r2
K ⫽ 1 ⫹ r1
I⫽
(
)
Figure 1
Figure 1 shows the circuit with some of the
analysis already indicated. Writing a loop
equation gives
Vo
Vo = IR +
K
1
Vo
Vo
R sC +
+
=
K
sL
K
3
3
+ 0.7 1 +
9
9
R4
+ VD 1 +
R5
= 15
= 5 + 0.93 = 15.93 V
R3
R3
− VD 1 +
L− = − V
R2
R2
3
3
= −15 × − 0.7 1 +
9
9
Limiter gain =
(1)
−Rf
−60
=
R1
30
= −2 V/V
Thus limiting occurs at
r2
K =1+
r1
±5.93
2
= ± 2.97 V
Multiplying Eq. (1) by (sK/CR) and dividing by
Vo and rearranging gives
1
1
(1 − K) +
=0
CR
LC
r2
gives
Substituting K = 1 +
r1
s2 + s
1 r2
1
+
=0
CR r1
LC
For s = jω, we have
1
1 r2
2
=0
− jω
−ω +
LC
LC r1
Re[D(jω)] = −ω2 +
Im[D(jω)] = −
= −5.93 V/V
where
s2 − s
R4
R5
1
LC
ω r2
CR r1
For sustained oscillation, both the real part and
the imaginary part must be zero at the frequency
of oscillation, thus
1
1
Re = 0 ⇒ ω02 = √
⇒ ω0 = √
LC
LC
r2
Im = 0 ⇒
= 0 ⇒ r2 = 0
r1
Slope in the limiting regions
=
−Rf R4
60 3
= −0.095 V/V
=−
R1
30
ZP
R2
Ex: 14.5 (a) L (s) = 1 +
R1 ZP + ZS
R2
1
= 1+
R1
1 + ZS YP
⎛
⎞
⎟
1
20.3 ⎜
⎜
⎟
= 1+
⎠
1
1
10 ⎝
1+ R+
+ sC
sC
R
=
3.03
3 + sCR +
1
sCR
where R = 10 k and C = 16 nF
Thus,
L (s) =
3.03
3 + s16 × 10−5 +
1
s × 16 × 10−5
Exercise 14–2
Ex: 14.7 Figure 1 shows the circuit together with
the analysis details. The current I can be found as
Vo
1
1
Vo
I=
1+
2+
+
Rf
sCR
sCRRf
sCR
The closed-loop poles are found by setting
L (s) = 1; that is, they are the values of s,
satisfying
3 + s × 16 × 10−5 +
1
= 3.03
s × 16 × 10−5
Finally, Vx can be found from
1
1
I
Vo 2 +
−
Vx = −
sCRf
sCR
sC
1
1
Vo
1
Vo 2 +
1+
−
=−
sCRf
sCR
sCRf
sCR
1
Vo
2+
− 2 2
s C RRf
sCR
5
⇒s=
10
(0.015 ± j)
16
(b) The frequency of oscillation is 105 /16 rad/s
or approximately 1 kHz.
(c) Refer to Fig. 14.6. At the positive peak V̂o , the
voltage at node b will be one diode drop (0.7 V)
above the voltage V1 which is about 1/3 of Vo ;
thus Vb = 0.7 + V̂O /3. Now if we neglect the
current through D2 in comparison with the
currents through R5 and R6 , we find that
−
Vo
=−
Vx
V̂o − Vb ∼ Vb − (−15)
=
R5
R6
Vo
=
Vx
Vb + 15
V̂o − Vb
=
1
3
4
V̂o = Vb + 5
3
4 + s3CR +
1
sCR
ω2 C 2 RRf
1
4 + j 3ωCR −
ωCR
Ex: 14.8 From the loop-gain expression
+5
Vo
=
Vx
ω2 C 2 RRf
4 + j 3ωCR −
⇒ V̂o = 10.68 V
1
ωCR
we see that the phase will be zero at
From symmetry, we see that the negative peak is
equal to the positive peak. Thus the output
peak-to-peak voltage is 21.36 V.
1
ω0 CR
1
⇒ ω0 = √
3CR
At this frequency, we have
3ω0 CR =
Ex: 14.6 (a) For oscillations to start, we need
R2 /R1 = 2; thus the potentiometer should be set
so that its resistance to ground is 20 k.
(b) f0 =
s2 C 2 RRf
For s = jω,
Thus,
4
V̂o
0.7 +
V̂o =
3
3
3
4
1
Vx
=
+ 2 2
+ 3 3 2
Vo
sCRf
s C RRf
s C R Rf
ω2 C 2 RRf
Vo
= 0
Vi
4
1 Rf
=
12 R
1
1
=
2πRC
2π10 × 103 × 16 × 10−9
= 1 kHz
This figure belongs to Exercise 14.7.
[⫺ sCR1 V ⫺ sC1 VR (1⫹ sCR1 ) ]
o
f
o
f
⫺
I C
Vo /Rf
Vo
sCRf
Vo /Rf
C
Vx
C
R
0
⫺
0
⫹
R
Vo
sCRRf
Vo
sCRRf
(2⫹ sCR1 )
Vo
1⫹ 1
sCR
Rf
(
Figure 1
Rf
)
Vo
Exercise 14–3
Thus the minimum value that Rf must have for
oscillations to start is
Equating the real part to zero gives
Rf = 12R
ω02 =
Using the values in Fig. 14.9, we obtain
Equating the imaginary part to zero and using
Eq. (1) gives
1
1
= 3.608 krad/s
ω0 = √
−9 × 10 × 103
16
×
10
3
3.608 × 103
ω0
=
= 574.3 Hz
f0 =
2π
2π
Rf ≥ 12 × 10 = 120 k
1
1
⇒ CR =
CR
2π103
For C = 16 nF, we have R = 10 k.
Ex: 14.9 ω0 =
∴ the output is twice as large as the voltage across
the resonator, and the peak-to-peak amplitude is
4(2 × 1.4)
4V
=
= 3.6 V
π
π
Ex: 14.10 For the Hartley oscillator of Fig.
14.13(b), let the emitter be grounded and assume
that the total effective resistance between
collector and emitter is R. Replacing the BJT with
its equivalent circuit but neglecting rπ , Cπ and Cμ
and assuming that ro is absorbed into R, we obtain
the circuit shown in Fig. 1.
1
(L1 + L2 )C
1
R = 1
(L1 + L2 )C
L2 CR
gm +
gm R = 1 +
gm R =
L1
L2
L1
L2
which is the condition for sustained oscillations.
To ensure that oscillation will start, we need
gm R >
L1
L2
Q.E.D.
Ex: 14.11 Refer to the circuit in Fig. 14.14(a).
R = Rcoil ro RL
=
Q
100 × 103 2 × 103
ω0 C1
=
100
105 2 × 103
106 × 0.01 × 10−6
= 104 105 2 × 103 = 1.64 × 103 = 1.64 k
gm =
IC
1 mA
=
= 40 mA/V
VT
0.025 V
For sustained oscillations, we have
gm R =
Figure 1
A node equation at C gives
1
1
1
Vπ
+
+ gm Vπ +
Vπ 1 + 2
=0
sL2
R sL1
s L2 C
1
1
1
1 1
+
+ gm +
+ 2
+
s L1
L2
R
s L2 CR
1
=0
s3 L1 L2 C
1
1
1
1
+ s2
+
+
s3 gm +
+s
R
L1
L2
L2 CR
1
=0
L1 L2 C
1
1
+
+
jω −ω2 gm +
L2 CR
R
1
1
1
+
=0
− ω2
L1 L2 C
L1
L2
(1)
C2
C1
⇒ C2 = 0.01 × 40 × 1.64
= 0.66 μF
ω02 L
C1 C2
=1
C1 + C2
1012 × L ×
0.01 × 0.66
× 10−6 = 1
0.01 + 0.66
⇒ L = 101.5 μH
To allow oscillations to grow in amplitude, we
need
gm R >
C2
C1
which can be achieved by using a somewhat
smaller C2 than the value found above.
Exercise 14–4
1
Ex: 14.12 ω0 = 10 Grad/s = 10 × 109 = √
LC
10
10
1
= √
10 × 10−9 × C
Ex: 14.16
vI (t)
10
1ms
5
⇒ C = 1 pF
t
Rp = ω0 LQ
= 1010 × 10 × 10−9 × 10 = 1000 –10
= 1 k
gm |min
–5
vO (t)
1
1
=
=
(Rp ro )
(1 10) × 103
10
= 1.1 mA/V
t
–10
Ex: 14.13 From Eq. (14.26), we have
fs =
Time delay =
1
1
=
√
2π LCs
2π 0.52 × 0.012 × 10−12
= 2.015 MHz
Ex: 14.17
From Eq. (14.27), we have
fp =
2π L
=
vO
1
Cs Cp
Cs + Cp
ωo L ∼ ωs L
=
r
r
vI
3
Ex: 14.18 |VT | =
50 × 10−3 = 10
Ex: 14.14 VTH = |VTL | = β|L|
R1
× 13
R1 + R2
100
= 50 mV
2
R1
R2
10
R2
=
R1
0.05
R2 = 200R1
For R1 = 1 k, we have R2 = 200 k.
R2
= 1.6
R1
Ex: 14.19
100
R1
=
= 0.091 V/V
β=
R1 + R2
100 + 1000
R2 = 16 k
Ex: 14.15 VTH = VTL =
vO
A comparator with a threshold of 3 V and output
levels of ±12 V.
∼
= 55,000
5=
⫹
–12
2π × 2.015 × 106 × 0.52
120
5=
⫺
vI
1
= 2.018 MHz
=
3V
12
0.012 × 4 × 10−12
2π 0.52 ×
0.012 + 4
Q=
1
ms = 0.125 ms
8
R1
|L|
R2
R1
× 10
R2
R2 = 2R1
Possible choice: R1 = 10 k, R2 = 20 k
T = 2τ ln
1+β
1−β
= 2 × 0.01 × 10−6 × 106 × ln
= 0.00365 s
1
= 274 Hz
f0 =
T
1.091
1 − 0.091
Exercise 14–5
Ex: 14.20
f =
1
=
T
R2
⫹
vO
⫺
C⫽
0.1 μF
500
12.7
ln
11.3
f |25◦ C =
10 k⍀
500
Hz
12 + VD
ln
12 − VD
= 4281 Hz
At 0◦ C, VD = 0.7 + 0.05 = 0.75 V
R
10 k⍀
f |0◦ C =
500
= 3,995 Hz
12.75
ln
11.25
At 50◦ C, VD = 0.7 − 0.05 = 0.65 V
T1 = T2 = T /2
f |50◦ C =
vO (V)
12
500
= 4,611 Hz
12.65
ln
11.35
At 100◦ C, VD = 0.7 − 0.15 = 0.55 V
T/2
T
f |100◦ C =
t
–12
500
= 5,451 Hz.
12.55
ln
11.45
Ex: 14.21 To obtain a triangular waveform with
10-V peak-to-peak amplitude, we should have
v⫹
VD
VTH = −VTL = 5 V
But VTL = −L+ ×
T/2
T
t
R1
R2
Thus, −5 = −10 ×
10
R2
⇒ R2 = 20 k
–VD
For 1-kHz frequency, T = 1 ms.
Thus,
v⫺
VD
T /2 = 0.5 × 10−3 = CR
0
= 0.01 × 10−6 × R × 10/10
t
⇒ R = 50 k
T/2
⫺VD
T1
VTH − VTL
L+
Ex: 14.22 Using Eq. (14.38), we obtain
12.7
100 × 10−6 = 0.1 × 10−6 × R3 ln
10.8
T2
R3 = 6171 During T1 , we have
v − (t) = 12 − (12 + VD ) e−t/τ
Ex: 14.23 T = 1.1CR ⇒ R = T /1.1C = 9.1 k
v − = VD at t = T /2
VD = 12 − (12 + VD ) e−T /2τ
12 + VD
T = 2τ ln
12 − VD
= 2 × 0.1 × 10−6 × 10 × 103 × ln
Ex: 14.24 T = 0.69C(RA + 2RB )
12 + VD
12 − VD
1
= 0.69 × 103 × 10−12 (RA + 2RB )
100 × 103
⇒ RA + 2RB =
1
= 14.49 k
0.69 × 10−4
(1)
Exercise 14–6
At v = 3 V, the circuit provides
Using Eq. (14.47), we obtain
0.75 =
RA + RB
RA + 2RB
i=
RA + RB = 0.75 × 14.49 = 10.88 k
(2)
(1) − (2) ⇒ RB = 3.61 k
3
= 0.6 mA, while ideally
5
i = 0.1 × 9 = 0.9 mA. Thus the error is −0.3 mA.
* At v = 5 V, the circuit provides
Now, substituting into (2), we get
i=
RA = 7.27 k
Use 7.2 k and 3.6 k, standard 5% resistors.
5 5−3
+
= 2.6 mA, while ideally
5
1.25
i = 0.1 × 25 = 2.5 mA. Thus the error is
+0.1 mA.
* At v = 7 V, the circuit provides
Ex: 14.25
i=
i
⫹
R2
R3
i = 0.1 × 49 = 4.9 mA. Thus the
error is –0.3 mA.
* At v = 10 V, the circuit provides,
R1
v
7 7−3
+
= 4.6 mA, while ideally
5
1.25
3V
7V
i=
⫺
10 10 − 3 10 − 7
+
+
= 10 mA,
6
1.25
1.25
while ideally i = 10 mA. Thus the error is 0 A.
i = 0.1v 2
At v = 2 V, we obtain i = 0.4 mA.
Thus, R1 =
2
= 5 k.
0.4
For 3 V ≤ V ≤ 7 V, we have
i=
v
v −3
+
R1
R2
To obtain a perfect match at
V = 4 V ( i.e., to obtain i = 1.6 mA), we need
1.6 =
4 4−3
+
5
R2
Ex: 14.26
VCC
R2 = 1.25 k
For v ≥ 7V , we have
i=
RC
v
v −3 v −7
+
+
R1
R2
R3
To obtain a perfect match at v = 8V , we must
select R3 so that i = 6.4 mA:
6.4 =
8 8 − 3 8.7
+
+
5
1.25
R3
⇒ R3 = 1.25 k
RC
⫺ vO ⫹
Q1
vI
Q2
⫹ 2·42 VT ⫺
I
R
⫺VEE
I
Exercise 14–7
Ie1 = I + (2.42 VT ) /R
2.42 VT
=I 1+
IR
2.42 VT
=I 1+
2.5 V T
2.42
=I 1+
2.5
2.42
Ic1 ∼
= I 1+
2.5
2.42
Ic2 ∼
= I 1−
2.5
v O = (VCC − Ic2 RC ) − (VCC − Ic1 RC )
= (Ic1 − Ic2 ) RC
= IRC × 2 ×
2.42
2.5
= 0.25 × 10 × 2 ×
2.42
= 4.84 V
2.5
Chapter 14–1
14.1 Since the second-order bandpass filter will
exhibit zero phase at ω = ω0 , the circuit if it
oscillates will do so at
Thus, the poles will be in the left half of the
s-plane at a radial frequency ω0 and a horizontal
distance from the jω axis of
ω = ω0
σ =−
For the circuit to oscillate, the magnitude of the
gain at ω = ω0 must be at least unity, thus
(a) For the poles to be on the jω axis, we need
AK ≥ 1
σ =0
For sustained oscillations, we have
⇒ AK = 1
AK = 1
14.2 (a) The bandpass function can be written as
ω0
Ks
Q
T (s) =
ω
0
+ ω02
s2 + s
Q
ωω0
j
K
Q
T (jω) =
ωω0
(ω02 − ω2 ) + j
Q
Thus,
φ(ω) = 90◦ − tan−1
dφ
=
dω
1+
×
=−
1
Q2
ωω0 /Q
ω02 − ω2
1
ωω0
ω02 − ω2
2 ×
which is achieved by making
AK = 2
14.4
1
Q
(ω02 − ω2 )ω0 − ωω0 (−2ω)
(ω02 − ω2 )2
dφ
2Q
(ω = ω0 ) = −
dω
ω0
(b) For a change in phase φ, the corresponding
change in ω0 will be
=−
(b) For the poles in the right half of the s-plane at
ω0
, we
a horizontal distance from the jω axis of
2Q
have
ω0
σ =+
2Q
(ω0 /Q)(ω02 + ω2 )
1
(ω02 − ω2 )2 + 2 ω2 ω02
Q
ω0 =
ω0
(1 − AK)
2Q
φ
d φ/d ω
φ
2Q/ω0
ω0
φ
⇒
=−
ω0
2Q
Figure 1
Figure 1 shows the resulting circuit. Here Rp can
be found from
Rp = ω0 LQ
where
1
1
ω0 = √
= √
1 × 10−6 × 100 × 10−12
LC
= 108 rad/s
Thus,
Rp = 108 × 1 × 10−6 × 50
= 5 k
The total parallel resistance can now be found as
14.3 The characteristic equation is obtained as
follows:
1 − L(s) = 0
ω0
Ks
Q
=0
1−A
ω0
2
+ ω02
s +s
Q
ω0
⇒ s2 + s (1 − AK) + ω02 = 0
Q
R = Ri Ro Rp
= 5 5 5 = 1.67 k
The circuit will oscillate when the loop gain is
unity, that is,
Gm R = 1
⇒ Gm =
1
= 0.6 mA/V
R
Chapter 14–2
and the frequency of oscillation will be
f0 =
10
ω0
=
= 15.92 MHz
2π
2π
8
14.5 (a) A change of +1% in the value of L
causes a change of −0.5% in the value of ω0 .
(b) A change of +1% in the value C causes a
change of −0.5% in the value of ω0 .
(c) Since ω0 does not depend on the value of R,
there will be no change in ω0 as R changes by
+1%.
14.6 For the circuit to oscillate, two conditions
must be satisfied:
(1) The total phase shift around the loop should
be 0 or 360◦ , and
(2) The loop gain must be at least unity.
Here we have three amplifier stages (Fig. P14.6).
Thus the phase angle of each amplifier at the
oscillation frequency ω0 , must be 120◦ . Now, for
each amplifier stage we have
Vo = −gm Vi
1
1
+ sC
R
gm R
Vo
=−
Vi
1 + sCR
At s = jω0 , we have
gm R
Vo
(jω0 ) = −
Vi
1 + jω0 CR
=−
=
gm R(1 − jω0 CR)
1 + (ω0 CR)2
gm R
(−1 + jω0 CR)
1 + (ω0 CR)2
For the phase angle to be 120◦ , we need
14.7 For oscillations to begin, the total phase
shift around the loop at ω0 must be 0 or 360◦ .
Since the phase shift of the frequency-selective
network is 180◦ , the amplifier must have a phase
shift of 180◦ . Also, the loop gain at ω0 must be at
least unity. Since the frequency-selective network
has 12-dB attenuation, the amplifier gain must be
at least 12 dB or 4 V/V.
14.8 Refer to Fig. 14.4(e).
L+ = −L− = 3 V
R4
R3
=
= 0.05
R1
R1
Now,
L+ = V
R4
R4
+ 0.7 1 +
R5
R5
thus,
R4
R4
3 = 5 + 0.7 1 +
R5
R5
⇒
R4
2.3
=
R5
5.7
R3
2.3
=
R2
5.7
(3)
Selecting R1 = 100 k, Eq. (1) gives
R3 = R4 = 5 k
Then using Eqs. (2) and (3), we obtain
R2 = R5 =
5 × 5.7
= 12.4 k
2.3
14.9 Refer to Fig. 1 on the next page. By
connecting VB and RB , we are injecting a current
into the virtual ground node of VB /RB . To
neutralize this current, v I has to be at a negative
value that pulls an equal current through R1 . Thus,
the comparator threshold shifts from v I = 0 to
v I = −VB
R1
RB
To obtain a −2-V threshold with VB = 5 V,
we have
R1
−2 = −5
RB
= 0.5gm R
⇒
For a loop gain of unity, we have
For a comparator input resistance of 100 k,
we have
(0.5gm R) = 1
gm R = 2
gm |min
2
=
R
(2)
Similarly, from the equation for L− we obtain
tan 60 = ω0 CR
√
3
⇒ ω0 =
CR
Vo
gm R
(jω0 ) = gm R
= √
V
1+3
i
1 + (ω0 CR)2
3
(1)
R1
2
=
RB
5
R1 = 100 k
Using Eq. (1), we obtain
RB = 250 k
(1)
Chapter 14–3
This figure belongs to Problem 14.9.
Slope 5 V
R1
RB
VB 5 V
with
VB , RB
without
VB , RB
R3
vO
VB/RB
vO
L 3 V
R2
vI
R4
R1
R1
VB
RB
R4
2 V
R4
5 V
0
vI
L 3 V
Slope R2
R1
Figure 1
To obtain a slope of 0.05 in the limiting regions,
we use
R3
R4
=
= 0.05
R1
R1
=
s/CR
s2 + s(3/CR) +
1
(CR)2
which is a bandpass function with a center
frequency ω0 given by
thus,
1
CR
R3 = R4 = 5 k
ω0 =
To obtain L+ = −L− = 3 V, we use Eqs. (14.8)
and (14.9) with VD = 0, thus
and a pole-Q of
1
3
Q=
R3
R4
3
=
=
R2
R5
5
and a center-frequency gain of
5×5
= 8.33 k
⇒ R2 = R5 =
3
Gain =
For standard 5% resistors, use: R1 = 100 k,
RB = 240 k, R3 = R4 = 5.1 k,
R2 = R4 = 8.2 k.
1
3
14.11 The characteristic equation can be written
using the expression for the loop gain in
Eq. (14.10) as follows:
14.10 Refer to Fig. 14.5.
1 − L(s) = 0
Zp
Va
=
Vb
Zp + Zs
1−
=
1
1 + Zs Yp
=
1
1
1
1+ R+
+ sC
sC
R
=
1 + R2 /R1
3 + sCR +
1
sCR
R2
1
−1−
=0
sCR
R1
R2
1
=0
CR +
s2 + s 2 −
R1
(CR)2
3 + sCR +
Thus the poles have
1
1 + 1 + 1 + sCR +
1
sCR
=0
ω0 =
1
CR
Chapter 14–4
To obtain an 8-V peak-to-peak output, we use
R5
R5
15
+ 1+
× 0.7
R6
R6
V̂o = 4 =
2 1 R5
−
3 3 R6
and
Q=
1
2−
R2
R1
The poles will be on the jω axis for R2 /R1 = 2
and will be in the right half of the s-plane for
R2 /R1 > 2.
Q.E.D.
⇒
R5
= 0.115
R6
Since R5 = 1 k, then
14.12 If the closed-loop amplifier in Fig. 14.5
exhibits a phase shift of −3◦ for ω around ω0 , then
the loop-gain expression in Eq. (14.11) becomes
L(jω) =
−jφ
(1 + R2 /R1 )e
3 + j(ωCR − 1/ωCR)
If R3 and R6 are open circuited, substituting
R6 = ∞ in Eq. (1) yields
3π
= π/60
180
V̂o = 1.5VD = 1.05 V
This result can be obtained directly from the
circuit: If R3 and R6 are open circuited, the
positive peak of the output will be the voltage at
which D2 conducts. At this point, v O = V̂o and
1
2
v 1 = V̂o , thus the voltage across VD is V̂o or,
3
3
equivalently,
Oscillation will occur at the frequency ω0 for
which the phase angle of L(jω) is 0◦ :
1
−1 1
−φ = tan
ω0 CR −
3
ω0 CR
ω0 CR −
⇒
ω02
1
= −3 tan 3◦ = −0.157
ω0 CR
V̂o = 1.5VD
0.157
1
ω0 −
+
=0
CR
(CR)2
⇒ ω0 =
and
R3 = 8.66 k
where
φ=
R6 = 8.66 k
A similar situation occurs at the negative peak at
which diode D1 conducts and the voltage across it
2
will be V̂o , etc.
3
0.925
CR
14.13 Refer to Fig. 14.6. Assume that R3 = R6
and R4 = R5 and consider the magnitude of the
positive peak. When v O = V̂o , D2 just conducts
and clamps node b to a voltage
V̂o
Vb = V1 + VD + VD . Neglecting the current
3
through D2 , we can write
14.14
R2
R1
sCV1
0
V1
Vˆo − Vb
Vb − (−15)
=
R5
R6
V1 sCV1R
Substituting
V1 (1 sCR)
R
Figure 1
1
V̂o + VD
3
we obtain
R5
R5
15
+ 1+
VD
R6
R6
V̂o =
2 1 R5
−
3 3 R6
C
R
C
R5
R5
V̂o = 1 +
Vb + 15
R6
R6
Vo
I
R
sCV1
Thus,
Vb =
V1
(1)
Figure 1 shows the circuit and some of the
analysis for the purpose of determining the
transfer function of the RC circuit. The current I
is given by
I=
V1
(1 + sCR) + sCV1
R
Chapter 14–5
For Vo we now can write
Vo = V1 (1 + sCR) +
I
sC
V1
(1 + sCR) + V1
sCR
V1
s/CR
⇒
=
1
3
Vo
+
s2 + s
CR
(CR)2
= V1 (1 + sCR) +
The loop gain L(s) can now be found as
R2
CR
s 1+
R1
L(s) =
1
3
+
s2 + s
CR (CR)2
R2
jω 1 +
CR
R1
L(jω) = 1
3ω
− ω2 + j
(CR)2
CR
2
⇒ ω01
+
0.3
1
ω01 −
=0
CR
(CR)2
⇒ ω01 =
0.86
CR
That is, the frequency of oscillation is reduced by
14% to
f01 = 0.86f0 = 8.6 kHz
To restore operation to f0 = 10 kHz, we modify
the shunt resistor R to Rx , as indicated in Fig. 1.
C
Rx
Va C
Vo
Figure 1
Zero phase shift will occur at ω = ω0 :
1
CR
At ω = ω0 , we have
R2
1
1+
|L(jω)| =
3
R1
R
ω0 =
For oscillations to begin, we need
R2
1
1+
≥1
3
R1
R2
≥2
R1
⇒ CR = 0.159 × 10−4 s
For R = 10 k, we have
0.159 × 10−4
= 1.59 nF
10 × 103
Now, refer to Eq. (14.11). If the closed-loop
◦
amplifier hasan excess
phase lag of 5.7 , then the
R2 −j5.7◦
gain will be 1 +
. Oscillations will
e
R1
occur at the frequency ω01 at which the phase
angle of the denominator is −5.7◦ , that is,
1
1
= −5.7◦
tan−1 ω01 CR −
3
ω01 CR
ω01 CR −
=
=
14.15 First we design the circuit to operate at
10 kHz.
1
ω0 =
CR
1
2π × 10 × 103 =
CR
C=
We now require the feedback RC circuit to have a
phase shift of −(−5.7◦ ) = +5.7◦ at f = 10 kHz.
The transfer function of the RC circuit can be
found as follows:
Zp
Va
=
Vo
Zp + Zs
1
= 3 tan(−5.7◦ ) = −0.3
ω01 CR
1
1 + Zs Yp
1
1+ R+
sC
= R
2+
Rx
1
1
+ sC
Rx
1
+ sCR +
1
sCRx
For s = jω, we have
Va
= Vo
2+
R
Rx
1
+ j ωCR −
1
ωCRx
Va
must be +5.7◦
Vo
or equivalently, the phase angle of the
denominator must be −5.7◦ . Thus,
At ω = ω0 , the phase angle of
1
ω0 CRx
tan−1
= −5.7◦
R
2+
Rx
1
R
ω0 CR −
= 2+
tan(−5.7◦ )
ω0 CRx
Rx
R
= 2+
× −0.0998
Rx
ω0 CR −
Chapter 14–6
Now, ω0 CR = 1, thus
R
R
1−
= −0.0998 2 +
Rx
Rx
inverting input terminal will be (V̂o /3). Some of
the analysis is shown in the figure. We complete
the analysis as follows:
R
R
(1 − 0.0998) ⇒
= 1.33
Rx
Rx
⇒ Rx = 0.75 R = 7.5 k
5
V̂o − V̂o − 0.65
50
6
I1 =
= 10V̂o − V̂o − 6.5
0.1
6
At ω = ω0 and for Rx = 7.5 k
Va
1
(ω0 ) = 10
10
Vo
2+
+j 1−
7.5
7.5
5
V̂o − V̂o
5
6
= 0.1V̂o − V̂o
I2 =
10
60
1 + 2 × 0.0998 =
I1 + I2 =
1
3.33 − j0.33
Va
1
1
(ω0 ) = =
V
3.35
o
(3.33)2 + (0.33)2
=
V̂o
30
Thus,
5
V̂o
50
+ 0.1 −
− 6.5 =
V̂o 10 −
6
60
30
Thus the magnitude of the gain of the amplifier
must be 3.35 V/V. Thus, R2 /R1 must be changed
to
⇒ V̂o = 3.94 V
Thus the peak-to-peak of the output sinusoid will
be 2 × 3.94 = 7.88 V.
R2
= 2.35
R1
14.17 Refer to Fig. 1, below.
14.16
I1 =
Vo
V
5
15 o Vo
30
3
6
0.1 k
I1
10 k
Vo
30 0
10 k
I3 = I1 + I2 =
Vo /3
V
o
30
10
(1)
I2 = sCV1
I2
Vo /3
Rf
V1
R
R
⇒ V1 = −
Vo
Rf
Vo = −Rf I1 = −
0.65 V
15 k
V1
R
Vo
I3 =
Figure 1
V1
+ sCV1
R
V1
(1 + sCR)
R
V2 = V1 + I3 R = V1 (2 + sCR)
The circuit in Fig. 1 depicts the situation when
v O = V̂o . We made use of the fact that for
sustained oscillations the closed-loop gain of the
amplifier must be 3. Thus the voltage at the
I4 = sCV2 = sCV1 (2 + sCR)
I5 = I3 + I4 =
V1
(1 + sCR) + sCV1 (2 + sCR)
R
This figure belongs to Problem 14.17.
Rf
I1
X
I7
Vx
R
V3 I5
R
V2 I3
R
V1 I1
R
I6
I4
I2
C
C
C
Figure 1
Vo
Chapter 14–7
V3 = V2 + I5 R
C=
= V1 (2 + sCR) + V1 (1 + sCR) + sCRV1 (2 + sCR)
Rf = 56 × 10 = 560 k
= V1 (3 + s4CR + s2 C 2 R2 )
I6 = sCV3
14.18 Figure 1 shows the circuit with the
additional resistance R included. The loop has
been broken at the output of the op amp. The
analysis will determine Vo /Vx and equate it to
unity, which is the condition for sustained
oscillations.
= sCV1 (3 + s4CR + s2 C 2 R2 )
I7 = I5 + I6
V1
(1 + sCR) + sCV1 (5 + s5CR + s2 C 2 R2 )
R
Vx = V3 + I7 R
=
To begin, observe that the voltage V1 is related to
Vo by
= V1 (3 + s4CR + s C R )
2
2 2
Rf
Vo
=−
V1
R
+V1 (1 + sCR) + V1 (s5CR + s2 5C 2 R2 + s3 C 3 R3 )
= V1 (4 + s 10CR + s 6C R + s C R )
2
2 2
3
√
10
= 3.36 nF
2π × 15 × 103 × 10 × 103
3 3
(1)
Also, the current I1 is given by
Substituting for V1 from Eq. (1) and equating Vx
with Vo , we obtain
V1
(2)
R
We now proceed to determine the various currents
and voltages of the RC network as follows:
I1 =
Rf
= 4 + s 10CR + s2 6 C 2 R2 + s3 C 3 R3
R
For s = jω
−
V2 = V1 +
Rf
= (4 − 6 ω2 C 2 R2 ) + jω (10CR − ω2 C 3 R3 )
−
R
Equating the imaginary part on the RHS to zero,
we obtain for the frequency of oscillation ω0
√
10
ω0 =
CR
Equating the real parts on both sides gives the
condition for sustained oscillations as
Rf
10
= 6 2 2 C 2 R2 − 4 = 56
R
C R
That is,
1
I1
sC
1 V1
1
= V1 1 +
sC R
sCR
V2
V1
1
=
1+
I2 =
R
R
sCR
V1
1
V1
+
1+
I3 = I1 + I2 =
R
R
sCR
1
V1
2+
=
R
sCR
= V1 +
V3 = V2 +
Rf = 56R
I3
sC
V1
1
+
2+
= V1
sCR
sCR
1
3
+
= V1 1 +
sCR s2 C 2 R2
V1
V3
3
1
=
1+
+ 2 2 2
I4 =
R
R
sCR s C R
1
1+
sCR
Numerical values:
f0 = 15 kHz
R = 10 k
√
10
CR =
2π × 15 × 103
This figure belongs to Problem 14.18.
Rf
V1
C
Vx
V3 I3 C
C
V2
R
I5
I1
R
R
I4
I2
Figure 1
Vo
Chapter 14–8
I5 = I3 + I4
1
V1
V1
3
1
2+
=
+
1+
+ 2 2 2
R
sCR
R
sCR s C R
4
1
V1
3+
+
=
R
sCR s2 C 2 R2
I5
Vx = V3 +
sC
3
1
+ 2 2 2
= V1 1 +
sCR s C R
4
1
V1
3+
+ 2 2 2
+
sCR
sCR s C R
5
1
6
+ 2 2 2 + 3 3 3
= V1 1 +
sCR s C R
sC R
14.19 Refer to the circuit in Fig. 14.10 with the
limiter eliminated and with the loop broken at X
to determine the loop gain
L(s) =
Vo2
Vx
To determine L(s), we note that it is the product
of the transfer functions of the inverting
integrator formed around op amp 1:
1
Vo1
=−
Vx
sCR
(1)
and the noninverting integrator formed around op
amp 2. To obtain the transfer function of the
latter, refer to Fig. 1.
Now, by replacing V1 by the value from Eq. (1),
we obtain
1
6
R
5
Vx = −Vo
1+
+ 2 2 2 + 3 3 3
Rf
sCR s C R
sC R
For sustained oscillations Vo = Vx , thus
−
Rf
6
5
1
=1+
+
+ 3 3 3
R
sCR s2 C 2 R2
sC R
For s = jω, we have
Figure 1
Rf
6
5
1
=1+
− 2 2 2 − 3 3 3
−
R
jωCR ω C R
jω C R
5
6
1
= 1− 2 2 2 −j
−
ω C R
ωCR ω3 C 3 R3
Thus, oscillation will occur at the frequency that
renders the imaginary part of the RHS zero:
1
6
= 3 3 3 :
ω0 CR
ω0 C R
Rf
5
=1−
= −29
R
1/6
Thus,
which is the minimum required value for Rf to
obtain sustained oscillations. Numerical values:
1
√
2π 6 × 16 × 10−9 × 10 × 103
Rf = 290 k
Vo2
=
Vo1
1
1
R
sCR + −
2 Rf
2R
, we obtain
1+
1
(2)
2
Using Eqs. (1) and (2), we obtain the loop gain as
sCR −
L(s) = −
Rf = 29R
= 406 Hz
Vo2
=
Vo1
Substituting for Rf =
At this frequency, the real part of the RHS must
be equal to (−Rf /R):
f0 =
1
Vo1 − Vo2
Vo2
Vo2
2
+
= sC
2R
2Rf
2
⇒
1
⇒ ω0 = √
6CR
−
Writing a node equation at the positive input
terminal of op amp 2, we obtain
1
sCR
1
2
The characteristic equation can now be written as
sCR −
1 − L(s) = 0
1
sCR
1
=0
2
+1=0
sCR sCR −
2
1+
sCR −
Chapter 14–9
s2 − s
1
1 + 2 2 =0
CR 2
C R
Thus, the poles are
s=
1
2CR
2
±
1
2
1
C 2 R2
2
2
−
4
C 2 R2
For 4, we have
1
±j
s
CR
4
R=
Thus, relative to the fundamental, we have:
(a) The second harmonic = 0.
(b) The third harmonic
from which it is obvious that the poles are in the
right half of the s-plane.
Q.E.D.
14.20 ω0 =
For the nth harmonic, we have ω = nω0 , where
n = 3, 5, 7, ...... Since n is large and Q = 20 is
large, we obtain
1
|T (jω)| 1/Q n −
n
=
1/3
1
20 3 −
3
= 6.25 × 10−3
(c) The fifth harmonic
1
CR
1
2π × 10 × 103 × 1.6 × 10−9
= 9.95 k
The square wave v 2 will have a peak-to-peak
amplitude
1/5
1
20 5 −
5
= 2.08 × 10−3
(d) The rms of harmonics to the tenth:
= 1.04 × 10−3
The component at the fundamental frequency ω0
will have a peak-to-peak amplitude of
4 V/π = 1.78 V. The filter has a center-frequency
gain of 2, thus at v 1 the sine wave will have a
peak-to-peak amplitude of approximately 3.6 V.
The ninth harmonic =
14.21 The different harmonic components will be
attenuated relative to the fundamental by the
selective response of the bandpass circuit. Let us
first determine the magnitude of the transmission
of the bandpass filter at a frequency ω relative to
that at the fundamental frequency ω0 ,
ω0
s
Q
T (s) =
ω
0
s2 + s
+ ω02
Q
ωω0
Q
|T (jω)| =
= 1/ 1 + Q2
ω02 − ω2
ωω0
2
ω
ω0
−
ω
ω0
1/9
20 9 −
1
9
1
7
= 0.625 × 10−3
Thus, the rms of harmonics to the tenth
= 6.252 + 2.082 + 1.042 + 0.6252 × 10−3
= 6.70 × 10−3
14.22
G
sC2Vgs
D
sC2Vgs
C2
Vgs
L
gmVgs
S
C1
RL
Figure 1
(ω02 − ω2 )2 +
= 1/ 1 + Q2
1/7
20 7 −
V = 1.4 V
The output amplitude can be doubled by adding a
diode in series with each of the diodes in the
limiter.
The seventh harmonic =
ωω0
Q
2
Figure 1 shows the equivalent circuit together
with some of the analysis. The voltage at the gate,
Vg , can be expressed as
Vg = −s2 LC2 Vgs
2
(1)
The voltage at the source, Vs , can be expressed as
Vs = Vg − Vgs
Chapter 14–10
Thus,
Vs = −s2 LC2 Vgs − Vgs
(2)
A node equation at S provides
1
sC2 Vgs + gm Vgs =
+ sC1 Vs
RL
The voltage Ve can be expressed as
Substituting for Vs from Eq. (2), we obtain
1
sC2 Vgs + gm Vgs = −
+ sC1 (s2 LC2 + 1)Vgs
RL
Dividing by Vgs and collecting terms, we obtain
LC2
1
s3 LC1 C2 +s2
+s(C1 +C2 )+ gm +
=0
RL
RL
For s = jω, we have
jω[−ω2 LC1 C2 + (C1+ C2 )] +
1
LC2
gm +
− ω2
=0
RL
RL
(3)
This is the equation that governs the operation of
the oscillator circuit. The frequency of oscillation
ω0 is the value of ω at which the imaginary part is
zero, thus
C1 C2
2
ω0 = 1
L
(4)
C1 + C2
⇒ ω0 = 1
L
C1 C2
C1 + C2
The condition for sustained oscillations can be
found by equating the real part of Eq. (3) to zero
and making use of (4), thus
1
C1 + C2
1
gm +
=
RL
C1
RL
⇒ gm RL =
C2
C1
Ve = Vb − Vπ
Thus,
Ve = −sL
1
+ sC2 Vπ − Vπ
rπ
C2
C1
Substituting for Ve from Eq. (2), we obtain
1
1
+ sC2 Vπ −
sL
− sC1 +
RL
rπ
1
sC1 +
Vπ
RL
1
= gm +
Vπ + sC2 Vπ
rπ
Dividing by Vπ and collecting terms, we obtain
C1
C2
+
+
s3 LC1 C2 + s2 L
rπ
RL
1
1
L
=0
+ (C1 + C2 ) + gm +
+
s
RL rπ
rπ
RL
For s = jω, we have
L
+ (C1 + C2 )
jω −ω2 LC1 C2 +
RL rπ
1
1
C1
C2
+
+
− ω2 L
+ gm +
rπ
RL
rπ
RL
(3)
This is the equation that governs the operation of
the oscillator circuit. The frequency of oscillation
ω0 is the value of ω at which the imaginary part
becomes zero, thus
ω02 =
14.23
(2)
Writing a node equation at E, we obtain
1
1
Ve = gm +
Vπ + sC2 Vπ
sC1 +
RL
rπ
=0
To ensure that oscillations start, we use
gm RL >
Figure 1 shows the equivalent circuit together
with some of the analysis. The voltage Vb can be
expressed as
1
Vb = −sL
+ sC2 Vπ
(1)
rπ
C1 + C2
1
+
LC1 C2
RL rπ C1 C2
(4)
Note that for rπ large so that the second term on
the RHS can be neglected, we have
C1 C2
L
ω02 1
C1 + C2
ω0 = 1
Figure 1
L
C1 C2
C1 + C2
which is the expected value. Taking rπ into
account will shift the oscillation frequency
slightly from this value.
(5)
Chapter 14–11
Substituting for Vc from (1), we obtain
1
1
−Vπ −
gm +
+ sC2 Vπ =
sC1
RL
1
+ sC2
Vπ sL
RL
The condition for sustained oscillations can be
obtained by equating the real part of Eq. (3) to
zero and making use of (4), thus
gm +
1
1
+
=
rπ
RL
1
C2
C1
C1 + C2
+
+
L
LC1 C2
RL rπ C1 C2
rπ
RL
(6)
s3 LC1 C2 + s2
For rπ large, we have
1
C1 + C2
C2
gm +
RL
C1 C2
RL
gm RL + 1 = 1 +
⇒ gm RL =
jω[−ω2 LC1 C2 + (C1 +C2 )] +
1
LC1
−ω2
+ gm +
=0
RL
RL
C2
C1
C2
C1
(7)
C2
C1
14.24
Vc
C1
E
C2
gmVp
−
Vp
rp
L
C1 C2
C1 + C2
The condition for sustained oscillation can be
found by equating the real part in Eq. (2) to zero
at ω = ω0 and by making use of Eq. (3). Thus,
I1
L
C1 + C2 1
1
+ gm +
=0
C2 RL
RL
C1
C2
While to ensure that oscillations start, we make
C1
gm RL >
C2
Observe then in this circuit, we did not have to
resort to assuming rπ to be large in order to obtain
simplified expressions. Here rπ is simply included
with RL to obtain RL and thus can be easily taken
into account. A drawback of our analysis,
however, is that ro was not taken into account.
⇒ gm RL =
RL
B
RL RL rp
Figure 1
Figure 1 shows the equivalent circuit where we
have neglected ro . A node equation at E provides
the following expression for I1 :
1
+ sC2
I1 = Vπ gm +
RL
14.25
The collector voltage Vc can now be found as
1
I1
sC1
1
1
Vc = −Vπ −
+ sC2 Vπ
gm +
sC1
RL
Vc = −Vπ −
A node equation at C provides
1
Vc
= Vπ gm +
+ sC2 − gm Vπ
sL
RL
1
+ sC2
= Vπ
RL
(2)
This is the equation that governs the operation of
the oscillator circuit. The frequency of oscillation
ω0 is the value of ω at which the imaginary part is
zero, thus
1
ω02 = (3)
C1 C2
L
C1 + C2
or
ω0 = 1
C
LC1
1
+ s(C1 + C2 ) + gm +
=0
RL
RL
For s = jω, we have
To ensure that oscillations start, we use
gm RL >
Dividing by Vπ and collecting terms results in
(1)
Figure 1
Chapter 14–12
Figure 1 shows the equivalent circuit where ro has
been absorbed into RL . We have neglected Rf with
the assumption that Rf
ω0 L. Some of the
analysis is shown on Fig. 1.
Note that,
Vb = Vπ
Vc = Vb + sL
1
+ sC2 Vπ
rπ
The condition for sustained oscillations can be
found from Eq. (2) by equating the real part to
zero at ω = ω0 and making use of (3), thus
1
1
1
C1
C2
+
=
+
gm +
C1 C2
RL
rπ
RL
rπ
L
C1 + C2 +
RL rπ
gm +
Thus,
1
Vπ
Vc = Vπ + sL sC2 +
rπ
(1)
A node equation at E yields
1
1
Vπ
+ sC2 + gm Vπ + Vc
+ sC1 = 0
rπ
RL
1
1
+
=
RL
rπ
C1 + C2 + (L/RL rπ )
C1 C2
C1
C2
+
RL
rπ
Neglecting the terms containing rπ , we obtain
1
C2 1
= 1+
gm +
RL
C1 RL
⇒ gm RL =
C2
C1
For oscillations to start, we need
Substituting for Vc from Eq. (1), we obtain
1
1
Vπ
+ sC2 + gm Vπ +
+ sC1 Vπ
rπ
RL
1
1
+
+ sC1 sL sC2 +
=0
RL
rπ
gm RL >
C2
C1
14.26 (a)
Dividing by Vπ and collecting terms gives
LC1
LC2
s3 LC1 C2 + s2
+
+
RL
rπ
1
L
1
s C1 + C2 +
+
=0
+ gm +
RL rπ
rπ
RL
For s = jω, we have
jω −ω2 LC1 C2 + C1 + C2 +
1
RL rπ
Figure 1
1
1
C2
C1
+
− ω2 L
+
= 0 (2)
+ gm +
rπ
RL
RL
rπ
This is the equation that governs the operation of
the oscillator circuit. The frequency of oscillation
ω0 is the value of ω that makes the imaginary part
zero, thus
⎡
⎤
⎢
⎥
C1 C2
⎥
(3)
ω02 = 1 ⎢
⎣L
L ⎦
(C1 + C2 ) +
RL rπ
Observe that including rπ changes the frequency
of oscillation slightly from that of the frequency
of the resonance circuit. If we neglect the term
containing rπ in Eq. (3), we obtain
ω0 1
C1 C2
L
C1 + C2
(4)
Figure 1 shows the equivalent circuit.
(b) Oscillations will occur at the frequency for
which the tuned circuit has infinite impedance.
This is because at this frequency the phase shift
around the loop will be zero. Thus,
√
ω0 = 1/ LC
At this frequency, no current flows through R.
Thus the voltage Vc2 will be
Vc2 = (gm2 Veb2 )RC
and the voltage Vo will equal Vc2 , thus
(gm2 Veb2 )RC = Vo = 2Veb2
which yields the condition for sustained
oscillation as
gm2 RC = 2
Chapter 14–13
For oscillations to start, we impose the condition
gm2 RC > 2
(1)
But
gm2 I /2
VT
Thus, the condition in (1) can be expressed as
IRC > 4VT
that is,
IRC > 0.1 V
(c) Selecting IRC = 1 V means that oscillations
will start and will grow in amplitude until Vo is
large enough to cause Q1 and Q2 to alternately
turn on and off. When this happens the collector
current of Q2 will be 0 in half a cycle and equal to
I in the other half cycle. Thus a square wave
voltage of amplitude IRC = 1 V peak-to-peak will
develop at the collector of Q2 . This square wave
voltage is applied through R to the bandpass filter
formed by the RLC circuit. Thus, the sinusoid
that develops across the LC circuit—that is,
Vo —will havea frequency
ω0 and a peak-to-peak
4
4
×1 =
V . There will be
amplitude of
π
π
third, fifth, and other odd harmonics, but those
will be attenuated because of the selectivity of the
bandpass RLC circuit.
14.27 ω0 = 20 Grad/s = 20 × 109 rad/s
1
ω0 = √
LC
∴ f 0H =
20 × 10 = √
5 × 10−9 × C
⇒ C = 0.5 pF
2π 0.52 × 0.01197 × 10−12
1/2
= 2.0173 MHz
1/2 −1
f0L = 2π 0.52 × 0.01198 × 10−12
= 2.0165 MHz
Difference = 800 Hz
14.29 VTH = −VTL = 1 V
L+ = −L− = 5 V
VTH = βL+
1=
⇒
R1
×5
R1 + R2
R2
=4
R1
R2 = 40 k
14.30
Rp = ω0 LQ
−9
= 20 × 10 × 5 × 10
9
× 10
V
= 1000 = 1 k
ro Rp = 5 1 =
gm |min =
1
For R1 = 10 k, we have
1
9
C2 = 10 pF C1 = 1 to 10 pF
10 × 1
0.012 4 +
10 + 1
= 0.01197 pF
CL = 10
0.012 + 4 +
11
10 × 10
0.012 4 +
10 + 10
= 0.01198 pF
CH = 100
0.012 + 4 +
20
1
5
× 103
6
5
k
6
= 1.2 mA/V
14.28 From Exercise 14.13, we have
L = 0.52 H
Cs = 0.012 pF
Cp = 4 pF
C1 C2
Cs Cp +
C1 + C 2
Ceq =
C1 C2
Cs + Cp +
C1 + C 2
R3
R2
R1
vI
vO
Figure 1
(a) Refer to Fig. 1. With v O = L+ , the voltage at
the op amp positive input terminal will be VTH .
Now, writing a node equation at the op amp
positive input terminal, we have
V − VTH
L+ − VTH
VTH
=
+
R1
R3
R2
Chapter 14–14
1
1
V
1
L+
+
+
+
=
R1
R2
R3
R2
R3
L+
V
⇒ VTH =
+
(R1 R2 R3 )
R2
R3
∴ V TL
Similarly, we can obtain
L−
V
+
(R1 R2 R3 )
VTL =
R2
R3
Similarly,
VR − VTH
L− − VR
=
R2
R1
(b) L+ = −L− = 10 V, V = 15 V, R1 = 10 k
10 15
+
(R1 R2 R3 )
VTH = 5.1 =
R2
R3
10 15
5.1 5.1 5.1
+
+
=
+
R1
R2
R3
R2
R3
4.9 9.9
+
R2
R3
−10 15
= 4.9 =
+
(R1 R2 R3 )
R2
R3
0.51 =
VTL
−14.9 10.1
+
R2
R3
(b) Given
VTL = 0
VTH = V /10
Substituting these values, we get
0 = VR (1 + 10/R2 ) − (10/R2 )V
14.9
, we obtain
4.9
−14.9 30.1
+
1.55 =
R2
R3
R1
L−
R2
R1 = 10 k
(1)
(2)
Multiplying Eq. (1) by
VTH = VR (1 + R1 /R2 ) −
L+ = −L− = V
10 15
4.9 4.9 4.9
+
+
=− +
R1
R2
R3
R2
R3
0.49 =
R1
R1
VR − L+
R2
R2
R1
R1
= VR 1 +
− L+
R2
R2
VTL = VR +
VTH
V
= VR (1 + 10/R2 ) + (10/R2 )V
10
(1)
(2)
Subtracting Eq. (2) from Eq. (1), we obtain
−
(3)
Adding (2) and (3) gives
20
V
=− ×V
10
R2
⇒ R2 = 200 k
0 = VR (1 + 10/200) −
40.2
2.04 =
R3
VR =
⇒ R3 = 19.7 k
10
V
200
V
10/200 V
=
1 + 10/200
21
Substituting in Eq. (1), we obtain
0.51 =
14.32 Output levels = ±0.7 V
9.9
4.9
+
R2
19.7
Threshold levels = ±
4.9
= 656.7 k
⇒ R2 =
0.0076
iD, max =
10
× 0.7 = 0.1 V
10 + 60
12 − 0.7
0.7
−
= 1.12 mA
10
10 + 60
14.31
vO
R1
R2
0.7
vI
VR
(a) For v I = VTL and v O = L+ initially
VR − VTL
L+ −VR
=
R2
R1
vO
–0.1
0.1
–0.7
vI
Chapter 14–15
14.33 (a) A 0.5-V peak sine wave is not large
enough to change the state of the circuit. Hence,
the output will be either +12 V or –12 V.
14.36
R2
R1
(b) The 1.1-V peak sine wave will change the
state when
1.1 sin θ = 1
θ = 65.40
R3
vO
R
C
1.1 V
1V
0° u
u
90°
β = 0.462
For VD = 0.7 V and VO = ±5 V, we have
VZ = 5 − 2VD
∴ The output is a symmetric square wave of
frequency f, and it lags the sine wave by an angle
of 65.4◦ . The square wave has a swing of ±12 V.
Since VTH = −VTL = 1 V, if the average shifts by
an amount so either the +ve or -ve swing is < 1 V,
then no change of state will occur. Clearly, if the
shift is 0.1 V, the output will be a DC voltage.
14.34 For L+ = −L− = 7.5 V, we have
VZ = 6.8 V with VD = 0.7 V.
For VTH = −VTL = 7.5, we have V ⇒ R1 = R2 .
For v i = 0, we have IR2 = 0.5 mA =
7.5
R1 + R2
⇒ R1 = R2 = 7.5 k
ID = 1 mA =
1=
VZ = 3.6 V
1+β
T = 2τ ln
1−β
1.462
10−3 = 2τ ln
⇒ τ = 0.5 ms
1 − 0.462
τ = RC ⇒ R = τ /C = 50 k
Thresholds = ±0.462 × 5 = ±2.31 V
1
Average current in R in cycle:
2
1 5 − 2.31 + 2.31 + 5
I∼
=
R
2
=
5
5
=
= 0.1 mA
R
50 k
Voltage across R
5 2.31
Vavg 5
5 2.31
12 − 7.5
7.5
−
R
2R1
4.5
− 0.5
R
R = 3 k
Vavg 5
5 2.31
5 2.31
5V
= 50 k
0.1 mA
R1
10
1+β
, β=
=
1−β
R1 + R2
26
1 + 10/26
T = 2 5 × 10−9 62 × 103 ln
1 − 10/26
R1 + R2 =
T = 0.503 ms ⇒ f = 1989 Hz
∴ R2 = 26.9 k
14.35 T = 2τ ln
R1
= 0.462 → R1 = 50 (0.462)
R1 + R2
= 23.1 k
Chapter 14–16
1=
13 − 5
− 0.1 − 0.1
R3
8
1.2
= 6.67 k
R3 =
14.37 From Fig. 14.25(b), for ±5-V output, we
have
VZ = 5 − 2VDIODE = 5 − 1.4 = 3.6 V
For ±5-V output:
R1 = R2 , L+ = −L− = 5 V
VTH = −V TL = 5 V
Max current in feedback network = 0.2 mA
10
∴ 0.2 =
⇒ R1 = R2 = 25 k
R1 + R2
Minimum zener current = 1 mA
12 − 5
∴
= (0.2 + 1) mA
R3
7
= 5.83 k
1.2
Now from Fig. 14.27(c) we have
R3 =
Slope =
−L−
VTH − VTL
=
RC
T /2
for f = 1 kHz
T = 10−3 s
C = 0.01 μF
5
10
= −3 ⇒ R = 25 k
RC
10 /2
14.38 Refer to the circuit of Fig. P14.38. To
obtain a square-wave voltage of ±7.5 V levels
across the zeners, we need
VZ + VD = 7.5 V
Figure 1
For VD = 0.7 V, we have
VZ = 6.8 V
Now, R1 = R2 , thus for the bistable we obtain
L+ = −L− = 7.5 V
R1
β=
= 0.5
R1 + R2
7.5
VTH = −VTL =
V
2
As shown in Fig. 1, the voltage across the
capacitor will be triangular, ranging between
−VTL and +VTH . The slope of the triangular
waveform edges is
7.5
7.5
1
Slope =
× =
R5
C
T /2
For R5 = R, we have
CR =
R=
T
1
1
=
=
2
2f
2 × 10 × 103
1
= 100 k
2 × 10 × 103 × 0.5 × 10−9
Since all resistors, except R7 , are equal, we have
R1 = R2 = R3 = R4 = R5 = R6 = 100 k
To determine R7 , we note that the minimum zener
current occurs when the current through R5 is at
its maximum. The latter condition occurs when
Chapter 14–17
the output of the bistable is at +7.5 V while
v C is (−7.5/2) V at which time
14.41 See sketches that follow:
v A (t = T ) = −Vref = − (L+ − L− ) e−T /RC
7.5 − (−7.5/2)
IR5 =
Rs
= 0.1125 mA
Thus, for a minimum zener current of 1 mA, we
write
7.5
13 − 7.5
=1+
+ 0.1125
R7
R1 + R2
7.5
+ 0.1125
=1+
200
⇒ R7 = 4.8 k
Vref
= e−T /RC
L+ − L−
Vref
T = −RC ln
L+ − L−
L+ − L−
Q.E.D.
= RC ln
Vref
Trigger: v
vB:
14.39 Refer to Fig. 14.28. The recovery time, trec ,
is the time for v B to go from βL− to VD1 :
Vref
v B (t) = L+ − (L+ − βL− )e−t/C1 R3
Thus,
vA:
VD = L+ − (L+ − βL− )e−trec /C1 R3
⇒ trec = C1 R3 ln
0
0
Vref
L+ − βL−
L+ − VD
t/RC
From Exercise 14.22, we have
vA (LL) e
(LL)
C1 = 0.1 μF, R3 = 6171 , L+ = −L− = 12 V
β = 0.1, and VD = 0.7 V, thus
−6
trec = 0.1 × 10
12 + 1.2
× 6.171 × 10 ln
12 − 0.7
vO:
L
3
= 96 μs
T
14.40 Choose C1 = 1 nF and C2 = 0.1 nF:
1
R1 = R2 = 100 k ⇒ β ≡
2
0.7 + 13
T = C1 R3 ln
0.5 × (−13) + 13
13.7
10−4 = 10−9 R3 ln
13 (0.5)
14.42 For v I > 2/3VCC , comp –1 = “1” and
comp –2 = “0” and flip flop is reset, i.e. v O = 0 V.
Now v O will not change until v I = 1/3VCC , when
comp –2 = “1” and comp –1 = “0” and FF is set:
i.e. v O = VCC
R3 = 134.1 k
For
Need R4
R1 ⇒ choose R4 = 470 k
L
1
2
VCC < v I < VCC , comp –1 = comp –2
3
3
= “0” and no change of state will occur.
The trigger pulse must be sufficiently large to
lower the voltage at node C from βL+ to VD , that
is, from +6.5 V to +0.7 V; thus it must be at least
5.8 V.
vO
VCC
For recovery we have
v B = 13 − 13 − βL− e−t/τ
= 13 − 19.5e−t/τ = 0.7
12.3
∴ t recovery = −τ ln
19.5
−9 3
= − 134.1 × 10 10 (−0.4608)
= 61.8 μs
0
VCC
3
2 V
3 CC
i.e. an inverting bistable circuit.
vI
Chapter 14–18
VCC − VTH
= e−TH /C(RA +RB )
VCC − VTL
VCC − VTL
TH = C(RA + RB ) ln
VCC − VTH
14.43
C = 680 pF, f = 20 kHz, duty cycle = 80%.
Using Eq. (14.46), we obtain
T = 0.69C(RA + 2RB )
For exponential fall:
Thus,
v C = VTH e−t/CRB
1
= 0.69 × 680 × 10−12 (RA + 2RB )
20 × 103
⇒ RA + 2RB =
∴ V TL = VTH e−TL /CRB
VTH
TL = CRB ln
VTL
1
20 × 0.69 × 0.68 × 10−6
RA + 2RB = 106.56 k
(1)
Using Eq. (14.47), we have
for VTH = 2VTL ⇒ TL = CRB ln(2)
(b) C = 1 nF, RA = 7.2 k, RB = 3.6 k
RA + RB
0.8 =
RA + 2RB
VCC = 5 V, no external voltage to VTH .
∴ T H + TL = T = ln 2 × (RA + 2RB )C
Thus,
RA + RB = 0.8 × 106.6 = 85.25 k
(2)
Subtracting Eq. (2) from Eq. (1) gives
RB = 21.31 k
and using Eq. (2), we obtain
RA = 63.94 k
T = 9.94 μs → f = 100.6 kHz
Duty cycle =
⇒ 75%
(c) VCC = 5 V,
VTH =
14.44 (a) C = 0.5 nF
RA + RB
TH
=
= 0.75
TH + TL
RA + 2RB
2
10
×5=
= 3.33 V
3
3
Using Eq. (14.41), we obtain
For 1-V input the high value of VTH will be
VTH = 4.33 V
T∼
= 1.1CR
and, VTL =
10 × 10−16 = 1.1 × 0.5 × 10−9 × R
⇒ R = 18.2 k
1
V = 2.17 V
2 TH
TH = 10−9(3.6 + 7.2) × 103 ln
5 − 2.17
5 − 4.33
(b) For T = 20 μs, R = 18.2 k,
C = 0.5nF, VCC = 12 V, and using Eq. (14.40)
with v C = VTH and t = T , we obtain
−6
− 20×10
VTH = 12 1 − e 9.1×10−6
= 15.6 μs
= 10.67 V
Duty cycle =
14.45
For 1-V input the low value of VTH will be
VTH = 2.33
VTH
TL = 10−9 × 3.6 × 103 ln 2 = 2.5 μs
∴ f =
1
= 55.2 kHz
(15.6 + 2.5)10−6
15.6
= 86.2%
2.5 + 15.6
and VTL = 1.17
VTL
For the rise:
v C = VCC − (VCC − VTL ) e−t/C(RA +RB )
VTH = VCC − (VCC − VTL ) e−TH /C(RA +RB )
5 − 1.17
∴ TH = 10 (3.6 + 7.2) 10 ln
5 − 2.33
−9
3
= 3.90 μs
TL = TL = 2.5 μs
∴ f =
106
= 156 kHz
(3.90 + 2.5)
Duty cycle =
3.90
= 61%
2.5 + 3.90
Chapter 14–19
14.46
v I = v O + iD R
(2)
vI
× 90◦
1.1
(3)
Ideal v O = 0.7 sin θ
(4)
θ=
Percentage error in v O =
v O − Ideal v O
× 100
Ideal v O
Figure 1
(5)
Equations (1)–(5) can be used for each of the
given values of v O to obtain the results given in
the table below.
For a sine wave, we have
v O = 0.7 sin ωt
Slope at zero crossings
v O (V)
= 0.7ω = 0.7 × 2πf
0.70
1.4π
=
T
Slope of triangular wave =
we obtain
V
1.4π
=
T
T /4
V
. Equating slopes,
T /4
1.4π
= 1.1 V
⇒V =
4
Refer to Fig. 1(b).
With v I = V = 1.1 V, we have v O = 0.7 V, thus
0.7 sin θ
% Error
0.7
0
◦
90
◦
0.65
63.6
0.627
3.7
0.60
52.4◦
0.554
8.2
◦
0.55
46.1
0.504
9.1
0.50
41.3◦
0.462
8.2
0.40
32.80
0.379
5.5
◦
0.30
24.6
0.291
3.0
0.20
16.4◦
0.198
1.2
0.0998
0.1
0
0.0
0.10
v R = 1.1 − 0.7 = 0.4 V
θ
0.00
◦
8.2
◦
0
At VD = 0.7 V we have iD = 1 mA, thus
0.4 = 1 × R
16
= 16f.
T
Slope at zero crossings of a sine wave with peak
amplitude of (VB + 0.7) V is
14.47 Slope of triangular wave =
⇒ R = 0.4 k = 400 The angle θ and the ideal value of the output
voltage are determined as follows:
= (VB + 0.7)ω
Since v D changes by 0.1 V per decade change in
current, we have
1 mA
v O = 0.7 − 0.1 log
iD
⇒ iD = 1010(v O −0.7) , mA
Equating slopes, we obtain
16f = (VB + 0.7) × 2πf
⇒ VB = 1.85 V
(1)
This figure belongs to Problem 14.47.
vI
6.8 k
4 V
0
t
vI
4 V
Slope 16
8V
(T/2) s
T
Figure 1
D1
vO
D2
VB
VB
Chapter 14–20
v O = −IS e
14.48
ln
v 1v 2
IS
v O = −v 1 v 2
Check:
R
vI
vO
0V
vI /R
For v 1 = 0.5 V and v 2 = 1 V, we have
iD1 = 0.5 mA
0.5
v D1 = 0.7 + 0.025 ln
1
vI > 0
= 0.683 V
Voltage across diode is −v O
vI
= IS e−v O /VT
iD =
R
vO
vI
−
= ln
VT
RIS
vI
, vI > 0
v O = −VT ln
RIS
v A = −0.683 V
iD2 = 1 mA
v D2 = 0.7 V
v B = −0.7 V
Q.E.D.
14.49 From the statement of Problem 14.48,
we have
vI
v O = −VT ln
IS R
Now, for the circuit in Fig. P14.49 we can write
v1
v A = −VT ln
IS
v2
v B = −VT ln
IS
1
v C = VT ln
IS
v1
v2
1
+ ln
− ln
v D = VT ln
IS
IS
IS
(v 1 v 2 /IS )
= V ln
T
Q.E.D.
iD3 = 1 mA
v C = 0.7 V
v D = −(−0.683 − 0.7 + 0.7)
= 0.683 V
iD4 = IS e0.683/0.025
But,
1 mA = IS e0.7/0.025
⇒ IS = e−0.7/0.025 , mA
iD4 = e(−0.7+0.683)/0.025
= 0.5 mA
v O = −0.5 V
which is −v 1 v 2
Q.E.D.
Other combinations can be used to verify the
operation of this analog multiplier.
Exercise 15–1
Ex: 15.1
The parameters VOH , VOL , VIL , VIH and thus NML
and NMH do not depend on the value R (but on
Vx ) and thus their values will not change.
VDD 1.8 V
ID 30 A
RD
VOL 90 mV
1.8 V
The current IDD drawn from the power supply
during the low-output interval becomes
VDD − VOL
1.8 − 0.12
= 168 μA
=
RD
10
IDD =
and the power drawn from the supply during the
low-output interval is
PD = VDD ID = 1.8 × 168 = 302 μW
Figure 1
Refer to Fig. 1.
VOL
90 mV
= 3 k
=
=
ID
30 μA
rDS
Substituting in the expression given for rDS , we
get
3=
0.125 ×
W
L
1
× (1.8 − 0.4)
W
= 1.9
L
The value of RD can be obtained from
⇒
RD =
VDD − VOL
ID
1.8 − 0.09
= 57 k
0.03
When the switch is open, ID = 0 and
=
PDrawn = VDD ID = 0
When the switch is closed, ID = 30 μA, and
PDrawn = VDD ID = 1.8 × 30 = 54 μW
Ex: 15.2 VOH = VCC − 0 × RC1,2 = 5 V
VOL = VCC − IEE RC1,2
=5−1×2=3V
Ex: 15.3 If Vx remains unchanged at 0.089 V,
then
1
1
k n RD =
=
= 11.24
Vx
0.089
For RD to be 10 k,
11.24
= 1.124 mA/V2
kn =
10
Thus,
1.124 = 0.3 ×
⇒
W
= 3.75
L
W
L
Since the inverter spends half of the time in this
state, we have
PDaverage =
1
PD = 151 μW
2
Ex: 15.4 k n RD =
1
Vx
For RD = 10 k and
W
= 0.3 × 1.5 = 0.45 mA/V2
kn = kn
L
we obtain
Vx =
1
= 0.22 V
0.45 × 10
Now,
VOH = 1.8 V
From Eq. (15.22) we get
1.8
= 0.26 V
1.8 − 0.5
1+
0.22
From Eq. (15.12) we obtain
VOL =
VIL = Vt + Vx = 0.5 + 0.22 = 0.72 V
From Eq. (15.20) we have
√
VIH = 0.5 + 1.63 1.8 × 0.22 − 0.22
= 1.31 V
Thus,
NML = VIL − VOL = 0.72 − 0.26 = 0.46 V
NMH = VOH − VIH = 1.8 − 1.31 = 0.49 V
During the output-low interval, we have
IDD =
VDD − VOL
RD
1.8 − 0.26
= 154 μA
10
and
=
PD = 1.8 × 154 = 277.2 μW
Thus,
PDaverage =
1
PD = 138.6 μW 139 μW
2
Exercise 15–2
Ex: 15.5 Refer to the circuit in Figure 15.21.
With v I = VM > Vt , QN will be conducting. Since
v O = VM > |Vt | and the gate of QP is at ground,
QP will be operating in the triode region, thus
iDP = k p (VDD − |Vt |)(VDD − VM )
1
− (VDD − VM )2
2
(1)
Since v O = v I = VM , QN will be operating in
saturation, thus
(2)
VIL =
1
(3VDD + 2Vt )
8
1
(3 × 1.2 + 2 × 0.4)
8
= 0.55 V
=
NMH = VOH − VIH
= 1.2 − 0.65 = 0.55 V
1
k n (VM − Vt )2 =
2
1
k p (VDD − Vt )(VDD − VM ) − (VDD − VM )2
2
1
r(VM2 − 2Vt VM + Vt2 )
2
1 2
1
= VDD
− VDD Vt + VM Vt − VM2
2
2
1
1
1
r+
VM2 − (r + 1) Vt VM + rVt2
2
2
2
1 2
V − VDD Vt
2 DD
2
(r + 1)VM2 − 2(r + 1)Vt VM + rVt2 = VDD
− 2VDD Vt
(r + 1)VM2 − 2(r + 1)Vt VM + (r + 1)Vt2
2
= VDD
− 2VDD Vt + Vt2
NML = VIL − VOL
= 0.55 − 0 = 0.55 V
(c) With v I = VDD and v O low, the output
resistance is rDSN :
W
(VDD − Vt )
rDSN = 1 μn Cox
L n
=
1
= 2.9 k
0.43 × 1(1.2 − 0.4)
With v I = 0 V and v O = VDD , the output
resistance is rDSP :
W
μp Cox
(VDD − |Vt |)
rDSP = 1
L p
1
= 2.9 k
0.43
× 4(1.2 − 0.4)
4
The two output resistances are equal because the
inverter is matched.
=
(r + 1)(VM − Vt )2 = (VDD − Vt )2
VDD − Vt
⇒ VM = Vt + √
r+1
To obtain VIL , we use Eq. (15.36):
The noise margins can now be found as
1
k n (VM − Vt )2
2
Equating (1) and (2) gives
iDN =
=
1
(5 × 1.2 − 2 × 0.4)
8
= 0.65 V
=
Q.E.D.
For VDD = 1.8 V, Vt = 0.4 V, and r = 5, we get
(d) Using Eq. (15.39), we obtain
1.8 − 0.4
VM = 0.4 + √
= 0.97 V
5+1
VM =
r(VDD − |Vtp |) + Vtn
r+1
where
Ex: 15.6 (a) For VM = 0.6 V =
inverter must be matched, thus
Wp
μn
=
Wn
μp
1
VDD , the
2
Wp
=4
0.13
⇒ Wp = 0.52 μm
⇒
|Vtp | = Vtn = 0.4 V
and
r=
μp Wp
=
μn Wn
1
1
×1=
4
2
Thus,
VM =
0.5(1.2 − 0.4) + 0.4
= 0.53 V
0.5 + 1
(b) VOH = VDD = 1.2 V
VOL = 0 V
Ex: 15.7 To obtain VM = 2.5 V =
To obtain VIH , we use Eq. (15.35):
inverter must be matched, thus
W
W
= μp Cox
μn Cox
L n
L p
VIH =
1
(5VDD − 2Vt )
8
1
VDD , the
2
Exercise 15–3
2μp Cox
W
L
p
W
L
= μp Cox
n
W
=2
L n
W
L
p
(1)
For v I = VDD = 5 V and v O = 0.2 V, QN will be
operating in the triode region. Thus,
W
1 2
(VDD − Vt )VDS − VDS
iD = μn Cox
L n
2
1
W
(5 − 1) × 0.2 − × 0.22
0.2 = 0.05 ×
L n
2
W
= 5.13 5
⇒
L n
W
= 2 × 5.13 = 10.26 10
L p
Ex: 15.8 ItPLH = C
= VDD (1 − e−t/τ )
At t = tPLH , v O = VDD /2, thus
VDD
= VDD (1 − e−tPLH /τ )
2
⇒ e−tPLH /τ = 0.5
⇒ tPLH = τ ln 2 = 0.69τ
and
tPLH = 0.69 × 200 = 138 ps
10 × 10−15 × 1.8
2I
Next we determine tPHL by considering the
situation depicted in Fig. 1(b). Here, PU has just
opened, leaving v O (0+) = VDD . Capacitor C then
discharges through the on resistance of the
pull-down switch, Rond , toward 0 V, thus
v O (∞) = 0, thus
1.8 × 10−14
= 0.9 mA
2 × 10−11
Ex: 15.9
v O = 0 − (0 − VDD )e−t/τ
VDD
= VDD e−t/τ
vO
At t = tPHL , v O = VDD /2 and we get
Ronu
VDD
= VDD e−tPHL /τ
2
vO VDD
C
PD
VDD
2
⇒ tPHL = τ ln 2 = 0.69τ
0
tPLH
t
Here,
τ = CRond
Figure 1(a)
= 10 × 10−15 × 10 × 103 = 100 ps
VDD
Thus,
vO
tPHL = 69 ps
PU
Rond
= VDD − (VDD − 0)e−t/τ
τ = 10 × 10−15 × 20 × 103 = 200 ps
To obtain tPLH = 10 ps with C = 10 fF and
VDD = 1.8 V, we need a current I obtained as
follows:
⇒I =
v O (t) = V∞ − (V∞ − V0+ )e−t/τ
For C = 10 fF and Ronu = 20 k, then
VDD
2
⇒ tPLH = CVDD /2I
10 × 10−12 =
To obtain tPLH , consider the situation in Fig. 1(a).
Here, PD has just opened (at t = 0) leaving
v O = 0 V at t = 0+. Capacitor C then charges
through the on resistance of the pull-up switch,
Ronu , toward VDD , thus
vO
C
VDD
VDD
2
0
Figure 1(b)
The propagation delay tP can now be obtained as
tP =
tPHL
t
=
1
(tPLH + tPHL )
2
1
(138 + 69) = 104 ps
2
Exercise 15–4
Ex: 15.10
tP =
vO
1
(tPHL + tPLH )
2
1
(24.8 + 49.6)
2
= 37.2 ps
=
VDD
0.9VDD
0.1VDD
0
tf
t1
Ex: 15.12 tPHL = 0.69RN C
t
50 × 10−12 = 0.69 ×
t2
12.5
× 103 × 20 × 10−15
(W/L)n
⇒ (W/L)n = 3.5
Figure 1
tPLH = 0.69RP C
Figure 1 shows the exponential discharge curve
and the two points that define the extent of the fall
time, tf . Here,
50 × 10−12 = 0.69 ×
30
× 103 × 20 × 10−15
(W/L)p
⇒ (W/L)p = 8.3
v O (t) = VDD e−t/τ
v O (t1 ) = 0.9VDD = e−t1 /τ
(1)
Note: If the 0.69 factor is replaced by 1 to account
for the fact that the pulse edges are not ideal, then
v O (t2 ) = 0.1VDD = e−t2 /τ
(2)
(W/L)n = 5
Dividing (1) by (2) gives
9=e
(W/L)p = 12
−(t1 −t2 )/τ
Ex: 15.13 With an additional 0.1 pF, C becomes
9 = etf /τ
⇒ tf = τ ln 9 = 2.2τ
C = 6.25 fF + 100 fF = 106.25 fF
For C = 100 fF and R = 2 k,
Thus,
τ = 100 × 10−15 × 2 × 103 = 200 ps
tPHL = 25.8 ×
and
= 438.6 ps
tf = 2.2 × 200 = 440 ps = 0.44 ns
7 3Vtn
Vtn 2
Ex: 15.11 αn = 2
−
+
4
VDD
VDD
0.5 2
7 3 × 0.5
−
+
= 2.01
=2
4
1.8
1.8
tPHL =
=
αn C
k n (W/L)n VDD
−15
2.01 × 10 × 10
300 × 10−6 × 1.5 × 1.8
= 24.8 ps
Vtp 2
7 3|Vtp |
−
+
αp = 2
4
VDD
VDD
= 2.01
tPLH
=
αp C
= k p (W/L)p VDD
2.01 × 10 × 10−15
75 × 10−6 × 3 × 1.8
= 49.6 ps
tPLH = 31.5 ×
106.25
6.25
106.25
6.25
= 535.5 ps
Thus,
1
(438.6 + 535.5)
2
= 487 ps
tP =
Ex: 15.14 Original area = Wn L + Wp L
= L(Wn + Wp )
= 0.25(0.375 + 1.125)
= 0.375 μm2
New area = L(Wn + Wp )
= L × 2Wn
= 0.25 × 2 × 0.375 = 0.1875 μm2
which is half the original area. Thus, the area is
reduced by 50%.
Next, we compute the new value of C as follows:
C = 2Cgd 1 +2Cgd 2 +Cdb1 +Cdb2 +Cg3 +Cg4 +Cw
Exercise 15–5
This component remains unchanged. The
extrinsic component
where
Cgd 1 = 0.1125 fF
Cgd 2 = 0.3 × Wp = 0.3 × 0.375 = 0.1125 fF
tP,ext = 28.7 − 13.3 = 15.4
Cdb1 = 1 fF
is reduced by a factor of 2. Thus, tP becomes
Cdb2 = 1 fF
tP = 13.3 +
Cg3 = 0.7875 fF
15.4
= 21 ps
2
(d) Area = Wn L + Wp L
Cg4 = 0.375 × 0.25 × 6 + 2 × 0.3 × 0.375
= 0.7875 fF
= L(Wn + Wp )
By scaling Wn and Wp by a factor of 2, the area
increases by a factor of 2.
Cw = 0.2 fF
Thus,
C = 2 × 0.1125 + 2 × 0.1125 + 1 + 1
+ 0.7875 + 0.7875 + 0.2 = 4.225 fF
4.225
tPHL = 25.8 ×
6.25
= 17.4 ps
4.225 1.125
×
tPLH = 31.5 ×
6.25
0.375
= 63.9 ps
tP =
1
(17.4 + 63.9) = 40.6 ps
2
Ex: 15.17 L = 0.18 μm, n = 1.5, p = 3
(a) Four-input NOR gate: Refer to Fig. 15.34.
For NMOS transistors: W/L = n = 1.5 =
0.27
0.18
For PMOS transistors: W/L = 4p = 12 =
2.16
0.18
(b) Four-input NAND gate: Refer to Fig. 15.35.
For NMOS transistors: W/L = 4n = 6 =
For PMOS transistors: W/L = p = 3 =
Ex: 15.15 fmax =
=
1
2tP
1
= 17.4 GHz
2 × 28.7 × 10−12
1.08
0.18
0.54
0.18
Area of NOR gate
= 4×0.18×0.27+4×0.18×2.16 = 1.7496 μm2
Area of NAND gate
= 4 × 0.18 × 1.08 + 4 × 0.18 × 0.54 = 1.1664
Ex: 15.16 Refer to Example 15.7.
(a) Cint = 2Cgd 1 + 2Cgd 2 + Cdb1 + Cdb2
Thus,
1.7496
NOR area
=
= 1.5
NAND area
1.1664
= 2 × 0.1125 + 2 × 0.3375 + 1 + 1
= 2.9 fF
Cext = Cg3 + Cg4 + Cw
= 0.7875 + 2.3625 + 0.2
= 3.35 fF
(b) To reduce the extrinsic component of tP by a
factor of 2, we need to scale (W/L)n and (W/L)p
by a factor
S=2
(c) The original value of tP = 28.7 ps is
composed of an intrinsic component
Cint
C
2.9
= 13.3 ps
= 28.7 ×
6.25
tP,int = tP ×
Ex: 15.18 Refer to Fig. 15.35.
(a) Maximum charging current is the current
supplied by the four identical PMOS transistors.
Minimum charging current is the current supplied
by one of the PMOS transistors. Thus, the ratio of
maximum to minimum currents is 4.
(b) There is only one possible configuration for
discharging a load capacitance, namely, when all
4 NMOS transistors are conducting. So, as far as
capacitor discharge is concerned, the ratio is one.
2
Ex: 15.19 Pdyn = fCVDD
= 1 × 109 × 6.25 × 10−15 × 2.52
= 39 μW
Exercise 15–6
2
Ex: 15.20 Pdyn = fCVDD
2
Ex: 15.22 PDP = fCVDD
tP
= 100 × 106 × 100 × 10−15 × 1.82
When f = fmax = 1/2tP ,
= 32.4 μW
PDP =
2
Ex: 15.21 Pdyn = fCVDD
C decreases by a factor (0.13/0.5) and VDD
decreases from 5 V to 1.2 V; thus for the same f ,
the power dissipation will decrease by a factor
=
5
0.5
×
= 66.8
0.13 1.2
1
1
CV 2 = × 6.25 × 10−15 × 2.52
2 DD
2
= 19.5 fJ
1
2
tP = 19.5 × 10−15 × 28.7 × 10−12
EDP = CVDD
2
= 5.6 × 10−25 Js
Chapter 15–1
15.1 (a) Ron = rDSN
=
15.3
1
W
(μn Cox )
(VDD − Vtn )
L n
(1)
VDD
1
= 2.18 k
=
0.470 × 1.5(1 − 0.35)
(b) Ron = rDSP
=
=
W
(μp Cox )
L
1
A
QPA
B
QPB
C
QPC
(2)
Y
(VDD − |Vtp |)
p
1
= 5.40 k
0.190 × 1.5(1 − 0.35)
A
QNA
(c) From (1) and (2) since Vtn = −|Vtp |, then if
Ron are to be equal, then
W
W
(μn Cox )
= (μp Cox )
L n
L p
⇒
W
L
p
μn Cox W
=
μp Cox L n
QNB
B
C
QNC
Figure 1
Y =A+B+C
⇒ Y = A + B + C ⇒ PDN
Y = A B C ⇒ PUN
The circuit realization is shown in Fig. 1.
470
=
× 1.5 = 3.71
190
15.4
15.2 (a) For QN , we have
VDD
Ron =
W
(μn Cox )
L
1
(VDD − Vtn )
n
A
QPA B
QPB C
QPC
For QP , we have
Ron =
Y
1
W
(μp Cox )
(VDD − |Vtp )|
L p
A
QNA
Since Vtn = |Vtp |, then for Ron of QP to equal Ron
of QN ,
B
QNB
W
W
(μp Cox )
= (μn Cox )
L p
L n
C
QNC
⇒
=
W
L
=
p
μn Cox W
μp Cox L n
500
× 1.5 = 6.0
125
(b) For both devices, we have
Ron =
1
= 1.67 k
0.5 × 1.5 × (1.2 − 0.4)
Figure 1
Y = ABC
⇒ Y = ABC ⇒ PDN
Y = A + B + C ⇒ PUN
Figure 1 shows the circuit realization.
Chapter 15–2
Figure 1 (left-hand column) shows the complete
CMOS logic circuit where we have obtained the
PDN as the dual of the given PUN. The logic
function can be written from the PDN as
15.5
Y = A + BCD
or equivalently
Y = A + BCD
15.7 The given Boolean expression can be
written as
Y = (A + B)(C + D)
from which the PDN of the complete circuit
shown in Fig. 1 can be directly obtained.
Figure 1
Figure 1 (left-hand column) shows the complete
CMOS logic gate where the PUN is obtained as
the dual of the given PDN. The function realized
can be found from the PDN as
Y = A + BC
VDD
A
C
B
D
or
Y = A + BC
15.6
Y
A
B
C
D
Figure 1
The PUN can then be found as the dual of
the PDN.
Figure 1
15.8 Figure 1 (top of next page) shows a
CMOS realization of the Exclusive-OR function.
This circuit is obtained by utilizing the PUN in
Fig. 15.10(a) and then
Chapter 15–3
VDD
A
A
B
B
Direct realization of the given expression results
in the PUN of the logic circuit shown in Fig. 1
(below, left-hand column). The PDN shown is
obtained as the dual of the PUN. Not shown are
the two inverters needed to obtain A and B.
15.10 Y = ABC + ABC + ABC
Y
A
A
B
B
Figure 1
finding the dual PDN. Note that two additional
inverters are needed to generate A and B, for a
total of 12 transistors.
(1)
Using this expression to directly synethesize the
PUN we obtain the circuit shown in Fig. 1. See
Figs. 1 and 2 on next page.
This PUN circuit requires 9 transistors plus three
inverters for a total of 15 transistors.
This, of course, does not include the transistors
required for the PDN which we shall consider
shortly. Inspecting the PUN circuit reveals the
potential for eliminating two transistors through
what is known as "path merging." Specifically the
two transistors in the top row that are controlled
by A can be merged into a single transistor, and
the two transistors in the bottom row that are
controlled by C can be merged into a single
transistor. The result is the 7-transistor PUN
shown in Fig. 2.
We next consider the realization of the PDN. A
straightforward realization can be obtained by
finding the dual of the PUN in Fig. 1. This is
shown in Fig. 3. It requires nine transistors
15.9
Y
A
B
C
A
B
C
A
B
C
Figure 3
Figure 1
plus three inverters. The latter, of course are the
same three inverters needed to obtain the
complemented variables in PUN. The circuit in
Fig. 3 does not lend itself to path merging, at least
not in a straightforward way.
Chapter 15–4
These figures belong to Problem 15.10.
VDD
A
A
VDD
A
A
A
Path
B
B
B
B
B
B
merging
C
C
C
C
C
Y
Y
Figure 1
Figure 2
There is, however, an alternative way to
synthesize a PDN with a lower number of
transistors. We simply obtain Y from the
expression in Eq. (1) using DeMorgan’s law as
follows:
= ABC + B C + A B + A C
= ABC + A(B + C) + B C
(3)
A direct realization of this expression results in
the PDN shown in Fig. 4. This circuit requires 8
transistors (not counting the inverters).
Y = ABC.ABC.ABC
= (A + B + C)(A + B + C)(A + B + C)
(2)
Direct synthesis of Eq. (2) results in the circuit of
Fig. 3. However, further manipulation of the
expression in (2) results in a more economical
realization, as follows:
Y = AB(A + B + C) + AC(A + B + C)
Y
A
A
B
+ B A(A + B + C) + B C(A + B + C)
C
B
B
C
C
+ C A(A + B + C) + CB(A + B + C)
+ C(A + B + C)
Figure 4
= ABC + AB C + A B + A BC + A B C
+BC+AC+ABC
= ABC + (A + A)B C + A B(1 + C) + (A + 1)B C
+ A C(1 + B)
15.11 Direct realization of the given expression
results in the PUN portion of the circuit shown in
Fig. 1 at the top of the next page. The PDN is
obtained as the dual of the PUN. Not shown are
the three inverters needed to obtain A, B and C.
Chapter 15–5
15.12 (a) Even-parity checker:
Y = A B C + ABC + ABC + ABC
See Fig. 1 below.
(b) This expression can be directly realized with
the PDN shown in Fig. 1. Note that the circuit
requires 12 transistors in addition to the three
inverters needed to generate A, B, and C.
(c) From inspection of the PDN in Fig. 1
we see that we can combine the two transistors
controlled by A and the two transistors controlled
by A. This results in the PDN realization
shown in Fig. 2 which requires 10 transistors,
not counting those in the inverters. See Fig. 2
below.
Figure 1
This figure belongs to Problem 15.12, part (a).
Y
A
A
A
A
B
B
B
B
C
C
C
C
Figure 1
This figure belongs to Problem 15.12, part (c).
Y
A
A
B
B
B
B
C
C
C
C
Chapter 15–6
VDD
shown in Fig. 4. However, it is not easy to obtain
a PUN as a dual of this circuit. See Fig. 4
below.
B
C
B
C
15.13 The Boolean expression for an odd-parity
checker in Eq. (1) can be directly realized by the
PUN in Fig. 1.
B
C
Y = AB C + A BC + AB C + ABC
B
C
A
A
= A (BC + BC) + A(BC + B C)
Y
(1)
Recall that we use for the switch control variables
the complements of the variables in the equation.
It requires 10 transistors in addition to the three
inverters needed to provide A, B and C. The dual
of the PUN can be obtained and results in the
PDN shown in Fig. 1 on the next page.
Figure 3
The equation S = AB C + A BC + AB C + ABC
(d) The PUN in Fig. 3 can be obtained as the dual
of the PDN in Fig. 2. Combining the PDN and the
PUN gives the complete realization of the
even-parity checker.
Note: The number of transistors in the PDN of
Fig. 2 can be reduced by 2 by combining the two
transistors in the bottom row that are controlled
by C, and the two transistors that are controlled
by C. The resulting 8-transistor realization is
= A(BC + BC) + A(BC + B C)
is the same function as that of the odd-parity
checker above. Thus the realization of the S
function will be identical to that in Fig. 1.
As for C0 we write
C0 = ABC + ABC + ABC + ABC
Y
A
B
A
B
This expression can be minimized as follows:
C0 = (A + A)BC + (B + B)AC + (C + C)AB
= BC + AC + AB = A(B + C) + BC
B
C
B
C
Figure 4
which can be realized directly by the PUN of the
circuit in Fig. 2 where the PDN is obtained as the
dual network of the PUN. In addition to the 10
transistors, we need three inverters to generate A,
B and C.
Chapter 15–7
This figure belongs to Problem 15.13.
VDD
A
A
B
B
B
B
PUN
C
C
C
C
Y
B
C
B
C
A
PDN
B
C
B
C
Figure 2
A
Figure 1
15.14 NMH = VOH − VIH
(b)
= 1.8 − 1.2 = 0.6 V
NML = VIL − VOL
= 0.9 − 0.2 = 0.7 V
15.15 (a) NMH = VOH − VIH
= 1.8 − 1.3 = 0.5 V
NML = VIL − VOL
= 1.2 − 0.4 = 0.8 V
Figure 1
Chapter 15–8
Refer to Fig. 1 on the previous page. Slope of the
VTC in the transition region is:
VOH − VOL
Slope =
VIL − VIH
=
1.8 − 0.4
= −14 V/V
1.2 − 1.3
But the slope can also be expressed as
Slope =
VM − VOH
VM − VIH
Thus,
VM − 0.4
= −14
VM − 1.3
⇒ VM = 1.24 V
(c) The voltage gain in the transition region is
equal to the slope found above, thus
Gain = −14 V/V
(b) Typical average power dissipation:
PD =
1
(5 × 3 + 5 × 1)
2
= 10 mW
15.18 (a) Refer to Fig. 15.17.
VOL = VDD
= 2.5 ×
Ron
R + Ron
0.1
= 0.12 V
2 + 0.1
VOH = VDD = 2.5 V
NMH = VOH − VIH
= 2.5 − 1 = 1.5 V
NML = VIL − VOL
= 0.8 − 0.12 = 0.68 V
(b)
15.16 NMH = VOH − VIH
= 0.8VDD − 0.6VDD = 0.2VDD
NML = VIL − VOL
= 0.4VDD − 0.1VDD = 0.3VDD
Width of transition region = VIH − VIL
Figure 1
= 0.6VDD − 0.4VDD = 0.2VDD
For a minimum noise margin of 0.4 V, we have
Refer to Fig. 1.
NMH = 0.4
VOH = VDD − N × 0.2 × R
⇒ 0.2VDD = 0.4
= 2.5 − N × 0.2 × 2
⇒ VDD = 2 V
= 2.5 − 0.4N
NMH = 2.5 − 0.4N − 1
15.17 VIH = 2 V
= 1.5 − 0.4N
VIL = 0.8 V
For NMH = NML , we have
VOH min = 2.4 V, VOH typ = 3.3 V
1.5 − 0.4N = 0.68
VOLmax = 0.4 V, VOLtyp = 0.22 V
⇒ N = 2.05
(a) Worst-case NMH = VOH min − VIH
which means
= 2.4 − 2 = 0.4 V
N =2
Worst-case NML = VIL − VOLmax
(c) (i) When the inverter output is low,
= 0.8 − 0.4 = 0.4 V
PD =
2
VDD
2.52
=
3 mW
R + Ron
2 + 0.1
Chapter 15–9
(ii) When the output is high and the inverter is
driving two inverters, the current drawn from the
supply is 2 × 0.2 = 0.4 mA and thus the power
dissipation is
Thus,
PD = VDD IDD = 2.5 × 0.4 = 1 mW
and VIL = 0.615/1.769 = 0.349 V
VIL = 0.923 − 0.769 (VIL + 0.4)
= 0.615 − 0.769VIL
whence VIH = 0.4 + 0.349 = 0.749 V
Alternatively, NMH = 0.769NML and
15.19 For an ideal inverter:
1
VM = VDD = 1 V
2
VIL = VIH = VM = 1 V
(VOH − VIH ) = 0.769 (VIL − VOL ) or
1.2 − VIH = 0.769VIL − 0 and
VIH = 1.2 − 0.769VIL , with (1),
VOL = 0 V
VIL + 0.4 = 1.2 − 0.769VIL , and
VOH = VDD = 2 V
1.769VIL = 0.8, whence VIL = 0.452 V
NML = VIL − VOL
and VIH = 0.4 + 0.452 = 0.852
=1−0=1V
Thus, overall, VOH = 1.2 V, VOL = 0.0 V,
NMH = VOH − VIH
VIH ranges from 0.749 V to 0.852 V, and
=2−1=1V
VIL ranges from 0.349 V to 0.451 V, in
which case the margins can be as low as
NML = VIL − VOL = 0.349 V and
NMH = VOH − VIH = 1.2 − 0.852 = 0.348 V
and as high as 0.451 V, and 0.451 V.
15.21
VDD
RD
Figure 1
Ron ⯝ rDS vO
The ideal transfer characteristic is shown in
Fig. 1, from which we see that
Gain in transition region = ∞
Equivalent circuit for output-low state
15.20 Here, VOH = 1.2 V, and VOL = 0.0 V
Also, VIH − VIL ≤ 1.2/3 = 0.4 V
(1)
The output-high level for the simple inverter
circuit shown in Fig. 15.12 of the text is
Now, the noise margins are “within 30% of one
other.” Thus, NMH = (1 + ±0.3) NML or
NML = (1 + ±0.3) NMH . Thus, they remain
“within” either NMH = 1.3NML or
NML = 1.3NMH , in which case either
NML = 0.769NMH or NMH = 0.769NML
When the output is low, the current drawn from
the supply can be calculated as
For the former case:
Therefore: RD + rDS =
0.769 (VOH − VIH ) = (VIL − VOL ) or
0.769 (1.2 − VIH ) = VIL − 0, whence
VIL = 0.923 − 0.769VIH
Now, from (1), VIH = VIL + 0.4
VOH = VDD ⇒ VDD = 1.2 V.
I=
VDD
= 30 μA
RD + Ron
1.2
= 40 k
30 × 10−6
Also:
rDS
× VDD
RD + rDS
0.05
= 40 k ×
= 1.67 k
1.2
VOL = 0.05 V =
⇒ rDS
Chapter 15–10
Hence: RD = 40 K − 1.67 K = 38.3 k
1
W
μn Cox (VGS − Vt )
L
1
=
W
−6
500 × 10 ×
(1.2 − 0.4)
L
= 1.67 k
W
= 1.5
⇒
L
When the output is low:
=
rDS =
PD = VDD IDD = 1.2 × 30 μA = 36 μW
When the output is high, the transistor is off:
PD = 0 W
VDD
= 0.054VDD
VDD − 0.3VDD
1+
0.04VDD
NMH = VOH − VIH
= VDD − 0.586VDD = 0.414VDD
NML = VIL − VOL
= 0.34VDD − 0.054VDD = 0.286VDD
For VDD = 1.2 V:
Vx = 0.048 V, VOH = 1.2 V, VIL = 0.408 V,
VIH = 0.703 V, VOL = 0.065 V,
NMH = 0.50 V, NML = 0.34 V
PD = VDD ID
= VDD ×
VDD − VOL
RD
15.22 The output voltage swing = RC1 I = 0.5 V.
Substituting for RD from
with IEE = 0.5 mA, RC1 = 1.0 k, similarly,
RD =
RC2 = 1.0 k
we obtain
VOH = VCC = 2 V
VOL = VCC − RC1 IEE = 1.5 V
15.23 Vt = 0.3VDD , VM = VDD /2
From Eq. (15.13) on page 1244 of text, we obtain
2
VDD
− Vt
2
Vx V = VDD =
M
2
VDD
=
(0.5VDD − 0.3VDD )2
VDD
⇒ Vx = 0.04VDD
1
k n Vx
PD = VDD (VDD − 0.054VDD ) × k n × 0.04VDD
W
3
PD = 0.038VDD
× k n
L
W
= 0.038 × 1.23 × 0.5 × 10−3
L
W
= 0.033
, mW
L
For PD = 100 μW = 0.1 mW, we obtain
W
0.1 = 0.033
L
⇒
W
=3
L
RD =
VOH = VDD
1
k n Vx
1
0.5 × 3 × 0.048
From Eq. (15.12), we get
=
VIL = Vt + Vx = 0.3VDD + 0.04VDD
= 13.9 k
= 0.34VDD
From Eq. (15.20), we obtain
VIH = Vt + 1.63 VDD Vx − Vx
= 0.3VDD + 1.63 VDD × 0.04VDD − 0.04VDD
15.24 Refer to Example 15.2 on page 1243 of the
text:
= 0.586VDD
The power drawn from the supply during the
low-output state is
From Eq. (15.22), we get
VOL
VDD
=
1 + [(VDD − Vt )/Vx ]
VOH = VDD = 1.2 V
PDD = VDD IDD ⇒ 60 μW = 1.2 × IDD
⇒ IDD = 50 μA
Chapter 15–11
(a) Figure 1 shows the i − v characteristic of the
load diode-connected transistor Q2 . Observe that
since v DG = 0, this transistor is always in
saturation. The current i that feeds Q2 is provided
by Q1 . Even when i is very small, Q2 will be
operating at v = Vt and thus the output voltage of
the inverter VOH will be
In this case:
VDD − VOL
1.2 − 0.05
⇒ 50 μA =
IDD =
RD
RD
⇒ RD = 23 k
W
, we note that
L
1
W
k n RD = 1/VX or k n RD =
L
VX
In order to determine
VOH = VDD − Vt
This loss of Vt volts in VOH is a drawback of this
form of logic circuit.
Therefore, we need to first calculate VX using
Eq. (15.22) on page 1246 of the text.
VOL =
(b) As v I increases and reaches Vt of Q1 ,
transistor Q1 begins to conduct an appreciable
current and v increases above Vt2 , thus v O begins
to decrease below VOH . The threshold voltage VIL
is usually taken as Vt1 :
VDD
or equivalently
VDD − Vt
1+
VX
0.05 V =
1.2
1.2 − 0.4
1+
VX
VIL = Vt
(c) When Q1 begins to conduct, it will be
operating in saturation, thus
0.8
= 0.035 V
23
1
W
gives
Hence, k n RD =
Vx
L
⇒ VX =
1
(1)
k n1 (v I − Vt )2
2
Transistor Q2 is always operating in saturation,
thus
1
(2)
iD2 = k 2 (VDD − v O − Vt )2
2
Since iD1 = iD2 = i, we can equate their values in
Eqs. (1) and (2) and thus obtain
iD1 =
W
W
1
×23×103 =
⇒
= 2.5
L
0.035
L
Using Eq. (15.12), we obtain
500×10−6 ×
VIL = Vt + VX = 0.4 + 0.035 = 0.435 V
From Eq. (15.14) we obtain
VM = Vt + 2 (VDD − Vt )Vx + V 2 x − Vx
= 0.4 + 2 (1.2 − 0.4) 0.035 + 0.0352 − 0.035
k n1 (v I − Vt )2 = k n2 (VDD − v O − Vt )2
k n1
⇒
(v I − Vt ) = VDD − v O − Vt
k n2
VM = 0.6 V
⇒ v O = VDD + (k r − 1)Vt − k r v I
From Eq. (15.20) we get
VIH = Vt + 1.63 VDD Vx − Vx
√
= 0.4 + 1.63 1.2 × 0.035 − 0.035 = 0.7 V
where
NMH = VOH − VIH = 1.2 − 0.7 = 0.5 V
Equation (3) is that of the inverter VTC in the
transition region. It is linear and has a slope
of −k r .
kr ≡
NML = VIL − VOL = 0.435 − 0.05 = 0.385 V
i
1 k (v V )2
t
2 n2
PD |v O =VOL = VDD IDD
1
k n2 VDD (VDD − Vt )2
2
Since the inverter spends half the time in this state
and the other half in the output-high state where
=
0
v
Vt
Figure 1
k n1
k n2
(d) With v I = VDD , v O = VOL 0, the voltage
v VDD and the current IDD that flows in the
inverter is
1
IDD = k n2 (VDD − Vt )2
2
Thus, the power dissipated in the inverter in the
low-output state is
15.25
i
(3)
Chapter 15–12
the power dissipation is essentially zero, the
average power dissipation will be
1
PD = k n2 VDD (VDD − Vt )2
4
(e) For VDD = 1.8 V, Vt = 0.5 V, (W/L)1 = 5,
1
and μn Cox = 300 μA/V2 , we have
5
= VDD − Vt = 1.8 − 0.5 = 1.3 V
(W/L)2 =
VOH
VIL = Vt = 0.5 V
k n1
5
=5
=
kr =
k n2
1/5
⇒ Wp = 2.5Wn = 2.5 × 1.5 × 65 = 244 nm
Silicon area = Wn Ln + Wp Lp
= 1.5 × 65 × 65 + 2.5 × 1.5 × 65 × 65
= 1.5 × 65 × 65(1 + 2.5)
= 22, 181 nm2
(b) VOH = VDD = 1 V
VOL = 0 V
To obtain VIH , we use Eq. (15.35):
VIH =
1
(5VDD − 2Vt )
8
v O = 1.8 + (5 − 1) × 0.5 − 5v I
1
(5 × 1 − 2 × 0.35)
8
= 0.5375 V
⇒ v O = 3.8 − 5v I
To obtain VIL , we use Eq. (15.36):
In the transition region, we have
1
1
IDD = × 0.3 × × (1.8 − 0.5)2
2
5
= 0.05 mA
1
PD = × 1.8 × 0.05 = 45 μW
2
=
VIL =
1
(3VDD + 2Vt )
8
1
(3 × 1 + 2 × 0.35)
8
= 0.4625 V
=
The noise margins can now be found as
15.26 Refer to Example 15.3 (page 1248 of text)
VOH = VDD = 1.2 V
VOL = (VDD − Vt ) 1 − 1 − (k p /k n )
= (1.2 − 0.4) 1 −
1−
1
5
= 0.084 V
1
IDD = k p (VDD − Vt )2
2
1
= × 0.1(1.2 − 0.4)2
2
= 0.032 mA = 32 μA
NMH = VOH − VIH
= 1 − 0.5375 = 0.4625 V
NML = VIL − VOL
= 0.4625 − 0 = 0.4625 V
The noise margins are equal at approximately
0.46 V; a result of the matched design of the
inverter.
(c) Since the inverter is matched, the output
resistances in the two states will be equal. Thus,
W
rDSP = rDSN = 1 (μn Cox )
(VDD − Vt )
L n
1
= 2.18 k
0.47 × 1.5(1 − 0.35)
Pav =
1
1
VDD IDD = × 1.2 × 32 = 19.2 μW
2
2
From the statement of Exercise 15.5, we have
=
VDD − Vt
VM = Vt + √
r+1
15.28 VOH = 2.5 V
where r = k n /k p = 5, thus
1.2 − 0.4
VM = 0.4 + √
5+1
= 0.73 V
15.27 (a) To obtain VM = VDD /2, the inverter
must be matched, thus
Wp
μn
=
= 2.5
Wn
μp
VOL = 0 V
(a) For the matched case we have
Wp = 3.5Wn
1
VDD = 1.25 V
2
1
Eq. (15.35): VIH = (5 VDD − 2 Vt )
8
1
= (5 × 2.5 − 2 × 0.5)
8
= 1.4375 V
VM =
Chapter 15–13
Eq. (15.36): VIL =
=
1
(3 VDD + 2 Vt )
8
1
(3 × 2.5 + 2 × 0.5)
8
Silicon area = Wn Ln + Wp Lp
= 1.5 × 0.25 × 0.25 + 2 × 1.5 × 0.25 × 0.25
= 3 × 1.5 × 0.252
= 1.0625 V
= 0.28 μm2
NMH = NML = 1.0625 V
Compared to the matched case, the silicon area is
reduced by 33%.
Silicon area = Wn Ln + Wp Lp
= 1.5 × 0.25 × 0.25 + 3.5 × 1.5 × 0.25 × 0.25
= 4.5 × 1.5 × 0.252 = 0.42 μm2
(b) Wp = Wn (minimum-size design):
μp Wp
1
× 1 = 0.53
=
Eq. (15.40): r =
μn Wn
3.5
r(VDD − |Vtp |) + Vtn
Eq. (15.39): VM =
r+1
0.53(2.5 − 0.5) + 0.5
=
0.53 + 1
= 1.02 V
Thus, VM shifts to the left by 0.23 V. Assuming
VIL shifts by approximately the same amount, then
VIL 1.0625 − 0.23 0.83 V
Since NML = VIL , NML will be reduced by
approximately 22% (relative to the matched case).
Silicon area = Wn Ln + Wp Lp
15.29 QN will be operating in the triode region,
thus
1
W
IDn = k n
(VDD − Vtn )VO − VO2
L n
2
For Vtn = 0.3VDD and VO = 0.1VDD , we have
IDn = k n
W
L
n
(VDD − 0.3VDD ) × 0.1VDD −
1
2
× 0.12 VDD
2
2
2
= k n (W/L)n (0.07VDD
− 0.005VDD
)
2
= 0.065k n (W/L)n VDD
Q.E.D.
k n
For VDD = 1.3 V, = 0.5 mA/V2 and
IDn = 0.1 mA, we have
0.1 = 0.065 × 0.5(W/L)n × 1.32
W
⇒
= 1.82
L n
= 1.5 × 0.25 × 0.25 + 1.5 × 0.25 × 0.25
= 3 × 0.252 = 0.19 μm2
which is a reduction of 55% relative to the
matched case.
(c) Wp = 2Wn (a compromise design):
μp Wp
1
2
=
×
Eq. (15.40): r =
μn Wn
3.5 1
= 0.756
Eq. (15.39): VM =
=
r(VDD − |Vtp |) + Vtn
r+1
0.756(2.5 − 0.5) + 0.5
0.756 + 1
15.30 From Eq. (15.39) we have
VM =
r(VDD − |Vtp |) + Vtn
r+1
rVM + VM = r(VDD − |Vtp |) + Vtn
r(VDD − |Vtp | − VM ) = VM − Vtn
⇒r=
VM − Vtn
VDD − |Vtp | − VM
Q.E.D.
For VDD = 1.3 V, Vtn = |Vtp | = 0.4 V, to obtain
VM = 0.6VDD , we need
r=
0.6 × 1.3 − 0.4
1.3 − 0.4 − 0.6 × 1.3
= 3.167
= 1.15 V
But,
Thus, relative to the matched case the switching
point (VM ) is shifted left by (1.25 − 1.15) = 0.1 V.
Assuming that VIL is reduced by approximately
the same amount, then
r=
VIL = 1.0625 − 0.1 = 0.9625 V
μp Wp
μn Wn
1 Wp
×
3.167 =
4 Wn
Thus, NML which equals VIL is reduced by about
9% (relative to the matched case).
Wp
= 3.1672 × 4 = 40.1
Wn
Chapter 15–14
15.31 Refer to Example 15.4 (page 1257 of text)
except here:
From symmetry, we can obtain the value of v O
corresponding to v I = VIL as
VDD = 1.3 V, Vtn = |Vtp | = 0.4 V, μn = 4 μp , and
μn Cox = 0.5 mA/V2 . Also, QN and QP have
L = 0.13 μm and (W/L)n = 1.5.
v O = VDD − 0.0625
(a) For VM = VDD /2 = 0.65 V, the inverter must
be matched, thus
Thus, the worst-case value of VOH is
VOH min 1.24 V, and the noise margin NMH is
reduced to
Wp
μn
=
=4
Wn
μp
= 1.3 − 0.0625 = 1.2375 V 1.24 V
NMH = VOH min − VIH
Since Wn /L = 1.5,
Wn = 1.5 × 0.13 = 0.195 μm. Thus,
Wp = 4 × 0.195 = 0.78 μm
= 1.2375 − 0.7125 = 0.5250 V
or approximately 0.53 V.
Note that the reduction in the noise margin (about
0.06 V) is slight.
For this design, the silicon area is
A = Wn L + Wp L = L(Wn + Wp )
= 0.13(0.195 + 0.78) = 0.127 μm
2
(b) VOH = VDD = 1.3 V
(c) The output resistance of the inverter in the
low-output state is
rDSN =
VOL = 0 V
To obtain VIH , we use Eq. (15.35):
VIH =
=
1
(5VDD − 2Vt )
8
1
(5 × 1.3 − 2 × 0.4)
8
= 0.7125 V
=
1
μn Cox (W/L)n (VDD − Vtn )
1
= 1.48 k
0.5 × 1.5(1.3 − 0.4)
Since QN and QP are matched, the output
resistance in the high-output state will be equal,
that is,
rDSP = rDSN = 1.48 k
= 0.5875 V
(d) If the inverter is biased to operate at
v I = v O = VM = 0.65 V, then each of QN and QP
will be operating at an overdrive voltage
VOV = VM − Vt = 0.65 − 0.4 = 0.25 V and will
be conducting equal dc currents ID of
1
W
V2
ID = μn Cox
2
L n OV
We can now compute the noise margins as
=
NMH = VOH − VIH = 1.3 − 0.7125
= 23.4 μA
To obtain VIL , we use Eq. (15.36):
VIL =
=
1
(3VDD + 2Vt )
8
1
(3 × 1.3 + 2 × 0.4)
8
= 0.5875 V 0.59 V
1
× 500 × 1.5 × 0.252
2
NML = VIL − VOL = 0.5875 − 0
Thus, QN and QP will have equal
transconductances:
= 0.5875 V 0.59 V
gmn = gmp =
For v I = VIH = 0.7125 V, we can obtain the
corresponding value of v O by substituting in
Eq. (15.34):
Transistors QN and QP will have output
resistances ron and rop given by
VDD
= 0.7125 − 0.65 = 0.0625 V
2
ron =
VAn
ID
Thus, the worst-case value of VOL is
VOmax = 0.0625 0.06 V, and the noise margin
NML reduces to
rop =
|VAp |
ID
v O = VIH −
NML = 0.5875 − 0.0625 = 0.5250 V
or approximately 0.53 V.
2ID
2 × 23.4
=
= 0.19 mA/V
VOV
0.25
Since no values are given for VAn and VAp we
shall use the data in Table K.1, namely
VAn
= 5 V/μm and |VAp
| = 6 V/μm
Chapter 15–15
Thus,
In this case, the silicon area required is
VAn = 5 × 0.13 = 0.65 V
A = L(Wn + Wp ) = L × 3Wn
|VAp | = 6 × 0.13 = 0.78 V
= 0.13 × 3 × 1.5 × 0.13
ron =
0.65 V
= 27.8 k
23.4 μA
rop =
0.78 V
= 33.3 k
23.4 μA
We can now compute the voltage gain at M as
Av = −(gmn + gmp )(ron
rop )
= −(0.19 + 0.19)(27.8
33.3)
= −5.8 V/V
When the straight line at M of slope −5.8 V/V is
extrapolated,
it intersects the line v O = 0 at
0.65
= 0.762 V and the line v O = VDD
0.65 +
5.8 0.65
at 0.65 −
= 0.538 V. Thus the width of
5.8
the transition region can be considered
(0.762 − 0.538) = 0.224 V.
(e) For Wp = Wn , the parameter r can be found
from Eq. (15.40):
μp Wp
1
× 1 = 0.5
=
r=
μn Wn
4
The corresponding value of VM can be
determined from Eq. (15.39) as
0.5(1.3 − 0.4) + 0.4
= 0.57 V
0.5 + 1
Thus, VM shifts by only −0.08 V. We can estimate
the reduction in NML to be approximately equal to
the shift in VM , that is, NML becomes
VM =
= 0.076 μm2
which represents a 40% reduction relative to the
matched case.
15.32 The current reaches its peak at
VDD
v I = VM =
. At this point, both QN and QP
2
are operating in the saturation region and
conducting a current
2
1
W
VDD
IDP = IDN = k n
− Vt
2
L n 2
2
1.3
1
− 0.4
= × 500 × 1.5
2
2
= 23.4 μA
15.33 (a) Switch opens at time t = 0, thus
v O (0+) = 0 V. The capacitor then charge by a
constant current I , thus
It = Cv O (t)
I
t
C
(b) For I = 1 mA and C = 10 pF the time t for
v O to reach 1 V can be found as
⇒ v O (t) =
1=
1 × 10−3
t
10 × 10−12
⇒ t = 10−8 s = 10 ns
NML = 0.5875 − 0.08 0.51 V
The silicon area for this design can be computed
as follows:
A = L(Wn + Wp )
= 0.13(1.5 × 0.13 + 1.5 × 0.13)
= 0.051 μm2
15.34 (a) Capacitor C is charged to 10 V and the
switch closes at t = 0, thus
v O (0+) = 10 V
Capacitor C then discharges through R
exponentially with v O (∞) = 0
v O (t) = 0 − (0 − 10) e−t/τ
This represents a 60% reduction from the
matched case!
⇒ v O (t) = 10e−t/τ
(f) For Wp = 2Wn , we have
(b) For C = 100 pF and R = 1 k, we have
τ = 100 × 10−12 × 1 × 103 = 100 ns
1
1
× 2 = √ = 0.707
r=
4
2
0.707(1.3 − 0.4) + 0.4
VM =
= 0.61 V
0.707 + 1
Thus, relative to the matched case, VM is reduced
by only 0.04 V. Correspondingly, NML will be
reduced by approximately an equal amount, thus
NML becomes
At t = 0, v I goes low and the transistor turns off
instantly, thus
NML 0.59 − 0.04 = 0.55 V
v O (0+) = VOL
tPHL = 0.69τ = 0.69 × 100 = 69 ns
tf = 2.22τ = 2.2 × 100 = 220 ns
15.35 VOH = VDD
Chapter 15–16
At t = tPLH , v O = VDD /2, thus
Now capacitor C charges through R towards
v O (∞) = VDD , thus
v O (t) = VDD − (VDD − VOL ) e−t/τ
VDD
= VDD (1 − e−tPLH /τ )
2
At t = tPLH ,
⇒ e−tPLH /τ = 0.5
vO =
1
1
(VOL + VOH ) = (VOL + VDD ), thus
2
2
⇒ tPLH = τ ln2 = 0.69τ
For C = 50 fF, Ronu = 2 k, then
1
(VOL + VDD ) = VDD − (VDD − VOL )e−t/τ
2
⇒ tPLH = 0.69τ
tPLH = 0.69 × 50 × 10−15 × 2 × 103
For R = 10 k and we wish to limit τPLH to 100
ps then the maximum value that C can have is
found from
0.69 × C × 10 × 103 = 100 × 10−12
⇒ C = 1.45 × 10−14 F
= 14.5 fF
= 69 ps
Next we determine tPHL by considering the
situation depicted in Fig. 1(b). Here, PU has just
opened, leaving v O (0+) = VDD . Capacitor C then
discharges through the on resistance of the
pull-down switch, Rond , toward 0 V, thus
v O (∞) = 0, thus
v O = 0 − (0 − VDD ) e−t/τ
= VDD e−t/τ
15.36
At t = tPHL , v O = VDD /2 and we get
VDD
vO
VDD
= VDD e−tPHL /τ
2
Ronu
⇒ tPHL = 0.69τ
vO VDD
C
PD
Here,
VDD
2
τ = CRond
tPLH
0
t
= 50 × 10−15 × 1 × 103 = 50 ps
Thus,
Figure 1(a)
tPHL = 0.69 × 50 35 ps
The propagation delay tP can now be obtained as
VDD
tP =
vO
PU
vO
Rond
C
=
VDD
VDD
2
0
1
(tPLH + tPHL )
2
1
(69 + 35) = 52 ps
2
15.37 (a) VOL = 0 V
tPHL
t
Figure 1(b)
VOH = VDD = 1.8 V
NML = VIL − VOL =
VDD
−0
2
= 0.9 V
To obtain tPLH , consider the situation in Fig. 1(a).
Here, PD has just opened (at t = 0), leaving
v O = 0 V at t = 0+. Capacitor C then charges
through the "on" resistance of the pull-up switch,
Ronu , toward VDD , thus
= 0.9 V
v O (t) = V∞ − (V∞ − V0+ )e−t/τ
(b) Capacitor C discharges through Ron of PD ,
= VDD − (VDD − 0)e−t/τ
v O (0+) = VDD = 1.8 V
= VDD (1 − e−t/τ )
v O (∞) = 0 V
NMH = VOH − VIH = VDD −
VDD
2
Chapter 15–17
15.38 See figure below.
Thus,
v O (t) = VDD e
−t/τ
(a) For a rising input, time to the full change of
output of second gate is
⇒ tPHL = 0.69τ
= 0.69 × 0.1 × 10−12 × 2 × 103
10 + 20 +
= 138 ps
30
= 45 ns
2
(b) For a falling input, time to the full change of
output of the second gate is
(c) Here the capacitor charges through Ron of PU
toward VDD . Thus,
20 + 10 +
v O (0+) = 0, v O (∞) = VDD ,
15
= 37.5 ns
2
v O (t) = VDD (1 − e−t/τ )
The propagation delay is
At t = tPLH , v O (t) = VDD /2, thus
tP =
tPLH = 0.69τ
=
= 0.69 × 0.1 × 10−12 × 2 × 103
1
(tPLH + tPHL )
2
1
(20 + 10) = 15 ns
2
= 138 ps
15.39 (a) tP =
Finally, we obtain τP as
τP =
=
1
(tPLH + tPHL )
2
1
(tPLH + tPHL )
2
Since tP = 0.9 ns, then
tPLH + tPHL = 1.8 ns
1
(138 + 138) = 138 ps
2
(1)
This figure belongs to Problem 15.38.
vI
vO2
vO1
vI
0
20
40
60
80
100
vO1
120
112.5
2.5
50%
117.5
t
20
10
30
40
50
60
70
80
55
17.5
90 100 110 120
85
vO2
50%
t
10
20
15
30
40
50
45
60
70
72.5
80
90 100 110 120 130
87.5
Chapter 15–18
For a matched inverter, we have
Now, since Icharge is half Idischarge , then
tPLH = 2tPHL
(2)
tPHL = tPLH = tP
Using (1) together with (2) yields
For tP ≤ 80 ps,
tPLH = 1.2 ns
tPHL ≤ 80 ps
tPHL = 0.6 ns
But,
(b) Since the propagation delay is directly
proportional to C, then the increase in
propagation delay by 50%, when the capacitance
is increased by 0.5 pF, indicates that the original
total capacitance is 1.0 pF.
tPHL =
(c) The reduction of propagation delays by 40%
when the load inverter is removed indicates that
the load inverter was contributing 40% of the
total capacitance found in (b), that is,
αn C
k n (W/L)n VDD
2.32 × 30 × 10−15
≤ 80 × 10−12
430 × 10−6 (W/L)n × 1.2
(W/L)n ≥ 1.7
(W/L)p ≥ 6.8
15.42 RN =
Cout = 0.6 pF
12.5
12.5
= 8.33 k
=
(W/L)n
1.5
tPHL = 0.69CRN
Cload = 0.4 pF
= 0.69 × 10 × 10−15 × 8.33 × 103
15.40 αn = 2
7 3 Vtn
−
+
4
VDD
7 3 × 0.4
−
+
4
1.2
=2
0.4
1.2
Vtn
VDD
2
RP =
2
=
= 0.69 × 10 × 10−15 × 10 × 103
= 69 ps
αn C
k n (W/L)n VDD
15.43 For
= 30 ps
tPHL = tPLH = tP ≤ 50 ps
αp = αn = 2.32
= we use
αp C
k p (W/L)p VDD
tPHL = 0.69CRN
2.32 × 10 × 10−15
430
× 10−6 × 3 × 1.2
4
= 0.69C ×
12.5
× 103
(W/L)n
and thus obtain
= 60 ps
tP =
1
(57.5 + 69) = 63.3 ps
2
tP =
2.32 × 10 × 10−15
430 × 10−6 × 1.5 × 1.2
tPLH =
30
30
= 10 k
=
(W/L)p
3
tPLH = 0.69CRP
= 2.32
tPHL =
= 57.5 ps
0.69 × 10 × 10−15 ×
1
(tPHL + tPLH )
2
⇒
1
= (30 + 60) = 45 ps
2
W
L
12.5
× 103 ≤ 50 × 10−12
(W/L)n
≥ 1.725
n
Similarly,
tPLH = 0.69 C RP
15.41 αn = 2
=2
= 2.32
7 3 Vtn
−
+
4
VDD
7 3 × 0.4
−
+
4
1.2
0.4
1.2
2
Vtn
VDD
2
= 0.69 C ×
30
× 103
(W/L)p
Thus,
0.69 × 10 × 10−15 ×
⇒ (W/L)p ≥ 4.14
30
× 103 ≤ 50 × 10−12
(W/L)p
Chapter 15–19
15.44 RN =
12.5
= 12.5 k
1
αp = αn = 2.01
tPLH =
30
RP =
= 30 k
1
tPHL = 0.69CRN
= 0.69 × 20 × 10−15 × 12.5 × 103
= 172.5 ps
=
k p
αp C
W
VDD
L p
2.01 × 11.16 × 10−15
0.27
380
× 10−6 ×
× 1.8
4
0.18
= 87.6 ps
tPLH = 0.69CRP
1
(21.9 + 87.6) = 54.8 ps
2
= 0.69 × 20 × 10−15 × 30 × 103
tP =
= 414 ps
If the design is changed to a matched one, then
tP =
Wp = 4Wn = 4 × 0.27 = 1.08 μm
1
(172.5 + 414)
2
C = 4 × 0.27 + 4 × 1.08 + 2 + 2 + 5
= 293.3 ps
= 14.4 fF
αn = αp = 2.01
15.45 Refer to Example 15.6.
The method of average currents yields
tPHL = 41.2 ps
The method of equivalent resistance yields
tPHL =
= 28.2 ps
tPLH =
tPHL = 57.5 ps
If the discrepancy is entirely due to the reduction
in current due to velocity saturation in the NMOS
transistor, then the factor by which the current
decreases is 41.2/57.5 = 0.716.
The value of tPLH does not change (in fact there is
a slight decrease due to various approximations).
We may therefore conclude that the effect of
velocity saturation is minimal in the PMOS
transistor.
= 11.16 fF
7 3 Vtn
−
+
4
VDD
αn = 2
=2
7 3 × 0.5
−
+
4
1.8
Vtn
VDD
0.5
1.8
tP =
1
(28.2 + 28.2) = 28.2 ps
2
15.47 αn = 2
=
2
k n
αn C
W
VDD
L n
2.01 × 11.16 × 10−15
0.27
380 × 10−6 ×
× 1.8
0.18
= 21.9 ps
7 3 Vtn
−
+
4
VDD
7 3 × 0.35
−
+
4
1
tPHL =
=
αn C
k n (W/L)n VDD
2.43 × 10 × 10−15
470 × 10−6 × 1.5 × 1
= 34.4 ps
αp C
k p (W/L)p VDD
Since |Vtp | = Vtn , we have
αp = αn = 2.43
Thus,
tPLH =
2.43 × 10 × 10−15
190 × 10−6 × 3 × 1
= 42.6 ps
0.35
1
= 2.43
tPLH =
= 2.01
tPHL =
2
2.01 × 14.4 × 10−15
380
1.08
× 10−6 ×
× 1.8
4
0.18
= 28.2 ps
=2
15.46 C = 4 × 0.27 + 4 × 0.27 + 2 + 2 + 5
2.01 × 14.4 × 10−15
0.27
380 × 10−6 ×
× 1.8
0.18
Vtn
VDD
2
2
Chapter 15–20
1
(34.4 + 42.6) = 38.5 ps
2
tP =
The theoretical maximum switching frequency is
1
1
=
13 GHz
2tP
2 × 38.5 × 10−12
fmax =
45
= 60 ps
45 + 15
tP = 80 ×
A reduction by 40 ps requires the use of a scale
factor S,
15.48 Wn = 0.75 μm
Wp =
15.49 To reduce tP by 40 ps, we need to reduce
the extrinsic part by 40 ps. Now the original value
of the extrinsic part is
μn Cox
× Wn
μp Cox
S=3
This is the factor by which (W/L)n and (W/L)p
must be scaled. The inverter area will be
increased by the same ratio, that is, 3.
180
× 0.75 = 3.0 μm
=
45
C = 2Cgd 1 + 2Cgd 2 + Cdb1 + Cdb2
15.50 (a) Examination of Eq. (15.59) reveals
that the NMOS transistors Q1 and Q3 contribute
+ Cg3 + Cg4 + Cw
where
Cn = 2 Cgd 1 + Cdb1 + Cg3
Cgd 1 = 0.4 × Wn = 0.4 × 0.75 = 0.3 fF
Cgd 2 = 0.4 × Wp = 0.4 × 3 = 1.2 fF
Cdb1 = 1 × Wn = 1 × 0.75 = 0.75 fF
Cdb2 = 1 × Wp = 1 × 3 = 3 fF
Cg3 = 0.75×0.5×3.7+2×0.4×0.75 = 1.9875 fF
Cg4 = 3 × 0.5 × 3.7 + 2 × 0.4 × 3 = 7.95 fF
and the PMOS transistors Q2 and Q4 contribute
Cp = 2 Cgd 2 + Cdb2 + Cg4
7 3 Vt
−
+
4
VDD
7 3 × 0.7
−
+
4
3.3
=2
Vt
VDD
0.7
3.3
2
2
= 1.73
tPHL
=
Cp = Cn
Wp
Wn
and the total capacitance C can be expressed as
= 18.7 fF
αn = 2
(2)
The only difference in determining the
corresponding capacitances in Eqs. (1) and (2) is
the transistor width W. Thus each of the
components in Eq. (2) can be written as the
corresponding component in Eq. (1) multiplied by
(Wp /Wn ). Overall, we can write
Thus,
C = 2×0.3+2×1.2+0.75+3+1.9875+7.95+2
(1)
αn C
= W
k n
VDD
L n
1.73 × 18.7 × 10−15
0.75
180 × 10−6 ×
× 3.3
0.5
= 36.3 ps
Since the inverter is matched,
tPLH = tPHL = 36.3 ps
and
tP = 36.3 ps
The propagation delay increases by 50% if C is
increased by 50%, that is, by 18.7/2 = 9.35 fF.
C = Cn + Cp + Cw
= Cn + Cn
Thus,
Wp
+ Cw
Wn
C = Cn
(b) RN =
Wp
1+
Wn
+ Cw
12.5
k
(W/L)n
For (W/L)n = 1, we have
RN = 12.5 k
Thus,
tPHL = 0.69CRN
= 0.69 × 12.5 × 103 C
= 8.625 × 103 C
RP =
=
Q.E.D.
30
k
(W/L)p
30
k
(Wp /Wn )(W/L)n
Q.E.D.
Chapter 15–21
For (W/L)n = 1, we have
RP =
Here C is entirely extrinsic, thus scaling the
PMOS transistors has resulted in a decrease in tP .
30
k
Wp /Wn
We conclude that using a matched design reduces
tP only when C is dominated by external
capacitances. The matched design, of course, has
the drawback of increased area.
and
tPLH = 0.69CRP
30
× ×103 C
Wp /Wn
= 0.69 ×
=
20.7 × 103
C
Wp /Wn
(c) tP =
=
15.51
Q.E.D.
1
(tPHL + tPLH )
2
20.7 × 103
1
8.625 × 103 C +
C
2
Wp /Wn
For Wp = Wn , we have
tP = 14.66 × 103 C
Wp
tP = 14.66 × 103 Cn 1 +
+ Cw
Wn
= 14.66 × 103 (2Cn + Cw )
(3)
(d) In the matched case, we have
tPLH = tPHL
From the results in (b), the required ratio
(Wp /Wn ) can be determined as
20.7
= 8.625
Wp /Wn
⇒
Wp
= 2.4
Wn
Figure 1
In this case, we have
C = Cn (1 + 2.4) + Cw = 3.4 Cn + Cw
and
tP = tPLH = 8.625 × 103 (3.4 Cn + Cw )
(4)
(e) (i) For Cw = 0, we have
Wp = Wn :
tP = 29.32 × 103 Cn
Wp = 2.4 Wn : tP = 29.32 × 103 Cn
Thus, in the case where C is entirely intrinsic,
scaling does not affect tP . This is what we found
in Eq. (15.65).
(ii) For Cw
Cn , we have
Wp = Wn :
tP = 14.66 × 10 Cw
3
Wp = 2.4 Wn : tP = 8.625 × 103 Cw
Figure 1 shows the CMOS logic gate with the
(W/L) ratios selected so that the worst-case tPLH
and tPHL are equal to the corresponding values of
the basic inverter with (W/L)n = n and
(W/L)p = p. Observe that the worst case for
discharging a capacitor occurs through the three
series transistors QNA , QNC , and QND . To make the
equivalent W/L for these three series transistors
equal to n, we select each of their (W/L) ratios to
be equal to 3n. Finally, for the discharge path
(QNA , QNB ) to have an equivalent W/L equal to n,
we selected W/L of QNB equal to 1.5n.
For the PUN, the worst-case charging path is that
through QPB and one of QPC or QPD . Thus we
select each of these three transistors to have
W/L = 2p. Finally, we selected W/L of QPA equal
to p.
Chapter 15–22
For the case in which all p-channel devices have
W/L = p and all n-channel devices have
W/L = n, we have
15.52
tPLH = 0.69 ×
30 × 103
×C
p
which is the same as in the first case. However,
tPHL = 0.69 ×
12.5 × 103
×C
n/4
4 × 12.5 × 103
×C
n
which is four times the value obtained in the
first case.
= 0.69 ×
15.54
L = 0.13 μm, Wn = 0.2 μm, Wp = 0.4 μm,
n = 0.2/0.13, p = 0.4/0.13
(a) Circuit (a) uses a six-input NOR gate and one
inverter.
Figure 1
The six-input NOR requires:
6 NMOS transistors each with W/L = n
0.40
0.20
, p=
n=
0.13
0.13
Figure 1 shows the circuit with the W/L ratio of
each of the eight transistors indicated. Observe
that the worst-case situation for both charging and
discharging is two transistors in series. To achieve
an equivalent W/L ratio for each path equal to
that of the corresponding transistor in the basic
inverter, each transistor is sized at twice that of
the inverter. Including the two inverters required
to obtain the complemented variable, the area is
A = 2Wn L + 2Wp L + 4 × 2Wn L + 4 × 2Wp L
= 10L(Wn + Wp )
= 10 × 0.13(0.2 + 0.4)
= 0.78 μm2
15.53 When the devices are sized as in
Fig. 15.35, tPLH that results when one PMOS
transistor is conducting (worst case) is
tPLH = 0.69RP C
= 0.69 ×
30 × 103
×C
p
and tPHL is obtained by noting that the equivalent
W/L of the discharge path is 4n/4 = n and thus
tPHL = 0.69 RN C
12.5 × 103
×C
= 0.69 ×
n
and
6 PMOS transistors each with W/L = 6p
The inverter requires
1 NMOS transistor with W/L = n
and
1 PMOS transistor with W/L = p
Thus,
Area = 6Wn L + 6 × 6Wp L + Wn L + Wp L
= L(7 Wn + 37 Wp )
= 0.13(7 × 0.2 + 37 × 0.4)
= 0.13 × 16.2 = 2.1 μm2
(b) Circuit (b) uses two three-input NOR gates
and one two-input NAND gate.
Each three-input NOR gate requires
3 NMOS transistors, each with W/L = n
3 PMOS transistors, each with W/L = 3p
The two-input NAND gate requires
2 NMOS transistors, each with W/L = 2n
2 PMOS transistors, each with W/L = p
Thus,
Area = 2 × 3 × Wn L + 2 × 3 × 3 × Wp L
+ 2 × 2 × W n L + 2 × Wp L
Chapter 15–23
= L(10 Wn + 20 Wp )
Thus,
= 0.13(10 × 0.2 + 20 × 0.4)
1
RCL
Q.E.D.
(1)
xn−1
(b) Differenting tP in Eq. (1) relative to x gives
= 0.13 × 10
= 1.3 μm2
Thus circuit (a) required 2.1/1.3 = 1.62 times the
area of circuit (b).
15.55 (a) n = 4
Minimum delay is obtained when the scaling
factor x is given by
xn =
CL
C
Here,
1200C
= 1200
C
⇒ x = 5.9
x4 =
tP = 4xCR
= 4 × 5.9CR = 23.6CR
(b) Let the number of the inverters be n.
Optimum performance is obtained when
CL
= 1200
xn =
C
and
x = e = 2.718
ln 1200
= 7.09 7
n=
ln e
Thus, we use 7 inverters. The actual scaling factor
required can be found from
x7 = 1200
⇒ x = (1200)1/7 = 2.75
The value of tP realized will be
tP = 7 × 2.75CR
= 19.25CR
which represents a reduction in tP by about
17.4%. Thus adding three inverters reduces the
delay by 17.4%.
15.56 (a) Refer to Fig. 15.37(c). By inspection
we see that
tP = τ1 + τ2 + ... + τn−1 + τn
But,
τ1 = τ2 = ... = τn−1 = xCR
and
τn =
R
x
C
n−1 L
tP = (n − 1)xRC +
∂tP
(n − 1)
= (n − 1)RC −
RCL
∂x
xn
∂tP
to zero gives
Equating
∂x
CL
xn =
Q.E.D.
(2)
C
(c) Differenting tP in Eq. (1) relative to n gives
∂tP
1
= xRC − n−1 (ln x)RCL
∂n
x
∂tP
to zero gives
Equating
∂n
C
xn
= ln x
Q.E.D.
CL
(3)
To obtain the value of x for optimum
performance, we combine the two optimality
conditions in (2) and (3). Thus
ln x = 1
⇒x=e
Q.E.D.
2
15.57 E = CVDD
= 10 × 10−15 × 1.82 = 32.4 fJ
For 2 × 106 inverters switched at f = 1 GHz,
PD = 2 × 106 × 1 × 109 × 32.4 × 10−15
= 64.8 W
PD
64.8
IDD =
=
= 36 A
VDD
1.8
2
15.58 Pdyn = fCVDD
= 2 × 109 × 5 × 10−15 × 1
= 10 μW
IDD =
10 × 10−6
= 10 μA
1
2
15.59 Since Pdyn is proportional to VDD
, reducing
the power supply from 5 V to 3.3 V reduces the
3.3 2
= 0.436.
power dissipation by a factor of
5
The power dissipation now becomes
0.436 × 10 = 4.36 mW. Since Pdyn is proportional
to f, reducing f by the same factor as the supply
voltage (0.66) results in reducing the power
dissipation further by a factor of 0.66, i.e.
Additional savings in power = (1 − 0.66) × 4.36
= 1.48 mW
Chapter 15–24
Figure 1 shows the circuit as the switch is opened
(t = 0+). Capacitor C will charge through R, and
its voltage will increase from the initial value of
VOL to the high value VOH ,
15.60 Each cycle, the inverter draws an average
current of
60 + 0
= 30 μA
Iav =
2
Since Iav = 150 μA, then the average current
corresponding to the dynamic power dissipation
is 120 μA. Thus,
v O = v O (∞) − [v O (∞) − v O (0+)]e−t/τ
= VOH − (VOH − VOL )e−t/τ1
where
Pdyn = 3.3 × 120 × 10−6 = 396 μW
τ1 = CR
But,
1
(VOH + VOL ) the time
2
required, tPLH , can be found as follows:
2
Pdyn = fCVDD
To reach the 50% point,
Thus,
1
(VOH + VOL ) = VOH − (VOH − VOL )e−tPLH /τ1
2
1
(VOH − VOL ) e−tPLH /τ1 = (VOH − VOL )
2
⇒ tPLH = τ1 ln2
396 × 10−6 = 100 × 106 × 3.32 × C
⇒ C = 0.36 pF
15.61 tPLH = 30 ns, tPHL = 50 ns
tP =
PDav
Q.E.D.
= 0.69τ1 = 0.69CR
1
(30 + 50) = 40 ns
2
1
= (1 + 0.6) = 0.8 mW
2
(b) Figure 2(a) shows the circuit after the switch
closes (t = 0+). At this instant the capacitor
voltage in VOH . The capacitor then discharges and
eventually reaches the low level VOL . To
determine τPHL , we simplify the circuit to that in
Fig. 2(b). Using this circuit, we can express v O as
PDP = 0.8 × 10−3 × 40 × 10−9 = 32 pJ
15.62 (a)
Q.E.D.
VDD
v O (t) = v O (∞) − [v O (∞) − v O (0)]e−t/τ1
= VOL − (VOL − VOH )e−t/τ2
when
R
τ2 = C(Ron
R) CRon
The value of tPHL can be found from
v O (tPHL ) =
C vO
1
(VOH + VOL )
2
= VOL − (VOL − VOH )e−tPLH /τ2
⇒ tPHL = τ2 ln2
Figure 1
This figure belongs to Problem 15.62, part (b).
VDD
R
R // Ron
Ron
C
vO
VDD
Ron
R Ron
C
vO
(a)
(b)
Figure 2
Chapter 15–25
Selecting R = 1 k yields
= 0.69τ2
= 0.69CRon
(c) tP =
=
Q.E.D.
1
(tPLH + tPHL )
2
1
(0.69CR + 0.69CRon )
2
tP =
1
× 0.69C(R + Ron )
2
Since Ron
R,
tP 0.35CR
Q.E.D.
(d) During the low-input state, the switch is
open, the current is zero, and the power
dissipation is zero.
During the high-input state, the switch is closed
and a current
IDD
VDD
VDD
=
R + Ron
R
flows, and the power dissipation is
PD = VDD IDD =
2
VDD
R
Now, if the inverter spends half the time in each
state, the average power dissipation will be
P=
2
1 VDD
2 R
tP = 0.35 × 10 × 10−12 × 1 × 103
= 3.5 ns
and
1 52
= 12.5 mW
2 1
Both values are within the design specifications.
P=
15.63 (a) The currents decrease by a factor of
1.8
= 0.72; that is, the new current values are
2.5
0.72 of the old current values. However, the
voltage swing is also reduced by the same factor.
The result is that tP remains unchanged. The PDP
will be reduced by a factor of 0.52.
Since the maximum operating frequency is
proportional to 1/tP , it also will remain
unchanged.
2
(b) If current is proportional to VDD
, the currents
2
become 0.72 of their old values. This together
with the reduction of voltage swing by a factor of
0.72 will result in tP increasing by a factor of
(1/0.72) and the maximum operating frequency
being reduced by a factor of 0.72. The PDP
decreases by a factor of 0.72.
15.64
vI
Q.E.D.
(e) For VDD = 5 V and C = 10 pF, we have
1.8
1.3
tP = 0.35 × 10 × 10−12 R
If tP is to be smaller or equal to 5 ns, we must have
0.35 × 10 × 10−12 R ≤ 5 × 10−9
⇒ R ≤ 1.43 k
If P is to be smaller or equal to 15 mW, we must
have
1 52
×
≤ 15
2
R
where R is in k, thus
0.5
0.28
1
t
(ns)
0.72
From Eq. (15.79), we have
2
1
W
VDD
Ipeak = μn Cox
− Vtn
2
L n 2
2
1
μA 1.8
Ipeak = × 450 2
− 0.5 = 36 μA
2
V
2
R ≥ 0.83 k
The time when the input reaches Vt is
Thus, to satisfy both constraints, R must lie in the
range
0.5
× 1 = 0.28 ns
1.8
The time when the input reaches VDD − Vt is
1.8 − 0.5
× 1 = 0.72 ns
1.8
0.83 k ≤ R ≤ 1.43 k
Chapter 15–26
So the base of the triangle is
t = 0.72 − 0.28 = 0.44 ns
1
E = Ipeak × VDD × t =
2
1
× 36 μA × 1.8 × 0.44 ns
2
= 14.3 fJ
P = f ×E = 100×106 ×14.3×10−15 = 1.43 μW.
Exercise 16–1
Ex: 16.1 Since dynamic power dissipation is
1
scaled by 2 and propagation delay is scaled by
S
1
1
1
1
1
, hence, PDP is scaled by 2 × = 3 = .
S
S
S
S
8
Thus, PDP decreases by a factor of 8.
VDS = VOV = (1.2 − 0.4) = 0.8 V to 1.2 V in the
absence of velocity saturation.
Ex: 16.2 If VDD and Vt are kept constant, the
entries in Table 16.1 that change are as follows:
iD =
1
110 × 10−6 × 1.5 × 0.6 1.2 − 0.4 − × 0.6
2
Obviously, VDD and Vt do not scale by
anymore. They are kept constant!
1
S
αC
Vt
: since α is a function of
, then α
k VDD
VDD
1
remains unchanged, while C is scaled by , and
S
k is scaled by S, therefore tP is scaled by
tP ∝
1
1/S
= 2
S
S
2
Energy/Switching cycle, i.e., CVDD
, is scaled
1
by
S
2
CVDD
1/S
and thus is scaled by
=S
2tP
1/S 2
thus Pdyn increases.
Pdyn ∝
For the PMOS
transistor, we see that since
|VGS | − Vtp = 0.8 V and |VDS | = 1.2 V are both
larger than |VDSsat | = 0.6 V the device will be
operating in velocity saturation and
(1 + 0.1 × 1.2) = 55.4 μA
0.6 ≤ VDS ≤ 1.2 V
Without velocity saturation
iD =
1
× 110 × 10−6 × 1.5 × (1.2 − 0.4)2 (1 + 0.1 × 1.2)
2
= 59.1 μA
VOV ≤ VDS ≤ 1.2 V or 0.8 V ≤ VDS ≤ 1.2 V
Note that the velocity saturation reduces the
NMOS current by 33% and the PMOS current by
∼ 6%.
Ex: 16.5 (a) Using Eq. (16.13), we have
Pdyn
, is scaled by
The power density, i.e.,
device area
S
= S3
1/S 2
Thus,
Ex: 16.3 Using Eq. (16.5), we have
log iD = log IS +
VDSsat =
L
0.25 × 10−6
νsat =
× 107 × 10−2
μn
400 × 10−4
= 0.63 V
Ex: 16.4 For the NMOS transistor, VGS = 1.2 V
results in VGS − Vtn = 1.2 − 0.4 = 0.8 V, which is
greater than VDSsat = 0.34 V. Also, VDS = 1.2 V
is greater than VDSsat , thus both conditions in
Eq. (16.12) are satisfied and the NMOS transistor
will be operating in the velocity-saturation region
and thus iD is given by Eq. (16.11),
1
iD = 430 × 10−6 × 1.5 × 0.34 1.2 − 0.4 − × 0.34
2
× (1 + 0.1 × 1.2) = 154.7 μA
If velocity-saturation were absent, the current
would be
1
iD = × 430 × 10−6 × 1.5(1.2 − 0.4)2 ×
2
(1 + 0.1 × 1.2) = 231.2 μA
Saturation is obtained over the range
VDS = 0.34 V to 1.2 V compared to
iD = IS ev GS /n VT
v GS
log(e)
nVT
Thus, the slope of the straight line that represents
log iD versus v GS is
Slope =
0.43
log(e)
=
nVT
nVT
or the inverse of the slope is
= 2.3nVT
Q.E.D.
(b) n = 1.22, iD = 100 × 10−9 A at v GS = 0.21 V
Substituting in Eq. (16.13), we obtain
−3 )
100 × 10−9 = IS e0.21/(1.22×25×10
⇒ IS = 0.1 nA
This is the value of iD at v GS = 0.
(c) Itotal = 500 × 106 × 0.1 × 10−9
= 50 mA
PD = VDD Itotal
= 1.2 × 50 = 60 mW
Exercise 16–2
1
k p(VDD − Vt )2
2
To lower PD to half its value, we must reduce Istat
to half its value. This can be accomplished by
reducing (W/L)p to half the original value, thus
W
= 0.5
L p
Ex: 16.6 Istat =
Since r is to remain unchanged, the value of
(W/L)n must be reduced by a factor of 2, thus
Using Eq. (16.25), we obtain
Istat =
PD = Istat VDD = 86.4 × 10−6 × 2.5 = 0.22 mW
Using Eqs. (16.28) and (16.29), we get
7
0.5
0.5 2
−3
+
= 1.68
αp = 2
4
2.5
2.5
tPLH =
1
(W/L)n = × 2.35 = 1.18
2
Both tPLH and tPHL will double, thus
1
(30) (1.44) (2.5 − 0.5)2 = 86.4 μA
2
1.68 × 7 × 10−15
= 0.11 ns
30 × 10−6 × 1.44 × 2.5
Using Eq. (16.30) and (16.31), we obtain
αn =
tPLH = 2 × 0.16 = 0.32 ns
3
1
1
0.5
0.5 2
2
1+
1−
− 3−
+
4
r
r
2.5
2.5
tPHL = 2 × 0.02 = 0.04 ns
Thus,
= 1.9
1
tP = (0.32 + 0.04) = 0.18 ns
2
Since all the VTC breakpoints are functions of
VDD , Vt , and r only, they will remain unchanged
and so will the noise margins.
tPHL =
1.9 × 7 × 10−15
= 0.03 ns
.375
115 × 10−6 ×
× 2.5
.25
1
1
(tPHL + tPLH ) = (0.11 + 0.03)
2
2
= 0.07 ns
tP =
Ex: 16.7 Using Eq. (16.24), we obtain
1
VOL = (VDD − Vt ) 1 − 1 −
r
1
= (2.5 − 0.5) × 1 − 1 −
4
Substituting values, we get
VOL = 0.27 V
Vt = 0.5 + 0.3
1.8 − Vt + 0.85 −
Using Eq. (16.26) and (16.27), we get
Vt = 0.5 + 0.3
√
2.65 − Vt − 0.3 0.85
NML =
1
1
Vt − (VDD − Vt ) 1 − 1 − − √
r
r (r + 1)
1
1
NML = 0.5 − (2) 1 − 1 − − √
4
4 (5)
= 0.68 V
2
NMH = (VDD − Vt ) 1 − √
3r
2
= 0.85 V
= (2) × 1 − √
3×4
W
0.375
μn Cox
115
L
0.25
=4
n =
r=
W
W
μp Cox
30
L p
L p
W
= 1.44
∴
L p
Ex: 16.8 Vt = Vt0 + γ
VOH + 2φ f −
2φ f
since VOH = VDD − Vt ,
Vt = Vt0 + γ
VDD − Vt + 2φ f −
2φ f
√
0.85
Vt − 0.223 = 0.3 2.65 − Vt
Squaring both sides yields
Vt2 − 0.446Vt + 0.05 = 0.09 (2.65 − Vt )
so that, Vt2 − 0.356Vt − 0.189 = 0
Solving this quadratic equation yields one
practical value for Vt :
Vt = 0.648 V
VOH = VDD − Vt = 1.8 V − 0.648 V
= 1.15 V
Ex: 16.9 (a) Referring to Fig. 16.21, we obtain
VOH = 5 V
VOL = 0 V
Exercise 16–3
(b) Referring to Fig. 16.21(a), we get
1
W
iDN (0) = k n
(VDD − Vt0 )2
2
L n
4
1
= (50)
(5 − 1)2 = 800 μA
2
2
1
W
iDP (0) = k P
(VDD − Vt0 )2
2
L p
4
1
= × 20 ×
(5 − 1)2 = 320 μA
2
2
Capacitor current is
iC (0) = iDN (0) + iDP (0) = 800 + 320
= 1120 μA
To obtain iDN (tPLH ), we note that this situation is
identical to that in Example 16.3 and we can use
the result of part (c):
iDN (tPLH ) = 50 μA
W
×
iDP (tPLH ) = k p
L p
1 VDD 2
VDD
−
(VDD − Vt0 )
2
2
2
1 5 2
5
4
−
= (20)
(5 − 1)
2
2
2 2
= 275 μA
Thus, iC (tPLH ) = 50 + 275 = 325 μA
1
(1120 + 325) = 722.5 μA
2
5
VDD
−15
C
70 10
2
2
=
=
iC |av
722.5 10−6
iC |av =
tPLH
= 0.24 ns
(c) Referring to Fig. 16.21(b), we obtain
1
W
iDN (0) = k n
(VDD − Vt0 )2
2
L n
1
4
= (50)
(5 − 1)2 = 800 μA
2
2
1
W
iDP (0) = k p
(VDD − Vt0 )2
2
L p
1
4
= (20)
(5 − 1)2 = 320 μA
2
2
iC (0) = iDN (0) + iDP (0) = 800 + 320
4
5
1 5 2
= 50
−
(5 − 1)
2
2
2 2
= 688 μA
To find iDP (tPHL ), we first determine Vtp when
VDD
VDD
, which corresponds to VSB =
2
2
VDD
Vtp = Vt0 + γ
+ 2φ f − 2φ f
2
√
5
+ 0.6 − 0.6 = 1.49 V
= 1 + 0.5
2
1
W
VDD 2
Thus, iDP (tPHL ) = k p
− Vtp
2
L p 2
2
1
4
5
= (20)
− 1.49 = 20 μA
2
2
2
vO =
iC (tPHL ) = iDN (tPHL ) + iDP (tPHL )
= 688 + 20 = 708 μA
iC |av =
1120 μA + 708 μA
= 914 μA
2
So,
5
2
= 0.19 ns
=
tPHL =
914 10−6
Qp will turn off when v O = Vtp C
VDD
2
iC |av
70 10−15
where
Vtp = Vt0 + γ
VDD − Vtp + 2φ f −
2φ f
Solving for Vtp , we get
√
Vtp = 1 + 0.5 5 − Vtp + 0.6 − 0.6
Vtp − 0.613 = 0.5 5.6 V − Vtp Squaring both sides, and setting one side equal to
zero, we have the quadratic equation
2
Vtp − 0.976 Vtp − 1.024 V2 = 0
Solving, we get Vtp = 1.6 V
1
1
(tPLH + tPHL ) = (0.24 ns + 0.19 ns)
2
2
0.22 ns
(d) tP =
Ex: 16.10 RTGAV =
RTG1 + RTG2
2
4.5 k + 6.5 k
= 5.5 k
2
= 1120 μA
=
iDN (tPHL ) =
VDD
1 VDD 2
W
−
× (VDD − Vt0 )
kn
L n
2
2
2
tPLH = 0.69 RC = 0.69 (5.5 k) (70) 10−15 F
tPLH = 0.27 ns, which is close to the value of
0.24 ns obtained in Exercise 16.9.
Exercise 16–4
Ex: 16.11
W
L
=
n
W
L
= 1.5
P
12.5
12.5
= 8.3 k
=
1.5
(W/L)n
Ex: 16.12 Using Eq. (15.57), we obtain
RP1 = 1
W
(μn Cox )
(VDD − Vt )2 ,
2
L eq
W
W
will double
and iD (VDD )
doubling
L
L eq
iD (VDD ) =
Using Eq. (16.49), we get
RTG ≈
Ex: 16.14 Since
30
30
k =
k = 15 k
W
(2)
L p
With Eq. (16.49), we see that
12.5
12.5
k = 12.5 k
RTG = k =
W
(1)
L n
Using Eq. (16.51), we get
tP = 0.69 [(Cout1 + CTG1 ) RP1 + (Cin2 + CTG2 )
× (RP1 + RTG )]
= 0.69 [(10fF + 5fF) (15 k) + (10fF + 5fF)
so iD (VDD ) = 2 (76.1 μA) = 152.2 μA
VDD
W
:
will also double iD
This new
L eq
2
VDD
= 2 (68.9 μA) = 137.8 μA
iD
2
This doubles Iav to 2 (72.5 μA) = 145 μA.
The new tPHL is
VDD
C VDD −
2
tPHL =
Iav
30 10−15 F (1.8 V − 0.9 V)
= 0.19 ns
=
145 10−6 A
× (15 k + 12.5 k)]
Ex: 16.15 The process technology parameters are
those specified in Example 16.3 (page 1330).
tP = 0.44 ns
With a ramp input, the factor 0.69 is dropped
resulting in tP = 0.64 ns.
Ex: 16.13
B
B
A
Y = A+B
OR
B
=
Y = AB = A + B
NOR
B
B
W
1
iD1 v y1 = Vt = k n
(VDD − Vt ) Vt − Vt2
L eq1
2
1
= 50 × 1 (5 − 1) 1 − × 1
2
B
= 175 μA
A
Y = AB + AB
XOR
iD1 |av =
400 + 175
= 288 μA
2
(c) iD1 |av t = CL1 v y1
A
A
1
× 50 × 1(5 − 1)2
2
= 400 μA
A
A
Refer to Fig. E16.15
W
1 W
1 4
(a)
=
= × =1
L eq1
2 L
2 2
1 W
1 4
W
=
= × =1
L eq2
2 L
2 2
1
W
(b) iD1 (v Y 1 = VDD ) = k n
(VDD − Vt )2
2
L eq1
Y = AB + AB
XNOR
t =
CL1 (VDD − Vt )
40 × 10−15 × 4
=
iD1 |av
288 × 10−6
= 0.56 ns
Exercise 16–5
(d) Following the hint, we assume that Qeq2
remains saturated during t.
1
W
iD2 |av = iD2 v y1 = 3 V = k n
(3 − 1)2
2
L eq2
1
iD2 |av = × 50 × 1(3 − 1)2
2
= 100 μA
(e) v y2
=−
iD2 |av · t
=−
CL2
100 × 10−6 × 0.56 × 10−9
40 × 10−15
= −1.4 V
Thus, v y2 decreases to 3.6 V.
Ex: 16.18 Refer to Fig. 16.35.
IE =
VR − VBE |QR − (−VEE )
RE
−1.32 − 0.75 + 5.2
≈ 4 mA
0.779
VC |QR = −α × 4 × RC2 ∼
= − 4 × 0.245 = −1 V
=
VC |QA QB = 0 V (because the current through RC1
is zero)
Ex: 16.19 Refer to Fig. 16.38(e).
VDD
= 2.5 V
2
2.5 = VGSN + VBE2
Vth =
= VGSN + 0.7
Ex: 16.16 VOH = 0
VOL = −4 × 0.22 = −0.88 V
SHOULD BE SHIFTED BY −0.88 V
VOH = −0.88 V AFTER SHIFTING
VOL = −1.76 V AFTER SHIFTING
Ex: 16.17 Refer to Fig. E16.17. Neglecting the
base current of Q1 , the current through R1 , D1 ,
D2 , and R2 is
I=
=
5.2 − VD1 − VD2
R1 + R2
5.2 − 0.75 − 0.75
= 0.6285 mA
0.907 + 4.98
Thus, VB = −IR1 = −0.57 V
VR = VB − VBE1 = −0.57 − 0.75 = −1.32 V
⇒ VGSN = 1.8 V
1
W
(VGSN − Vt )2
IDN = k n
2
L n
1 W
= kn
(1.8 − 0.6)2
2
L n
2
1
W
VDD
VDD −
− Vt
IDP = k p
2
L p
2
1
W
= k p
(5 − 2.5 − 0.6)2
2
L p
Equating (1) and (2) gives
W
W
(1.2)2 = k p
(1.9)2
k n
L n
L p
Substituting k n = 2.5k p and Ln = Lp yields
Wp
=1
Wn
(1)
(2)
Chapter 16–1
16.1 Here the scaling factor is
5 μm
= 156.25
32 nm
Therefore, Moore’s law predicts that the number
of transistors on a chip of equal area, fabricated in
the 32-nm process, would be
S=
Power density =
Pdyn
is thus scaled by
area
2
2
=8
=
1
1
S2
4
PDP is scaled by 2 ×
20,000 × S 2 = 20,000 × 156.252
= 4.88 × 108 or 488 million transistors.
αC
, and k is scaled by S, and C
k VDD
1
are scaled by ; thus tP is scaled by
S
16.2 (a) tP ∝
and VDD
1
1
S
=
1
S
S×
S
1
(tP decreases)
2
1
and
The maximum operating speed is
2tp
therefore is scaled by 2.
S = 2 ⇒ tP is scaled by
Pdyn = fmax CV 2 DD and thus is scaled by
1
1
1
1
× 2 = 2 = (Pdyn decreases).
S
S
S
4
Pdyn
and thus is scaled by
Power density =
area
1
S 2 = 1, i.e., remains unchanged.
1
S2
1
1
PDP is scaled by 3 power is scaled by 2 and
S
S
1
1
delay by
and thus it is scaled by (PDP
S
8
decreases).
S×
(b) If VDD and Vtn remain unchanged while
S = 2, we have
tp =
αC
2
and α =
so α
k VDD
Vtn 2
7 3Vtn
−
+
4
VDD
VDD
remains unchanged and tP is scaled by
1
S = 1 = 1
S
S2
4
1
and
The maximum operating speed is
2tP
therefore is scaled by 4.
Pdyn = fmax CV 2 DD and thus is scaled by
4×
1
×1=2
2
1
1
=
4
2
16.3 From Eq. (16.5), we have for the NMOS
transistor
0.25 =
65 × 10−9
× 105
μn
where we have assumed νsat = 107 cm/s = 105
m/s. Thus,
μn = 260 cm2 /V.s
For the PMOS transistor
0.45 =
65 × 10−9
× 105
μp
⇒ μp = 144.4 cm2 /V.s
The value of Ecr can be determined using
Eq. (16.3),
VDSsat
L
For the NMOS transistor we have
0.25
= 3.85 × 106 V/m
Ecr =
65 × 10−9
Ecr =
= 3.85 × 104 V/cm
and for the PMOS transistor
0.45
= 6.92 × 104 V/cm
Ecr =
65 × 10−9
16.4 (a) From equation (16.9), we have
W
1
VDSsat VGS − Vt − VDSsat
IDsat = μn Cox
L
2
Thus, for VGS = VDD we have
1
W
VDSsat VDD − Vt − VDSsat
IDsat = μn Cox
L
2
In the absence of velocity saturation, we have
1
W
ID = μn Cox
(VGS − Vt )2 ; and for
2
L
1
W
VGS = VDD , ID = μn Cox
(VDD − Vt )2
2
L
Therefore,
IDsat
ID
μn Cox
=
1
W
VDSsat VDD − Vt − VDSsat
L
2
W
1
μ Cox
(VDD − Vt )2
2 n
L
Chapter 16–2
1
2VDSsat VDD − Vt − VDSsat
2
=
(VDD − Vt )2
(b) Using Eqs. (14.45) and (14.56), we obtain
Q.E.D.
(b) For this 65-nm process, we have
1
2 × 0.25 1.0 − 0.35 − × 0.25
IDsat
2
=
ID
(1.0 − 0.35)2
tPHL = 0.69C
12.5 × 103
(W/L)n
Q.E.D.
(c) Equating the values of tPHL given by Eqs. (1)
and (2), we obtain
12.5 × 103
CVDD
= 0.69C
2IDsat
(W/L)n
= 0.62
⇒ IDsat = 0.058 × 10−3 VDD (W/L)n
16.5 (a) From Eq. (16.9), we have
Substituting VDD = 1.2 V, we get
IDSsatn = W
1
μn Cox
VDSsatn VGS − Vtn − VDSsatn
L n
2
IDsat = 0.07 × 10−3 (W/L)n
IDSsatp =
W 1 μp Cox
VDSsatp |VGS | − Vtp −
VDSsatp L p
2
Since |VGS | = VDD (i.e., for NMOS)
VGS = VDD and for PMOS |VGS | = VDD and
IDSsatn = IDSsatp , we have
W
1
VDSsatn VDD − Vtn − VDSsatn
μn Cox
L n
2
μp Cox
W
L
VDSsatp VDD − Vtp − 1 VDSsatp 2
p
(4)
Substituting μn Cox = 325 × 10−6 A/V,
VGS = VDD = 1.2 V, and Vt = 0.4 V and
equating the resulting value of IDsat to that given
by Eq. (3), we obtain
W
1
VDSsat 1.2 − 0.4 − VDSsat
325 × 10−6
L
2
⇒ VDSsat = 0.34 V
16.7 IS ∝ e−Vt /nVT
1
VDD − Vtn − VDSsatn
Wp
μ VDSsatn
2
= n
1
Wn
μp VDSsatp VDD − Vtp − VDSsatp 2
1
VDD − Vtn − VDSsatn
Wp
μn VDSsatn
2
(b)
=
1
Wn
μp VDSsatp VDD − Vtp − VDSsatp
2
0.25
1.0 − 0.35 −
0.25
2
= 2.75
=4×
0.45
0.45
1.0 − 0.35 −
2
IS ∝ e−(Vt −0.1)/nVT
∝ e−Vt /nVT e0.1/nVT
Thus IS increases by a factor
= e0.1/nVT
= e0.1/(2×0.025)
Thus the static power dissipation increases by a
factor of 7.4.
If Vt is reduced by 0.2 V, a similar analysis to that
above shows that IS increases by a factor
= e0.2/(2×0.025) = e4 = 54.6
and the static power dissipation increases by the
same factor.
IDsat tPHL = C(VDD /2)
which yields
Q.E.D.
If Vt is reduced by 0.1 V, then
= e2 = 7.4
16.6 (a) Since QN provides a constant current
IDsat to discharge C from a voltage of VDD to
VDD /2, the discharge interval tPHL can be found
by writing the charge equilibrium equation
CVDD
2IDsat
IDsat = W
1
μn Cox
VDSsat VGS − Vt − VDSsat
L
2
= 0.07 × 10−3 (W/L)
Ln = Lp ⇒ Thus,
tPHL =
(3)
But IDsat is given by Eq. (16.9) as
and
=
(2)
(1)
We conclude that in process design, the higher the
value one chooses for Vt , the lower the static
power dissipation.
Chapter 16–3
16.8 (a) iD = IS e−v GS /nVT
Corresponding to iD changing by a factor of 10,
v GS changes by 2.3nVT , thus
2.3nVT = 80 mV
80
= 1.4
2.3 × 25
Using the given information that iD = 20 nA at
v GS = 0.16 V, we obtain
⇒n=
−9
20 × 10
= IS e
0.16/(1.4×0.025)
⇒ IS = 207 pA
This is the value of iD at v GS = 0
(b) For a chip with 1 billion transistors, the
current drawn from the power supply as a result
of subthreshold conduction will be
Itotal = 207 × 10−12 × 109
16.10 (a) R = 27 m ×
= 27 × 10−3 ×
5 mm
0.5 μm
5 × 10−3
0.5 × 10−6
= 270 (b) C = 0.1 ×
5 mm
1 μm
= 0.1 × 5 × 103 = 500 fF
= 0.5 pF
(c) tdelay = 0.69RC
= 0.69 × 270 × 0.5 × 10−12
= 93.2 ps
= 207 mA
16.11 (a) For the circuit in Fig. P16.11(a),
assuming v O (0−) = 0, we can write
and the power dissipation will be
v O (t) = VDD − VDD e−t/τ
PD = Itotal VDD
where
= 207 × 1 = 207 mW
τ = CR
Substituting, we obtain
1
16.9 ID = k n (VGS − Vtn )2
2
1
0.2 = × 0.4(VGS − 0.4)2
2
⇒ VGS = 1.4V
(a) For Vtn = 0.4 + 10% = 0.44 V, we have
1
× 0.4(1.4 − 0.44)2 = 0.184 mA
2
For Vtn = 0.4 − 10% = 0.36 V, we have
ID =
1
× 0.4(1.4 − 0.36)2
2
= 0.216 mA
ID =
v O (tPLH ) =
1
VDD = VDD − VDD e−tPLH /τ
2
⇒ tPLH = 0.69τ = 0.69CR
I tPLH = C(VDD /2)
⇒ tPLH =
(b) If the time for a 0.1-V change of the capacitor
voltage is denoted T , then
thus,
ID T = CV
tPLH =
For ID = 0.184 mA, we have
100 × 10−15 × 0.1
= 54.3 ps
T=
0.184 × 10−3
For ID = 0.216 mA, we have
100 × 10−15 × 0.1
= 46.3 ps
T=
0.216 × 10−3
Thus, the discharge time ranges from 46.3 ps to
54.3 ps.
1 VDD
C
2
I
But,
I=
CV
ID
(1)
(b) For the circuit in Fig. P16.11(b), assuming
v O (t−) = 0, we can write
Thus, ID will range from 0.184 mA to 0.216 mA
(i.e., 0.2 ± 8%, mA).
T=
1
VDD
2
VDD
R
VDD
1
C
= 0.5CR
2 VDD /R
(2)
Comparing Eqs. (1) and (2), we see that using a
current-source load reduces tPLH by
0.69 − 0.5
× 100 = 27.5%
0.69
16.12 VOH = VDD = 1.3 V
Using Eq. (16.24), we find
VOL = (VDD − Vt ) 1 −
1−
1
r
Chapter 16–4
1
5
= 0.095 V
16.14 Using Eqs. (16.29) and (16.28), we find
0.4
0.4 2
7
αp = 2
−3×
+
4
1.3
1.3
Using Eq. (16.25), we obtain
= 2.17
1
k p (VDD − Vt )2
2
tPLH =
= (1.3 − 0.4) 1 −
Istat =
1−
1
= × 100(1.3 − 0.4)2
2
= 40.5 μA
αp C
k p VDD
2.17 × 10 × 10−15
100 × 10−6 × 1.3
= 167 ps
=
Using Eqs. (16.31) and (16.30), we obtain
PD = Istat VDD
= 40.5 × 1.3 = 52.7 μW
αn =
1+
2
3
1
1
0.4
0.4 2
1−
− 3−
+
4
5
5
1.3
1.3
= 2.4
16.13 Using Eq. (16.24), we obtain
1
VOL = (VDD − Vt ) 1 − 1 −
r
1
= (1.3 − 0.4) 1 − 1 −
5
2.4 × 10 × 10−15
500 × 10−6 × 1.3
= 36.9 ps
= 0.095 V
tP =
Using Eq. (16.20), we obtain
=
VDD − Vt
VIL = Vt + √
r(r + 1)
1.3 − 0.4
= 0.4 + √
5×6
tPHL =
αn C
k n VDD
=
1
(tPLH + tPHL )
2
1
(167 + 36.9) = 102 ps
2
16.15
= 0.56 V
Using Eq. (16.21), we obtain
VDD − Vt
VM = Vt + √
r+1
= 0.4 +
1.3 − 0.4
√
6
= 0.77 V
Using Eq. (16.23), we find
VIH
2
= Vt + √ (VDD − Vt )
3r
= 0.4 + √
2
3×5
(1.3 − 0.4)
= 0.86 V
VOH = VDD = 1.3 V
NML = VIL − VOL
= 0.56 − 0.095 = 0.465 V
NMH = VOH − VIH
= 1.3 − 0.86 = 0.44 V
Figure 1
VDD
= 0.625 V
4
Figure 1 shows the inverter when
v O = VDD /4 = 0.625 V. At this output value, if
QN is off, QP will be operating in the triode
region (because v DG = 0.625 V is greater than
|Vt | = 0.5 V) and charging the capacitor with a
current
W
[(VDD − |Vt |)(VDD − v O )
iDP = k p
L p
1
− (VDD − v O )2 ]
2
Chapter 16–5
W
(2.5 − 0.5)(2.5 − 0.625)
= 30
L p
1
− (2.5 − 0.625)2
2
= 59.8(W/L)p , μA
When v I is high at 2.5 V, QN will be operating in
the triode region (because v I > Vtn + v O ) and
will be conducting a current
W
1
iDN = k n
(v I − Vt )v O − v 2O
L n
2
1
2
= 115 × 1.5 (2.5 − 0.5) × 0.625 − × 0.625
2
= 181.9 μA
The capacitor discharge current will be
= iDN − iDP
= 181.9 − 59.8(W/L)p , μA
The design is based on equal charging and
discharging current, thus
59.8(W/L)p = 181.9 − 59.8(W/L)p
= (2.5 − 0.5) 1 −
1−
1
3.78
= 0.28 V
Now,
NMH = VOH − VIH
= 2.5 − 1.69 = 0.81 V
NML = VIL − VOL
= 0.97 − 0.28 = 0.69 V
16.16 From Eq. (16.27), we obtain
2
NMH = (VDD − Vt ) 1 − √
3r
Setting NMH = 0, we have
2
1− √
=0
3r
Solving, r = 1.33
⇒ (W/L)p = 1.52
Using Eqs. (16.27) and (16.26),we can find NMH
and NM L , respectively, versus r:
We now can find the value of r from
k (W/L)n
kn
= n
r=
kp
k p (W/L)p
with VDD = 1.3 V and Vt = 0.4 V,
2
NMH = (VDD − Vt ) 1 − √
3r
115 × 1.5
= 3.78
30 × 1.52
Using Eq. (16.20), we obtain
VDD − Vt
VIL = Vt + √
r(r + 1)
2.5 − 0.5
VIL = 0.5 + √
3.78 × 4.78
= 0.97 V
1.8
2
= 0.9 − √
, (V)
NMH = (1.3 − 0.4) 1 − √
3r
3r
=
NML = Vt − (VDD − Vt )
1
1
× 1− 1− − √
r
r (r + 1)
NML = 0.4 − 0.9 1 −
Using Eq. (16.23), we obtain
2
VIH = Vt + √ (VDD − Vt )
3r
2
= 0.5 + √
(2.5 − 0.5)
3 × 3.78
= 1.69 V
Using Eq. (16.21), we obtain
VDD − Vt
VM = Vt + √
r+1
2.5 − 0.5
= 0.5 + √
3.78 + 1
= 1.41 V
1−
Table 1 below gives NMH and NML for r ranging
from 2 to 10. Observe that equal values of NML
Table 1
r
NMH (V) NML (V)
2
0.17
0.50
3
0.30
0.49
4
0.38
0.48
5
0.44
0.47
6
0.48
0.46
VOH = VDD = 2.5 V
7
0.51
0.45
Using Eq. (16.24), we obtain
8
0.53
0.45
9
0.55
0.44
10
0.57
0.44
Using Eq. (16.18), we have
VOL = (VDD − Vt ) 1 −
1−
1
r
1
1
−√
, (V)
r
r (r + 1)
Chapter 16–6
and NMH can be obtained by selecting r between
5 and 6. To obtain a more precise value for r, we
iterate to obtain the results shown in Table 2.
From the latter table we see that the r value lies
between 5.6 and 5.7.
1
1
1−
r
=
r
(2r + 1)2
(r + 1)3
r(2r + 1)2
r
=
r−1
(r + 1)3
Table 2
r
Multiplying both sides by r 4 :
NMH (V) NML (V)
(r + 1)3
= (2r + 1)2
r−1
5.5
0.457
0.465
Multiplying out:
5.6
0.461
0.464
r 3 + 2r 2 + r + r 2 + 2r + 1 = 4r 3 − 3r − 1
5.7
0.465
0.463
Simplifying, we get
r 3 − r 2 − 2r − 2/3 = 0
We can further iterate; however, it seems likely
that a good estimate would be
r = 5.65
Solving for the roots of this cubic equation can be
done with a calculator or by hand. With these
coefficients, there is only one real root:
r = 2.1 (by hand)
For this value,
If VDD = 1.3 V and Vt = 0.4 V,
NMH = 0.463 V
NML = 0.4 V − (1.3 V − 0.4 V) ×
1
1
−√
1− 1−
2.1
2.1 (3.1)
and
NML = 0.463 V
NML = 0.5 V
16.17 From Eq. (16.26), we get
For r = 2.0, we obtain NML = 0.5 V
NML = Vt − (VDD − Vt )
1
1
× 1− 1− − √
r
r (r + 1)
For r = 5.0, we have NML = 0.47 V
∂ML
= − (VDD − Vt )
∂r
1 −1/2 1
1
1
1−
× −
−
−
2
r
r2
2
× (r (r + 1))−3/2 (2r + 1)
Maximum NML is found by setting this equal
to zero:
1 −1/2 1
1
1
0=− 1−
+
2
2
r
r2
−3/2
× (r (r + 1))
(2r + 1)
−1/2 1
1
1−
= (r (r + 1))−3/2 (2r + 1)
r
r2
Squaring both sides, we get
1 −1
1−
r
= r −3 (r + 1)−3 (2r + 1)2
r4
For r = 10, we have NML = 0.44 V
We thus conclude that the maximum is a very
broad one and that NML does not change greatly
with r.
16.18 Substituting VDD = 1.3 V, Vt = 0.4 V, and
r = 5.7 in Eqs. (16.26) and (16.27), we obtain:
NML =
Vt − (VDD − Vt ) 1 −
= 0.4 − (1.3 − 0.4) 1 −
= 0.463 V
1−
1
1
−√
r
r(r + 1)
1−
1
1
−√
5.7
5.7 × 6.7
2
NMH = (VDD − Vt ) 1 − √
3r
2
= (1.3 − 0.4) 1 − √
3 × 5.7
= 0.465 V
Thus,
NML NMH
Q.E.D.
Chapter 16–7
tPHL =
Since
r=
kn
=
kp
k n (W/L)n
k p (W/L)p
tP =
then
1
(1.34 + 0.26) = 0.8 ns
2
2
Pdyn = fCVDD
4(W/L)n
5.7 =
(W/L)p
⇒
tPLH
= 0.26 ns
5.22
= f × 100 × 10−15 × 1.32 = 169f fW
(W/L)n
5.7
= 1.425
=
(W/L)p
4
Selecting
The frequency at which Pdyn = Pstat is found from
169f × 10−15 = 65.8 × 10−6
⇒ f = 389 MHz
(W/L)p = 1
The theoretical maximum frequency of operation
is found as follows:
1
fmax =
2tP
we have
(W/L)n = 1.425
Using Eq. (16.25), we find
1
Istat = k p (VDD − Vt )2
2
1
= × 125 × 1(1.3 − 0.4)2
2
= 50.6 μA
=
1
= 625 MHz
2 × 0.8 × 10−9
Thus, it is possible to operate the inverter at
389 MHz.
16.19 Y = A + B (C + D),
The static power dissipation is
whence Y = A + B (C + D)
PD = Istat VDD
Thus the PDN can be formed directly as shown:
= 50.6 × 1.3 = 65.8 μW
Using Eq. (16.29), we obtain
7
|Vt |
|Vt | 2
−3
+
αp = 2
4
VDD
VDD
2
0.4
0.4
7
−3×
+
=2
4
1.3
1.3
= 2.17
Using Eq. (16.31), we find
1
3
1−
1+
αn = 2
4
5.7
0.4
0.4 2
1
+
− 3−
5.7
1.3
1.3
or Y = A B + AB
= 2.37
The PDN results directly:
16.20 For an Exclusive OR, Y = AB + AB, and
Y = AB + AB = AB · AB = A + B A + B
VDD
Now using Eqs. (16.28) and (16.30), we obtain
αp
kn
tPLH
=
tPHL
αn
kp
2.17
× 5.7 = 5.22
2.37
Using Eq. (16.28), we obtain
Y
=
tPLH
=
αp C
=
k p VDD
−15
2.17 × 100 × 10
= 1.34 ns
125 × 10−6 × 1 × 1.3
A
A
B
B
Chapter 16–8
16.21 For a NOR gate similar to that of
Fig. 16.13, the worst-case VOL will occur when
only one input is high and one NMOS transistor is
conducting. From Eq. (16.24), we obtain
1
VOL = (VDD − Vt ) 1 − 1 −
r
1
0.1 = (1.3 − 0.4) 1 − 1 −
r
0.1
1
⇒ 1− =1−
r
0.9
Transistor QN will be operating in the triode
region and conducting an equal current, thus
1 2
36 = k n (VGS − Vt )VDS − VDS
2
1 2
36 = 500 (1.3 − 0.4)VOL − VOL
2
⇒ r = 4.76
⇒ VOL = 0.08 V
Since
which is indeed very small, as assumed.
k n (W/L)n
k p (W/L)p
kn
4 × 1.5
=
=
kp
(W/L)p
W
6
then
=
= 1.26
L p
4.76
r=
1 2
0.072 = 0.9VOL − VOL
2
If VOL is very small, then we have
0.072 0.9VOL
16.23
16.22
VDD 1.3 V
QP
IDsat
vI VDD 1.3 V
VOL
QN
Figure 1
Figure 1
Refer to Fig. 1. For transistor QP , we have
Refer to Fig. 1.
|VSG | − |Vt | = 1.3 − 0.4 = 0.9 V
(a) VO = 0 V
which is greater than VDSsat = 0.6 V. Also, since
we expect VOL to be very small, we have
(b) VO = 0 V
VSD > |VDSsat |
Thus QP will be operating in the velocity
saturation region and its current IDsat will be given
by Eq. (16.9) (adapted for the p-channel case),
IDsat = 1
W
μp Cox
|VDSsat | |VSG | − |Vt | − |VDSsat |
L p
2
1
= 100 × 0.6 1.3 − 0.4 − × 0.6
2
= 36 μA
(c) VO = VDD − Vtn
where
Vtn = Vtn0 + γ
VO + 2φf − 2φf
(d) VO = |Vtp |
= |Vtp0 | + γ
VDD − VO + 2φf − 2φf
16.24 Refer to Fig. 16.17. Since VOH is the value
of v O at which Q stops conducting,
VDD − VOH − Vt = 0
Chapter 16–9
At t = tPHL , Q will be operating in the triode
region, and thus
then
VOH = VDD − Vt
where
Vt = Vt0 + γ VOH + 2φf − 2φf
= Vt0 + γ VDD − Vt + 2φf − 2φf
iD (t = tPHL ) =
1
500 × 1.5 (1.2 − 0.4) × 0.6 − × 0.62
2
= 225 μA
Substituting Vt0 = 0.4 V, γ = 0.2 V1/2 ,
VDD = 1.2 V, and 2φf = 0.88 V, we obtain
√
Vt = 0.4 + 0.2 1.2 − Vt + 0.88 − 0.88
√
Vt − 0.4 + 0.2 0.88 = 0.2 2.08 − Vt
Thus, the average discharge current is given by
(Vt − 0.212)2 = 0.04(2.08 − Vt )
tPHL =
⇒ Vt2 − 0.384 Vt − 0.038 = 0
⇒ Vt = 0.466 V
1
(240 + 225) = 232.5 μA
2
iD |av =
and tPHL can be determined as
=
C(VDD /2)
iD |av
10 × 10−15 × 0.6
= 25.8 ps
232.5 × 10−6
VOH = 1.3 − 0.466
= 0.834 V
16.27
1.8 V
16.25 Refer to Fig. 16.17.
We need to find the current iD at t = 0 (where
v O = 0, Vt = Vt0 = 0.4 V) and at t = tPLH (where
VDD
vO =
= 0.6 V, Vt to be determined), as
2
follows:
1
iD (0) = × 500 × 1.5 (1.2 − 0.4)2 = 240 μA
2
Vt (at v O = 0.6 V) =
√
√
0.6 + 0.88 − 0.88
0.4 + 0.2
QP
1.15 V
Figure 1
1
× 500 × 1.5 (1.2 − 0.456 − 0.6)2
2
= 7.8 μA
We can now compute the average charging
current as
240 + 7.8
iD |av =
= 123.9 μA
2
and tPLH can be found as
tPLH =
=
VOL
QN
= 0.456 V
iD (tPLH ) =
iD
C(VDD /2)
iD |av
10 × 10−15 × 0.6
= 48.4 ps
123.9 × 10−6
16.26 Refer to the circuit in Fig. 16.18. Observe
that, here, Vt remains constant at Vt0 = 0.4 V. At
t = 0, Q will be operating in saturation, and the
drain current will be
1
iD (0) = × 500 × 1.5 (1.2 − 0.4)2
2
= 240 μA
From Exercise 16.8 we have the output voltage of
the switch as 1.15 V. This is the voltage applied to
the input of the CMOS inverter, as shown in
Fig. 1. Because we expect VOL to be small, QP
will be operating in the saturation region and its
drain current will be
1
W
iD = (μp Cox )
(1.8 − 1.15 − 0.4)2
2
L p
=
0.54
1
× 75 ×
× 0.0625
2
0.18
= 7 μA
This is also the current conducted by QN which is
operating in the triode region, thus
W
1 2
7 = (μn Cox )
(1.15 − 0.4)VOL − VOL
L n
2
Assuming VOL to be very small, we obtain
W
× 0.75VOL
7 (μn Cox )
L n
Chapter 16–10
7 = 300 ×
1 0.54
×
× 0.75 VOL
2 0.18
⇒ VOL = 0.02 V
The static power dissipation is
PD = 7 μA × 1.8 V
At t = tPLH , v O = VDD /2 = 0.6 V and Q will be
operating in the triode region. Thus,
iD (tPLH ) =
k p (VDD − |Vt0 |)
VDD
2
−
1 VDD 2
2
2
1
= 125 (1.2 − 0.4) × 0.6 − (0.6)2
2
= 12.6 μW
= 37.5 μA
16.28
The average charging current can now be found as
iD |av =
1
(40 + 37.5) = 33.75 μA
2
The propagation delay tPLH can then be
determined from
tPLH =
Figure 1
=
C(VDD /2)
iD |av
C × 0.6
= 17.8 × 103 C s
33.75 × 10−6
No value for C is given. If C = 10 fF, we get
(a) Figure 1(a) shows the situation for t ≥ 0. In
this case Vt remains constant at Vt0 and the
capacitor charges to VDD .
tPLH = 17.8 × 103 × 10 × 10−15 = 178 ps
Thus,
16.29 For the switch gate and input both at
VDD = 3.3V, the switch output is
VOH = VDD
VOH = VDD − Vt
(b) Figure 1 (b) shows the situation for t ≥ 0.
Here as C discharges through Q, the threshold
voltage changes. The discharge current reduces to
zero when v O = |Vt |. Thus,
where Vt = Vt0 + γ
VOL = |Vt |
|Vt | = |Vt0 | + γ
VDD − VOL + 2φf − 2φf
Substituting |Vt | = VOL , we obtain
VOL = |Vt0 | + γ
VDD − VOL + 2φf − 2φf
VOH + 2φ f −
2φ f
Substituting for VOH , we get
VDD − Vt + 2φ f − 2φ f
Vt = Vt0 + γ
= 0.8 + 0.5
where
√ 3.3 − Vt + 0.6 − 0.6
so that
Vt = 0.413 + 0.5 3.9 − Vt
Vt − 0.413 = 0.5 3.9 − Vt
Squaring both sides, we get
(c) Refer to Fig. 1(a).
Vt2 − 0.826Vt + 0.171 = 0.975 − 0.25Vt
At t = 0, v O = 0 and Q will be operating in
saturation. Thus,
or Vt2 − 0.576Vt − 0.804 = 0
Solving this quadratic, we find that
1
iD (0) = k p (VDD − |Vt0 |)2
2
=
1
× 125 (1.2 − 0.4)2
2
= 40 μA
Vt = 1.23 V
VOH = VDD − Vt = 3.3 V − 1.23 V = 2.07 V
With the input low and the switch gate high,
VOL → 0 V
Chapter 16–11
If VOH = 2.07 V, the PMOS transistor of the
inverter is in the saturation region. Since the
inverter transistors are matched, we get
W
k W
= n
so that
L p
kp L n
1
W
iDP = μp Cox
(VDD − VOH − Vt0 )2
2
L p
iDP =
1
1.2
(25)
(3) × (3.3 − 2.07 − 0.8)2
2
0.8
1
(352 + 311) = 332 μA
2
VDD
C
100 10−15 (1.65)
2
=
=
iD |av
332 × 10−6
iD |av =
tPHL
= 0.5 ns
16.30
VDD
= 10.4 μA
For tPLH , at t = 0, we have
1
W
iD (0) = μn Cox
(VDD − Vt0 )2
2
L n
1.2
1
= (75)
(3.3 − 0.8)2 = 352 μA
2
0.8
VDD
At v O =
, we have
2