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Design of Analog Integrated
Systems (ECE 615)
Lecture 4
Nyquist Rate Digital-to-Analog
Converters
Ayman H. Ismail
Integrated Circuits Laboratory
Ain Shams University
Cairo, Egypt
ayman.hassan@eng.asu.edu.eg
ECE615 – Lecture 4
Outline
• Monotonicity
• DAC types and architectures
• Resistor based architectures
– Resistor String DAC
– Resistor String DAC with Digital Decoder
– Resistor-String DAC Including Interpolation
– Folded Resistor String DAC
• Capacitor based architectures
– Charge scaling DAC
– Charge scaling DAC with Split Array
– Charge-Redistribution Switched-Capacitor DAC
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Outline
• Current source Based architectures
– Thermometer current source DAC
– current source DAC binary weighted
– Segmented current source DAC
• Segmented/Hybrid DAC
• Components Mismatch
– current sources
– Resistors and capacitors
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Outline
• DAC design
– Static DAC Errors (INL/DNL)
• Thermometer
• Binary weighted
• Segmented
– Dynamic errors
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Monotonicity
• Recall from first lecture:– A monotonic DAC converter is one in which the output
always increases as the input increases. In other words, the
slope of the DAC transfer response is of only one sign.
– If the maximum DNL error is less than 1 LSB, then a D/A
converter is guaranteed to be monotonic..Similarly, a
converter is guaranteed to be monotonic if the maximum INL
is less than 0.5 LSB .
– The equivalent term for ADC converters is missing codes.
An A/D converter is guaranteed not to have any missing
codes if the maximum DNL error is less than 1 LSB or if the
maximum INL error is less than 0.5 LSB.
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DAC Types and Architectures
• DACs are composed of current, voltage, and/or charge based
elements. Examples for these DACs categories are:
– Current source based
– Resistor string
– Charge scaling
, respectively
• Architectures
– Thermometer (unit element)
– Binary weighted
– Segmented
• In general each of the different DAC categories can be
implemented as thermometer, binary or segmented.
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Resistor String DAC
• 2N Rs generate 2N equally
spaced voltage values
• Inherently monotonic
• Disadvantages:
– 2N resistors & ~2.2N
switches
– High settling time, τmax=
0.25 x 2NR.C (Speed
power trade-off).
• Actually settling time may
be much higher due to
switches delay.
• Use digital decoding, 2N
transistor junctions at buffer
input, though.
Ayman H. Ismail
Unit element
3-bit DAC
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Resistor String DAC with Digital
Decoder
• 2N Rs generate 2N equally
spaced voltage values
• Inherently monotonic
• Disadvantages:
– 2N resistors & ~2.2N
switches
– High settling time, τmax=
0.25 x 2NR.C (Speed
power trade-off).
• Actually settling time may
be much higher due to
switches delay.
• Use digital decoding, 2N
transistor junctions at buffer
input, though.
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Unit element
3-bit DAC with digital decoder
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Resistor-String DAC Including
Interpolation
Unit element
• Buffers may limit performance:
– Random offset
– Speed
• 2.2N/2 resistors. Suitable for high
resolutions
• Since the second resistor string
is used to decode only the
lower-order bits, the matching
requirements of the second
resistor string are relaxed (more
about matching requirements
later)
• The first resistor string must be
accurate to N-bits.
6-bit DAC
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Folded Resistor String DAC
Unit element
• folded resistor-string D/A
reduces the amount of
digital decoding and large
capacitive loading.
• Total number of transistor
junctions at buffer input
2√2N.
• Still 2N resistors are
needed.
4-bit DAC
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Charge Scaling DAC
B-bit DAC
Binary
Weighted
• In reset phase all cap’s are discharged.
• In evaluation phase, depending on the digital
word, the caps either remain connected to
ground or are connected to Vref, and DAC
operates as a capacitor divider.
• DAC output sensitive to parasitics
• Monotonicity depends on element matching (as
explained later)
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Charge Scaling DAC
B-bit DAC
Binary
Weighted
•
OTA helps eliminate the parasitic capacitor
effect (parasitic cap at virtual ground).
• Total cap = 2BC
• OTA issues
– Offset/ flicker noise
– Speed
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Charge Scaling DAC with Split
Array
6-bit DAC
Binary
Weighted
• Total cap (2.2n/2-1) C, instead of 2nC
• For 6 bits 15C, instead of 64C, area saving
• OTA Common mode has to extend to all
values of VDAC out
• Sensitive to parasitic cap
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Charge-Redistribution SwitchedCapacitor DAC
4-bit DAC
Binary
Weighted
• Offset/ flicker noise insensitive
• Similar to capacitive reset switched-capacitor amplifier
presented earlier, but with programmable gain (switched cap.
Circuits – lecture 2)
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Thermometer Current Source DAC
B-bit DAC
Unit
Element
• Monotonicity does not depend on element matching
• 2B-1 current sources & switches
• Need large encoder with 2B-1 outputs. Therefore, impractical for
large B (high resolution)
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Current Source DAC
Binary Weighted
B-bit DAC
Binary weighted
• Monotonicity depends on element matching
• B current sources & switches . However, 2B-1 unit elements as
for unit element implementation.
• No encoder needed
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Segmented DAC 1
• B-bits DAC
• B= Bt + Bb
• MSB bits (Bt) are
implemented using unit
elements (thermometer).
Therefore, guaranteed
monotonicity.
• LSB implemented using
binary weighted
elements. Monotonicity
depends matching.
However, matching
requirements are relaxed
in this case (as
discussed later)
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Segmented DAC 2
• Segmented/Hyprid
(different types used)
• Example: 12bit DAC
• 6-bit MSB DAC using R
string
• 6-bit LSB DAC using
binary weighted charge
redistribution
• Segmented results in
Complexity much lower
than full R string
• Full R string4096
resistors
• Segmented 64 R + 7 Cs
(64 unit caps)
• Why use hyprid?
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Sub-DAC (6bit accurate)
Main DAC
(12-bit Accurate)
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Components Mismatch
• Systematic errors
– routing
– Contact resistance
– Edge effects in capacitor arrays
– Process gradient
– Finite current source output resistance
• Random errors
– Often Gaussian distribution (central limit theorem)
• Systematic error should be minimized/ eliminated in the
design phase. In this case, the circuit is limited by
“random” errors.
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Random Mismatch in Current
Mirror
• Mismatch in current mirrors can be described as
• Offset voltage/current is function in σ∆Vth and σ ∆β/ β, which
are given by
where Avth and Aβ are technology dependent constants, W and L
are the device dimensions
• Hence, the larger the area of the device, the smaller the random
error. The same applies to resistors and capacitors.
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Random Mismatch in R and C
• For resistors
R1
R2
• Similarly for capacitor
• Note that mismatch defines the value of unit cap, but does not
define the value of resistor
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The Gaussian Distribution
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Yield
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Yield
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Thermometer DAC Static Errors
(DNL)
• The LSB can be expressed as
• DNL can be expressed as
• Therefore
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Thermometer DAC Static Errors
(INL)
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Thermometer DAC Static Errors
(INL)
• Max error
•
Therefore
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Binary Weighted DAC Static
Errors (INL and DNL)
• INL same as for the thermometer DAC case
• DNL depends on transition
• Worst case at mid-scale
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Segmented DAC Static Errors (INL
and DNL)
• INL same as for the thermometer
DAC case
• DNL depends on transition
• Worst case occurs when LSB DAC
turns off and one more MSB DAC
element turns on
• Same DNL as a binary weighted
DAC with Bb+1 bits
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Unit Element, Binary Weighted
and Segmented Comparison
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For 12-bit DAC
• For B=12, σu=1%
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Example 1
• Assume a thermometer 6-bit DAC with σu = 1% and it is
required to have 99.73% of all converters to meet the spec.
What is the DNL spec that can be set?
• For 99.73% yield, need X = 3
• σDNL = σu = 1%
• DNL=3 σDNL = 3%
• DNL specification for a yield of 99.73% is ±0.03 LSB
• However, a converter will meet specs only if all codes meet DNL
spec, i.e. DNL(i) < DNLspec for all i
• A converter with more codes is less likely to have all codes meet
the specification
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Example 1
• Assuming that all DNL(i) values are independent, then
•
•
•
•
P(all codes meet spec) = P(single code meets spec)N
P(all codes meet spec)1/N = P(single code meets spec)
N=63 (6 bits)
P(single code meets spec) =0.99731/63 = 0.99995708
• Therefore for all codes to meet the spec with probability of
99.73%. Each code, must meet the spec with prob. 0.99731/63.
• X = sqrt(2)*erfinv(0.99731/63) = 4.09
• Refined result. For 99.73% yield, DNL spec should be ±0.0409
LSB
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Example 2
• It is required to design an 8-bit a binary weighted charge
scaling capacitive DAC. Assume capacitance matching
coefficient of 1%.μm.
(Note : If INL and DNL are not specified, assume target
specifications INL=DNL=±0.5 LSB with 99.73% yield)
•
•
•
•
•
For 99.73% yield
INL= 3σINL
Therefore, σINL = 0.5/3= 0.167 LSB
Similarly, σDNL = 0.5/3= 0.167 LSB
For binary weighted
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Example 2
• From DNL spec
σu= 0.167 /16 = 0.0625 =1.04%
• From INL spec
σu=2x 0.167/16 =2.08%
•
•
•
•
•
σu is limited by DNL
σu=Ac/√Area, Ac= 1 %.μm.
Cu area = (1/6.25)2 μm2= 0.924μm2
Assuming capacitance density= 20fF/ μm2
Cu = 18.5fF. Is this value OK? In general, what can be done if you get
a very small Cu?
• Total Capacitance= 28 x 18.5= 4736fF
• Note that having a non zero INL and DNL results in an SNDR
lower than the ideal value predicted by 6.02+1.76 dB expression
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Example 3
• It is required to design a 4-bit a binary weighted charge scaling
capacitive DAC with 8-bits of accuracy. Assume capacitance
matching coefficient of 1%.μm. An example of such DAC is a
DAC used as the Main DAC of a segmented 8-bit DAC. Note
that the sub DAC needs to be accurate to the 4-bit level only.
• (Note: If INL and DNL are not specified, assume target
specifications INL=DNL=0.5 LSB)
•
•
•
•
Referring to previous example
C’u=16 x Cu=296fF
Total cap= 16 x C’u=4736fF
How does the area of the 4-bit, 8-bit accuracy DAC compare to
that of an 8-bit DAC?
• Then why use segmentation in the first place?
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Dynamic DAC Errors
• Finite settling time and slewing
– Finite RC time constant
– Signal dependent slewing  non-linearity
• Feed-through
– Coupling from switch signals to DAC output
– Clock feed-through
• Glitches due to timing errors
– Different current sources not switching simultaneously .
• Reducing dynamic errors, usually, requires higher power
dissipation
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Dynamic Errors: Glitches
– I1 represents the MSB current, and I2 represents the sum of
N-1 LSB currents.
– If MSB current turns off slightly early, a glitch of zero current
occurs. A glitch to the maximum current value occurs if both
currents are temporarily ON
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References
•
Analog Integrated Circuit Design, David Johns and Ken Martin, Jon
Wiley & sons, 2012.
•
Data Converters, Franco Maloberti, Springer 2007.
•
Haideh Khorramabadi, ECS 247(Analog-Digital Interface Integrated
Circuits) Handouts, University of California, Berkeley, 2005
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Additional slide
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Binary Weighted Resistor DAC
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R-2R Based Resistor DAC
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Dynamic Element Matching
• Dynamic element matching (DEM)algorithms were introduced in
1974 by Klaas Klaassen [K.B. Klaasen, “Digitally controlled absolute
voltage division,” IEEE Trans.Instrumentation and Measurement,
vol. 24, no. 2, pp. 106-112, June 1975] who used DEM to obtain a
constant division ratio from a voltage divider consisting of a
mismatched resistors
• DEM average out errors due
to component mismatch and
therefore achieves accuracy
beyond intrinsic device
matching
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Dynamic Element Matching
Algorithms
• DEM is implemented by using different instances of circuit
elements (transistors, resistors, caps) used to build the system
each time the system the output analog signal is generated
• Since different instances introduce different errors. The errors
introduced by instances is averaged out
• DEM is used to linearize DAC’s
• Dynamic Element Matching Algorithms:– Data weighted averaging
– Individual level averaging
– Vector based mismatch shaping
– Tree-structure element selection
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DATA-Weighted Averaging
• The data weighted averaging DEM algorithm
rotates circuit elements, insuring that each
element is used the same number of times.
• The circuit elements are selected sequentially from
the array starting with the next available unused
element.
• Data weighted averaging generates tones at the
output if the DAC input is not busy (DC input or
low frequency input)
• It can be shown that DWA is equivalent to shaping
mismatch error (noise) by a first order high pass
filter
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Individual Level Averaging
• Individual level averaging (ILA) is basically a DWA carried out
for each code.
• Individual level averaging rotates or flips circuit elements in a
periodic fashion, but a separate rotation state is maintained for
each digital level.
• The advantage of the individual level averaging algorithm over
DWA is that it ILA is less likely to generate tones even for DC or
periodic inputs
• However, compared to DWA, ILA converges more slowly to zero
average condition
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