Ad Hoc Testable Design
Techniques
Prepared By:Ketan Jadav
Roll No.IMI2013003
• Collections of ideas aimed at reducing the
combinational explosion of testing
• To increase the testability is to make
nodes more accessible at some cost by
physically inserting more access circuits
to the original design
Improve Controllability and
Observability
• When a node has difficult access from primary
inputs or outputs (pads of the circuit), a very
efficient method is to add internal pads.
Partition and Multiplexer techniques
• With this design technique, the number of
accessible nodes can be increased and the
number of test patterns can be reduced.
Disable Internal Oscillators and
Clocks
• To avoid synchronization problems
during testing, internal oscillators and
clocks should be disabled.
• Disable =1
Avoid Asynchronous Logic and
Redundant Logic
• Design and test of an asynchronous logic
circuit are more difficult than for a
synchronous logic circuit
• Its state transition times are difficult to
predict.
Avoid Asynchronous Logic and
Redundant Logic
• The operation of an asynchronous logic
circuit is sensitive to input test patterns,
often causing race problems and hazards
of having momentary signal values
opposite to the expected values.
• Logic redundancy is used to mask a static
hazard condition for reliability.
Avoid Delay-Dependent Logic
• Chains of inverters can be used to design in
delay times and use AND operation of their
outputs along with inputs to generate pulses
• ATPG programs.
Avoid Clock Gating
Initialize Sequential Logic
.
Initialize Sequential Logic
Strictly Distinguish Between Signal
and Clock
Disadvantages
• Circuit too large for manual inspection and test
generation.
• Not too many testability experts to consult.
• High fault coverage not guaranteed
• All the techniques do not represent an
exhaustive list for Ad Hoc Testing, but give a
set of rules to respect as possible.
• Some of these guidelines goals are the
simplification of test vectors generation, others
goals are the simplification of test vectors
application, and many others are to avoid
timing problems in the design.
References
• VLSI Test Principles and Architectures:
Design for Testability By Laung-Terng
Wang, Cheng-Wen Wu, Xiaoqing Wen
• CMOS Digital integrated circuit analysis and
design by Sung Mo kang,Yusuf Leblebici
• http://book.huihoo.com/design-of-vlsisystems/ch08/ch08.html
• http://www.eet.bme.hu/~benedek/Vlsi_Design/
Lectures/Design_for_Test.pdf
THANKS