2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
Organic Interposer CoWoS-R+ (plus) Technology
M.L. Lin, M.S. Liu, H.W. Chen, S.M. Chen, M.C. Yew, C.S. Chen, and Shin-Puu Jeng*
Taiwan Semiconductor Manufacturing Company
No.6, Creation Rd. II, Hsinchu Science Park, Hsinchu, Taiwan (R.O.C.) 30077
*spjeng@tsmc.com
Abstract—Organic interposer (CoWoS-R) technology is one of
the most promising heterogeneous integration platforms for
high performance computing (HPC) applications. Components
such as chiplets, high-bandwidth memory (HBM), and
passives can be integrated into an organic interposer with
excellent yield and reliability. CoWoS-R provides low RC
interconnect with good signal isolation and design scalability.
The new organic interposer CoWoS-R+ (plus) successfully
integrates both a large amount of high density IPD (integrated
passive device) and fine pitch Si-based connection block for
convenient IP migration. IPD serves as decoupling (de-cap)
capacitor, which is critical to the high-speed data operations in
advanced logic circuits, where stable voltage supplies are
required. The distance between SOC devices and capacitors is
minimized to assure fast response. The feeding resistance is
greatly reduced by thick power mesh and bump via in the
organic interposer. The advantages in connectivity and power
integrity of new CoWoS-R+ (plus) technology are presented.
Both signal bandwidth and circuit speed driving
capability are considered critical in the interconnection
design of HPC packages. Signal bandwidth requires high
line speed and density, while high-speed circuits
require short connection length and low RC loading. Figure
1 shows various signal interconnects on interposers as a
function of line length and operating frequency. High-speed
I/O, such as PCIE and Serdes, which connect the silicon die
to package-out, use short vertical routing paths with low
insertion loss and coupling, while low-speed I/O, like GPIO
and JTAG, use long routing lines to achieve signal fan-outs
from the silicon die to the edges of the interposer. There are
three types of die-to-die (D2D) connections on interposers.
The first type of D2D connections is intended for die-split
applications. Silicon dice with the same function, like
FPGA split dice, are interconnected with short and
high-density fine pitch lines. The second type of D2D
connections is intended for die-partition applications. Logic
dies with different functions, like I/O dies partition with
SOC cores, are interconnected with mid length lines. The
third type of D2D connections is meant for heterogeneous
integration. Devices of different functions, like HBM
memory and optical devices, are interconnected with long
lines.
HPC heterogeneous integration drives demand for high
signal bandwidth and high-speed circuits [1-4]. The
situation becomes more challenging with increasingly
higher data rates and longer interconnection lengths. The
data rate of HBM1 is 1Gbps, while HBM2 and HBM2E
operate at 2.4Gbps and 3.2Gbps respectively. HBM3 is
moving to a data rate higher than 6.4Gbps.
Keywords—Organic interposer; HPC package; CoWoS-R;
RDL; fine pitch Si-based connection block; IPD capacitor
integration
I.
INTRODUCTION
A. HPC package development
High performance computing (HPC) applications in
artificial intelligence, machine learning, 3D imaging, and
internet of things are growing rapidly. HPC solutions
seamlessly perform all high-speed
data
computing,
networking, and storage tasks and functions.
Figure 1. Various interconnections on interposer.
2377-5726/22/$31.00 ©2022 IEEE
DOI 10.1109/ECTC51906.2022.00008
1
solution for high-speed HBM integration [5,6].
Increasing SOC-HBM interconnection length come from
the growing HBM package sizes. The package widths of
HBM2 and HBM2E are 7.8mm and 10mm, respectively.
Meanwhile, the package width of HBM3 has been increased
to 11mm and the interconnection length between the HBM
and SOC PHY is ~5.5mm. Interconnects with low RC
value are the key to solving the challenges of high data rate
transmission along long interconnect lengths. Figure 2
(a) illustrates normalized RC values for interconnects with
different metal and dielectric thickness. Figure 2 (b) shows
the normalized RC values with different metal width/space
and dielectric constant. CoWoS-R optimizes the metal and
dielectric thickness with low DK polymer to gain low RC
impedance and for high-speed devices like HBM3.
TABLE I. KEY COMPOENETS OF ORGANIC AND SI
INTERPOSER
Figure 2. Interconnect optimization for HBM integration.
Interposer
Organic
Interposer
Si
Interposer
RDL
Cu traces in low-k
polymer, and
optional Si-based
connection block
in CoWoS-R plus
Cu traces in SiO2
Interconnect to
top die
Micro bump
Micro bump
Interconnect to
substrate
Cu via in polymer
TSV
C4
Cu/solder bump
Cu/solder bump
HBM, I/O
chiplet, passive
device, die
partition
Attachment based
on minimum bump
pitch capability
Attachment based
on minimum bump
pitch capability
Decoupling
capacitor
Discrete IPD
in CoWoS-R plus
Embedded
DTC (iCap)
B. CoWoS-R plaftorm
CoWoS-R adopts the same CoWoS process assembly on
the organic interposer. The primary difference between
the CoWoS-R and the CoWoS-S is that the silicon
interposer is replaced with an organic interposer. The key
components in CoWoS-R include the redistribution layer
(RDL) and TSV-less vertical interconnects. Table I
summarizes these differences. The low-RC electrical
property of the organic interposer, including good eye
diagram and low insertion loss performance of multiple
RDLs with a coplanar GSGSG isolation scheme, was
demonstrated [5]. Multiple redistribution layers (RDLs)
form an effective stress buffer to reduce the stress induced
in the C4 joints and its underfill from the mismatch between
top dies and substrate. RDL lines with a minimum line
width/spacing of 2/2 μm exhibit excellent robustness,
ensuring the long functional lives of high-performance
computing products. The excellent package reliability
of CoWoS-R was previously presented in the reference [6].
II.
Performance demands drive the continual increase in the
number of processing cores on SOCs, which in turn lead to
more produced power noise in power domains. Figure 3
shows how power noise is generated in an unprotected IP0
through the coupling with a noisy IP1. To suppress the
power noise affection in IP0, the noise in IP1 can be
reduced with a decoupling capacitor, which bypasses the
noise to ground to achieve good signals in IP0. This is the
basic power noise protection mechanism. High density IPD
is placed directly under the hotspots to suppress power
noise.
Figure 4 (a) shows the eye diagram of a victim HBM
PHY IP degraded by the power noise from the power
domain. High power noise is coupled into the signals from
the VDD of HBM PHY and degrades the eye diagram.
Power noise can be suppressed by adding IPD, and a clearer
eye diagram is obtained with a larger eye width of 88%.
The path for the high-density capacitor to top dies is
through the C4 bump and thick RDL of the organic
interposer as shown in Figure 4 (b). The path is of low
feeding resistance due to low resistance power routing
provided by the thick and wide RDL, while the C4-via
provides a short distance from C4 [Figure 4 (c)]. With a low
IR drop, the integrated IPD capacitor provides good noise
decoupling and stable voltages for high power ASIC.
FEATURES IN COWOS-R+ ĩPLUS) PACKAGE
A. Decoupling capacitor integration
The demands for HPC performance drives DRAM to
higher bandwidths. As a result, more high-speed HBM3
dice and more SOC chiplets are integrated on an interposer
[7-10]. High speed HBM3 requires low resistance and low
capacitance interconnect between SOC and HBM. The low
RC CoWoS-R platform has been demonstrated as a good
2
(a)
Figure 3. Signal noise improvement by decoupling capacitor.
Decoupling
Capacitor
Eye
Width
6.4Gbps HBM3
Eye Diagram
CoWoS-R
without IPD
76%
76%
CoWoS-R+
(plus)
with IPD
88%
88%
(c)
B. Flexible interconnect IP selection
Chiplets with multi-processor cores and memories are
integrated on an interposer. Both the dense short length
interconnect for nearby D2D connections and the long
length low RC interconnect for faraway device connection
are required. CoWoS-R provides robust 2/2um L/S RDL
traces for both short D2D interconnect and long chiplets
interconnect as shown in Figure 5 (a). The line density
increases with the number of RDL layers and shrinking line
pitch. As shown in Figure 5 (b), the multilayer RDL
effectively provides abundant connectivity, which satisfies
the very demanding HPC high routing density requirements.
Localized high density interconnect technology has been
developed for various packaging forms [11-13]. The chief
reason that the optional Si-level interconnection block is
added to CoWoS-R for the convenience of migrating
existing Si based PHY IP to the CoWoS-R platform. The
Si-based D2D interconnect is treated as an existing Si-IP in
the design phase. In CoWoS-R, the Si-base connector is
assembled on the landside same as a discrete IPD. Figure 6
(a) shows CoWoS-R+ (plus) with only de-cap IPD, and
Figure 6 (b) shows the addition of a Si-base connector.
On CoWoS-R+, the combination of low RC fine pitch RDLs
and Si-base connectors provides more flexible options for
interconnect IP selection.
Copper thickness
C4 Via number
IR drop
;
;
;
;
;
;
;
;
;
Figure 4. (a) Under high power domain noise, HBM3 eye diagram
with and without IPD de-cap at 6.4Gbps, (b) Low resistance
feeding path, (c) IR drop for various voltage supply routings.
Figure 5. (a) Schematic of CoWoS-R package, (b) Line density as
a function of number of multilayer RDL and line pitch.
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density IPD are attached to the landside of organic
interposer. Figure 7 (a) shows the CoWoS-R+ (plus)
package. The corresponding CSAM image with 20 discrete
IPD is shown in Figure 7 (b). The CSAM image shows a
void-free underfill filling with the presence of multiple IPD.
The electrical property of the integrated IPD is carefully
characterized. Figure 8 (a) shows a comparable distribution
of capacitance density before and after the attachment of
IPD. The cumulative plots of measured leakage current in
Figure 8 (b) also show that there is little impact on the
intrinsic values by the attachment. This not only proves the
integration flow, but also demonstrates the advantage of
low-IR drop in voltage supply routing [Figure 4 (b)] for the
discrete IPD integration in CoWoS-R.
Figure 6. (a) Schematic of CoWoS-R+ (plus) package with de-cap
IPD, (b) The addition of Si-based connection block.
Figure 9. X-ray images of the CoW C4 bump joints at four corners
of CoWoS-R+ package.
Figure 7. (a) Completed CoWoS-R+ package (b) CSAM image of
organic interposer CoW package with the presence of multiple
IPD.
The IPD insertion may occupy the C4-bump area on the
interposer, which may result in the loss of C4 bumps. In this
study, the area used by 20 pcs of IPD consumes ~8% of the
total number of the C4-bumps. The C4 bump patterns are
re-arranged to retain the full C4-Bump I/O numbers. The
joints of C4 bump on substrate (oS) are not affected by the
presence of landside IPD. There are no cold joint and
bridging defects. Figure 9 shows the X-ray images of good
C4 bump joints in the four corners of this CoWoS-R
package. The underfill filling in the gap between IPD and
substrate surface is carefully examined. Both cross-sections
and CSAM show good encapsulation without voids.
Figure 8. (a) Cumulative capacitance density for before and after
the attachment of IPD on CoWoS-R package. Little impact on
capacitance density after attachment shows the advantages of low
feeding impedance path on organic interposer. (b) Cumulative
distribution of leakage current after attachment.
B. Optional Si-based connection block integration
Si-based connection blocks are used to interface two split
SOC dies. The connection blocks have 0.8um/0.8um
routing and 24um fine ubump pitch to minimize the
footprint of the blocks. Figure 10 (a) shows the CSAM
image of a CoWoS-R package with connection blocks and
two discrete IPD. The quality of the small ubump joints is
good without joint defects, as shown in X-ray image in
Figure 10 (b).
III. COWOS-R+ ĩPLUS) PACKAGES
A. Landside IPD integration
The CoWoS-R+ (plus) package consists of two split SOC
dies and 2HBM with a nominal C4 bump pitch of 150um.
The size of the interposer and package is 32x35mm2 and
55x55mm2, respectively. Known-good high capacitance
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D. Packaging Reliability performance
The component level reliability result of CoWoS-R+ (plus)
package with 20 pcs IPD is summarized in Table II. The
package pass 3x mass reflow and up to 850 TCG (-55 – 125
o
C) cycles. The cross-section sanity check exhibits no
delamination in critical interfaces, such as ubump joint of
IPD to interposer, C4 bump joint, oS underfilling, and SOC
PHY area ubump joint and underfilling. The packages also
pass the items of u-HAST (110℃/85% RH, 264hrs) and
HTS (150oC, 500hrs).
Figure 10. (a) CSAM image of an organic interposer package with
Si-based connection blocks and two discrete IPD, (b) X-ray
images of the good 24um pitch ubump joints on the Si-based
connection blocks.
TABLE II. COMPOENET LEVEL RELIABILITY
Reliability Item
Result
Mass reflow 3x
Pass
Precon + TCG 850
Pass
Precon + uHAST 264h
Pass
HTS 500h
Pass
C. Interposer CoW module warpage
The assembly process margin is critically dependent
upon the interposer CoW module warpage [14,15]. The
high warpage not only causes process challenges in jointing
the CoW module to substrate, but also potentially degrades
the package reliability. The plain CoW has a low high
temperature warpage of ~26um, as shown in Figure 11. The
additions of IPD and Si-based connection blocks don’t
change the warpage of CoW module. The organic
interposers with up to 20 pcs of IPD or Si-based connection
blocks all have comparable shadow Moire curves. This is
highly advantageous to maintain good assembly process
window and reliability.
IV. CONCLUSION
The organic interposer CoWoS-R+ (plus) package
technology for HPC application is presented. The integrated
de-cap capacitors suppress the power domain noise and
enhance the HBM3 signal integrity at high data rate. The
optional Si based connection blocks serve as high density
short length die-to-die interconnects for IP re-use on
organic interposer platform. The impact on I/O density due
to landside insertion is minimized through the adjustment of
bump arrangement and IPD locations. The warpage of the
CoW module of CoWoS-R+ (plus) remains small and
unchanged, which is advantageous for building large size
packages. These added advanced features on organic
interposer offer an excellent integrated packaging solution
for high-speed HPC applications.
ACKNOWLEDGEMENT
CoW package
RT 25C
warpage (um)
HT 260C
warpage (um)
(a) No chiplet integration
61um
26um
(b) Si-based connection
block + 2pcs IPD
59um
27um
(c) 20pcs IPD integration
57um
24um
The authors would like to have special thanks to Dr.
De-Dui Marvin Liao and NTM (New Technology
Management) members for their contributions in
investigation resources, and corresponding supports.
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