Predicting Noise Voltage from Trace
Crossing Split Planes on Printed Circuit
Boards
Weifeng Pan1, Samuel Connor2, Bruce Archambeault2
1
EMC Lab, Missouri University of Science & Technology, Rolla, MO 65401 (wpqk7@mst.edu)
2
IBM Corporation 3039 Cornwallis Rd, Research Triangle Park, NC 27709 (sconnor, barch@us.ibm.com)
capacitor distance for critical traces crossing split
reference planes was discussed in 0.
Abstract --- Printed circuit Boards (PCBs)
often have high speed data traces crossing
splits in the adjacent reference planes due to
space limitations and cost constraints. These
split planes are usually different power
islands on nearby layers.
This work
quantifies the effect of the split plane and the
associated stitching capacitor for various
stackup configurations.
Full wave numerical modeling methods can be
used to provide a good estimation of the amount
of noise voltage induced across the split.
However, these tools require careful use, and
take a significant amount of time and are not
practical for a quick engineering answer. Hybrid
model of transmission lines, mode conversion
and lumped circuit is also an effective approach
00 but has difficulty in handling structures other
than microstrip
I. Introduction
Splits in the power or ground planes are typically
used to introduce DC isolation between different
supply voltages 0, to isolate RF signals from
digital signals, or to isolate low noise analog
from digital circuits. Under special I/O
circumstances, intentional splits are used to
minimize radiated emissions 0. It is well known
that high speed traces should never be routed
across a reference plane split in an adjacent
layer. However, due to the increasing demand
for smaller board size and less number of layers,
there is often little flexibility to use optimum
trace routing.
In many circumstances high
speed signal traces have to run across splits
between reference planes, even though EMC and
signal integrity design rules would advise against
this design practice.
This paper discusses the development of
predictions for quick calculation of the noise
voltage across split under all the common PCB
layer configurations, including microstrip,
stripline and both with and without an additional
reference plane. The predictions take into
account the width of the split s, the distance of
the stitching capacitor to the trace d, the
separation between trace and planes h1,2,3. The
output from the prediction is an equivalent
‘transfer inductance’ Le. Using this transfer
inductance, the maximum voltage across the
split can be calculated using the intentional
signal current on the trace.
The noise voltage across the split (due to a
normalized signal harmonic current) was found
using a full wave simulation which employs the
Finite-Difference Time-Domain (FDTD). A
variety of different stackup configurations were
modeled using EZ-FDTD [10] simulation
software. Each model has one signal trace and
one shorting tab (as a perfect stitching capacitor)
connecting the two split planes. While the signal
may also be on many traces (bus) 0 or
differential pairs 0 the effects of the noise across
the split will be additive.
It is well known that the high frequency
harmonic content of the data signal’s current
takes the nearest reference plane as its
predominate return path. If a split in this
reference plane exists, it will cut off the path for
the conduction current and induce noise voltage
across the split. The impact of trace crossing
split planes on both signal integrity and EMI has
been observed and evaluated in 0-0. One
counter-measure is to use stitching capacitors
across the split to reduce impedance in the
current return path. The effect of stitching
978-1-4244-4267-6/09/$25.00 ©2009 IEEE
In addition to the transfer inductance, Le, the
connection inductance for the stitching capacitor
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[11] and the equivalent series inductance (ESL)
of the capacitor must be included.
The
algorithms developed under this effort are only
for perfect stitching capacitors with now
connection inductance or ESL.
result. The value of the slot termination was
verified by observing no reflection from the end
of the slot.
Finally, some measurement validation of the
simulation
results
for
the
microstrip
configuration will be discussed.
Trace
Perfect
Capacitor
II. Microstrip Configuration
Split in the microstrip reference plane is the
simplest and most often discussed structure
among all the split plane cases. The general
configuration is shown in Figure 1.
In the
FDTD model, the cell size is 0.5 mm, 0.25 mm
and 0.1 mm along X, Y and Z axis, respectively.
The trace has 1 mm width and 0.3 mm height
above the reference plane. Air dielectric is used
within the structure, thus the characteristic
impedance Z0 is about 57 Ÿ. The source and
load are matched to Z0. The split is in the middle
of the reference plane, with both ends of the split
terminated with resistors. The termination of the
split is to avoid length dependant resonances,
and to obtain a more general length independent
Split
Width
Distance to
‘Capacitor’
Figure 1 General Configuration for
Microstrip
Estimated Transfer Inductance for Trace Crossing Split Plane
Microstrip Configuration (Valid to 2 GHz)
12
Split Width = 20 mil
Split Width = 40 mil
Split Width = 60 mil
Transfer Inductance (nH)
10
d
8
6
4
2
0
0
100
200
300
400
500
600
700
Distance to Capacitor (mils)
Figure 2 Transfer Inductance for Microstrip Configuration
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reference plane. Figure 3 shows the Transfer
Inductance results as well as a diagram of the
stack up configuration for the case of a 40 mil
wide split. As can be seen by comparing Figures
2 and 3, the additional unbroken plane can have
a very positive effect by lowering the transfer
inductance when the unbroken plane is close to
the initial reference plane.
Figure 2 shows the Transfer Inductance for the
simple microstrip configuration for plane split
widths of 20, 40 and 60 mils. The Transfer
Inductance Le increases with distance to the
shorting tab (perfect stitching capacitor). Note
that this Transfer Inductance is independent of
frequency up to ~ 2 GHz. Above 2 GHz, the
noise voltage no longer increases with distance
of the shorting tab since the capacitance between
the two co-planer reference planes dominates
and the shorting tab is no longer the major path
for the return current.
Note that this Transfer Inductance is independent
of frequency up to approximately 400 MHz.
Above 400 MHz, the noise voltage no longer
increases with distance of the shorting tab since
the capacitance dominates and the shorting tab is
no longer the major path for the return current.
The microstrip configuration is then modified by
adding an additional solid plane below the split
Estimated Transfer Inductance for Trace Crossing Split Plane
Microstrip Configuration with Solid Plane Below (Valid to 400 MHz)
Split Width = 40 mils
2.5
Distance to Solid Plane = 4 mils
Distance to Solid Plane = 6 mils
Distance to Solid Plane = 8 mils
Transfer Inductance (nH)
2
1.5
1
h1
Split Plane
0.5
h2
Solid Plane
0
0
100
200
300
400
500
600
700
Distance to Capacitor (mils)
Figure 3 Transfer Inductance for Microstrip Configuration with Additional Unbroken Plane
configuration for the cases when the split plane
is closest to the signal trace and the unbroken
plane is furthest from the trace (h2/h1 ratio
greater than 1.0), when the configuration is a
symmetrical stripline (same distance to both
planes, h2/h1 = 1.0) and when the unbroken plane
is closest to the trace (h2/h1 ratio less than 1.0).
As would be expected, when the solid plane is
closes, the transfer inductance is less than when
III. Stripline configuration
The next configuration studied is the
asymmetrical and symmetrical strip line
configuration. For this configuration, one plane
includes the split and the other plane is
unbroken.
Figure 4 shows the transfer inductance (and
stackup configuration) for the strip line
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the split plane is closest to the trace. However,
the transfer inductance is never insignificant.
the split plane and the unbroken plane below is
the dominate factor, similar to the microstrip
case. The transfer inductance is shown in Figure
5 along with a stackup diagram.
These results are valid to approximately 600
MHz. At higher frequencies, the noise voltage
across the split becomes a constant and
independent of the distance to the stitching
capacitor.
It can be seen in Figure 5 that the addition of a
nearby solid plane greatly reduces the transfer
inductance, and the closer the solid plane, the
lower the transfer inductance. However, once
again, the transfer inductance never becomes
insignificant.
Finally, an additional solid plane is placed below
the split plane. A common stackup configuration
of the previous asymmetrical strip line case for
h2/h1 = 0.667 is used and the distance between
Estimated Transfer Inductance for Trace Crossing Split Plane
Stripline Configuration (Valid to 600 MHz)
Split Width = 40 mils (h2=Distance to Solid Plane, h1 = Distance to Split Plane)
3
Solid
Plane
h2
2.5
Transfer Inductance (nH)
h1
Split
Plane
2
1.5
1
Ratio h2/h1 = 0.5
Ratio h2/h1 = 0.666
Ratio h2/h1 = 1.0
Ratio h2/h1 = 1.33
Ratio h2/h1 = 2
0.5
0
0
100
200
300
400
500
600
700
Distance to Capacitor (mils)
Figure 4 Transfer Inductance for Strip Line Configuration
Figure 7 and show good agreement. The FSV
ADMc is shown in the insert in Figure 7.
IV. Validation
The microstrip configuration simulations were
validated by building a test board with microstrip
crossing a split was built and is shown in Figure
6. Three configurations were measured and
modeled in
EZ-FDTD simulation: (1) no
shorting piece connecting the split (FSV
ADMc=4 fair-to-excellent); (2) shorting piece
under the trace (in the middle) (FSV ADMc=3
good-to-excellent); (3) shorting piece halfway
from trace to board edge(FSV ADMc=3 good-toexcellent). S21 was measured with a vector
network analyzer (VNA) for all three cases. The
simulation and measurement results are shown in
V. Summary
This work has characterized the amount of
transfer inductance seen by a trace crossing an
adjacent reference plane. A number of different
typical configurations were studied. The transfer
inductance can be used to quantify the amount of
noise voltage seen across a split in the reference
plane as a function of harmonic frequency
current amplitude, distance to stitching capacitor,
and split width. It was also observed that an
unbroken plane below the split plane can reduce
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the
transfer
inductance,
but
the
transfer
inductance never becomes insignificant.
Estimated Transfer Inductance for Trace Crossing Split Plane
Symetrical Stripline Configuration (Valid to 600 MHz)
Split Width = 40 mils (h3=Distance to Solid Plane, h1 = Distance to Split Plane)
2.5
Solid Plane
h2
h1
2
Split Plane
Transfer Inductance (nH)
h3
Solid Plane
1.5
1
No Additional Plane
Ratio h3/h1 = 1.0
Ratio h3/h1 = .666
Ratio h3/h1 = 1.333
0.5
0
0
100
200
300
400
500
600
700
Distance to Capacitor (mils)
Figure 5 Transfer Inductance for Strip Line Configuration with Additional Unbroken Plane
Figure 6 Validation Fixture for PCB
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Simulation/Measurement Validate of Microstrip Configuration
Trace Crossing Split in Reference Plane
0
Transfer Function (dB)
-10
-20
FSV Validation ADMc
-30
0.6
No Shorting Tab
0.5
-40
ADMc
Measurement -- No Shorting Tab across split
Simulation -- No Shorting Tab across split
Shorting Tab Halfway to Edge
0.3
0.2
Measurement -- Shorting tab directly under trace
-50
0.1
Simulation -- Shorting tab directly under trace
Measurement -- Shorting tab halfway to edge of board
0
Excellent Very Good
Simulation -- Shorting tab halfway to edge of board
-60
0.0E+00
Shorting Tab Under Trace
0.4
2.0E+08
4.0E+08
6.0E+08
8.0E+08
1.0E+09
1.2E+09
Good
Fair
Agreement Quality
1.4E+09
Poor
1.6E+09
Very Poor
1.8E+09
2.0E+09
Frequency (Hz)
Figure 7 Validation Demonstration Between Simulation and Measurement
[7] Effect of stitching capacitor distance for critical
traces crossing split reference planes Roden, J.A.;
Archambeault, B.; Lyle, R.D.; Electromagnetic
International
Compatibility,
2003
IEEE
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[3] Crossing the planes at high speed. Signal integrity
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[11] IEEE EMC Society Newsletter, Winter 2006
issue, pp 56-67. www.emsc.org
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