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Lec 06 Transistor Biasing EEE EEE 235-converted

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Transistor Biasing
EEE 235
ELECTRONICS 1
Prepared by Md. Kamrul Hasan, EEE, CUET
Reference Book
2
 Electronic Devices- Thomas L Floyd.
 Electronic Devices and Circuit Theory- Robert Boylestad
This presentation slide only contains the overview of the related
topics. Students are advised to take decent class-notes and read
thoroughly from the prescribed text books.
Prepared by Md. Kamrul Hasan, EEE, CUET
Biasing
 DC biasing is a method to establish fixed dc values
for the transistor to operate the device in linear
region.
Prepared by Md. Kamrul Hasan, EEE, CUET
DC Load Line
The DC operation of a transistor can be described
graphically using a dc load line.
This is a straight line between the cutoff point (VCE =
VCC) and the saturation point (IC(Sat)= VCC/RC).
Prepared by Md. Kamrul Hasan, EEE, CUET
DC Load Line Analysis
Prepared by Md. Kamrul Hasan, EEE, CUET
Waveform Distortion
Prepared by Md. Kamrul Hasan, EEE, CUET
Waveform Distortion
Prepared by Md. Kamrul Hasan, EEE, CUET
Math Problem
 Determine the Q-point for the circuit in Figure 5–7
and draw the dc load line. Find the maximum peak
value of base current for linear operation. Assume
βDC = 200.
Prepared by Md. Kamrul Hasan, EEE, CUET
DC Biasing Configuration
 Fixed Bias
 Emitter Bias
 Voltage Divider Bias
 Collector Feedback
 Emitter Follower
 Common Base
Prepared by Md. Kamrul Hasan, EEE, CUET
 Base- Emitter Loop:
Fixed Bias
 Collector- Emitter Loop:
Prepared by Md. Kamrul Hasan, EEE, CUET
Math Problem
 Determine how much the Q-point (IC, VCE) for the
circuit in Figure will change over a temperature
range where βDC increases from 100 to 200.
Prepared by Md. Kamrul Hasan, EEE, CUET
Math Problem
 Given the load line in Fig. and the defined Q-point,
determine the required values of VCC, RC, and RB for
a fixed-bias configuration.
Prepared by Md. Kamrul Hasan, EEE, CUET
 Base-Emitter Loop:
Emitter Bias
 Collector- Emitter Loop:
Prepared by Md. Kamrul Hasan, EEE, CUET
Voltage
Divider Bias
Exact
Analysis
Prepared by Md. Kamrul Hasan, EEE, CUET
Approximate
Anaysis
Collector
Feedback Bias
 Base-Emitter Loop:
 Collector- Emitter Loop:
Prepared by Md. Kamrul Hasan, EEE, CUET
Math Problem
 Determine the quiescent levels of ICQ and VCEQ for
the network of Fig
Prepared by Md. Kamrul Hasan, EEE, CUET
SELF STUDY
1.
Emitter Follower Configuration.
2. Common Base Configuration
3. Miscellaneous
Configurations, related analysis,
mathematics problem from reference books.
Prepared by Md. Kamrul Hasan, EEE, CUET
Prepared by Md. Kamrul Hasan, EEE, CUET
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