ECE 233 – Intro to Digital Systems
Topics:
More on Finite State Machines
ECE 233 – Intro to Digital Systems
1
Administrative
• Homework #6 due Monday (01/23/23)
• Lab #4 on Wednesday/Thursday (01/18/23 or 01/19/23)
– Checkpoint #1 due Monday (01/16/23)
– Checkpoint #2 due Tuesday (01/17/23)
ECE 233 – Intro to Digital Systems
2
Review
• Finite State Machines are a common sequential circuit
that can be represented four different ways:
1. A Sequential Circuit: Combinational logic and flip-flops
2. A State Table: A truth table representation
3. A State Diagram: A graphical representation using states
(circles) and transitions (arrows) that illustrate the behavior
4. A Waveform: Usually used for design verification, but also
illustrates the behavior
• In this lecture, we’ll look at designing a finite state
machine from scratch
– i.e. only given a word description or behavior
ECE 233 – Intro to Digital Systems
3
State Machine Design
• Specification defines the desired behavior of the needed
circuit
• Must determine required circuit states
– Initially we design the FSM at an abstract level
– Later, this initial design is translated to actual flip-flops and
combinational logic
ECE 233 – Intro to Digital Systems
4
State Machine Design – Overall Strategy
State Diagram
• Obtain detailed
specification
• Create high level
design
• Draw the state
diagram
State Table
K-Maps
Circuit
• Fill in values from
the State
diagram
• Obtain the
equations for
D0, D1 &
Output
• Build the
circuit from
the
equations
ECE 233 – Intro to Digital Systems
5
State Machine Design – Practical Strategy
1. Draw state diagram based on specification
– With the state diagram, we can derive the other parts
– Again, start with determining what states you need
2. Derive state table from state diagram
– Truth table for the next state logic and output logic
3. Optimize next state and output logic (K-Maps)
– Solve for each flip-flop input and each output
4. Draw schematic diagram
5. Verify through simulation that circuit operation is correct
(functional and timing-based)
ECE 233 – Intro to Digital Systems
6
Reset Signal
• “Where do we start?”
• Reset puts system into a known state
– Sets the initial state of all critical flip-flops
– This is the initial state or reset state
• This master reset is used at very specific times:
– Applied on circuit power-up
– Applied when soft failure puts circuit into invalid/incorrect state
• Can be asynchronous or synchronous
– Asynchronous requires asynchronous reset input to FFs
– Synchronous reset can be added to FF
ECE 233 – Intro to Digital Systems
7
Designing a State Machine
• Given a description or specification, start by generating a
state diagram that illustrates the correct behavior
• Example: Output a 1 whenever the circuit recognizes a
sequence of “110” within a serial bit pattern
– Serial input: information arrives one bit at a time
o Each active clock edge marks a new bit
– Serial sequences are generally specified from oldest to newest
• Design Process (Some pointers to start)
– Is the description sufficient? Do we need more information?
– Does this description indicate Mealy or Moore?
– Determine states required, using placeholders for state values, and
reusing states whenever possible.
ECE 233 – Intro to Digital Systems
8
Example 1 : Moore Machine
• Need to start somewhere…
• State “Seen 11”
– Start with Reset state!
– Haven’t seen a useful part of the
pattern yet…
– A=0 completes the pattern
– A=1 neither continues nor ruins
pattern (still have “11”)
• State “Seen Nothing”
– A=0 doesn’t start a pattern
– A=1 starts a pattern
• State “Seen 110”
– A=0: start over…
– A=1: start over with first 1
• State “Seen 1”
– A=0 ruins pattern: start over
– A=1 continues the pattern
reset
1
Nada
0
0
0
1
“1”
“11”
0
0
“110”
1
0
1
1
0
ECE 233 – Intro to Digital Systems
9
Example Version 2: Mealy Machine
• Start with the reset…
• State “Seen 11”
– A=0 completes pattern; start over
for next
– A=1 holds place in pattern
• State “Seen Nothing”
– A = 0 doesn’t start a pattern
– A = 1 starts a pattern
• Mealy needs fewer states than
Moore for similar functionality
• State “Seen 1”
– A = 0 ruins pattern: start over
– A = 1 continues pattern
reset
1/0
Nada
0/0
– Remember, the functionality is not
the same
0/0
1/0
“1”
“11”
1/0
0/1
ECE 233 – Intro to Digital Systems
10
State Assignment
• Given a state diagram, assign state values
– If m states, must be at least n flip-flops, where 2n≥m
o Sometimes use more than necessary…
– “Minimum FF” state assignment uses as few FFs as possible
– Choice of state values can affect the complexity of the next-state and
output logic
• Determine the reset state
– Usually is the first state we created
– Usually, it is assigned the value 0 for reset
o But not always!
• One technique:
– Use gray code for state #s along state trajectories
ECE 233 – Intro to Digital Systems
11
Example: State Assignment
• Use meaningful names to help us build diagram
• Now need to pick binary state encoding
– Doesn’t have to be Gray code, but it works well here
reset
1
Nada
00
0
0
1
0
“1”
01
“11”
11
0
0
1
1
0
“110”
10
1
0
reset
1/0
00
Nada
0/0
0/0
1/0
01
“1”
11
“11”
0/1
ECE 233 – Intro to Digital Systems
1/0
Mealy has
unused state
10
12
State Machine Design
• Now that we have the state diagram, we can find the
state table, solve the K-maps, implement the circuit, and
verify functionality
ECE 233 – Intro to Digital Systems
13
Example: Moore Machine
Input: A
Output: Y
reset
1
00
0
0
1
01
0
0
11
0
1
1
10
1
0
CURR
Q1 Q0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
IN
A
0
1
0
1
0
1
0
1
NEXT
D 1 D0
0 0
0 1
0 0
1 1
0 0
0 1
1 0
1 1
0
OUT
Y
0
0
0
0
1
1
0
0
Q0 A
Q1
D1
00 01 11 10
0 0
0 1 0
1 0 0 1 1
D1 = Q1Q0 + Q0A
Y
Q0 A
Q1
Q0 A
Q1
D0
00 01 11 10
0 0
1 1 0
1 0 1 1 0
D0 = A
00 01 11 10
0 0
0 0 0
1 1 1 0 0
ECE 233 – Intro to Digital Systems
Y = Q1 Q0
14
Example: Mealy Machine
Input: A
Output: Y
CURR
Q1 Q0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
IN
A
0
1
0
1
0
1
0
1
reset
1/0
00
0/0
NEXT OUT
D 1 D0 Y
0 0 0
0 1 0
0 0 0
1 1 0
X X X
X X X
0 0 1
1 1 0
0/0
1/0
01
1/0
11
0/1
Q0 A
Q1
D1
00 01 11 10
0 0
0 1 0
1 X X 1 0
D1 = Q0 A
Y
Q0 A
Q1
D0
Q0 A
Q1
00 01 11 10
0 0
1 1 0
1 X X 1 0
D0 = A
00 01 11 10
0 0
0 0 0
1 X X 0 1
ECE 233 – Intro to Digital Systems
Y = Q1 A
15
Example Circuits
• Moore
• Mealy
– D1 = Q1Q0 + Q0A = Q0(Q1 + A)
– D0 = A
– D1 = Q0 A
– D0 = A
– Y = Q1 Q0
– Y = Q1 A
D1
A
CLK
D
Q
D1
Q1
D
Q
FF1
FF1
CLRN
CLRN
D
Q
Q1
Y
Q0
Y
A
FF0
CLK
CLRN
D
Q
Q0
FF0
CLRN
RST
RST
ECE 233 – Intro to Digital Systems
16
Verification
• Show that the circuit matches the original specification
– Exhaustive testing is only practical for smaller circuits, and cannot test all
possible sequences
• Instead test each transition and output, with a minimum set of
input vectors
– Start with reset and then go from there
– Each state has (at least) two transitions so make sure those both work
– Continue and make sure every state transition works…
• Even if current and next state are not circuit outputs, add output
pins for them for testing!
– Hard to know what’s going on if you don’t know what the state is
– Just because you think it should be in a state doesn’t mean it is
ECE 233 – Intro to Digital Systems
17
Example: Verification
• Create input sequence to test Mealy version of pattern
recognizer
– Remember: do not change input values on the active clock edge!
reset
reset
Input: A
Output: Y
1/0
00
0/0
0 1 0 1 1 1 0
0/0
1/0
01
11
1/0
0/1
ECE 233 – Intro to Digital Systems
18
Example: Verification
• How does this look on a waveform?
reset
1/0
00
0/0
0/0
Showing current
state & next state
each as 2-bit vector
1/0
01
1/0
11
0/1
reset 0
CLK
RST
A
00
curr
00
next
Y
0
Mealy outputs depend on state
and current input value
(positive edge triggered)
1
0
01
01 11
0
If the input changes at halfcycle, so might the output
1
00
00
0
1
01
01
0
1
0
11
00
11
0
00
0
ECE 233 – Intro to Digital Systems
1
19
In-class Activity
• Design a (Moore) sequential circuit that outputs a “1”
when it sees the binary pattern “101”
Reset
Input: A
Output: Y
0
1
1
1
0
Nothing
00
Seen
01 1
Seen
11 10
Seen
10101
0
0
0
1
0
0
ECE 233 – Intro to Digital Systems
1
20
In-class Activity
1
0
Reset
1
1
0
00
01
11
10
0
0
0
1
0
Curr
In
Next
Out
Q1
Q0
A
D1
D0
Y
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
1
0
1
0
0
1
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
0
Q0 A
Q1
Q0 A
Q0 A
00 01 11 10 Q1
0 0
0 0 1
1 1 0 1 0
00 01 11 10 Q1
0 0
1 1 1
1 1 1 0 0
0 0
0 0 0
1 1 1 0 0
D0
Y
D0 = Q1Q0 + Q1A
+ Q1Q0
Y = Q1Q0
D1
D1 = Q1Q0A + Q1Q0A
+ Q1Q0A
00 01 11 10
ECE 233 – Intro to Digital Systems
21
In-class Activity
• D1 = Q1Q0A + Q1Q0A + Q1Q0A
• D0 = Q1Q0 + Q1A + Q1Q0
Q1
• Y = Q1Q0
A
D
Q
Q1
CLR
Y
Q Q0
D
CLK
CLR
RST
ECE 233 – Intro to Digital Systems
22
Summary
• To design a state machine from a specification:
1. Analyze the specification to determine the required states
2. Using those states, make a state diagram that implements the
desired behavior
o
3.
4.
5.
6.
Start with a Reset state and take care of its transitions and go from there
With that state diagram, make a state table
Using the state table, find the excitation and output equations
Implement the circuit that adheres to the state table
Verify your circuit correctly implements the specification
o
Test all transitions and outputs
ECE 233 – Intro to Digital Systems
23
Next class
• State Minimization and Counters
• Upcoming deadlines:
1. Homework #6 due Monday (01/23/23)
2. Lab #4 on Wednesday/Thursday (01/18/23 or 01/19/23)
o Checkpoint #1 due Monday (01/16/23)
o Checkpoint #2 due Tuesday (01/17/23)
ECE 233 – Intro to Digital Systems
24