ECE 233-04, -05 – Intro to Digital Systems
Spring 2022
Lab #4 2-Digit BCD Counters on Altera DE2-115
Start Date: Wednesday, 04/06/2022
Checkpoint #1 on page 5 about D flip-flop ddf_enrst.bdf: Due Friday, 04/08/2022 at 11:59PM EST
Checkpoint #2 on page 7 about 2-digit BCD counter: Due Friday, 04/22/2022 at 11:59PM EST
Final Demo: Wednesday, 04/27/2022 at 5PM EST
Report: Due at the beginning of Friday (04/29/2022)’s class
1
Description and Lab Objectives
This lab is performed by a group of two students. You are free to form your own group. All your documents such as
your circuit title blocks, checkpoint files and final report must include the name and CM numbers of both team members of
your group.
In this lab, you will create components that you will later use to create an implementation of the Guitar Hero game. In particular,
you will add logic to a D flip-flop to create a D flip-flop with enable and synchronous reset inputs. You will then use this
modified D flip-flop, along with your BCD incrementer from Lab #2 to create 2 two-digit BCD counter with enable and
synchronous clear. These flip-flops will be used to keep track of the player's score, the number of missed notes, and the musical
notes themselves. Next, you will create an edge detector to detect when someone presses a button on the DE2 board. At your
demo, you will demonstrate the functionality of your circuit and show that your incrementer and edge detection circuits work
on the DE2 board.
After this lab, you should be able to:
1.
Design sequential circuits for implementation in an FPGA
2.
Use simulation to verify sequential circuit functionality
3.
Use an FPGA prototyping system to verify sequential circuit funtionality
2
Create a New Lab #4 Project and Copy Files from Lab #3
Create a new project under your C:/ ece233spring2022labs folder. Name your project lab4ece233jjs_jjs where jjs_jjs are
your name initials of two team members. Click Yes to create a new project folder /lab4ece233jjs_jjs if it does not exist. Choose
an empty project. Skip Add Files. Choose Cyclone IV E, EP4CE115F29C7 chip. Click Next. Choose ModelSim-Altera as
simulation tool and Verilog as Format(s). click Next and click Finish.
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Copy components and symbol files from your Lab #3 folder to lab4ece233jjs directory, including SegAv2.v, SegB.v to
SegG.v, bcd_7seg.bdf, increment4bits.v, fix_bcd_4bits.v, bcd_inc .v and ten_detect.v.
Copy files from Lab4DistributionECE233_04_05 under Lab #4 2-Digit BCD Counters from the class page on Moodle
to this project folder /lab4ece233jjs. Here are files from Lab4Distribution_ECE233_04_05 folder.
Choose Files under lab4ece233jjs with Quartus Prime Lite. Right click to choose “Add/Remove Files in Project”. Click
browse folder and choose all *.v and *.bdf files in the project folder. Click OK and click Apply and OK. Here are files to be
added your project.
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Add DE2_115_pin_assignments.csv file to this project. Choose Assignments->Import Assignments. Browse to your
project folder and select DE2_115_pin_assignments.csv. Click OK. You can now compile Lab4_top_level.bdf but some
components are incomplete.
3
Lab Tasks
The main task of this lab is to create three components: a D flip-flop with enable and synchronous reset; a 2-digit BCD
counter with registered output and one-shot or edge detector circuits to interface with active low push buttons.
3.1
Design and Simulate a D Flip-Flop with Enable and Synchronous Reset
D flip-flop with various capabilities are available in the Quartus II primitive library; however, starting with a basic D
flip-flop and augmenting it to provide more capabilities will give you more practice with important concepts such as enabling
logic and clearing logic. After you create this augmented D flip-flop according to the instructions below, you will use it in other
circuits in both this and later Labs.
Implementing the Logic:
1.
open Lab #4 project Lab4_top_level.qsf in lab4ece233jjs folder. This shows the full top-level design for Lab #4.
Although this design appears to be complete, a few of the modules are currently empty. Double-click the bcd_count2
module to open it, and then inside bcd_count2, double-click one of the eight dff_enrst modules. It is an empty
schematic, apart from labeled input and output pins. CLK is the clock signal.
2.
Insert one copy of the dff primitive. Click on Symbol icon and enter dff under Name to find the component. Be sure
that it is the one called “dff” with no additional letters in the name.
3.
Connect the Q output of the flip-flop to the Q output pin. Also connect the CLK, PRN, and CLRN input pins directly
to the appropriate pins of the flip-flop. Only the D, EN, and RSTN input pins should still be unconnected at this point.
4.
In this part of the lab, we will refer to the D input of the dff primitive as DIN. You will need to create gate-level logic
that computes DIN as a function of Q and the D, EN, and RSTN inputs. Remember that RSTN is a synchronous
reset, which means that we cannot connect it to the asynchronous clear input of the dff primitive. Instead, we have to
use it, along with inputs D and EN, to compute DIN. You will need to create this logic, based on
the below requirements:
1.
a.
If RSTN is 0, then the next state of the flip-flop should be 0, regardless of the value of D
or EN.
b.
If RSTN is 1 and EN is 1, then DIN should be equal to D.
c.
If RSTN is 1 and EN is 0, then the flip-flop value should not change at the clock edge.
Note that not all of these requirements are stated explicitly in terms of the value that DIN should be. You must
determine what DIN should be in order to match the required behavior for each of these cases.
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5.
Insert the required logic to match the behavior described above. Make sure that you do not move the pins, because the
hierarchy of the rest of the Lab #4 design requires this pin order. Set this file as Top Level Entry. Start Compilation
to make sure there is no syntax error. Check its circuit schematic with Tools->Netlist Viewers->RTL Viewer. To
create a symbol for this device, open File->Create/Update->Create symbol files for current file.
6.
Create a simulation setup file dff_enrst.vwf by clicking File->New and select Verification/Debugging Files>University Program VWF and save this file as dff_enrst.vwf. Add circuit I/O wires to this setup up file by Edit>Insert->Insert Node or Bus. Click Node Finder. Click List. Click >> and OK to add all I/O pins.
7.
Click Edit->Set End Time to set it to be 100ns. Click OK.
8.
Set clock to operate at 10ns period and 50% duty cycle with Overwrite Clock.
9.
You should test the following situations (in this order), changing the inputs prior to the rising clock edge. In your
waveform, make the order of signals match the pin order, with inputs above outputs.
1.
PRN=0, CLRN=1, RSTN=1, EN=0, D=1
2.
PRN=1, CLRN=0, RSTN=1, EN=0, D=0
3.
PRN=1, CLRN=1, RSTN=0, EN=0, D=1
4.
PRN=1, CLRN=1, RSTN=1, EN=0, D=1
5.
PRN=1, CLRN=1, RSTN=1, EN=1, D=1
6.
PRN=1, CLRN=1, RSTN=0, EN=1, D=1
7.
PRN=1, CLRN=1, RSTN=1, EN=1, D=1
8.
PRN=1, CLRN=1, RSTN=1, EN=0, D=0
9.
PRN=1, CLRN=1, RSTN=1, EN=1, D=0
10. PRN=1, CLRN=1, RSTN=1, EN=0, D=1
Here is an example test pattern waveforms generated manually and saved as dff_enrst.vwf file.
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Spring 2022
To manually select a time interval on an input pin to be a logic value, point the mouse cursor at the start time of the
internal and drag the curse to the end time and then right click on the interval to choose a logic value. Here is an example to set
CLRN logic high “1” from 0 to 10ns manually.
Simulate your dff_enrst.bdf to verify its correctness. Snip a screen capture of the simulation report that shows the first
100ns waveforms. Annotate each input combination with one of the following phrases based on what should happen. Note that
“hold” means “does not change value”.
Hold, Load a 1, Load a 0, Synchronous Reset, Asynchronous Preset, Asynchronous Clear
If your waveform does not show the correct behavior, go back and fix your circuit before printing
and annotating the waveform.
Checkpoint #1: Submit a photo copy of your waveform generated by functional simulation of your
dff_enrst module to Moodle Dropbox by Friday, 04/08/2022 at 11:59PM EST
3.2
Design and Simulate a Two-Digit BCD Counter with Registered Output
You will combine eight instances of your new dff_enrst module with two instances of your BCD incrementer from Lab
#3 to create a two-digit BCD counter. Each digit of the BCD counter stores one 4-bit BCD number in its four D flip-flops. The
tens digit will only be incremented by one if the ones digit reach 10 to wrap back to 0. The counter uses the bcd_inc.v module
from Lab #3 to increment count value by one each time Cin of the bcd_inc.v is 1.
Within a two-digit counter, there are two instances of the bcd_inc modules (one per BCD digit) and eight instances of
the dff_enrst module (four per BCD digit). outputs of the flip-flops are inputs of the incrementers and outputs of the
incrementers are inputs to the flip-flops. In other words, each cycle that the incrementer is enabled, the incrementer adds 1 to
the value stored in the flip-flops, and the result is stored back to the corresponding flip-flops.
Figure 1 shows a partial diagram for a single-digit BCD incrementer. This figure is conceptual – a lot of the detail and
many required connections are not shown. The key idea, however, is that the bcd_inc module will increment its input by 1 if
Cin is 1. Its output value is stored into the flip-flops at the next active clock edge when the flip-flops are enabled by the same
Cin signal. The eight D flip-flops form an 8-bt register to store the two-digit BCD number.
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Spring 2022
There are four input pins. INC causes the counter to increment to the next BCD value on the next active edge of the
clock. RSTN (active low) synchronously clears the counter. CLK is the clock signal, and CLRN is an active-low asynchronous
clear.
Q3
Q2
Q1
Q0
A3
A2
A1
S3
S2
A0
Cin
S0
bcd_inc
D
Q
S1
D
Q
Q3
D
Q2
Q
bcd_inc
A3
S3
A2
S2
A1
S1
A0
S0
Cin Cout
inst11
D
Q1
Q
bcd_inc
Q0
A3
S3
A2
S2
A1
S1
A0
S0
Cin Cout
inst12
dff_enrst
D
EN
RSTN
CLK
PRN
CLRN
Q
inst8
Figure 1: A partial diagram for a single-digit BCD incrementer.
Figure 2 shows the template file bcd_count2.bdf as the starting point for you to complete the BCD counter with registered
output. It is composed of eight D flip-flops dff_enrst.bdf modules and two bcd_inc.bdf modules. The D flip-flops are essentially
a register store the BCD count digits from the bcd_inc.bdf. They will store the output BCB digits of bcd_inc.bdf module. The
ones digit is stored in D flip-flops Q3-0 and the tens digit is stored in Q4-7.
A larger copy of bcd_count2 schematic is provided on page 8 to help you design its connections. Use it to lay out how
you think the components should be connected. Notice you also need to add VCC component for PRN PIN.
Figure 2: the bcd_cocunt2.bdf template module
Implementing the Logic:
There is a hard copy of bcd_count2.bdf schematic on page 8 that you can use to help you design your counter.
1.
Inside the bcd_count2 schematic, double-click one of the bcd_inc modules to verify that your bcd_inc schematic
opens.
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Spring 2022
2.
The two bcd_inc and eight required dff_enrst modules are already present in the bcd_count2 schematic. All of the
I/O pins are also given to you. There are four input pins. INC causes the counter to increment to the next BCD value
on the next active edge of the clock. RSTN (active low) synchronously clears the counter. CLK is the clock signal,
and CLRN is an active-low asynchronous clear. There are eight outputs, Q7 through Q0. Q7 through Q4 are the bits
of the most significant BCD digit, and Q3 through Q0 are the bits of the least significant BCD digit.
3.
Some of the connections have already been made for you. You must complete the required
connections to make the BCD counter operate correctly. Note that the provided connections indicate
which bit position each flip-flop represents. Do not modify the existing connections, and be sure that
you take this information into account when completing the connections.
4.
Two pins can be connected by a direct wire connection or by assigning a small piece wire to each of
them and naming the two wires with the same name. After a wire is made, right click on it and choose
Properties to name the wire.
bcd_count2
INC
RSTN
CLK
CLRN
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
inst2
5.
Unused input pins of a device should be tied to proper voltage levels to be disabled. For example, active high input
VCC
pins should be tied to ground: and active low pins should be tied to power VCC:
to make them inactive. GND
and VCC components are available from symbol library: primitives->others. For this component, PRN pin is not used
and should be tied to VCC as it is active low.
6.
Create a simulation setup file by choosing File->New->University Program VWF and click OK. Save it as
bcd_cnt2.vwf and select Edit->Set End Time to change the end time to 240ns. Save this file as bcd_count2.vwf file.
7.
Choose Edit->Insert->Insert Node or Bus. Click Node Finder. Click List. Click >> to add all nodes or signals. Click
OK and OK.
8.
Right click on CLK waveform to select the entire wave interval. Right click to choose Value->Overwrite Clock. Set
CLK signal at 0, and have it change every 10ns with Overwrite Clock.
9.
Right click to select the entire wave from interval for CLRN and set it to 1 manually. Point and drag the mouse cursor
to select the first period of CLRN from 0 to 10ns, manually set the logic value to be 0. Set CLRN to logic 0 again
from 200ns to 210ns.
10. Highlight to set INC to 1 from 0ns until the counter output is equal to 0001 0011 BCD (or 13), which is until 140ns.
Then set INC to 0 from 140ns to 150ns (remembering to only change it at the midpoint between active edges) for one
cycle to show that the counter value does not change. Next, set INC to 1.
11. Set RSTN to 1 for the entire waveform interval and then select the period from 170ns to 180 ns to set RSTN to be 0.
In your waveform, make the order of signals match the pin order, with inputs above outputs.
In the vwf waveform generation window, combine ones digit output pins Q3-0 to form one group
called ones and tens digit output pins Q7-4 to form one group called tens as shown below. To do this,
select and highlight Q3-0, right click to open Grouping->Group as shown on the right hand side. Name
the group ones. Choose Radix to be Unsigned Decimal.
Right click on ones or tens to open Group and Bus Bit Order-> LSB on Top and MSB on Bottom
if needed.
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Run functional simulation to verify your bcd_count2 works. In your simulation waveforms, display the two 4-bit
numbers, ones and tens in decimal only by hiding Q7 to Q0. An example simulation waveforms screenshot is shown below.
Print out your waveform, and annotate each input combination with what is supposed to happen (e.g., “5→6”, “Hold”,
“Synchronous Reset”, etc.)
Checkpoint #2: Submit a photo copy of your waveform showing correct functionality of your 2-digit
BCD Counter module to Moodle Dropbox by Friday, 04/22/2022 at 11:59PM EST
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3.3
Spring 2022
Design and Simulate two Edge Detector or One-Shot Circuits
For the Guitar Hero game, the player will press the push buttons on the FPGA to input the correct note sequence. You will also
use these to test your Lab #4 during the demo. The push buttons are active-low and provide a 0 when pressed, and a 1 when
not pressed. However, they provide a 0 the entire time they are pressed, and we will want to create circuitry that reacts only
once each time the button is pressed. If not, the incrementer will increment a lot. You will therefore create an edge detector
circuit or one-shot circuit, that outputs a 1 only at the start of the button press, and a 0 the rest of the time. The input to this
circuit will be a single serial bit. You will create both Mealy and Moore-style state machines that output a 1 when the previous
value of the signal was a 1 and the current value is 0. Figure 3 shows the push button circuits on DE2-115.
5V
10K
R2
output
Reset
Figure 3 Push buttons on Altera DE2-115 are active low.
An edge detector circuit is also called one-shot circuit. It has one input IN, one output OUT and one reset input CLRN.
Input CLRN is active low. The circuit will produce an active high output for one clock cycle in length each time input IN goes
from high to low, e.g., “1” to “0”. CLRN can be either synchronous or asynchronous.
Designing the one-shot circuits with the worksheets:
1.
Using the sheets provided near the end of this document, draw the Moore and Mealy finite state machine diagrams
with as few states as possible that have the behavior described above. Make state 0 (or 00) the reset state while the
input of the state machine should be called IN, and the output should be called OUT. Use states 0b00, 0b01 and
0b11.Assume Sate 0b10 as Don’t Cares in your state table.
2.
Also fill out the state table, solve the K-maps, and give the final input and output questions.
You will need to turn in both sheets with your report.
Implementing and simulating Moore one-shot circuit:
1.
Double-click the edge_det_moore module. This module is empty apart from
pins. Implement the logic for your Moore FSM using the Quartus dff primitive
(not your dff_enrst module). Don't forget to wire the PRN and CLRN inputs
as well. Notice the two state variables are made visitable at the outputs.
2.
Choose simulation waveform setup file edge_det_moore.vwf file and execute
this simulation with the edge_det_moore module. Here are the simulation
waveform setup values. Notice the state variables are visible on the waveforms.
3.
Include your annotated simulation waveforms in your report.
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Use the unique transition numbers from your state diagram to annotate your waveforms.
Implementing and simulating Mealy one-shot circuit:
1.
Double-click the edge_det_mealy.bdf module. This module is empty apart
from pins. Implement the logic for your Mealy FSM using the Quartus dff
primitive (not your dff_enrst module). Notice the single state variable Q is
visible at output.
2.
Choose simulation waveform setup file edge_det_mealy.vwf file and execute
this simulation with the edge_det_mealy module. Here are the simulation
waveform setup values. Notice the state variables are visible on the waveforms.
3.
Include your annotated simulation waveforms in your report.
Use the unique transition numbers from your state diagram to annotate your waveforms.
Simulating both one-shot circuits together:
1.
Set the file mealy_vs_moore.bdf as the top level schematic. This
module is composed of two one-shot circuits: edge_det_mealy and
edge_det_moore.
2.
Functionally simulate the mealy_vs_moore.bdf module using
edge_det_both.vfw from Lab4Distribution folder
Here is a screenshot of the simulation waveform configuration.
Explain the differences that you observe in the behavior of the Mealy and Moore statemachines.
4
Demo Your Lab #4 Top Level Circuit on Altera DE2-115
Once you have created the components correctly, you should be able to build the top level circuit of Lab #4 and download
it to your Altera DE2 board to see how it works. Three push buttons are used to controlled your circuit: KEY3, KEY2 and
KY0. To correctly demo the circuit, SW0 (asynchronous clear CLRN) needs to be placed at the correct value. Look at the toplevel schematic to know what value this is and why it must be set this way.
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4.1
Spring 2022
Addedum added on April 26, 2022
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5
Spring 2022
Lab Report
REMINDER:
•
For any schematics you turn in this quarter, you must include a title block. A title block is shown in Figure 2 in the
Lab #1 documentation. It is available in Symbols under “Other”. The title block must include the name of the circuit and
your name.
•
For any waveforms you turn in this quarter, you must annotate the waveform to indicate whether it is a functional or
timing waveform, and what circuit it is for. You also should ensure that your waveforms are zoomed in enough that they
can be read. For a combinational circuit, you only need to include enough of the waveform to show each tested input
combination a single time. If requested to use a specific signal order (top to bottom), be sure to do so! Annotate each
input combination to show what is being tested.
Your report should have the following:
1) A cover with the lab number, lab name, your name(s), your instructor’s name, and your lab section.
2) The RTL schematic and the annotated functional waveforms for dff_enrst. (To obtain the RTL schematic, set the file at
top level, compile it and then open Tools->Netlist Viewers-> RTL Viewer.)
3) The RTL schematic and the annotated functional waveforms for bcd_count2.
4) The state diagram, K-maps, and equations for edge_det_moore. The RTL schematic for edge_det_moore. The annotated
functional waveforms for edge_det_moore with edge_det_moore.vwf.
5) The state diagram, K-maps, and equations for edge_det_mealy. The RTL schematic for edge_det_mealy. The annotated
functional waveforms for edge_det_mealy with edge_det_mealy.vwf.
6) The RTL schematic of mealy_vs_moore circuit. The annotated functional waveforms for mealy_vs_moore with
edge_detect_both.vwf.
6
1.
REFERENCES
M.M. MANO and C.R. KIME. Logic and Computer Design Fundamentals, 3rd ed. Upper Saddle River, NJ: Prentice Hall,
2003.
LAB #4 GRADING RUBRIC
Description
Max
Points
dff_enrst
Direct connections (PRN, CLRN, CLK, Q) are correct
1
RSTN is synchronous, has higher priority than EN, and loads FF with 0
1
When RSTN is 0, EN=0 prevents FF value from changing, and EN=1 causes D value to be loaded into the FF
1
Schematic uses good design practices, is well-organized, has pins in the correct places, and includes title block.
1
Functional waveform includes appropriate inputs and outputs in the requested order. It is correctly annotated according
1
to the stated requirements, and has reasonable zoom.
Functional waveform matches behavior of submitted logic, and any incorrect behavior is annotated. It includes all
1
requested input combinations at requested transition times.
bcd_count2
Flip-flop CLK, RSTN, CLRN, and PRN connections are correct
1
The INC input has the required function, either through the carry-in of the counter, the flip-flop enables, or both.
2
Schematic uses good design practices, is well-organized, has pins in the correct places, and includes title block.
1
Functional waveform includes appropriate inputs and outputs in the requested order. It is correctly annotated according
1
to the stated requirements, and has reasonable zoom.
Functional waveform matches behavior of submitted logic, and any incorrect behavior is annotated. It includes all
1
requested input combinations at requested transition times.
edge_det moore/mealy
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FSM diagram has the correct number of states
1
FSM diagram has the required transitions and the transitions are correctly labeled
2
State table correctly filled in from the state diagram on the provided sheet
2
Equation for D and OUT are given on the sheet and correct
2
Circuit has a reset input, it is correctly connected to the FF asynchronous reset input (through an inverter if the input is
active-high), and the preset is connected to 1. The reset can be active-low if labeled correctly and the waveform shows 1
it is treated as such.
Schematic is based on provided logic equations and is logically correct
1
Schematic uses good design practices, is well-organized, has pins in the correct places, and includes title block.
1
Functional waveform includes appropriate inputs and outputs in the requested order. It is correctly annotated according
1
to the stated requirements, and has reasonable zoom.
Functional waveform matches behavior of submitted logic, and any incorrect behavior is annotated.
1
Functional waveform demonstrates good testing methodology, testing all state transitions with as short of an input
1
sequence as possible
DESIGN TOTAL
25
Description
Report Format
Report includes title page according to template, with correct info
2
Report includes list of attachments, attachment order matches requested order, and actual organization matches list of
3
attachments
REPORT TOTAL
5
Description
Max
Points
Demonstration
Demonstrates understanding of dff_enrst
3
Demonstrates understanding of bcd_count2
3
Demonstrates understanding of edge_det
3
Demonstrates understanding of Top-level module and the module works correctly on the FPGA board
11
DEMO TOTAL
20
OVERALL
50
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Name(s):________________________________________ CM _______________
7
Moore Edge Detector FSM
Each time input IN goes from high “1” to low “0”, output OUT will produce a
logic “1” for one clock cycle only. The circuit will wait until input IN to go from low
“0” to high “1” again before it will start to detect the falling edge again. Input CLRN is
an active low reset signal to make OUT “0”.
State Machine:
State Table
Q1
Q0
IN
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
D1
D0
OUT
DFF Input Equations (Two-level SoP representation)
D0 =
D1 =
Output Equation
ECE233-04. -05 Jianjian Song
Lab #4 BCD Counters on DE2-115 Board
Page 16 of 18
ECE 233-04, -05 – Intro to Digital Systems
ECE233-04. -05 Jianjian Song
Spring 2022
Lab #4 BCD Counters on DE2-115 Board
Page 17 of 18
ECE 233-04, -05 – Intro to Digital Systems
Spring 2022
Name(s):________________________________________ CM _______________
Mealy Edge Detector FSM
State Machine:
Q
IN
0
0
0
1
1
0
1
1
D OUT
DFF Input Equation (Two-level SoP representation)
D0 =
Output Equation
ECE233-04. -05 Jianjian Song
Lab #4 BCD Counters on DE2-115 Board
Page 18 of 18