Matt Ozalas
Senior RF Power
Amplifier & Module
Design Expert.
Keysight EEsof EDA
Agilent’s Electronic Measurement Group
is now Keysight Technologies.
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How to Design an RF Power Amplifier: The Basics
Matthew Ozalas, RF Power Amplifier & Module Design Expert
Matt received his BSEE from Penn State University in 2001 and his MSEE
and MBA from Arizona State University in 2010. From 2001 to 2005, he
worked at the Mitre Corporation where he did RFIC and Power Amplifier
Design for a variety of high frequency applications. From 2005-2013, he
worked at Skyworks Solutions in the Santa Rosa Design Center, designing
and developing high volume multiband power amplifier and front end
modules for wireless handsets. He joined Keysight EEsof EDA in 2013,
where he is currently working as a Senior RF Power Amplifier & Module
Design Expert.
http://www.keysight.com/find/eesof-how-to-videos
Video App Notes:
How to Design an RF Power Amplifier: The Basics
How to Design an RF Power Amplifier: Class A, AB, B
How to Design an RF Power Amplifier: Class E
How to Design an RF Power Amplifier: Class F
Objectives and Topics
Objective: Show how to design an RF Power amplifier using concepts and
techniques introduced in the YouTube videos (link below)
• Define Power and Efficiency in a way which is practical and useful for PA design
• Discuss a model for a non-linear transistor, and show how to use this to design a PA
• Design a simple Power Amplifier (Class B, using a
Device )
• Design some advanced mode PAs (Class J, Class E using a
Device)
Example workspaces with tools from today’s designs are available for download:
http://www.keysight.com/find/eesof-how-to-videos
Video App Notes:
How to Design an RF Power Amplifier: The Basics
How to Design an RF Power Amplifier: Class A, AB, B
How to Design an RF Power Amplifier: Class E
How to Design an RF Power Amplifier: Class F
What is power?
www.keysight.com
AN1449-1
To get power in the time
domain, integrate the
product of voltage and
current over one period
Power Generation and Dissipation
Power
Dissipated
Pavg 
Vp I p
2
cos 
Power
Dissipater
Power
Generator
+
V
-
I
V=IR
Power
Generated
Conservation of Energy:
Pgen = Pdiss (+Pstored)
Large Signal Transistor
Add large signal effects
(nonlinear regions)
Transconductance (gm)
Start w/ standard small signal model
Iout
Output I vs. V
Iout
Saturation Region
Iout
Iin
1/RL
Input
Signal
Vin
gm*Vin
Vin
RL
Vout
Current
Voltage
Vin
sweep
current
time
Vknee
time
Output Signal is also constrained by external load
Analysis of Current Generator Waveforms
T
1
Pdiss   v(t )  i (t ) dt
T 0
Pdc
v (t )  V p sin(t )  Vdc

i (t )  I p sin(t   )  Idc
Voltage
Current
Vdc
Idc
Pdc
T
1
Pgen   [v (t )  Vdc ]  [i (t )  Idc ] dt
T 0
Pdc  Pdiss  Pgen
(Output
Efficiency)
out 
Pgen
Pgen  Pdiss

Pgen
Pdc
All values
in watts
Iout
Vout
Classical Modes of Operation
Large Signal Input Region
Vin
Output Waveforms
Large Signal Output Region
Iout
Voltage
Iout
-1/RL
Current
Vin
Voq, Ioq
Voq
Ioq
Viq, Ioq
Vin
Vout
time
Class A 50% Efficient
Class AB 50-78% Efficient
Class B 78.5% Efficient
Dissipated Power
Idrf ~ 4.7A
Vdmax<120V
PA Design Techniques
The point with the highest efficiency
might just be the most compressed
or saturated loadline
50 real, 50 imag
10 real, 10 imag
25 powers
35 Voltages
24 Second; 24 Third
Sweep size:
50 x 50 x 10 x 10 x 25 x 35 x 24 x 24
= 126 Billion Points
Class B Design
– Generate IV Curves
• Draw a loadline
– Present fundamental and harmonic impedances to the intrinsic
current generator
– Input Match (Conjugate)
– Sweep power
Class B Design
Draw Loadline using interactive utility
Sweep and Optimize External Load
Internal Device Parasitics
bondwire
Equation based
S1P block
Sweep External 2fo from –j50 to +j50
Z2ext~0
(C||L Resonance)
bondwire
Z2ext=-j*50
Explicitly set
harmonic
impedances
Present harmonic impedance externally
which provides a harmonic short
internally
Z2ext=+j*50
Class B PA Configuration
Biased off
Adjusted to achieve resistive fundamental,
harmonic shorts, inside the device
Class B Results
Advanced Modes of Operation
– Harmonic controls and switching modes can be used to further improve performance
through “waveform engineering” to minize I/V overlap regions
• Class D, E, F, J
• Device and package parasitics can limit ability to operate in these modes:
Class J and Continuous Modes
– First described by Cripps in 2006
• Relies on harmonic “boost” plus phase shifted fundamental
VA / B (t )  V pk * cos   Vdc
ideal
A / B  V pk  Vdc
α=-1 (Class J*)
α=1 (Class J)
VA / B (t )  Vdc (1  cos  )
VJ (t )  VA / B (t ) * (1   sin  )
 Vdc * 1  sin   cos   sin  cos  
sin  cos  
α=0 (Class B)
1
sin(2 )  sin 0
2
All of these have the
exact same performance!
Class J Design
– Generate IV Curves
• Draw a loadline
• Modify the waveforms to have a continuum operator
• Derive the resulting frequency domain impedances
– Present these impedances to the intrinsic current generator of
the device
– Input Match (Conjugate)
– Sweep power
Interactive Design: Class J
All other harmonics terminated in the
same way as the standard mode of
operation (Class B = Shorts)
Class J Circuit with Impedances
More on realization of physical circuits later…
Class J Results
Predicted From Interactive Synthesis Tool
Class E Topology
Voltage and current swings can push device limits
Vdc
(for 50% Duty Cycle)
Short @ 1fo
Open @ Harmonics
IDC
Current
Isw
T=0
T=π
T=2π
IPK=2.862*IDC
Vc 
1
I c dt
C
(180)
Voltage
Switch Point
I*sin(2πfrest)
Switch Closed
Current through Switch
π
VPK=3.562*VDC
Switch Open
Current through Cap
Duty cycle is an important design parameter
to ensure reliable operation…
However, design equations are not compact!
Class E Design Using Circuit Synthesis Approach
– Set limits based on reliability and intrinsic device parasitics
– Calculate circuit values using first principles
– Validate using ideal configuration, and extract fundamental and
harmonic impedances
– Present fundamental/harmonic impedances to real device
– Input Match (Conjugate)
– Sweep power
Class E Design Using Circuit Synthesis Approach
Difficult to realize at 3 GHz …
Idealized Validation of Synthesized Circuit
Class E using Cree Device
Physical Network Realization
These impedances
are external
bondwire
Tuned load
to achieve
LS impedances
These become
optimization targets…
Matching Network Synthesis
Output Design Through Optimizer
(Random + Gradient)
Matching Network Synthesis
(plus some additional iteration
and tuning)
First Cut Physical Class E Circuit
What to do with all the time you saved…
– Stability:
• Standard Small Signal Stability Analysis on Source and Load
• Large signal stability analysis: Use Techniques to look for RHP zeros
• Bypass Network Design and Feedback Analysis
– Product level PA specifications and considerations to think about:
• Achieving performance over frequency, corner conditions (Voltage, Temperature)
• Performance Robustness, Reliability, and Performance into VSWR
• Noise power leakage into adjacent Tx and Rx bands
• Electro-thermal Coupling and Memory Effects
• Design sensitivity to device and integration process technologies
How to Download the Workspaces
http://www.keysight.com/find/eesof-how-to-videos
How to design an RF Power Amplifier: The Basics
Class A, AB, B
Class E
You’re Invited!
www.keysight.com/find/eesof-innovations-in-eda-webcast-dvd
www.keysight.com/find/eesof-innovations-in-eda
Innovations in EDA Webcast
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