DR. AKHILESH DAS GUPTA
INSTITUTE OF TECHNOLOGY AND
MANAGEMENT
SUBMITTED TO: KAMYA DHINGRA
SUBJECT: DIGITAL SYSTEM DESIGN
NAME: EISHA GOEL
BRANCH & SEC: ECE, T3
ENROLLMENT NO: 01615602818
Name: Eisha Goel
Enrollment No.: 01615602818
INDEX
S.No.
Name of program
Date
1.
VHDL program to design all
basic gates using dataflow
modeling.
2.
VHDL program to design Half
Adder using dataflow modeling.
07/09/2020
3.
VHDL program to design Full
Adder using dataflow modeling.
14/09/2020
4.
VHDL program to design Half
Adder using structural modeling.
28/09/2020
5.
VHDL program to design 4:1
Multiplexer using behavioral
modeling.
05/10/2020
6.
VHDL program to design 1:4
Demultiplexer using behavioral
modeling.
26/10/2020
7.
VHDL program to design 1-Bit
Comparator using behavioral
modeling.
02/11/2020
8.
VHDL program to design Binary
to Gray Code Converter using
dataflow modeling.
09/11/2020
9.
To study and realize Encoder and
Decoder.
Remark Teacher
Sign
24/08/2020
23/11/2020
Name: Eisha Goel
Enrollment No.: 01615602818
EXPERIMENT-1
Aim: VHDL program to design all basic gates using dataflow modeling.
Software Version: Xilinx ISE Version 14.7
1. AND GATE :
Truth Table:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_or_top is
Port ( a : in STD_LOGIC; -- AND gate input
b: in STD_LOGIC; -- AND gate input
c : out STD_LOGIC; -- AND gate output
end and_or_top;
architecture Behavioral of and_or_top is
begin
c <= a and b; -- 2 input AND gate
end Behavioral;
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic:
Technology Schematic :
Simulation Result: Waveform:
Name: Eisha Goel
Enrollment No.: 01615602818
2. OR GATE :
Truth Table:
Code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_or_top is
Port ( a : in STD_LOGIC; -- OR gate input
b: in STD_LOGIC; -- OR gate input
c : out STD_LOGIC); -- OR gate output
end and_or_top;
architecture Behavioral of and_or_top is
begin
c<= a or b; -- 2 input OR gate
end Behavioral;
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic:
Technology Schematic :
Simulation Result: Waveform:
Name: Eisha Goel
Enrollment No.: 01615602818
3. NOT GATE:
Truth Table:
Code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity not1 is
Port (
a : in STD_LOGIC; -- NOT gate input
b : out STD_LOGIC); -- NOT gate output
end not1 ;
architecture Behavioral of not1 is
begin
b<= not a;
end Behavioral;
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic:
Technology Schematic:
Simulation Result: Waveform:
Name: Eisha Goel
Enrollment No.: 01615602818
4. NAND GATE:
Truth Table:
Code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nand1 is
Port ( a : in STD_LOGIC; -- NAND gate input
b: in STD_LOGIC; -- NAND gate input
c : out STD_LOGIC); -- NAND gate output
end nand1;
architecture Behavioral of nand1 is
begin
c<= a nand b; -- 2 input NAND gate
end Behavioral;
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic:
Technology Schematic:
Name: Eisha Goel
Enrollment No.: 01615602818
Simulation Result: Waveform:
Name: Eisha Goel
Enrollment No.: 01615602818
5. NOR GATE:
Truth Table:
Code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nor1 is
Port ( a : in STD_LOGIC; -- NOR gate input
b: in STD_LOGIC; -- NOR gate input
c : out STD_LOGIC); -- NOR gate output
endnor1;
architecture Behavioral of nor1 is
begin
c<= a nor b; -- 2 input OR gate
end Behavioral;
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic:
Technology Schematic:
Name: Eisha Goel
Enrollment No.: 01615602818
Simulation Result: Waveform:
Name: Eisha Goel
Enrollment No.: 01615602818
6. Ex-OR GATE:
Truth Table:
Code :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor1 is
Port ( a : in STD_LOGIC; -- XOR gate input
b: in STD_LOGIC; -- XOR gate input
c : out STD_LOGIC); -- XOR gate output
end xor1;
architecture Behavioral of xor1 is
begin
c<= a xor b; -- 2 input XOR gate
end Behavioral;
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic:
Technology Schematic:
Name: Eisha Goel
Enrollment No.: 01615602818
Simulation Result: Waveform:
Result: All basic gates have been realised successfully by dataflow modelling using Xilinx Software.
Name: Eisha Goel
Enrollment No.: 01615602818
EXPERIMENT-2
Aim: VHDL program to design Half adder using dataflow modeling.
Software Version: Xilinx ISE Version 14.7
1. Half Adder:
Truth Table:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ha1 is
Port ( a : in STD_LOGIC; -- input
b: in STD_LOGIC; -- input
c : out STD_LOGIC; -- output
s : out STD_LOGIC); -- output
end ha1;
architecture Behavioral of ha1 is
begin
s<= a xor b; -- 2 input XOR gate
c<=a and b; -- 2 input AND gate
end Behavioral;
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic:
Technology schematic :
Simulation Result: Waveform:
Result: Half Adder has been designed successfully by dataflow modelling using Xilinx Software.
Name: Eisha Goel
Enrollment No.: 01615602818
EXPERIMENT-3
Aim: VHDL program to design full adder using dataflow modeling.
Software Version: Xilinx ISE Version 14.7
1. Full Adder:
Truth Table:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ha1 is
Port ( a : in STD_LOGIC; -- input
b: in STD_LOGIC; -- input
c : out STD_LOGIC; -- output
s : out STD_LOGIC); -- output
end ha1;
architecture Behavioral of ha1 is
begin
s<= a xor b; -- 2 input XOR gate
c<=a and b; -- 2 input AND gate
end Behavioral;
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic:
Technology Schematic :
Simulation Result: Waveform:
Result: Full Adder has been designed successfully by dataflow modelling using Xilinx Software.
Name: Eisha Goel
Enrollment No.: 01615602818
EXPERIMENT-4
Aim: VHDL program to design Half adder using structural modeling.
Software Version: Xilinx ISE Version 14.7
1. Half Adder:
Truth Table:
Code:
Name: Eisha Goel
Enrollment No.: 01615602818
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic:
Technology Schematic :
Simulation Result: Waveform:
Result: Half Adder has been designed successfully by structural modelling using Xilinx Software.
Name: Eisha Goel
Enrollment No.: 01615602818
EXPERIMENT-5
Aim: VHDL program to design 4:1 Multiplexer using behavioral modeling.
Software Version: Xilinx ISE Version 14.7
1. 4:1 MULTIPLEXER:
Truth Table:
Code:
Library ieee;
use ieee.std_logic_1164.all;
entity mux is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s0 : in STD_LOGIC;
s1 : in STD_LOGIC;
y : out STD_LOGIC);
end mux;
architecture Behavioral of mux
is begin
p1:
process(a,b,c,d,s0,s1)
begin
if (s0= '0' and s1='0') then Y<=a;
elsif(s0='0' and s1='1') then
Y<=b; elsif(s0 ='1' and s1='0')
then Y<=c; else Y<=d;
end if;
end process;
end Behavioral;
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic:
Technology Schematic:
Name: Eisha Goel
Enrollment No.: 01615602818
Simulation Result: Waveform:
Result: 4:1 Multiplexer has been designed successfully by behavioral modelling using Xilinx Software.
Name: Eisha Goel
Enrollment No.: 01615602818
EXPERIMENT-6
Aim: VHDL program to design 1:4 Demultiplexer using behavioral modeling.
Software Version: Xilinx ISE Version 14.7
1. 1:4 DEMULTIPLEXER
Truth Table:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DMUX is
Port ( y, S0, S1 : inbit ;
A,B,C,D : outbit);
end ha1;
Architecture DMUX1 of DMUX is
begin
Process(y, S0,S1)
Begin
If (S0 = ‘0’ and S1 = ‘0’) then A<= y ;
elsif (S0 = ‘0’ and S1 = ‘1’) then B<= y ;
elsif (S0 = ‘1’ and S1 = ‘0’) then C<= y ;
else
D<=y;
end process;
end DMUX1;
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic :
Technology Schematic :
Name: Eisha Goel
Enrollment No.: 01615602818
Simulation Result: Waveform:
Result: 1:4 Demultiplexer has been designed successfully by behavioral modelling using Xilinx Software.
Name: Eisha Goel
Enrollment No.: 01615602818
EXPERIMENT-7
Aim: VHDL program to design 1-Bit Comparator using behavioral modeling.
Software Version: Xilinx ISE Version 14.7
1. 1-Bit Comparator:
Truth Table:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comp is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
agb : out STD_LOGIC;
aeb : out STD_LOGIC;
alb : out STD_LOGIC);
end comp;
architecture behavioural of comp is
begin
process(a,b)
begin
if a>b then
agb<='1';
aeb<='0';
alb<='0';
elsif a<b then
alb<='1';
aeb<='0';
agb<='0'; elsif
a=b then
aeb<='1';
agb<='0';
alb<='0';
end if;
end process; end
behavioural;
Name: Eisha Goel
Enrollment No.: 01615602818
RTL Schematic :
Truth Tables:
Name: Eisha Goel
Enrollment No.: 01615602818
Name: Eisha Goel
Enrollment No.: 01615602818
K-MAPS:
Name: Eisha Goel
Enrollment No.: 01615602818
Technology Schematic:
Name: Eisha Goel
Enrollment No.: 01615602818
Name: Eisha Goel
Enrollment No.: 01615602818
Simulation Result: Waveform:
Result: 1-Bit Comparator has been designed successfully by behavioral modelling using Xilinx Software.
Name: Eisha Goel
Enrollment No.: 01615602818
EXPERIMENT -8
Aim: VHDL program to design Binary to Gray Code Converter using dataflow modeling.
Software Version: Xilinx ISE Version 14.7
1. Binary to Gray Code Converter:
Truth Table:
Code:
Library ieee;
Use ieee.std_logic_1164.all;
Entity BG is ;
Port(B0, B1 ,B2 , B3 : inbit;
G0, G1, G2, G3 : outbit);
End BG ;
Architecture BG_D of BG is
Begin
G1<= B1 XOR B0;
G2<= B1 XOR B2;
G3<= B2 XOR B3;
G0<= B0;
End BG_d;
Name: Eisha Goel
Enrollment No.: 01615602818
Truth Table:
K- Map:
Name: Eisha Goel
Enrollment No.: 01615602818
Technology Schematic:
Name: Eisha Goel
Enrollment No.: 01615602818
Simulation Result: Waveform:
Result: Binart to Grey Code Converter has been designed successfully by dataflow modelling using Xilinx Software.
Name: Eisha Goel
Enrollment No.: 01615602818
EXPERIMENT-9
Aim: To study and realize Encoder and Decoder.
Software Version: Xilinx ISE Version 14.7
Theory:
Encoder:
An encoder is a device whose inputs are decimal or alphabetic character. An encoder has a number of input lines, only
one of which is activated at given time, and produces n bit output code.
Truth Table
Block Diagram
Decoder:
A decoder is a logic circuit that converts N bit input code to M output lines such that one output line is activated for
each one of the possible combinations of inputs. In other words we can say that a decoder identifies or recognize or
detect a particular code.
Truth Table
Block Diagram
Name: Eisha Goel
Enrollment No.: 01615602818
Code: VHDL Code for 4:2 Encoder using case statement:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity encoder is
port(a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(1 downto 0));
end encoder;
architecture bhv of encoder is
begin
process(a)
begin
case a is
when "1000" => b <= "11";
when "0100" => b<= "10";
when "0010" => b <= "01";
when "0001" => b <= "00";
when others => b <= "--";
end case;
end process;
end bhv;
Code: VHDL Code for 2:4 Decoder using case statement:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder is
port(a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0));
end decoder;
architecture bhv of decoder is
begin
process(a)
begin
case a is
when "00" => b <= "0001";
when "01" => b<= "0010";
when "10" => b <= "0100";
when "11" => b <= "1000";
when others => b <= "--";
end case;
end process;
end bhv;
Name: Eisha Goel
Enrollment No.: 01615602818
Simulation:
Result: Encoder and Decoder have been realised successfully using Xilinx Software.
Name: Eisha Goel
Enrollment No.: 01615602818