The Tenth International Conference on Electronic Measurement & Instruments
ICEMI’2011
Design and Implement of the Digital Storage Oscilloscope Card
Based on VHDL
He Zhiqiang, Feng Guonan, Zhang Jingzhi
College of Information Technology, Hebei University of Economics and Business,
NO.47 Xuefu Road, Shijiazhuang, Hebei province, 050061, China
Email: 153898461@qq.com
64MB. It can accomplish real-time data acquisition,
digital storage and waveform display. The digital storage
oscilloscope card adopts VHDL method to realize digital
logic functions in FPGA, which can controlling the card,
generating clock and processing trigger signal etc.
Abstract –This paper discusses the chief techniques and design
principles of a digital storage oscilloscope card based on VHDL,
which takes full advantage of high-speed data acquisition
technology. FPGA is adopted as the kernel controller, and
VHDL design method is utilized to achieve the global logic
control. The instrument consists of pre-process circuit,
acquisition circuit and FPGA and so on. The test result indicates
that the system works stably and the design is successful.
Keywords –Oscilloscope, Data acquisition, VHDL, FPGA.
II. ARCHITECTURAL DESIGN
The architecture of digital storage oscilloscope card
based on VHDL is shown in Figure 1. There are three
input signal channels in the front of the card: channel A,
channel B, and external trigger channel. The analog signal
can be input into channel A or channel B or the both, and
both of the two channels may work independently at the
same time, namely double-trace oscilloscope. After
passing the sensors, the outside signal comes into
front-end conditioning circuit through BCN interface; the
front-end conditioning circuit amplifies or attenuates the
analog signal to satisfy the input requirements of sampling
chip. Then sampling circuit converts the analog signal into
the digital signal which is convenient for host computer to
compute and store. Afterwards, the digital signal is
processed by the digital filtering in FPGA and stored into
SDRAM. Finally, the data in SDRAM is ready to be
loaded, processed and displayed by host computer through
PC104 bus. The interface controller is accord with PC104
bus specification and can fulfill complete interface
functions of PC104 bus. The entire oscilloscope card
works orderly under the control of the stable
high-frequency clock which is generated by clock circuit,
so the whole system is synchronous.
I. INTRODUCTION
In the field of electronic measurement, digital storage
oscilloscope is gradually replacing analog oscilloscope.
The great difference between digital storage oscilloscope
and analog oscilloscope is that when the signal enters the
digital storage oscilloscope, the front analog signal is
immediately converted into the digital signal by the
high-speed ADC, and then the digital signal is stored into
the SDRAM. Digital storage oscilloscope is not only
small size, low power consumption, easy to use, but also
has powerful ability for real-time signal processing and
analysis. Digital storage oscilloscope with digital signal
processing technology can process the stored data fleetly,
and get the waveform and parameter of the signal, as well
as display the waveform on related software and devices;
it has high accuracy and fast processing speed [1].
The digital storage oscilloscope card which is designed
and implemented in this paper is a kind of virtual digital
storage device based on VHDL. It can achieve
dual-channel 400MS/s real-time sampling rate, the analog
bandwidth is 100MHz, and the capacity of SDRAM is
Fig.1 The Architecture of Digital Storage Oscilloscope
The entire hardware design of oscilloscope card system
can be divided into two parts by ADC: the analog circuit
part and the signal circuit part. The main function of
analog circuit is conditioning input signal to make it
suitable for the A/D converting and the digital processing,
and the main function of digital circuit is controlling the
card by the digital logic control circuit, including the
control of the front analog channel, the switching of
___________________________________
978-1-4244-8161-3/11/$26.00 ©2011 IEEE
Authorized licensed use limited to: ULAKBIM UASL - ANKARA UNIVERSITESI. Downloaded on January 19,2023 at 12:44:40 UTC from IEEE Xplore. Restrictions apply.
The Tenth International Conference on Electronic Measurement & Instruments
electric relay, the control of trigger signal and A/D
converter, refreshing the memory, generating clock, and
the control of power and so on.
IV.
ICEMI’2011
DESIGN FOR SAMPLING CIRCUIT
Sampling circuit structure is shown in Figure 3.
Sampling circuit applies multiple parallel high-speed data
acquisition architecture, it uses several ADCs to sample
the input analog signal at the same time, then
parallel-serial converter combines signal from each ADC
as one flow which has higher speed and higher precision.
Thus the design can achieve high-speed data acquisition
without using high-speed ADC and meet the requirements
of high-speed system.
III. DESIGN FOR FRONT-END CONDITIONING
CIRCUIT
Front-end conditioning circuit is shown in Figure 2. In
high-speed data acquisition systems, the input voltage
range of ADC (Analog to Digital Converter) is limited,
ADC can not work normally if analog signal is out of the
range, larger signal may damage ADC and smaller signal
may not take full advantage of ADC resolution, so the
design of front-end conditioning circuit is necessary.
Front-end conditioning circuit can adjust input signal to
adapt the voltage requirements of ADC. Front-end
conditioning circuit includes RC attenuation network,
impedance transformation, the main amplifier, driver
amplifier and the bias adjustment and so on [2].
Fig.3 Parallel High-speed Data Acquisition Architecture
AD9288 is used as ADC chip, its output is completely
based on PECL logic. It is with 3.0V single voltage power
supply (2.7V-3.6V), low power consumption (90mW) and
small size (only 7 * 7mm). Its input peak-to-peak voltage
range is 1V, and its output data format is able to be either
offset binary or binary complement [3]. Either channel of
the card is using two pieces of AD9288. Either AD9288
contains two pieces of ADC. Either ADC has 100MSa/s
sampling rate. Each phase-difference among these 4
ADCs is 90°, and all the 4 ADCs are spliced together to
accomplish the 400MSa / s sampling rate. In the data
output section of the chip, either AD9288 uses two output
ports which are working in ping-pong mode, so that
maximum data transfer rate of each port reduced to
100MS/s. In this transmission rate, TTL circuitry still can
be used to implement the data latch, so no need for level
conversion to connect with memory interface, that
significantly reduce the requirement for the following
circuit.
Fig.2 Fron-end Conditioning Circuit
The main amplifier circuit adopts AD8008, which
contains two high-performance, current feedback
amplifier, with ultra-low distortion and noise, low
quiescent current, in addition to a wide supply voltage
range (5V-12V) and the wide range of bandwidths
(650MHz). Driving current of each amplifier is only 9mA,
rated operating temperature range is from -40 °C to
+85 °C. The two amplifiers is working in cascade, the
total magnification assessed by the two amplifiers,
therefore magnification of each amplifier is not high and
the whole amplifier circuit has good linearity, high
signal-to-noise ratio, and wide analog input bandwidth.
Both of the two amplifiers are connected with negative
feedback, which may decrease the magnification of
amplifier, but it can improve the performance of amplifier
in many respects: such as increasing the magnification
constant, reducing the nonlinear distortion, restraining
noise and expanding bandwidth etc.
For the data acquisition chip (AD9288) requires a
differential input, so it is necessary to convert the
single-ended signal into the differential signal before the
signal is sent into AD9288. AD8138 is adopted here to
solve this problem, which is a high speed differential
amplifier, with ± 5V power supply, 320MHz bandwidth.
The differential output common-mode voltage of AD8138
can be adjusted as user-defined. It does not have to use
transformer-coupling to transform the single-ended input
signal into differential output signal, for AD8138 can just
do all the work only by itself, thus the circuit structure is
simplified greatly.
V. VHDL DESIGN FOR DIGITAL LOGIC CONTROL
CIRCUIT
Digital logic control circuit of the digital storage
oscilloscope card is designed in FPGA. The greatest
feature of FPGA is flexible. FPGA can customize a
variety of circuits, which reduces the limit to ASIC. FPGA
can not only realize very complex high-speed logic, but
also integrate with DSP (Digital signal processing)
functions. Many manufacturers now offer ready-made
free IP cores to shorten the design cycle and reduce
development costs.
Digital logic control circuit is designed by VHDL.
Traditional graphic design (such as GDF graphic or state
diagram) is intuitive, but with poor accessibility and very
complicated to change in large-scale circuits, which is not
Authorized licensed use limited to: ULAKBIM UASL - ANKARA UNIVERSITESI. Downloaded on January 19,2023 at 12:44:40 UTC from IEEE Xplore. Restrictions apply.
The Tenth International Conference on Electronic Measurement & Instruments
conducive to improve circuit board. In contrast, VHDL
design approaches have obvious advantages. VHDL is a
standard hardware description language (HDL), and it is
an important method for the FPGA design. VHDL has
clear structure, simple grammar, fast simulation speed and
multi-library support, etc., which can descript the digital
circuit intuitively and accurately, so it is widely used in
simulation, synthesis design and so on [4].
ICEMI’2011
the number of rising edges of the tested signal "clk_x",
when "clk_1ms" count 8 rising edges, make the number of
the rising edge of "clk_x" 1024 multiplied, the result is the
real frequency "freq". According to the principle of
frequency measurement circuit to write VHDL code, then
compile, debug and build simulation, getting a detailed
simulation timing of the frequency measurement circuit
shown in Figure 5.
A. Frequency Measurement Circuit
The digital storage oscilloscope card often need to
measure the frequency in real time, so designing the
frequency measurement circuit is necessary. There are
two kinds of frequency measurement circuit design
approach: one is a direct frequency measurement method,
that is, measure the number of signal pulses in a certain
counting time (typically 1s); the other is an indirect
frequency measurement method, the most typical indirect
frequency measurement method is the cycle frequency
measurement method, that is, measure the signal cycle at
first, and then calculate the signal frequency according to
the signal cycle. Indirect measurement can calculate the
frequency by only calculating one cycle of the signal, so it
has a faster measurement speed and update speed, but if
signal is high-frequency, the cycle of signal will be very
small, the error of measuring cycle is severe, then the
result of the frequency is also severely error, so the
indirect measurement method is generally suitable only
for low-frequency signal measurement; in contrast with
indirect frequency measurement method, direct frequency
measurement method is imprecise in low-frequency signal
measurement, but very precise in high-frequency signal
measurement.
The digital storage oscilloscope card is a high-speed
data acquisition systems, the collected objects are high
frequency signals, so the design of frequency circuit is
using direct measurement method. The traditional direct
measurement method has a low measuring speed and a
low updating speed (usually update every second), in my
design, the method is improved according the practical
situation, the counting time is compressed to about the
same as one millisecond, the improved method has not
only very high precision in high frequency signal
measurement, but also faster measurement speed and
update speed. Frequency measurement circuit diagram is
shown in Figure 4.
Fig.5 Timing Simulation of Frequency Measurement Circuit
B. Trigger Circuit
Because memory storage has limited capacity and the
data in it is covered by cycle, general digital storage
oscilloscope system can only load the data that is collected
and stored after trigger arriving, loading the data which is
stored before the arrival of the trigger is very difficult. The
design of negative delay in the trigger circuit is a good
solution to this problem.
Design Principle of negative delay is shown in Figure 6,
the memory size is 1024 words, the storing procedure is:
start storing from address 0 at first, after all the 1K
memory is full, the storing process cover the data from
address 0 to 1K in cycles. In order to read the data before
the arrival of the trigger signal, we must ensure the wanted
data is not be covered by new data, and the address of
wanted data is also need to be known. For these two
objectives, the design of negative delay circuit use two
counters: counter A starts counting from a given initial
value, stops counting when the value is 1024; the counter
B is a ring address counter that counts the data address,
and the counting process is also cycling from address 0 to
1K synchronously with the storing process.
Assuming 300 words of data before the arrival of
trigger signal are wanted to load, so that the counter A
starts counting from 300 at time 1, the same time
recording the current value of the counter B (assuming
900), then the two counters are counting together, counter
A stops counting when the value is 1K (time 2) ,then the
value of counter B(600) is the start address to read, and the
data from 600th to 900th is not covered, thus these 300
words of data is just the data before the arrival of trigger.
Fig.4 Design Principle of Frequency Measurement Circuit
The clock signal generated by quartz crystal (32768Hz)
were divided by 8, so that a signal "clk_1ms" which is
8KHz (8*1024Hz) is obtained, then count the number of
rising edges of "clk_1ms", at the same time start counting
Fig.6 Design Principle of Negative Delay
Write VHDL code According to the design principle of
negative delay circuit, then compile, debug and build
Authorized licensed use limited to: ULAKBIM UASL - ANKARA UNIVERSITESI. Downloaded on January 19,2023 at 12:44:40 UTC from IEEE Xplore. Restrictions apply.
The Tenth International Conference on Electronic Measurement & Instruments
simulation with it, getting a detailed simulation timing of
the negative delay circuit which is shown in Figure 7.
ICEMI’2011
Research Project of Hebei Province Colleges and
Universities (ZD2010213).
REFERENCES
[1]
Fig.7 Timing Simulation of Trigger Circuit
VI.
CONCLUSION
[2]
This paper presents a digital storage oscilloscope card
based on VHDL, the actual test results show that the
performance indexes meet the design requirements, and
the system works stably. FPGA technology and VHDL
programming language are used in the design to improve
the performance; the design with VHDL is simple and
flexible, which shortens the development cycle. The
oscilloscope card adopts multi-channel parallel
acquisition architecture, it is with high speed, trusting
performance, strong currency and low cost, it can be
widely used for many occasions such as high-speed and
large capacity data acquisition and oscilloscope.
[3]
[4]
GUO Xiao-hu, CHEN Peng-peng. Design of a simple digital
memory oscilloscope based on MCU and FPGA. International
Electronic Elements. Mol. Research and Development. J. No.06.
pp. 39--42 (2008)
KANG Hua-guang. Basic Analog Electronic Technology (fifth
edition) M. pp. 241--247. Press, Higher Education (2006).
http://www.analog.com/zh/analog-to-digital-converters/ad-conver
ters/ad9288/products/product.html.
Liu Chang--hua. Research on the Basic Structure and Description
Style of VHDL. Computer & Digital Engineering. J. Vol.38 No.12,
pp. 141--143 (2010).
AUTHOR BIOGRAPHY
He Zhiqiang was born in Xingtai, China, in 1972. He
received D.E. from China University of Mining and Technology,
China, in 1999. Now he is a professor in Hebei University of
Economics and Business, China. His research interests include
high-speed data acquisition and processing, computer test and
control.
Feng Guonan was born in Shijiazhuang, China, in 1985.
Now he is MS Candidate in Hebei University of economics and
business, China.
Zhang Jingzhi was born in Nanyang, China, in 1986. Now
she is MS Candidate in Hebei University of economics and
business, China.
ACKNOWLEDGMENT
The author wishes to thank the basic research Project
of Applied Basic Research Projects in Hebei Province
(10963529D) and the key Science and Technology
Authorized licensed use limited to: ULAKBIM UASL - ANKARA UNIVERSITESI. Downloaded on January 19,2023 at 12:44:40 UTC from IEEE Xplore. Restrictions apply.